MSP430G2001IRSA16R [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430G2001IRSA16R |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总45页 (文件大小：847K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
MIXED SIGNAL MICROCONTROLLER
1
FEATURES
•
Low Supply-Voltage Range: 1.8 V to 3.6 V
•
16-Bit Timer_A With Two Capture/Compare
Registers
•
Ultralow Power Consumption
•
•
Brownout Detector
–
–
–
Active Mode: 220 µA at 1 MHz, 2.2 V
Standby Mode: 0.5 µA
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D (See Table 1)
Off Mode (RAM Retention): 0.1 µA
•
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
•
•
Five Power-Saving Modes
Ultrafast Wake-Up From Standby Mode in Less
Than 1 µs
•
•
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
•
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Basic Clock Module Configurations
•
•
For Family Members Details, See Table 1
–
Internal Frequencies up to 16 MHz With
One Calibrated Frequency
Available in a 14-Pin Plastic Small-Outline Thin
Package (TSSOP), 14-Pin Plastic Dual Inline
Package (PDIP), and 16-Pin QFN
–
Internal Very Low Power Low-Frequency
(LF) Oscillator
•
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
–
–
32-kHz Crystal
External Digital Clock Source
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2x01/11 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and ten
I/O pins. The MSP430G2x11 family members have a versatile analog comparator. For configuration details see
Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
www.ti.com
Table 1. Available Options(1)
FLASH
(KB)
RAM
(B)
COMP_A+
CHANNEL
PACKAGE
TYPE(2)
DEVICE
BSL
EEM
Timer_A
CLOCK
I/O
MSP430G2211IRSA16
MSP430G2211IPW14
MSP430G2211IN14
16-QFN
14-TSSOP
14-PDIP
-
1
2
2
128
128
128
128
128
1x TA2
8
-
LF, DCO, VLO
10
MSP430G2201IRSA16
MSP430G2201IPW14
MSP430G2201IN14
16-QFN
14-TSSOP
14-PDIP
-
-
-
-
1
1
1
1
1x TA2
1x TA2
1x TA2
1x TA2
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
10
10
10
10
MSP430G2111IRSA16
MSP430G2111IPW14
MSP430G2111IN14
16-QFN
14-TSSOP
14-PDIP
1
8
-
MSP430G2101IRSA16
MSP430G2101IPW14
MSP430G2101IN14
16-QFN
14-TSSOP
14-PDIP
1
MSP430G2001IRSA16
MSP430G2001IPW14
MSP430G2001IN14
16-QFN
14-TSSOP
14-PDIP
0.5
-
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Device Pinout, MSP430G2x01
N OR PW PACKAGE
(TOP VIEW)
14
DVSS
DVCC
1
2
3
4
5
6
7
13
12
11
10
9
XIN/P2.6/TA0.1
XOUT/P2.7
P1.0/TA0CLK/ACLK
P1.1/TA0.0
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/TDO/TDI
P1.2/TA0.1
P1.3
P1.4/SMCLK/TCK
8
P1.6/TA0.1/TDI/TCLK
P1.5/TA0.0/TMS
NOTE: See port schematics in Application Information for detailed I/O information.
RSA PACKAGE
(TOP VIEW)
16 15 14 13
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
12
11
10
9
XIN/P2.6/TA0.1
XOUT/P2.7
1
2
3
4
TEST/SBWTCK
RST/NMI/SBWTDIO
5
6
7
8
NOTE: See port schematics in Application Information for detailed I/O information.
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
www.ti.com
Device Pinout, MSP430G2x11
N OR PW PACKAGE
(TOP VIEW)
14
DVSS
DVCC
1
2
3
4
5
6
7
13
12
11
10
9
XIN/P2.6/TA0.1
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/CAOUT/CA7/TDO/TDI
P1.6/TA0.1/CA6/TDI/TCLK
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
P1.4/SMCLK/CA4/TCK
8
P1.5/TA0.0/CA5/TMS
NOTE: See port schematics in Application Information for detailed I/O information.
RSA PACKAGE
(TOP VIEW)
16 15 14 13
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
1
2
3
4
12 XIN/P2.6/TA0.1
11 XOUT/P2.7
10 TEST/SBWTCK
RST/NMI/SBWTDIO
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
9
5
6
7
8
NOTE: See port schematics in Application Information for detailed I/O information.
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MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Functional Block Diagram, MSP430G2x11
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
2
ACLK
Port P2
Port P1
Clock
System
SMCLK
Flash
RAM
128B
2 I/O
Interrupt
8 I/O
Interrupt
2KB
1KB
capability
pullup/down
resistors
capability
pullup/down
resistors
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
Comp_A+ Watchdog Timer0_A2
WDT+
Brownout
Protection
JTAG
Interface
8
Channels
2 CC
Registers
15-Bit
Spy-Bi
Wire
RST/NMI
Functional Block Diagram, MSP430G2x01
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
2
ACLK
Port P2
Port P1
Clock
System
Flash
SMCLK
RAM
128B
2 I/O
Interrupt
8 I/O
Interrupt
2KB
1KB
capability
pull-up/down
resistors
capability
pull-up/down
resistors
MCLK
0.5KB
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
Watchdog Timer0_A2
WDT+
2 CC
Brownout
Protection
JTAG
Interface
15-Bit
Registers
Spy-Bi
Wire
RST/NMI
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
www.ti.com
Table 2. Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
P1.0/
14
16
N, PW RSA
General–purpose digital I/O pin
TA0CLK/
ACLK/
CA0
Timer0_A, clock signal TACLK input
ACLK signal output
Comparator_A+, CA0 input(1)
2
1
I/O
P1.1/
General–purpose digital I/O pin
TA0.0/
CA1
3
4
5
2
3
4
I/O
I/O
I/O
Timer0_A, capture: CCI0A input, compare: Out0 output
Comparator_A+, CA1 input(1)
P1.2/
General–purpose digital I/O pin
TA0.1/
CA2
Timer0_A, capture: CCI1A input, compare: Out1 output
Comparator_A+, CA2 input(1)
P1.3/
General–purpose digital I/O pin
Comparator_A+, CA3 input(1)
CA3/
CAOUT
P1.4/
Comparator_A+, output(1)
General–purpose digital I/O pin
SMCLK/
CA4/
SMCLK signal output
Comparator_A+, CA4 input(1)
6
7
8
9
5
6
7
8
I/O
I/O
I/O
I/O
TCK
JTAG test clock, input terminal for device programming and test
General–purpose digital I/O pin
P1.5/
TA0.0/
CA5/
Timer0_A, compare: Out0 output
Comparator_A+, CA5 input(1)
TMS
JTAG test mode select, input terminal for device programming and test
General–purpose digital I/O pin
P1.6/
TA0.1/
CA6/
Timer0_A, compare: Out1 output
Comparator_A+, CA6 input(1)
TDI/TCLK
P1.7/
JTAG test data input or test clock input during programming and test
General–purpose digital I/O pin
CA7 input(1)
CA7/
CAOUT/
TDO/TDI(2)
XIN/
Comparator_A+, output(1)
JTAG test data output terminal or test data input during programming and test
Input terminal of crystal oscillator
General–purpose digital I/O pin
P2.6/
13
12
10
11
12
11
9
I/O
TA0.1
XOUT/
P2.7
Timer0_A, compare: Out1 output
Output terminal of crystal oscillator(3)
General–purpose digital I/O pin
I/O
RST/
Reset
NMI/
I
I
Nonmaskable interrupt input
SBWTDIO
TEST/
SBWTCK
DVCC
DVSS
NC
Spy–Bi–Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
10
Spy–Bi–Wire test clock input during programming and test
1
14
-
16
14
15
NA
NA
NA
Supply voltage
Ground reference
Not connected
(1) MSP430G2x11 only
(2) TDO or TDI is selected via JTAG instruction.
(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
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MSP430G2x01
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Table 2. Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
QFN Pad
14
16
N, PW RSA
-
Pad
NA
QFN package pad connection to VSS recommended.
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
www.ti.com
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
SP/R1
Stack Pointer
Status Register
SR/CG1/R2
CG2/R3
R4
Constant Generator
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
register-to-register operation execution time is one
cycle of the CPU clock.
R5
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
R6
R7
R8
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
R9
R10
R11
R12
R13
R14
R15
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
Table 3. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g., ADD R4,R5
e.g., CALL R8
e.g., JNE
R4 + R5 –-> R5
PC –>(TOS), R8–> PC
Jump-on-equal bit = 0
Table 4. Address Mode Descriptions(1)
ADDRESS MODE
Register
S
D
✓
✓
✓
✓
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
✓
✓
✓
✓
✓
R10 – –> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
M(2+R5) – –> M(6+R6)
M(EDE) – –> M(TONI)
M(MEM) – –> M(TCDAT)
M(R10) – –> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) – –> R11
R10 + 2– –> R10
Indirect autoincrement
Immediate
✓
✓
MOV @Rn+,Rm
MOV #X,TONI
#45 – –> M(TONI)
(1) S = source, D = destination
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MSP430G2x01
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
•
•
Low-power mode 1 (LPM1)
–
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
DCO's dc generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator remains enabled
ACLK remains active
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
–
–
–
–
–
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
Crystal oscillator is stopped
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will go
into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range(1)
PORIFG
RSTIFG
WDTIFG
KEYV(2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
ACCVIFG(2)(3)
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
29
28
27
26
25
24
23
22
21
20
19
18
17
16
COMP_A+
Watchdog Timer+
Timer_A2
CAIFG(4)(5)
WDTIFG
TACCR0 CCIFG(4)
TACCR1 CCIFG, TAIFG(2)(4)
maskable
maskable
maskable
Timer_A2
I/O Port P2 (two flags)
I/O Port P1 (eight flags)
P2IFG.6 to P2IFG.7(2)(4)
P1IFG.0 to P1IFG.7(2)(4)
maskable
maskable
(6)
See
0FFDEh to
0FFC0h
15 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) Devices with COMP_A+ only
(6) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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MSP430G2x01
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw-0
NMIIE
rw-0
OFIE
rw-0
WDTIE
rw-0
WDTIE
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
OFIE
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
Address
7
6
5
4
3
2
1
0
01h
Table 7. Interrupt Flag Register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw-0
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFG
rw-1
WDTIFG
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
PORIFG
RSTIFG
NMIIFG
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
Address
03h
7
6
5
4
3
2
1
0
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MSP430G2x11
MSP430G2x01
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Memory Organization
Table 8. Memory Organization
MSP430G2001
MSP430G2011
MSP430G2101
MSP430G2111
MSP430G2201
MSP430G2211
Memory
Size
Flash
Flash
Size
512B
1kB
2kB
Main: interrupt vector
Main: code memory
Information memory
0xFFFF to 0xFFC0
0xFFFF to 0xFE00
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xFC00
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xF800
256 Byte
Flash
Size
010FFh to 01000h
128B
010FFh to 01000h
128B
010FFh to 01000h
128B
RAM
027Fh to 0200h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
027Fh to 0200h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
027Fh to 0200h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
Peripherals
16–bit
8–bit
8–bit SFR
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
•
Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1µs. The basic
clock module provides the following clock signals:
•
•
•
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 9. DCO Calibration Data
(Provided From Factory In Flash Information Memory Segment A)
CALIBRATION
REGISTER
DCO FREQUENCY
SIZE
ADDRESS
CALBC1_1MHZ
CALDCO_1MHZ
byte
byte
010FFh
010FEh
1 MHz
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull-up/pull-down resistor.
WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
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Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 10. Timer_A2 Signal Connections – Devices With No Analog
INPUT PIN NUMBER
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
MODULE
BLOCK
PW, N
RSA
PW, N
RSA
2 - P1.0
1 - P1.0
TACLK
ACLK
SMCLK
TACLK
TA0
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
NA
TA0
TA1
2 - P1.0
3 - P1.1
1 - P1.0
2 - P1.1
3 - P1.1
7 - P1.5
2 - P1.1
6 - P1.5
ACLK (internal)
VSS
VCC
VCC
4 - P1.2
3 - P1.2
TA1
CCI1A
CCI1B
GND
4 - P1.2
8 - P1.6
13 - P2.6
3 - P1.2
7 - P1.6
12 - P2.6
TA1
VSS
VCC
VCC
Table 11. Timer_A2 Signal Connections – Devices With COMP_A+
INPUT PIN NUMBER
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
MODULE
BLOCK
PW, N
RSA
PW, N
RSA
2 - P1.0
1 - P1.0
TACLK
ACLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
NA
SMCLK
TACLK
TA0
2 - P1.0
3 - P1.1
1 - P1.0
2 - P1.1
3 - P1.1
7 - P1.5
2 - P1.1
6 - P1.5
ACLK (internal)
VSS
TA0
VCC
VCC
4 - P1.2
3 - P1.2
TA1
CCI1A
4 - P1.2
8 - P1.6
13 - P2.6
3 - P1.2
7 - P1.6
12 - P2.6
CAOUT
(internal)
CCI1B
CCR1
TA1
VSS
VCC
GND
VCC
Comparator_A+ (MSP430G2x11 only)
The primary function of the comparator_A+module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
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Peripheral File Map
Table 12. Peripherals With Word Access
REGISTER
NAME
MODULE
Timer_A
REGISTER DESCRIPTION
OFFSET
0174h
Capture/compare register
TACCR1
Capture/compare register
Timer_A register
TACCR0
TAR
0172h
0170h
0164h
0162h
0160h
012Eh
012Ch
012Ah
0128h
0120h
Capture/compare control
Capture/compare control
Timer_A control
TACCTL1
TACCTL0
TACTL
TAIV
Timer_A interrupt vector
Flash control 3
Flash Memory
FCTL3
FCTL2
FCTL1
WDTCTL
Flash control 2
Flash control 1
Watchdog Timer+
Watchdog/timer control
Table 13. Peripherals With Byte Access
REGISTER
NAME
MODULE
REGISTER DESCRIPTION
OFFSET
Comparator_A+
(MSP430G2x11 only)
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P2 resistor enable
Port P2 selection
CAPD
05Bh
05Ah
059h
053h
058h
057h
056h
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
027h
026h
025h
024h
023h
022h
021h
020h
003h
002h
001h
000h
CACTL2
CACTL1
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P2REN
P2SEL
P2IE
Basic Clock System+
Port P2
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 output
Port P2 input
Port P1
Port P1 resistor enable
Port P1 selection
P1REN
P1SEL
P1IE
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special Function
SFR interrupt flag 2
IFG2
SFR interrupt flag 1
IFG1
SFR interrupt enable 2
SFR interrupt enable 1
IE2
IE1
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MSP430G2x11
MSP430G2x01
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Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin(2)
–0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device pin
Unprogrammed device
Programmed device
–55°C to 150°C
–40°C to 85°C
(3)
Storage temperature range, Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
MIN NOM
MAX UNIT
During program execution
During flash program/erase
1.8
2.2
0
3.6
V
VCC
Supply voltage
3.6
VSS
TA
Supply voltage
V
Operating free-air temperature
I version
–40
85
°C
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
dc
dc
4.15
VCC = 2.7 V,
Duty cycle = 50% ± 10%
fSYSTEM
Processor frequency (maximum MCLK frequency)(1)(2)
12 MHz
16
VCC ≥ 3.3 V,
Duty cycle = 50% ± 10%
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
16 MHz
Supply voltage range
during flash memory
programming
12 MHz
Supply voltage range
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
2.2 V
220
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (1 MHz)
IAM,1MHz
µA
3 V
300
370
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics – Active Mode Supply Current (Into VCC)
5.0
4.0
3.0
2.0
1.0
0.0
4.0
3.0
2.0
1.0
0.0
f
= 16 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
V
= 3 V
CC
f
= 12 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
f
= 8 MHz
DCO
f
= 1 MHz
V
CC
= 2.2 V
DCO
1.5
2.0
2.5
3.0
3.5
4.0
0.0
4.0
8.0
12.0
16.0
V
CC
− Supply Voltage − V
f
DCO
− DCO Frequency − MHz
Figure 2. Active Mode Current vs VCC, TA = 25°C
Figure 3. Active Mode Current vs DCO Frequency
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MSP430G2x11
MSP430G2x01
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(2)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Low-power mode 0
(LPM0) current(3)
ILPM0,1MHz
25°C
2.2 V
65
µA
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 2
(LPM2) current(4)
ILPM2
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
Low-power mode 3
(LPM3) current(4)
ILPM3,LFXT1
ILPM3,VLO
ILPM4
25°C
25°C
2.2 V
2.2 V
0.7
0.5
1.5
0.7
µA
µA
µA
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
Low-power mode 3
current, (LPM3)(4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C
85°C
2.2 V
2.2 V
0.1
0.8
0.5
1.5
Low-power mode 4
(LPM4) current(5)
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
Vcc = 3.6 V
Vcc = 3 V
Vcc = 3.6 V
Vcc = 3 V
Vcc = 2.2 V
Vcc = 2.2 V
Vcc = 1.8 V
Vcc = 1.8 V
60 80
-40
-20
0
20
TA – Temperature – °C
Figure 5. LPM4 Current vs Temperature
40
-40
-20
0
20
40
60
80
TA – Temperature – °C
Figure 4. LPM3 Current vs Temperature
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Schmitt-Trigger Inputs – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45 VCC
1.35
TYP
MAX UNIT
0.75 VCC
VIT+
Positive-going input threshold voltage
V
V
3 V
2.25
0.55 VCC
1.65
0.25 VCC
0.75
VIT–
Negative-going input threshold voltage
3 V
3 V
Vhys
RPull
CI
Input voltage hysteresis (VIT+ – VIT–
Pullup/pulldown resistor
Input capacitance
)
0.3
1
V
For pullup: VIN = VSS
For pulldown: VIN = VCC
3 V
20
35
5
50
kΩ
pF
VIN = VSS or VCC
Leakage Current – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
±50 nA
(1) (2)
Ilkg(Px.x)
High-impedance leakage current
3 V
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –6 mA(1)
I(OLmax) = 6 mA(1)
VCC
3 V
3 V
MIN
TYP
VCC – 0.3
VSS + 0.3
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
V
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Px.y, CL = 20 pF, RL = 1 kΩ(1) (2)
Px.y, CL = 20 pF(2)
VCC
3 V
3 V
MIN
TYP
12
MAX UNIT
MHz
Port output frequency
(with load)
fPx.y
fPort_CLK
Clock output frequency
16
MHz
(1) A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
40.0
30.0
20.0
10.0
0.0
30.0
25.0
20.0
15.0
10.0
5.0
V
= 2.2 V
V
= 3 V
CC
CC
T
= 25°C
= 85°C
A
T
= 25°C
= 85°C
P1.7
A
P1.7
T
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 6.
Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
V
= 2.2 V
V
= 3 V
CC
CC
P1.7
P1.7
−10.0
−15.0
−20.0
−25.0
T
A
= 85°C
T
= 85°C
A
T
A
= 25°C
0.5
T
= 25°C
0.5
A
0.0
1.0
1.5
2.0
2.5
0.0
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 8.
Figure 9.
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POR/Brownout Reset (BOR)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
See Figure 10
TEST CONDITIONS
dVCC/dt ≤ 3 V/s
VCC
MIN
TYP
MAX UNIT
VCC(start)
V(B_IT–)
Vhys(B_IT–)
td(BOR)
0.7 × V(B_IT–)
1.35
V
V
See Figure 10 through Figure 12
See Figure 10
dVCC/dt ≤ 3 V/s
dVCC/dt ≤ 3 V/s
140
mV
See Figure 10
2000
µs
Pulse length needed at RST/NMI pin to
accepted reset internally
t(reset)
2.2 V/3 V
2
µs
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–)
+
Vhys(B_IT–)is ≤ 1.8 V.
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics – POR/Brownout Reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
Typical Conditions
CC
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(drop)
0.5
t = t
f
r
0
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
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Main DCO Characteristics
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
•
•
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × f
× f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
f
=
average
MOD × f
+ (32 – MOD) × f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.8
2.2
3
TYP
MAX UNIT
RSELx < 14
RSELx = 14
RSELx = 15
3.6
3.6
3.6
V
V
V
VCC
Supply voltage
fDCO(0,0)
fDCO(0,3)
fDCO(1,3)
fDCO(2,3)
fDCO(3,3)
fDCO(4,3)
fDCO(5,3)
fDCO(6,3)
fDCO(7,3)
fDCO(8,3)
fDCO(9,3)
fDCO(10,3)
fDCO(11,3)
fDCO(12,3)
fDCO(13,3)
fDCO(14,3)
fDCO(15,3)
fDCO(15,7)
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
0.06
0.14 MHz
MHz
0.12
0.15
0.21
0.3
MHz
MHz
MHz
0.41
0.58
0.8
MHz
MHz
MHz
0.8
1.5 MHz
MHz
1.6
2.3
MHz
3.4
MHz
4.25
MHz
4.3
8.6
7.3 MHz
MHz
7.8
13.9 MHz
MHz
15.25
21
MHz
Frequency step between
range RSEL and
RSEL+1
SRSEL
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3 V
1.35
ratio
Frequency step between
tap DCO and DCO+1
SDCO
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
Measured at SMCLK output
3 V
3 V
1.08
50
ratio
%
Duty cycle
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
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MAX UNIT
Calibrated DCO Frequencies – Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
BCSCTL1= CALBC1_1MHz,
1-MHz tolerance over temperature(1) DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
0°C to 85°C
3 V
-3
±0.5
+3
+3
+6
%
%
%
BCSCTL1= CALBC1_1MHz,
1-MHz tolerance over VCC
1-MHz tolerance overall
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
1.8 V to 3.6 V
-3
-6
±2
±3
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
-40°C to 85°C
(1) This is the frequency change from the measured frequency at 30°C over temperature.
Wake-Up From Lower-Power Modes (LPM3/4) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DCO clock wake-up time from
LPM3/4(1)
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
tDCO,LPM3/4
tCPU,LPM3/4
3 V
1.5
µs
1/fMCLK
+
CPU wake-up time from LPM3/4(2)
tClock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
DCO Frequency − MHz
Figure 13. DCO Wake-Up Time From LPM3 vs DCO Frequency
10.00
24
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MSP430G2x01
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32768
Hz
LFXT1 oscillator logic level
fLFXT1,LF,logic
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
1.8 V to 3.6 V 10000
32768 50000
Hz
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
200
Oscillation allowance for
LF crystals
OALF
kΩ
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
8.5
11
Integrated effective load
capacitance, LF mode(2)
CL,eff
pF
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
Duty cycle
fFault,LF
LF mode
2.2 V
2.2 V
30
10
50
70
%
Oscillator fault frequency,
LF mode(3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3(4)
10000
Hz
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TA
VCC
3 V
MIN
TYP
12
MAX UNIT
20 kHz
%/°C
fVLO
-40°C to 85°C
-40°C to 85°C
25°C
4
dfVLO/dT
3 V
0.5
4
dfVLO/dVCC VLO frequency supply voltage drift
1.8 V to 3.6 V
%/V
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
fTA
Timer_A input clock frequency
Timer_A capture timing
External: TACLK, INCLK
Duty cycle = 50% ± 10%
fSYSTEM
MHz
ns
tTA,cap
TA0, TA1
3 V
20
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
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Comparator_A+ (MSP430G2x11 only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
I(DD)
CAON = 1, CARSEL = 0, CAREF = 0
3 V
45
µA
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
No load at CA0 and CA1
I(Refladder/RefDiode)
3 V
3 V
45
µA
V(IC)
Common–mode input voltage
Voltage @ 0.25 V node
CAON = 1
0
VCC-1
V
CC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at CA0 and CA1
V(Ref025)
3 V
0.24
V
CC
Voltage @ 0.5 V
CC
node
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at CA0 and CA1
V(Ref050)
3 V
3 V
0.48
490
V
CC
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at CA0 and CA1, TA = 85°C
V(RefVT)
See Figure 14 and Figure 15
mV
V(offset)
Vhys
Offset voltage(1)
Input hysteresis
3 V
3 V
±10
0.7
mV
mV
CAON = 1
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
120
1.5
ns
µs
Response time
(low-high and high-low)
t(response)
3 V
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1
(1) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Typical Characteristics – Comparator_A+
650
650
600
550
500
450
400
VCC = 3 V
VCC = 2.2 V
600
550
500
450
400
Typical
Typical
-45
-25
-5
15
35
55
75
95
115
-45
-25
-5
15
35
55
75
95
115
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 14. V(RefVT) vs Temperature, VCC = 3 V
Figure 15. V(RefVT) vs Temperature, VCC = 2.2 V
100
VCC = 1.8 V
VCC = 2.2 V
VCC = 3 V
10
VCC = 3.6 V
1
0
0.4
0.6
0.8
1
0.2
VIN/VCC – Normalized Input Voltage – V/V
Figure 16. Short Resistance vs VIN/VCC
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE) Program and erase supply voltage
2.2
3.6
476
5
V
kHz
mA
fFTG
Flash timing generator frequency
Supply current from VCC during program
Supply current from VCC during erase
Cumulative program time(1)
257
IPGM
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
1
1
IERASE
tCPT
7
mA
10
ms
tCMErase
Cumulative mass erase time
20
104
100
ms
Program/erase endurance
105
cycles
years
tFTG
tFTG
tRetention
tWord
Data retention duration
TJ = 25°C
(2)
Word or byte program time
30
25
(2)
(2)
tBlock, 0
Block program time for first byte or word
Block program time for each additional byte or
word
tBlock, 1-63
18
tFTG
(2)
(2)
(2)
tBlock, End
tMass Erase
tSeg Erase
Block program end-sequence wait time
Mass erase time
6
10593
4819
tFTG
tFTG
tFTG
Segment erase time
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
(1)
V(RAMh)
RAM retention supply voltage
1.6
V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
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MSP430G2x01
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
JTAG and Spy-Bi-Wire Interface – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0
TYP
MAX
20
UNIT
MHz
µs
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
2.2 V/3 V
tSBW,Low Spy-Bi-Wire low clock pulse length
0.025
15
Spy-Bi-Wire enable time
tSBW,En
2.2 V/3 V
1
µs
(TEST high to acceptance of first clock edge(1)
)
tSBW,Ret
fTCK
Spy-Bi-Wire return to normal operation time
TCK input frequency(2)
2.2 V/3 V
2.2 V
15
0
100
5
µs
MHz
MHz
kΩ
3 V
0
10
90
RInternal
Internal pulldown resistance on TEST
2.2 V/3 V
25
60
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse(1) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
2.5
6
MAX
UNIT
V
VCC(FB)
VFB
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse blow
Supply current into TEST during fuse blow
Time to blow fuse
7
100
1
V
IFB
mA
ms
tFB
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
www.ti.com
APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger – MSP430G2x01
PxSEL.y
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.y
1
PxOUT.y
0
1
From Timer
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 14. Port P1 (P1.0 to P1.3) Pin Functions – MSP430G2x01
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1.0/
P1.x (I/O)
TA0CLK
ACLK
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
TA0CLK/
ACLK
P1.1/
0
0
1
P1.x (I/O)
TA0.CCI0A
TA0.0
I: 0; O: 1
TA0.0
1
1
0
P1.2/
P1.x (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
TA0.1
2
3
1
0
P1.3
P1.x (I/O)
I: 0; O: 1
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger – MSP430G2x01
PxSEL.y
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.y
1
PxOUT.y
0
1
From Module
P1.4/SMCLK/TCK
P1.5/TA0.0/TMS
P1.6/TA0.1/TDI/TCLK
P1.7/TDO/TDI
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
Table 15. Port P1 (P1.4 to P1.7) Pin Functions – MSP430G2x01
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
P1.4/
x
FUNCTION
P1DIR.x
P1SEL.x
JTAG Mode
CAPD.y
P1.x (I/O)
SMCLK
TCK
I: 0; O: 1
0
1
x
0
1
x
0
1
x
0
x
0
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
SMCLK/
TCK
4
5
1
x
P1.5/
P1.x (I/O)
TA0.0
I: 0; O: 1
TA0.0/
TMS
1
TMS
x
P1.6/
P1.x (I/O)
TA0.1
I: 0; O: 1
TA0.1/
TDI/TCLK
P1.7/
6
7
1
TDI/TCLK
P1.x (I/O)
TDO/TDI
x
I: 0; O: 1
x
TDO/TDI
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
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Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger – MSP430G2x11
To Comparator
from Comparator
PxSEL.y
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.y
1
PxOUT.y
ACLK
0
1
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
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MSP430G2x01
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Table 16. Port P1 (P1.0 to P1.3) Pin Functions – MSP430G2x11
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
CAPD.y
P1.0/
P1.x (I/O)
TA0.TACLK
ACLK
I: 0; O: 1
0
1
1
x
0
1
1
x
0
1
1
x
0
1
x
0
TA0CLK/
ACLK/
CA0
0
0
0
1
0
CA0
x
1 (y = 0)
P1.1/
P1.x (I/O)
TA0.0
I: 0; O: 1
0
TA0.0/
1
0
1
TA0.CCI0A
CA1
0
0
CA1
x
1 (y = 1)
P1.2/
TA0.1/
P1.x (I/O)
TA0.1
I: 0; O: 1
0
1
0
2
3
TA0.CCI1A
CA2
0
0
CA2
x
1 (y = 2)
P1.3/
CAOUT/
CA3
P1.x (I/O)
CAOUT
CA3
I: 0; O: 1
0
0
1
x
1 (y = 3)
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
www.ti.com
Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger – MSP430G2x11
To Comparator
from Comparator
CAPD.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
DVSS
DVCC
0
1
PxSEL.y
1
PxOUT.y
0
1
From Module
P1.4/SMCLK/CA4/TCK
P1.5/TA0.0/CA5/TMS
P1.6/TA0.1/CA6/TDI/TCLK
P1.7/CAOUT/CA7/TDO/TDI
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Table 17. Port P1 (P1.4 to P1.7) Pin Functions – MSP430G2x11
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
JTAG Mode
CAPD.y
P1.4/
P1.x (I/O)
SMCLK
CA4
I: 0; O: 1
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
SMCLK/
CA4/
1
0
4
x
1 (y = 4)
TCK
TCK
x
0
P1.5/
P1.x (I/O)
TA0.0
I: 0; O: 1
0
TA0.0/
CA5/
1
0
5
6
7
CA5
x
1 (y = 5)
TMS
TMS
x
0
P1.6/
P1.x (I/O)
TA0.1
I: 0; O: 1
0
TA0.1/
CA6/
1
0
CA6
x
1 (y = 6)
TDI/TCLK
P1.7/
TDI/TCLK
P1.x (I/O)
CAOUT
CA7
x
0
I: 0; O: 1
0
CAOUT/
CA7/
1
x
x
0
1 (y = 7)
0
TDO/TDI
TDO/TDI
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MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
www.ti.com
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger – MSP430G2x01 and
MSP430G2x11
XOUT/P2.7
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
PxSEL.6
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.6
1
PxOUT.y
0
1
from Module
Bus
Keeper
EN
XIN/P2.6/TA0.1
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 18. Port P2 (P2.6) Pin Functions – MSP430G2x01 and MSP430G2x11
CONTROL BITS / SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.6
P2SEL.7
XIN
XIN
0
I: 0; O: 1
1
1
0
1
1
x
x
P2.6
6
P2.x (I/O)
Timer0_A3.TA1
TA0.1
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MSP430G2x01
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SLAS695C –FEBRUARY 2010–REVISED JULY 2010
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger – MSP430G2x01 and
MSP430G2x11
XIN/P2.6/TA0.1
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
from P2.6/XIN
PxSEL.7
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.7
1
PxOUT.y
0
1
from Module
Bus
Keeper
EN
XOUT/P2.7
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 19. Port P2 (P2.7) Pin Functions – MSP430G2x01 and MSP430G2x11
CONTROL BITS / SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2SEL.6
P2SEL.7
P2DIR.x
P2SEL.7
XOUT
P2.7
XOUT
1
1
0
1
x
7
P2.x (I/O)
I: 0; O: 1
Copyright © 2010, Texas Instruments Incorporated
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37
MSP430G2x11
MSP430G2x01
SLAS695C –FEBRUARY 2010–REVISED JULY 2010
www.ti.com
REVISION HISTORY
REVISION
DESCRIPTION
SLAS695
Limited Product Preview release
Updated Product Preview
Changes throughout for sampling
Updated Product Preview
Production Data release
SLAS695A
SLAS695B
SLAS695C
38
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2001IN14
MSP430G2001IPW14R
MSP430G2001IRSA16R
MSP430G2001IRSA16T
MSP430G2101IN14
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
TSSOP
QFN
N
14
14
16
16
14
14
14
16
16
25
2000
3000
250
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
PW
RSA
RSA
N
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
PDIP
Pb-Free (RoHS)
Contact TI Distributor
or Sales Office
MSP430G2101IPW14
MSP430G2101IPW14R
MSP430G2101IRSA16R
MSP430G2101IRSA16T
TSSOP
TSSOP
QFN
PW
PW
RSA
RSA
90
Green (RoHS
& no Sb/Br)
Purchase Samples
2000
3000
250
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
Green (RoHS
& no Sb/Br)
Purchase Samples
Purchase Samples
Purchase Samples
QFN
Green (RoHS
& no Sb/Br)
MSP430G2111IN14
MSP430G2111IPW14
ACTIVE
ACTIVE
PDIP
N
14
14
25
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
MSP430G2111IPW14R
MSP430G2111IRSA16R
MSP430G2111IRSA16T
MSP430G2201IN14
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
QFN
PW
RSA
RSA
N
14
16
16
14
14
14
2000
3000
250
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
PDIP
Pb-Free (RoHS)
Contact TI Distributor
or Sales Office
MSP430G2201IPW14
MSP430G2201IPW14R
TSSOP
TSSOP
PW
PW
90
Green (RoHS
& no Sb/Br)
Purchase Samples
2000
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2010
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2201IRSA16R
MSP430G2201IRSA16T
MSP430G2211IPW14R
MSP430G2211IRSA16R
MSP430G2211IRSA16T
QFN
QFN
RSA
RSA
PW
16
16
14
16
16
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Contact TI Distributor
or Sales Office
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Request Free Samples
Request Free Samples
Purchase Samples
TSSOP
QFN
2000
3000
250
Green (RoHS
& no Sb/Br)
RSA
RSA
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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