MSP430G2001IRSA16 [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430G2001IRSA16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总47页 (文件大小：1061K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
D
D
Low Supply Voltage Range 1.8 V to 3.6 V
D
D
Brownout Detector
Ultralow Power Consumption
-- Active Mode: 220 µA at 1 MHz, 2.2 V
-- Standby Mode: 0.5 µA
-- Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultrafast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5 ns
Instruction Cycle Time
Basic Clock Module Configurations:
-- Internal Frequencies up to 16 MHz With
One Calibrated Frequency
-- Internal Very Low Power LF Oscillator
-- 32-kHz Crystal
-- External Digital Clock Source
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D (See
Table 1)
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Family Members details see Table 1
Available in a 14-Pin Plastic Small-Outline
Thin Package (TSSOP), 14-Pin Plastic Dual
Inline Package (PDIP), and 16-Pin QFN
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide
D
D
D
D
D
D
D
D
D
D
16-Bit Timer_A With Two Capture/Compare
Registers
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1 µs.
The MSP430G2x01/11 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and
ten I/O pins. The MSP430G2x11 family members have a versatile analog comparator. For configuration details
see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert themto digitalvalues,
and then process the data for display or for transmission to a host system.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright 2010 Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Table 1. Available Options -- MSP430G2xxx Devices
Flash RAM
COMP_A+
Channel
Package
Type
BSL
EEM
Timer_A
CLOCK
I/O
10
Device
(KB)
(B)
MSP430G2211IRSA16
MSP430G2211IPW14
MSP430G2211IN14
16-QFN
14-TSSOP
14-PDIP
--
1
2
128
1x TA2
8
--
8
--
--
LF, DCO, VLO
MSP430G2201IRSA16
MSP430G2201IPW14
MSP430G2201IN14
16-QFN
14-TSSOP
14-PDIP
--
--
--
--
1
1
1
1
2
1
128
128
128
128
1x TA2
1x TA2
1x TA2
1x TA2
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
10
10
10
10
MSP430G2111IRSA16
MSP430G2111IPW14
MSP430G2111IN14
16-QFN
14-TSSOP
14-PDIP
MSP430G2101IRSA16
MSP430G2101IPW14
MSP430G2101IN14
16-QFN
14-TSSOP
14-PDIP
1
MSP430G2001IRSA16
MSP430G2001IPW14
MSP430G2001IN14
16-QFN
14-TSSOP
14-PDIP
0.5
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
device pinout, MSP430G2x01
DVCC
1
2
3
4
5
6
7
14
13
12
11
10
9
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/TDO/TDI
P1.6/TA0.1/TDI/TCLK
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/ADC10CLK/CAOUT/CA3
P1.4/SMCLK/TCK
N14
PW14
8
P1.5/TA0.0/TMS
NOTE: See port schematics section for detailed I/O information.
16 15 14 13
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
1
2
3
4
12 XIN/P2.6/TA0.1
11 XOUT/P2.7
10 TEST/SBWTCK
RST/NMI/SBWTDIO
RSA
9
5
6
7
8
NOTE: See port schematics section for detailed I/O information.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
device pinout, MSP430G2x11
14
13
12
11
10
9
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/CAOUT/CA7/TDO/TDI
P1.6/TA0.1/CA6/TDI/TCLK
DVCC
P1.0/TA0CLK/ACLKCA0
P1.1/TA0.0/CA1
1
2
3
4
5
6
7
N14
P1.2/TA0.1/CA2
PW14
P1.3/CAOUT/CA3
P1.4/SMCLK/CA4/TCK
8
P1.5/TA0.0/CA5/TMS
NOTE: See port schematics section for detailed I/O information.
16 15 14 13
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
1
2
3
4
12 XIN/P2.6/TA0.1
11 XOUT/P2.7
10 TEST/SBWTCK
RST/NMI/SBWTDIO
RSA
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
9
5
6
7
8
NOTE: See port schematics section for detailed I/O information.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
functional block diagram, MSP430G2x11
XIN
XOUT
DVCC
DVSS
P1.x
P2.x
2
8
ACLK
SMCLK
Port P2
Port P1
Clock
System
Flash
RAM
128B
2 I/O
Interrupt
8 I/O
Interrupt
capability
pull-up/down
resistors
2KB
1KB
capability
pull-up/down
resistors
MCLK
16MHz
CPU
MAB
incl. 16
MDB
Registers
Emulation
2BP
Comp_A+
Watchdog Timer0_A2
Brownout
Protection
WDT+
2 CC
JTAG
8
Interface
Channels
15-Bit
Registers
Spy-Bi
Wire
RST/NMI
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
functional block diagram, MSP430G2x01
XIN
XOUT
DVCC
DVSS
P1.x
8
P2.x
2
ACLK
SMCLK
Port P2
Port P1
Clock
System
Flash
RAM
128B
2 I/O
Interrupt
8 I/O
Interrupt
capability
pull-up/down
resistors
2KB
1KB
capability
pull-up/down
resistors
MCLK
0.5KB
16MHz
CPU
MAB
incl. 16
MDB
Registers
Emulation
2BP
Watchdog Timer0_A2
Brownout
WDT+
2 CC
JTAG
Protection
Interface
15-Bit
Registers
Spy-Bi
Wire
RST/NMI
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Terminal Functions, MSP430G2x01 and MSP430G2x11
TERMINAL
14
16
DESCRIPTION
N, PW RSA
NAME
I/O
NO.
NO.
P1.0/
General-purpose digital I/O pin
Timer0_A, clock signal TACLK input
ACLK signal ouput
TA0CLK/
ACLK/
CA0
2
1
I/O
Comparator_A+, CA0 input (see Note 1)
P1.1/
TA0.0/
CA1
General-purpose digital I/O pin
I/O Timer0_A, capture: CCI0A input, compare: Out0 output
Comparator_A+, CA1 input (see Note 1)
3
4
5
2
3
4
P1.2/
TA0.1/
CA2
General-purpose digital I/O pin
I/O Timer0_A, capture: CCI1A input, compare: Out1 output
Comparator_A+, CA2 input (see Note 1)
P1.3/
CA3/
CAOUT
General-purpose digital I/O pin
I/O Comparator_A+, CA3 input (see Note 1)
Comparator_A+, output (see Note 1)
P1.4/
General-purpose digital I/O pin
SMCLK/
CA4/
SMCLK signal output
6
7
5
6
I/O
Comparator_A+, CA4 input (see Note 1)
JTAG test clock, input terminal for device programming and test
TCK
P1.5/
TA0.0/
CA5/
TMS
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
I/O
Comparator_A+, CA5 input (see Note 1)
JTAG test mode select, input terminal for device programming and test
P1.6/
TA0.1/
CA6/
TDI/
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
Comparator_A+, CA6 input (see Note 1)
8
9
7
8
I/O
I/O
JTAG test data input or test clock input during programming and test
TCLK
P1.7/
CA7/
CAOUT
TDO/
TDI
General-purpose digital I/O pin
CA7 input (see Note 1)
Comparator_A+, output (see Note 1)
JTAG test data output terminal or test data input during programming and test
NOTES: 1. MSP430G2x11 only.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Terminal Functions, MSP430G2x01 and MSP430G2x11 (continued)
TERMINAL
14
16
DESCRIPTION
N, PW RSA
NAME
I/O
NO.
NO.
XIN/
P2.6/
TA0.1
Input terminal of crystal oscillator
I/O General-purpose digital I/O pin
Timer0_A, compare: Out1 output
13
12
XOUT/
P2.7
Output terminal of crystal oscillator (see Note 1)
General-purpose digital I/O pin
12
10
11
11
9
I/O
RST/
NMI/
SBWTDIO
Reset
I
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
10
I
DVCC
DVSS
1
16
14
NA Supply voltage
14
NA Ground reference
15
13
NC
--
NA Not connected.
QFN Pad
--
Pad
NA QFN package pad connection to V recommended.
SS
NOTES: 1. If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
†
TDO or TDI is selected via JTAG instruction.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 2 shows examples of the three types of
instruction formats; Table 3 shows the address
modes.
R14
R15
Table 2. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g., ADD R4,R5
R4 + R5 ------> R5
e.g., CALL
e.g., JNE
R8
PC ---->(TOS), R8----> PC
Jump-on-equal bit = 0
Table 3. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
F
F
F
F
F
F
F
F
F
MOV Rs,Rd
R10 ----> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
M(2+R5)----> M(6+R6)
M(EDE) ----> M(TONI)
M(MEM) ----> M(TCDAT)
M(R10) ----> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) ----> R11
R10 + 2----> R10
F
MOV @Rn+,Rm
Immediate
F
MOV #X,TONI
#45 ----> M(TONI)
NOTE: S = source
D = destination
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
Active mode (AM)
-- All clocks are active
D
Low-power mode 0 (LPM0)
-- CPU is disabled
-- ACLK and SMCLK remain active. MCLK is disabled
Low-power mode 1 (LPM1)
D
D
-- CPU is disabled
-- ACLK and SMCLK remain active. MCLK is disabled
-- DCO’s dc-generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2)
-- CPU is disabled
-- MCLK and SMCLK are disabled
-- DCO’s dc-generator remains enabled
-- ACLK remains active
D
D
Low-power mode 3 (LPM3)
-- CPU is disabled
-- MCLK and SMCLK are disabled
-- DCO’s dc-generator is disabled
-- ACLK remains active
Low-power mode 4 (LPM4)
-- CPU is disabled
-- ACLK is disabled
-- MCLK and SMCLK are disabled
-- DCO’s dc-generator is disabled
-- Crystal oscillator is stopped
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
PORIFG
RSTIFG
WDTIFG
KEYV
Watchdog Timer+
Reset
0FFFEh
31, highest
Flash key violation
PC out-of-range (see Note 1)
(see Note 2)
NMIIFG
OFIFG
NMI
(non)-maskable,
(non)-maskable,
(non)-maskable
Oscillator fault
0FFFCh
30
ACCVIFG
Flash memory access violation
(see Notes 2 and 5)
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
29
28
27
26
25
COMP_A+
Watchdog Timer+
Timer_A2
CAIFG (see Note 3 and 4)
WDTIFG
maskable
maskable
maskable
TACCR0 CCIFG (see Note 3)
TACCR1 CCIFG.
TAIFG (see Notes 2 and 3)
Timer_A2
maskable
0FFF0h
24
0FFEEh
0FFECh
0FFEAh
0FFE8h
23
22
21
20
I/O Port P2
(two flags)
P2IFG.6 to P2IFG.7
(see Notes 2 and 3)
maskable
maskable
0FFE6h
0FFE4h
19
18
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 and 3)
0FFE2h
0FFE0h
17
16
(see Note 6)
0FFDEh ... 0FFC0h
15 ... 0, lowest
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module
4. Devices with COMP_A+ only.
5. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
6. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
notallocated to a functionalpurpose are notphysically presentin the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
OFIE
WDTIE
ACCVIE
NMIIE
rw-0
rw-0
rw-0
rw-0
WDTIE:
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
OFIE:
NMIIE:
ACCVIE:
Oscillator fault enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
Address
01h
interrupt flag register 1 and 2
7
6
5
4
3
2
1
0
Address
02h
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-1
rw-(0)
rw-(1)
WDTIFG:
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
OFIFG:
RSTIFG:
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC
power-up
PORIFG:
NMIIFG:
Power-On Reset interrupt flag. Set on VCC power-up.
Set via RST/NMI-pin
7
6
5
4
3
2
1
0
Address
03h
Legend
rw:
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-0,1:
rw-(0,1):
SFR bit is not present in device
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
memory organization
MSP430G2001
MSP430G2011
MSP430G2101
MSP430G2111
MSP430G2201
MSP430G2211
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
512B
0xFFFF to 0xFFC0
0xFFFF to
1kB
0xFFFF to 0xFFC0
0xFFFF to
2kB
0xFFFF to 0xFFC0
0xFFFF to
0xFE00
0xFC00
0xF800
Information memory
RAM
Size
256 Byte
256 Byte
256 Byte
Flash
010FFh -- 01000h
010FFh -- 01000h
010FFh -- 01000h
Size
128B
027Fh -- 0200h
128B
027Fh -- 0200h
128B
027Fh -- 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
flash memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D
Segment A contains calibration data. After reset segment A is protected against programming and erasing.
It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data
is required.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, and an internal digitally controlled oscillator
(DCO). The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
D
D
D
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO CALIBRATION DATA
(PROVIDED FROM FACTORY IN FLASH INFO MEMORY SEGMENT A)
DCO FREQUENCY
CALIBRATION
REGISTER
SIZE
ADDRESS
1 MHz
CALBC1_1MHZ
CALDCO_1MHZ
byte
byte
010FFh
010FEh
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull-up/pull-down resistor.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A2 SIGNAL CONNECTIONS -- DEVICES WITH NO ANALOG
INPUT
PIN NUMBER
MODULE
INPUT NAME
MODULE
OUTPUT
SIGNAL
DEVICE
INPUT SIGNAL
MODULE
BLOCK
OUTPUT
PIN NUMBER
PW, N
RSA
PW, N
RSA
2 - P1.0
1 - P1.0
TACLK
ACLK
TACLK
ACLK
Timer
CCR0
CCR1
NA
TA0
TA1
SMCLK
SMCLK
INCLK
CCI0A
CCI0B
GND
2 - P1.0
3 - P1.1
1 - P1.0
2 - P1.1
TACLK
TA0
3 - P1.1
7 - P1.5
2 - P1.1
6 - P1.5
ACLK (internal)
V
SS
CC
V
V
CC
4 - P1.2
3 - P1.2
TA1
TA1
CCI1A
CCI1B
GND
4 - P1.2
8 - P1.6
13 - P2.6
3 - P1.2
7 - P1.6
12 - P2.6
V
SS
CC
V
V
CC
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
TIMER_A2 SIGNAL CONNECTIONS -- DEVICES WITH COMP_A+
INPUT
PIN NUMBER
MODULE
INPUT NAME
MODULE
OUTPUT
SIGNAL
DEVICE
INPUT SIGNAL
MODULE
BLOCK
OUTPUT
PIN NUMBER
PW, N
RSA
PW, N
RSA
2 - P1.0
1 - P1.0
TACLK
ACLK
TACLK
ACLK
Timer
CCR0
CCR1
NA
TA0
TA1
SMCLK
SMCLK
INCLK
CCI0A
CCI0B
GND
2 - P1.0
3 - P1.1
1 - P1.0
2 - P1.1
TACLK
TA0
3 - P1.1
7 - P1.5
2 - P1.1
6 - P1.5
ACLK (internal)
V
SS
CC
V
V
CC
4 - P1.2
3 - P1.2
TA1
CCI1A
CCI1B
GND
4 - P1.2
8 - P1.6
13 - P2.6
3 - P1.2
7 - P1.6
12 - P2.6
CAOUT (internal)
V
SS
CC
V
V
CC
comparator_A+ (MSP430G2x11 only)
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_A
Capture/compare register
Capture/compare register
Timer_A register
TACCR1
TACCR0
TAR
TACCTL1
TACCTL0
TACTL
TAIV
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog Timer+
Watchdog/timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
Comparator_A+
(MSP430G2x11 only)
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock System+
Port P2
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P2 output
Port P2 input
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Port P1 output
Port P1 input
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
003h
002h
001h
000h
IE1
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Storage temperature, Tstg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 85°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage
SS
FB
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
MIN
1.8
NOM
MAX
3.6
UNIT
V
Supply voltage during program execution, V
CC
Supply voltage during program/erase flash memory, V
2.2
3.6
V
CC
Supply voltage, V
0
V
SS
Operating free-air temperature range, T
I version
= 1.8 V,
-- 4 0
dc
85
°C
A
V
CC
4.15
Duty Cycle = 50% ±10%
V
= 2.7 V,
CC
dc
dc
12
16
Processor frequency f
(Maximum MCLK frequency)
MHz
SYSTEM
Duty Cycle = 50% ±10%
V
≥ 3.3 V,
CC
Duty Cycle = 50% ±10%
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data
sheet.
Legend:
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage --V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V of 2.2 V.
CC
Figure 1. Save Operating Area
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
= f = f = 1MHz,
MCLK
T
A
V
MIN
TYP
MAX UNIT
CC
f
f
DCO
SMCLK
= 32,768Hz,
2.2 V
3 V
220
ACLK
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (1MHz)
I
µA
AM, 1MHz
300
370
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
typical characteristics -- active mode supply current (into VCC
)
5.0
4.0
3.0
2.0
1.0
0.0
4.0
3.0
2.0
1.0
0.0
f
= 16 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
V
= 3 V
CC
f
= 12 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
f
= 8 MHz
DCO
f
= 1 MHz
V
= 2.2 V
CC
DCO
1.5
2.0
2.5
3.0
3.5
4.0
0.0
4.0
8.0
12.0
16.0
V
-- Supply Voltage -- V
f
DCO
-- DCO Frequency -- MHz
CC
Figure 2. Active mode current vs VCC, TA = 25°C
Figure 3. Active mode current vs DCO frequency
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low-power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
T
A
V
MIN
TYP
MAX UNIT
CC
f
f
f
= 0 MHz,
SMCLK
MCLK
= f
= 1 MHz,
DCO
= 32,768 Hz,
Low-power mode 0
(LPM0) current,
see Note 3
ACLK
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
I
I
25°C
25°C
2.2 V
2.2 V
65
µA
LPM0, 1MHz
f
f
f
= f
= 0 MHz,
SMCLK
MCLK
DCO
ACLK
= 1 MHz,
= 32,768 Hz,
Low-power mode 2
(LPM2) current,
see Note 4
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
22
µA
LPM2
f
f
= f
ACLK
= f
= 0 MHz,
SMCLK
DCO
MCLK
= 32,768 Hz,
Low-power mode 3
(LPM3) current,
see Note 4
I
I
I
25°C
25°C
2.2 V
2.2 V
0.7
0.5
1.5
0.7
µA
µA
LPM3,LFXT1
LPM3,VLO
LPM4
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
f
f
= f
= f
= 0 MHz,
SMCLK
DCO
MCLK
Low-power mode 3
current, (LPM3)
see Note 4
from internal LF oscillator (VLO),
ACLK
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
f
f
= f
= f
= 0MHz,
SMCLK
DCO
MCLK
25°C
85°C
2.2 V
2.2 V
0.1
0.8
0.5
1.5
µA
µA
Low-power mode 4
(LPM4) current,
see Note 5
= 0 Hz,
ACLK
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- LPM3 current
10.0
9.0
8.0
7.0
6.0
5.0
Vcc = 3.6 V
4.0
Vcc = 3 V
3.0
Vcc = 2.2V
2.0
1.0
Vcc = 1.8 V
0.0
--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
T
A
-- Temperature -- °C
typical characteristics -- LPM4 current
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
Vcc = 3.6 V
Vcc = 3 V
Vcc = 2.2V
Vcc = 1.8 V
--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
-- Temperature -- °C
T
A
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs -- Ports Px
PARAMETER
TEST CONDITIONS
V
MIN
0.45
1.35
0.25
0.75
TYP
MAX UNIT
CC
0.75
2.25
0.55
1.65
V
CC
Positive-going input threshold
voltage
V
IT+
3 V
V
V
CC
Negative-going input threshold
voltage
V
V
IT--
3 V
3 V
V
Input voltage hysteresis (V
--
IT+
0.3
20
1.0
50
V
hys
V
)
IT--
For pullup: V = V
;
SS
IN
R
C
Pull-up/pull-down resistor
Input Capacitance
3V
35
kΩ
Pull
For pulldown: V = V
IN
CC
V
= V or V
CC
5
pF
I
IN
SS
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t
is met. It may be set even with trigger signals
(int)
shorter than t
.
(int)
leakage current -- Ports Px
PARAMETER
TEST CONDITIONS
see Notes 1 and 2
NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.
V
MIN
TYP
MAX UNIT
±50 nA
CC
I
High-impedance leakage current
3 V
lkg(Px.x)
SS
CC
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is
disabled.
outputs -- Ports Px
PARAMETER
TEST CONDITIONS
= --6 mA (see Notes 2)
= 6 mA (see Notes 2)
V
MIN
TYP
V -- 0 . 3
CC
MAX
UNIT
V
CC
V
V
High-level output voltage
Low-level output voltage
I
I
3 V
3 V
OH
OL
(OHmax)
(OLmax)
V
+0.3
SS
V
NOTES: 1. The maximum total current, I
voltage drop specified.
and I
, for all outputs combined, should not exceed ±12 mA to hold the maximum
OHmax
OLmax
2. The maximum total current, I
voltage drop specified.
and I
, for all outputs combined, should not exceed ±48 mA to hold the maximum
OHmax
OLmax
output frequency -- Ports Px
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
Port output frequency
Px.y, C = 20 pF, R = 1 kOhm
L
L
f
f
3 V
3 V
12
MHz
Px.y
(with load)
(see Note 1 and 2)
Px.y, C = 20 pF
L
Clock output frequency
16
MHz
Port_CLK
(see Note 2)
NOTES: 1. A resistive divider with 2 times 0.5 kΩ between V and V is used as load. The output is connected to the center tap of the divider.
CC
SS
2. The output voltage reaches at least 10% and 90% V at the specified toggle frequency.
CC
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
30.0
25.0
20.0
15.0
10.0
5.0
50.0
40.0
30.0
20.0
10.0
0.0
V
= 2.2 V
V
P1.7
= 3 V
CC
CC
P1.7
T
= 25°C
= 85°C
A
T
= 25°C
= 85°C
A
T
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
-- Low-Level Output Voltage -- V
V
-- Low-Level Output Voltage -- V
OL
OL
Figure 4
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0.0
--10.0
--20.0
--30.0
--40.0
--50.0
0.0
-- 5 . 0
V
= 3 V
V
= 2.2 V
CC
P1.7
CC
P1.7
--10.0
--15.0
--20.0
--25.0
T
A
= 85°C
T
= 85°C
A
T
A
= 25°C
T
= 25°C
A
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
V
-- High-Level Output Voltage -- V
V
-- High-Level Output Voltage -- V
OH
OH
Figure 6
Figure 7
NOTE: One output loaded at a time.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
V
V
V
(see Figure 8)
dV /dt ≤ 3 V/s
0.7 × V
(B_IT--)
V
V
CC(start)
CC
(see Figure 8 through Figure 10)
(see Figure 8)
dV /dt ≤ 3 V/s
CC
1.35
140
(B_IT--)
hys(B_IT--)
d(BOR)
dV /dt ≤ 3 V/s
CC
mV
µs
t
(see Figure 8)
2000
Pulse length needed at RST/NMI pin
to accepted reset internally
t
2.2 V/3 V
2
µs
(reset)
NOTES: 1. The current consumption of the brownout module is already included in the I current consumption data.
CC
The voltage level V
+ V
is ≤ 1.8V.
(B_IT--)
hys(B_IT--)
2. During power up, the CPU begins code execution following a period of t
after V = V
+ V
. The default DCO
hys(B_IT--)
d(BOR)
CC
(B_IT--)
settings must not bechangeduntil V ≥ V
, where V
is the minimum supply voltage for the desired operating frequency.
CC
CC(min)
CC(min)
V
CC
V
hys(B_IT--)
V
(B_IT--)
V
CC(start)
1
0
t
d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
-- Pulse Width -- µs
t
pw
-- Pulse Width -- µs
t
pw
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(drop)
0.5
0
t = t
f
r
0.001
1
1000
t
f
t
r
t
pw
-- Pulse Width -- µs
t
pw
-- Pulse Width -- µs
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D
D
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO)+(32−MOD) × fDCO(RSEL,DCO+1)
faverage
=
DCO frequency
PARAMETER
TEST CONDITIONS
V
MIN
1.8
TYP MAX UNIT
CC
RSELx < 14
3.6
3.6
3.6
V
V
V
RSELx = 14
RSELx = 15
2.2
Vcc
Supply voltage range
3.0
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
0.06
0.14 MHz
MHz
DCO(0,0)
DCO(0,3)
DCO(1,3)
DCO(2,3)
DCO(3,3)
DCO(4,3)
DCO(5,3)
DCO(6,3)
DCO(7,3)
DCO(8,3)
DCO(9,3)
DCO(10,3)
DCO(11,3)
DCO(12,3)
DCO(13,3)
DCO(14,3)
DCO(15,3)
DCO(15,7)
0.12
0.15
0.21
0.30
0.41
0.58
0.80
MHz
MHz
MHz
MHz
MHz
MHz
0.80
1.50 MHz
MHz
1.60
2.30
3.40
4.25
MHz
MHz
MHz
4.30
8.60
7.30 MHz
MHz
7.8
13.9 MHz
MHz
15.25
21.00
MHz
Frequency step between
range RSEL and RSEL+1
S
S
S
S
= f /f
DCO(RSEL+1,DCO) DCO(RSEL,DCO)
3 V
1.35
RSEL
DCO
RSEL
DCO
ratio
%
Frequency step between
tap DCO and DCO+1
= f
/f
3 V
3 V
1.08
50
DCO(RSEL,DCO+1) DCO(RSEL,DCO)
Duty Cycle
Measured at SMCLK output
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance
PARAMETER
TEST CONDITIONS
T
V
MIN
-- 3
TYP
MAX UNIT
A
CC
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
calibrated at 30°C and 3.0V
1 MHz tolerance over temperature
(see Note 1)
0°C to 85°C
30°C
3.0 V
±0.5
+3
+3
+6
%
%
%
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
calibrated at 30°C and 3.0V
1 MHz tolerance over V
1.8 V to 3.6 V
1.8 V to 3.6 V
-- 3
-- 6
±2
±3
CC
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
calibrated at 30°C and 3.0V
-- 4 0 °C to
85°C
1 MHz tolerance overall
NOTES: 1. This is the frequency change from the measured frequency at 30°C over temperature.
wake-up from lower power modes (LPM3/4)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
DCO clock wake-up time from
LPM3/4
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
t
t
3 V
1.5
µs
DCO,LPM3/4
CPU,LPM3/4
(see Note 1)
CPU wake-up time from LPM3/4
(see Note 2)
1/f
+
MCLK
Clock,LPM3/4
t
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics -- DCO clock wake-up time from LPM3/4
10.00
RSELx = 0...11
1.00
RSELx = 12...15
0.10
0.10
1.00
DCO Frequency -- MHz
10.00
Figure 11. DCO wake-up time from LPM3 vs DCO frequency
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
LFXT1 oscillator crystal
frequency, LF mode 0, 1
f
f
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32768
Hz
LFXT1,LF
LFXT1 oscillator logic level
square wave input frequency,
LF mode
XTS = 0, XCAPx = 0,
LFXT1Sx = 3
1.8 V to 3.6 V
10000
32768 50,000
Hz
LFXT1,LF,logic
XTS = 0, LFXT1Sx = 0,
LFXT1,LF
f
= 32,768 kHz,
500
200
C
L,eff
= 6 pF
Oscillation allowance for
LF crystals
OA
kΩ
LF
XTS = 0, LFXT1Sx = 0,
= 32,768 kHz,
f
LFXT1,LF
C
L,eff
= 12 pF
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
8.5
11
Integrated effective load
capacitance, LF mode
(see Note 1)
C
L,eff
pF
XTS = 0,
Duty cycle
LF mode
Measured at P2.0/ACLK,
2.2 V
2.2 V
30
10
50
70
%
f
= 32,768Hz
LFXT1,LF
Oscillator fault frequency,
LF mode (see Note 3)
XTS = 0, XCAPx = 0.
LFXT1Sx = 3 (see Note 2)
f
10000
Hz
Fault,LF
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
internal very low power, low frequency oscillator (VLO)
PARAMETER
TEST CONDITIONS
T
A
V
MIN
TYP
MAX UNIT
CC
f
VLO frequency
-40 -- 85°C
3.0 V
4
12
20
kHz
VLO
VLO frequency
temperature drift
df
df
/dT
/dV
-40 -- 85°C
3.0 V
0.5
4
%/°C
VLO
VLO
VLO frequency supply
voltage drift
25°C
1.8 V -- 3.6 V
%/V
CC
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
Internal: SMCLK, ACLK;
External: TACLK, INCLK;
Duty Cycle = 50% ±10%
f
t
Timer_A clock frequency
Timer_A, capture timing
f
MHz
ns
TA
SYSTEM
TA0, TA1
3 V
20
TA,cap
Comparator_A+ (MSP430G2x11 only)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
I
I
CAON=1, CARSEL=0, CAREF=0
3 V
45
µA
(DD)
CAON=1, CARSEL=0,
CAREF=1/2/3,
no load at CA0 and CA1
3 V
45
µA
(Refladder/RefDiode)
V
V
Common-mode input voltage
Voltage @ 0.25 V
CAON=1
3 V
3 V
0
V
-- 1
CC
V
(IC)
node
PCA0=1, CARSEL=1, CAREF=1,
no load at CA0 and CA1
CC
0.24
(Ref025)
V
CC
node
Voltage @ 0.5V
PCA0=1, CARSEL=1, CAREF=2,
no load at CA0 and CA1
CC
V
V
3 V
3 V
0.48
490
(Ref050)
(RefVT)
V
CC
PCA0=1, CARSEL=1, CAREF=3,
no load at CA0 and CA1, T = 85°C
(see Figure 12 and Figure 13)
mV
A
V
V
Offset voltage
See Note 2
CAON=1
3 V
3 V
±10
mV
mV
(offset)
hys
Input hysteresis
0.7
T
= 25°C, Overdrive 10 mV,
A
Without filter: CAF=0
3 V
120
1.5
ns
Response time
(low--high and high--low)
t
(response)
T
= 25°C, Overdrive 10 mV,
A
With filter: CAF=1
3 V
µs
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- Comparator_A+
650
600
550
500
450
400
650
600
550
500
450
400
V
= 2.2 V
V
= 3 V
CC
CC
Typical
Typical
--45 --25
--5
15
35
55
75
95
115
--45 --25
--5
15
35
55
75
95
115
T
A
-- Free-Air Temperature -- °C
T
A
-- Free-Air Temperature -- °C
Figure 13. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 12. V(RefVT) vs Temperature, VCC = 3 V
100.00
V
V
= 1.8V
CC
V
= 2.2V
= 3.0V
CC
V
CC
10.00
= 3.6V
0.6
CC
1.00
0.0
0.2
/V
0.4
0.8
1.0
V
-- Normalized Input Voltage -- V/V
IN CC
Figure 14. Short Resistance vs VIN/VCC
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
PARAMETER
TEST CONDITIONS
V
MIN
2.2
TYP
MAX UNIT
CC
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from V during program
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
1
1
PGM
CC
Supply current from V during erase
CC
7
mA
ERASE
CPT
Cumulative program time (see Note 1)
Cumulative mass erase time
Program/Erase endurance
Data retention duration
10
ms
20
ms
CMErase
4
5
10
10
cycles
years
t
T = 25°C
J
100
Retention
t
t
t
t
t
t
Word or byte program time
30
25
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
18
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 2
t
FTG
6
10593
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (t
= 1/f
).
FTG
FTG
RAM
PARAMETER
TEST CONDITIONS
CPU halted
MIN
TYP
MAX UNIT
V
RAM retention supply voltage (see Note 1)
1.6
V
(RAMh)
NOTE 1: This parameter defines the minimum supply voltage V when the data in RAM remains unchanged. No program execution should
CC
happen during this supply voltage condition.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
JTAG and Spy-Bi-Wire interface
TEST
CONDITIONS
PARAMETER
V
MIN
TYP
MAX
UNIT
CC
f
t
Spy-Bi-Wire input frequency
2.2 V / 3 V
2.2 V / 3 V
0
20
15
MHz
us
SBW
Spy-Bi-Wire low clock pulse length
0.025
SBW,Low
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge, see
Note 1)
t
2.2 V/ 3 V
1
us
SBW,En
t
f
Spy-Bi-Wire return to normal operation time
2.2 V/ 3 V
2.2 V
15
0
100
5
us
SBW,Ret
TCK
MHz
MHz
kΩ
TCK input frequency -- 4-wire JTAG (see Note 2)
Internal pull-down resistance on TEST
3 V
0
10
90
R
2.2 V/ 3 V
25
60
Internal
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t
before applying the first SBWTCK clock edge.
time after pulling the TEST/SBWTCK pin high
SBW,En
2.
f
may be restricted to meet the timing requirements of the module selected.
TCK
JTAG fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
MIN
TYP
MAX
UNIT
CC
V
V
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse-blow
Supply current into TEST during fuse blow
Time to blow fuse
T
A
= 25°C
2.5
6
V
V
CC(FB)
FB
7
100
1
I
t
mA
ms
FB
FB
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched
to bypass mode.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt trigger -- MSP430G2x10
PxSEL.y
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.y
1
PxOUT.y
From Timer
0
1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
PxSEL.y
PxIES.y
Select
Port P1 (P1.0 to P1.3) pin functions -- MSP430G2x10
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
P1.0/
0
P1.x (I/O)
TA0.TACLK
ACLK
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
TA0CLK/
ACLK
0
1
P1.1/
1
2
3
P1.x (I/O)
TA0.0
I: 0; O: 1
TA0.0
1
TA0.CCI0A
P1.x (I/O)
TA0.1
0
P1.2/
I: 0; O: 1
TA0.1
1
0
TA0.CCI1A
P1.x (I/O)
P1.3/
I: 0; O: 1
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P1 pin schematic: P1.4 to P1.7, input/output with Schmitt trigger -- MSP430G2x10
PxSEL.y
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.y
1
PxOUT.y
From Module
0
1
P1.4/SMCLK/TCK
P1.5/TA0.0/TMS
P1.6/TA0.1/TDI/TCLK
P1.7/TDO/TDI
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
PxSEL.y
PxIES.y
Select
From JTAG
To JTAG
Port P1 (P1.4 to P1.7) pin functions -- MSP430G2x10
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
JTAG
P1SEL.x
P1DIR.x
CAPD.y
Mode
P1.4/
4
P1.x (I/O)
SMCLK
TCK
I: 0; O: 1
0
1
x
0
1
x
0
1
x
0
x
0
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
SMCLK/
TCK
1
x
P1.5/
5
6
7
P1.x (I/O)
TA0.0
I: 0; O: 1
TA0.0/
TMS
1
TMS
x
P1.6/
P1.x (I/O)
TA0.1
I: 0; O: 1
TA0.1/
TDI/TCLK
P1.7/
1
TDI/TCLK
P1.x (I/O)
TDO/TDI
x
I: 0; O: 1
x
TDO/TDI
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt trigger -- MSP430G2x11
To Comparator
from Comparator
PxSEL.y
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.y
1
PxOUT.y
0
1
ACLK
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
PxSEL.y
PxIES.y
Select
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P1 (P1.0 to P1.3) pin functions -- MSP430G2x11
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
CAPD.y
P1.0/
0
P1.x (I/O)
TA0.TACLK
ACLK
I: 0; O: 1
0
1
1
x
0
1
1
x
0
1
1
x
0
1
x
0
TA0CLK/
ACLK/
CA0
0
0
1
0
CA0
x
1 (y = 0)
P1.1/
1
2
3
P1.x (I/O)
TA0.0
I: 0; O: 1
0
TA0.0/
1
0
TA0.CCI0A
CA1
0
0
CA1
x
1 (y = 1)
P1.2/
TA0.1/
P1.x (I/O)
TA0.1
I: 0; O: 1
0
1
0
TA0.CCI1A
CA2
0
0
CA2
x
1 (y = 2)
P1.3/
CAOUT/
CA3
P1.x (I/O)
CAOUT
CA3
I: 0; O: 1
0
0
1
x
1 (y = 3)
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P1 pin schematic: P1.4 to P1.7, input/output with Schmitt trigger -- MSP430G2x11
To Comparator
from Comparator
CAPD.y
PxSEL.y
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.y
1
PxOUT.y
From Module
0
1
P1.4/SMCLK/CA4/TCK
P1.5/TA0.0/CA5/TMS
P1.6/TA0.1/CA6/TDI/TCLK
P1.7/CAOUT/CA7/TDO/TDI
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
PxSEL.y
PxIES.y
Select
From JTAG
To JTAG
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P1 (P1.4 to P1.7) pin functions -- MSP430G2x11
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
JTAG
P1SEL.x
P1DIR.x
CAPD.y
Mode
P1.4/
4
P1.x (I/O)
SMCLK
CA4
I: 0; O: 1
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
SMCLK/
CA4/
1
0
x
1 (y = 4)
TCK
TCK
x
0
P1.5/
5
6
7
P1.x (I/O)
TA0.0
I: 0; O: 1
0
TA0.0/
CA5/
1
0
CA5
x
1 (y = 5)
TMS
TMS
x
0
P1.6/
P1.x (I/O)
TA0.1
I: 0; O: 1
0
TA0.1/
CA6/
1
0
CA6
x
1 (y = 6)
TDI/TCLK
P1.7/
TDI/TCLK
P1.x (I/O)
CAOUT
CA7
x
0
I: 0; O: 1
0
CAOUT/
CA7/
1
x
x
0
1 (y = 7)
0
TDO/TDI
TDO/TDI
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P2 pin schematic: P2.6, input/output with Schmitt trigger -- MSP430G2x10 and MSP430G2x11
XOUT/P2.7
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
PxSEL.6
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.6
1
PxOUT.y
from Module
0
1
Bus
Keeper
EN
XIN/P2.6/TA0.1
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
PxSEL.y
PxIES.y
Select
Port P2 (P2.6) pin functions -- MSP430G2x10 and MSP430G2x11
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.6
PSEL2.7
XIN
6
XIN
0
I: 0; O: 1
1
1
0
1
1
x
x
P2.6
P2.x (I/O)
Timer0_A3.TA1
TA0.1
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430G2x01, MSP430G2x11
MIXED SIGNAL MICROCONTROLLER
SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P2 pin schematic: P2.7, input/output with Schmitt trigger -- MSP430G2x10 and MSP430G2x11
XIN/P2.6/TA0.1
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
from P2.6/XIN
PxSEL.7
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.7
1
PxOUT.y
from Module
0
1
Bus
Keeper
EN
XOUT/P2.7
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
PxSEL.y
PxIES.y
Select
Port P2 (P2.7) pin functions -- MSP430G2x10 and MSP430G2x11
CONTROL BITS / SIGNALS
P2SEL.6
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
P2SEL.7
P2SEL.7
XOUT
P2.7
7
XOUT
1
1
0
1
x
P2.x (I/O)
I: 0; O: 1
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2010
PACKAGING INFORMATION
Orderable Device
MSP430G2001IN14
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
14
14
16
16
14
14
14
16
16
14
14
14
16
16
14
14
14
16
16
14
16
16
25
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430G2001IPW14R
MSP430G2001IRSA16R
MSP430G2001IRSA16T
MSP430G2101IN14
TSSOP
QFN
PW
RSA
RSA
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
PDIP
25
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430G2101IPW14
MSP430G2101IPW14R
MSP430G2101IRSA16R
MSP430G2101IRSA16T
MSP430G2111IN14
TSSOP
TSSOP
QFN
PW
PW
RSA
RSA
N
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
PDIP
25
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430G2111IPW14
MSP430G2111IPW14R
MSP430G2111IRSA16R
MSP430G2111IRSA16T
MSP430G2201IN14
TSSOP
TSSOP
QFN
PW
PW
RSA
RSA
N
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
PDIP
25
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430G2201IPW14
MSP430G2201IPW14R
MSP430G2201IRSA16R
MSP430G2201IRSA16T
MSP430G2211IPW14R
MSP430G2211IRSA16R
MSP430G2211IRSA16T
TSSOP
TSSOP
QFN
PW
PW
RSA
RSA
PW
RSA
RSA
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
QFN
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2010
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
Automotive
www.ti.com/automotive
www.ti.com/communications
Communications and
Telecom
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Consumer Electronics
Energy
www.ti.com/consumer-apps
www.ti.com/energy
Logic
Industrial
www.ti.com/industrial
Power Mgmt
Microcontrollers
RFID
power.ti.com
Medical
www.ti.com/medical
microcontroller.ti.com
www.ti-rfid.com
Security
www.ti.com/security
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明