MSP430G2231IRSA16T [TI]

MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器


型号：	MSP430G2231IRSA16T
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER 混合信号微控制器微控制器和处理器外围集成电路装置 PC 时钟
文件：	总61页 (文件大小：1276K)
中文：	中文翻译
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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Low Supply Voltage Range 1.8 V to 3.6 V

Universal Serial Interface (USI) Supporting

SPI and I2C (See Table 1)

Brownout Detector

10-Bit 200-ksps A/D Converter With Internal

Reference, Sample-and-Hold, and Autoscan

(See Table 1)

Serial Onboard Programming,

No External Programming Voltage Needed

Programmable Code Protection by

Security Fuse

Ultralow Power Consumption

-- Active Mode: 220 µA at 1 MHz, 2.2 V

-- Standby Mode: 0.5 µA

-- Off Mode (RAM Retention): 0.1 µA

Five Power-Saving Modes

Ultrafast Wake-Up From Standby Mode in

Less Than 1 µs

16-Bit RISC Architecture, 62.5 ns

Instruction Cycle Time

Basic Clock Module Configurations:

-- Internal Frequencies up to 16 MHz With

One Calibrated Frequency

-- Internal Very Low Power LF Oscillator

-- 32-kHz Crystal

-- External Digital Clock Source

On-Chip Emulation Logic With Spy-Bi-Wire

Interface

Family Members Details See Table 1

Available in a 14-Pin Plastic Small-Outline

Thin Package (TSSOP), 14-Pin Plastic Dual

Inline Package (PDIP), and 16-Pin QFN

For Complete Module Descriptions, See the

MSP430x2xx Family User’s Guide

16-Bit Timer_A With Two Capture/Compare

Registers

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code

efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less

than 1µs.

The MSP430G2x21/31 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and

ten I/O pins. The MSP430G2x31 family members have a 10-bit A/D converter and built-in communication

capability using synchronous protocols (SPI or I2C). For configuration details, see Table 1.

Typical applications include low-cost sensor systems that capture analog signals, convert themto digitalvalues,

and then process the data for display or for transmission to a host system.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Table 1. Available Options -- MSP430G2x21 and MSP430G2x31

Flash RAM

ADC10

Package

Type

BSL EEM

Timer_A

USI

CLOCK

I/O

Device

(KB)

(B)

Channel

MSP430G2231IRSA16

MSP430G2231IPW14

MSP430G2231IN14

16-QFN

14-TSSOP

14-PDIP

128

1x TA2

LF, DCO, VLO

MSP430G2221IRSA16

MSP430G2221IPW14

MSP430G2221IN14

16-QFN

14-TSSOP

14-PDIP

128

1x TA2

LF, DCO, VLO

MSP430G2131IRSA16

MSP430G2131IPW14

MSP430G2131IN14

16-QFN

14-TSSOP

14-PDIP

MSP430G2121IRSA16

MSP430G2121IPW14

MSP430G2121IN14

16-QFN

14-TSSOP

14-PDIP

†

‡

For the most current package and ordering information, see the Package Option Addendum at the end of this document,

or see the TI web site at www.ti.com.

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

device pinout, MSP430G2x21

DVSS

XIN/P2.6/TA0.1

XOUT/P2.7

TEST/SBWTCK

RST/NMI/SBWTDIO

P1.7/SDI/SDA/TDO/TDI

P1.6/TA0.1/SDO/SCL/TDI/TCLK

DVCC

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3

P1.4/SMCLK/TCK

N14

PW14

P1.5/TA0.0/SCLK/TMS

NOTE: See port schematics section for detailed I/O information.

16 15 14 13

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3

12 XIN/P2.6/TA0.1

11 XOUT/P2.7

10 TEST/SBWTCK

RST/NMI/SBWTDIO

RSA

NOTE: See port schematics section for detailed I/O information.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

device pinout, MSP430G2x31

DVSS

XIN/P2.6/TA0.1

XOUT/P2.7

TEST/SBWTCK

RST/NMI/SBWTDIO

P1.7/A7/SDI/SDA/TDO/TDI

P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK

DVCC

P1.0/TA0CLK/ACLK/A0

P1.1/TA0.0/A1

P1.2/TA0.1/A2

P1.3/ADC10CLK/A3/VREF-/VEREF-

P1.4/SMCLK/A4/VREF+/VEREF+/TCK

N14

PW14

P1.5/TA0.0/A5/SCLK/TMS

NOTE: See port schematics section for detailed I/O information.

16 15 14 13

P1.0/TA0CLK/ACLK/A0

P1.1/TA0.0/A1

P1.2/TA0.1/A2

P1.3/ADC10CLK/A3/VREF-/VEREF-

12 XIN/P2.6/TA0.1

11 XOUT/P2.7

10 TEST/SBWTCK

RST/NMI/SBWTDIO

RSA

NOTE: See port schematics section for detailed I/O information.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

functional block diagram, MSP430G2x21

XIN

XOUT

DVCC

DVSS

P1.x

P2.x

ACLK

SMCLK

Port P2

Port P1

Clock

System

Flash

RAM

128B

2 I/O

Interrupt

8 I/O

Interrupt

capability

pull-up/down

resistors

2KB

1KB

capability

pull-up/down

resistors

MCLK

16MHz

CPU

MAB

incl. 16

MDB

Registers

Emulation

2BP

USI

Watchdog Timer0_A2

Brownout

Protection

WDT+

2 CC

Universal

Serial

JTAG

Interface

15-Bit

Registers

Interface

SPI, I2C

Spy-Bi

Wire

RST/NMI

functional block diagram, MSP430G2x31

XIN

XOUT

DVCC

Flash

DVSS

P1.x

P2.x

ACLK

SMCLK

Port P2

Port P1

ADC

Clock

System

RAM

128B

2 I/O

Interrupt

8 I/O

Interrupt

capability

pull-up/down

resistors

10-Bit

8 Ch.

2kB

1kB

capability

pull-up/down

resistors

Autoscan

1 ch DMA

MCLK

16MHz

CPU

MAB

incl. 16

MDB

Registers

Emulation

2BP

USI

Watchdog Timer0_A2

Brownout

Protection

WDT+

2 CC

Universal

Serial

JTAG

Interface

15-Bit

Registers

Interface

SPI, I2C

Spy-Bi

Wire

RST/NMI

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Terminal Functions, MSP430G2x21 and MSP430G2x31

TERMINAL

DESCRIPTION

N, PW RSA

NAME

I/O

NO.

P1.0/

General-purpose digital I/O pin

Timer0_A, clock signal TACLK input

ACLK signal ouput

TA0CLK/

ACLK/

I/O

ADC10 analog input A0 (see Note 1)

P1.1/

TA0.0/

General-purpose digital I/O pin

I/O Timer0_A, capture: CCI0A input, compare: Out0 output

ADC10 analog input A1 (see Note 1)

P1.2/

TA0.1/

A2/

General-purpose digital I/O pin

I/O Timer0_A, capture: CCI1A input, compare: Out1 output

ADC10 analog input A2 (see Note 1)

P1.3/

ADC10CLK/

A3/

General-purpose digital I/O pin

ADC10, conversion clock output (see Note 1)

I/O

ADC10 analog input A3 (see Note 1)

ADC10 negative reference voltage (see Note 1)

VREF--/VEREF/

P1.4/

General-purpose digital I/O pin

SMCLK signal output

ADC10 analog input A4 (see Note 1)

ADC10 positive reference voltage (see Note 1)

JTAG test clock, input terminal for device programming and test

SMCLK/

A4/

I/O

VREF+/VEREF+/

TCK

P1.5/

TA0.0/

A5/

SCLK/

TMS

General-purpose digital I/O pin

Timer0_A, compare: Out0 output

ADC10 analog input A5 (see Note 1)

USI: clk input in I2C mode; clk in/output in SPI mode

JTAG test mode select, input terminal for device programming and test

P1.6/

TA0.1/

A6/

General-purpose digital I/O pin

Timer0_A, compare: Out1 output

ADC10 analog input A6 (see Note 1)

USI: Data output in SPI mode

USI: I2C clock in I2C mode

SDO/

SCL/

TDI/

I/O

JTAG test data input or test clock input during programming and test

TCLK

P1.7/

A7/

SDI/

SDA/

TDO/

TDI

General-purpose digital I/O pin

ADC10 analog input A7 (see Note 1)

USI: Data input in SPI mode

USI: I2C data in I2C mode

JTAG test data output terminal or test data input during programming and test

NOTES: 1. MSP430G2x31 only

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Terminal Functions, MSP430G2x21 and MSP430G2x31 (continued)

TERMINAL

N, PW RSA

DESCRIPTION

NAME

I/O

NO.

XIN/

P2.6/

TA0.1

Input terminal of crystal oscillator

I/O General-purpose digital I/O pin

Timer0_A, compare: Out1 output

XOUT/

P2.7

Output terminal of crystal oscillator (see Note 1)

General-purpose digital I/O pin

I/O

RST/

NMI/

SBWTDIO

Reset

Nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

TEST/

SBWTCK

Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST.

Spy-Bi-Wire test clock input during programming and test

DVCC

DVSS

NA Supply voltage

NA Ground reference

NA Not connected

QFN Pad

Pad

NA QFN package pad connection to V recommended.

NOTES: 1. If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver

connection to this pad after reset.

†

TDO or TDI is selected via JTAG instruction.

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

short-form description

CPU

Program Counter

Stack Pointer

PC/R0

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3

General-Purpose Register

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator respectively. The

remaining registers are general-purpose

registers.

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

R10

R11

instruction set

R12

R13

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 2 shows examples of the three types of

instruction formats; Table 3 shows the address

modes.

R14

R15

Table 2. Instruction Word Formats

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

e.g., ADD R4,R5

R4 + R5 ------> R5

e.g., CALL

e.g., JNE

PC ---->(TOS), R8----> PC

Jump-on-equal bit = 0

Table 3. Address Mode Descriptions

ADDRESS MODE

SYNTAX

EXAMPLE

MOV R10,R11

MOV 2(R5),6(R6)

OPERATION

MOV Rs,Rd

R10 ----> R11

Indexed

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM,&TCDAT

MOV @Rn,Y(Rm)

M(2+R5)----> M(6+R6)

M(EDE) ----> M(TONI)

M(MEM) ----> M(TCDAT)

M(R10) ----> M(Tab+R6)

Symbolic (PC relative)

Absolute

Indirect

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

Indirect

autoincrement

M(R10) ----> R11

R10 + 2----> R10

MOV @Rn+,Rm

Immediate

MOV #X,TONI

#45 ----> M(TONI)

NOTE: S = source

D = destination

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

operating modes

The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request, and restore back to

the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

Active mode (AM)

-- All clocks are active

Low-power mode 0 (LPM0)

-- CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

Low-power mode 1 (LPM1)

-- CPU is disabled

-- ACLK and SMCLK remain active. MCLK is disabled

-- DCO’s dc-generator is disabled if DCO not used in active mode

Low-power mode 2 (LPM2)

-- CPU is disabled

-- MCLK and SMCLK are disabled

-- DCO’s dc-generator remains enabled

-- ACLK remains active

Low-power mode 3 (LPM3)

-- CPU is disabled

-- MCLK and SMCLK are disabled

-- DCO’s dc-generator is disabled

-- ACLK remains active

Low-power mode 4 (LPM4)

-- CPU is disabled

-- ACLK is disabled

-- MCLK and SMCLK are disabled

-- DCO’s dc-generator is disabled

-- Crystal oscillator is stopped

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will

go into LPM4 immediately after power-up.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

External reset

PORIFG

RSTIFG

WDTIFG

KEYV

Watchdog Timer+

Reset

0FFFEh

31, highest

Flash key violation

PC out-of-range (see Note 1)

(see Note 2)

NMIIFG

OFIFG

NMI

(non)-maskable,

(non)-maskable

Oscillator fault

0FFFCh

ACCVIFG

Flash memory access violation

(see Notes 2 and 5)

0FFFAh

0FFF8h

0FFF6h

0FFF4h

0FFF2h

Watchdog Timer+

Timer_A2

WDTIFG

maskable

TACCR0 CCIFG (see Note 3)

TACCR1 CCIFG.

TAIFG (see Notes 2 and 3)

Timer_A2

maskable

0FFF0h

0FFEEh

0FFECh

0FFEAh

ADC10 (see Note 4)

USI

ADC10IFG (see Note 3 and 4)

maskable

USIIFG, USISTTIFG

(see Notes 2, 3)

0FFE8h

0FFE6h

0FFE4h

I/O Port P2

(two flags)

P2IFG.6 to P2IFG.7

(see Notes 2 and 3)

maskable

I/O Port P1

(eight flags)

P1IFG.0 to P1IFG.7

(see Notes 2 and 3)

0FFE2h

0FFE0h

(see Note 6)

0FFDEh ... 0FFC0h

15 ... 0, lowest

NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or

from within unused address ranges.

2. Multiple source flags

3. Interrupt flags are located in the module

4. MSP430G2x31 only.

5. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

6. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

notallocated to a functionalpurpose are notphysically presentin the device. Simple software access is provided

with this arrangement.

interrupt enable 1 and 2

Address

OFIE

WDTIE

ACCVIE

NMIIE

rw-0

WDTIE:

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer

is configured in interval timer mode.

OFIE:

NMIIE:

ACCVIE:

Oscillator fault enable

(Non)maskable interrupt enable

Flash access violation interrupt enable

Address

01h

interrupt flag register 1 and 2

Address

02h

NMIIFG

RSTIFG

PORIFG

OFIFG

WDTIFG

rw-0

rw-(0)

rw-1

rw-(0)

rw-(1)

WDTIFG:

Set on Watchdog Timer overflow (in watchdog mode) or security key violation.

Reset on V_CCpower-up or a reset condition at RST/NMI pin in reset mode.

Flag set on oscillator fault

OFIFG:

RSTIFG:

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V_CC

power-up

PORIFG:

NMIIFG:

Power-On Reset interrupt flag. Set on V_CCpower-up.

Set via RST/NMI-pin

Address

03h

Legend

rw:

Bit can be read and written.

Bit can be read and written. It is Reset or Set by PUC.

Bit can be read and written. It is Reset or Set by POR.

rw-0,1:

rw-(0,1):

SFR bit is not present in device

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

memory organization

MSP430G2021

MSP430G2031

MSP430G2121

MSP430G2131

MSP430G2221

MSP430G2231

Memory

Main: interrupt vector

Main: code memory

Size

Flash

512B

0xFFFF to 0xFFC0

0xFFFF to

1kB

0xFFFF to 0xFFC0

0xFFFF to

2kB

0xFFFF to 0xFFC0

0xFFFF to

0xFE00

0xFC00

0xF800

Information memory

RAM

Size

256 Byte

Flash

010FFh -- 01000h

Size

128B

027Fh -- 0200h

128B

027Fh -- 0200h

128B

027Fh -- 0200h

Peripherals

16-bit

8-bit

8-bit SFR

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

flash memory

The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can

perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

Segment A contains calibration data. After reset segment A is protected against programming and erasing.

It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data

is required.

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using

all instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide.

oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator

(DCO). The basic clock module is designed to meet the requirements of both low system cost and low power

consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic

clock module provides the following clock signals:

Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

DCO CALIBRATION DATA (PROVIDED FROM FACTORY IN FLASH INFO MEMORY

SEGMENT A)

DCO FREQUENCY

CALIBRATION

SIZE

ADDRESS

1 MHz

CALBC1_1MHZ

CALDCO_1MHZ

byte

010FFh

010FEh

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on

and power off.

digital I/O

There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt condition is possible.

Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.

Read/write access to port-control registers is supported by all instructions.

Each I/O has an individually programmable pull-up/pull-down resistor.

WDT+ watchdog timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be disabled or configured as an interval timer and can

generate interrupts at selected time intervals.

Timer_A2

Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A2 Signal Connections -- Device with ADC10

Input

Pin Number

Device

Input Signal

Module

Input Name

Module

Block

Module

Output Signal

Output

Pin Number

PW, N

RSA

PW, N

RSA

2 - P1.0

1 - P1.0

TACLK

ACLK

TACLK

ACLK

Timer

CCR0

CCR1

TA0

TA1

SMCLK

INCLK

CCI0A

CCI0B

GND

2 - P1.0

3 - P1.1

7 - P1.5

1 - P1.0

2 - P1.1

6 - P1.5

TACLK

TA0

3 - P1.1

7 - P1.5

2 - P1.1

6 - P1.5

ACLK (internal)

4 - P1.2

8 - P1.6

3 - P1.2

7 - P1.6

TA1

CCI1A

CCI1B

GND

4 - P1.2

8 - P1.6

13 - P2.6

3 - P1.2

7 - P1.6

12 - P2.6

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MIXED SIGNAL MICROCONTROLLER

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USI

The universal serial interface (USI) module is used for serial data communication and provides the basic

hardware for synchronous communication protocols like SPI and I2C.

ADC10 (MSP430G2x31 only)

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion

result handling, allowing ADC samples to be converted and stored without any CPU intervention.

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peripheral file map

PERIPHERALS WITH WORD ACCESS

ADC10

(MSP430G2x31 only)

ADC control 0

ADC control 1

ADC memory

ADC10CTL0

ADC10MEM

01B0h

01B2h

01B4h

Timer_A

Capture/compare register

Timer_A register

TACCR1

TACCR0

TAR

TACCTL1

TACCTL0

TACTL

TAIV

0174h

0172h

0170h

0164h

0162h

0160h

012Eh

Capture/compare control

Timer_A control

Timer_A interrupt vector

Flash Memory

Flash control 3

Flash control 2

Flash control 1

FCTL3

FCTL2

FCTL1

012Ch

012Ah

0128h

Watchdog Timer+

Watchdog/timer control

WDTCTL

0120h

PERIPHERALS WITH BYTE ACCESS

Analog enable

ADC10

(MSP430G2x31 only)

ADC10AE

04Ah

USI

USI control 0

USICTL0

USICTL1

USICKCTL

USICNT

USISR

078h

079h

07Ah

07Bh

07Ch

USI control 1

USI clock control

USI bit counter

USI shift register

Basic Clock System+

Port P2

Basic clock system control 3

Basic clock system control 2

Basic clock system control 1

DCO clock frequency control

BCSCTL3

BCSCTL2

BCSCTL1

DCOCTL

053h

058h

057h

056h

Port P2 resistor enable

Port P2 selection

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

Port P2 direction

P2REN

P2SEL

P2IE

P2IES

P2IFG

P2DIR

P2OUT

P2IN

02Fh

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

Port P2 output

Port P2 input

Port P1

Port P1 resistor enable

Port P1 selection

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

P1REN

P1SEL

P1IE

P1IES

P1IFG

P1DIR

P1OUT

P1IN

027h

026h

025h

024h

023h

022h

021h

020h

Port P1 output

Port P1 input

Special Function

SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

IFG2

IFG1

IE2

003h

002h

001h

000h

IE1

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

absolute maximum ratings^†

Voltage applied at V_CCto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V

Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to V_CC+0.3 V

Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA

Storage temperature, T_stg(unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C

Storage temperature, T_stg(programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 85°C

NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended

operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

2. All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage

is applied to the TEST pin when blowing the JTAG fuse.

3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with

peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

recommended operating conditions

MIN

1.8

NOM

MAX

3.6

UNIT

Supply voltage during program execution, V

Supply voltage during program/erase flash memory, V

2.2

3.6

Supply voltage, V

Operating free-air temperature range, T

I Version

= 1.8 V,

-- 4 0

°C

4.15

Duty Cycle = 50% ±10%

= 2.7 V,

Processor frequency f

(Maximum MCLK frequency)

MHz

SYSTEM

Duty Cycle = 50% ±10%

≥ 3.3 V,

Duty Cycle = 50% ±10%

NOTES: 1. The MSP430 CPU is clocked directly with MCLK.

Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.

2. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Legend:

16 MHz

Supply voltage range,

during flash memory

programming

12 MHz

Supply voltage range,

during program execution

7.5 MHz

4.15 MHz

1.8 V

2.2 V

2.7 V

3.3 V 3.6 V

Supply Voltage --V

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V of 2.2 V.

Figure 1. Save Operating Area

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MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

active mode supply current (into V_CC) excluding external current (see Notes 1 and 2)

PARAMETER

TEST CONDITIONS

= f = f = 1MHz,

MCLK

MIN

TYP

MAX UNIT

DCO

SMCLK

= 32,768Hz,

2.2 V

3 V

220

ACLK

Program executes in flash,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

Active mode (AM)

current (1MHz)

µA

AM, 1MHz

300

370

NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.

2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.

The internal and external load capacitance is chosen to closely match the required 9pF.

typical characteristics -- active mode supply current (into V_CC

)

5.0

4.0

3.0

2.0

1.0

0.0

4.0

3.0

2.0

1.0

0.0

= 16 MHz

DCO

= 85 °C

= 25 °C

= 3 V

= 12 MHz

DCO

= 85 °C

= 25 °C

= 8 MHz

DCO

= 1 MHz

= 2.2 V

DCO

1.5

2.0

2.5

3.0

3.5

4.0

0.0

4.0

8.0

12.0

16.0

-- Supply Voltage -- V

DCO

-- DCO Frequency -- MHz

Figure 2. Active mode current vs V_CC, T_A= 25°C

Figure 3. Active mode current vs DCO frequency

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MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

low-power mode supply currents (into V_CC) excluding external current (see Notes 1 and 2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

= 0 MHz,

SMCLK

MCLK

= f

= 1 MHz,

DCO

= 32,768 Hz,

Low-power mode 0

(LPM0) current,

see Note 3

ACLK

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

25°C

2.2 V

µA

LPM0, 1MHz

= f

= 0 MHz,

SMCLK

MCLK

DCO

ACLK

= 1 MHz,

= 32,768 Hz,

Low-power mode 2

(LPM2) current,

see Note 4

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 1,

OSCOFF = 0

µA

LPM2

= f

ACLK

= f

= 0 MHz,

SMCLK

DCO

MCLK

= 32,768 Hz,

Low-power mode 3

(LPM3) current,

see Note 4

25°C

2.2 V

0.7

0.5

1.5

0.7

µA

LPM3,LFXT1

LPM3,VLO

LPM4

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

= f

= 0 MHz,

SMCLK

DCO

MCLK

Low-power mode 3

current, (LPM3)

see Note 4

from internal LF oscillator (VLO),

ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

= f

= 0MHz,

SMCLK

DCO

MCLK

25°C

85°C

2.2 V

0.1

0.8

1.5

µA

Low-power mode 4

(LPM4) current,

see Note 5

= 0 Hz,

ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 1

NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.

2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.

3. Current for brownout and WDT clocked by SMCLK included.

4. Current for brownout and WDT clocked by ACLK included.

5. Current for brownout included.

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical characteristics -- LPM3 current

10.0

9.0

8.0

7.0

6.0

5.0

Vcc = 3.6 V

4.0

Vcc = 3 V

3.0

Vcc = 2.2V

2.0

1.0

Vcc = 1.8 V

0.0

--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0

-- Temperature -- °C

typical characteristics -- LPM4 current

10.0

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

Vcc = 3.6 V

Vcc = 3 V

Vcc = 2.2V

Vcc = 1.8 V

--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0

-- Temperature -- °C

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs -- Ports Px

PARAMETER

TEST CONDITIONS

MIN

0.45

1.35

0.25

0.75

TYP

MAX UNIT

0.75

2.25

0.55

1.65

Positive-going input threshold

voltage

IT+

3 V

Negative-going input threshold

voltage

IT--

3 V

Input voltage hysteresis (V

IT+

0.3

1.0

hys

)

IT--

For pullup: V = V

;

Pull-up/pull-down resistor

Input Capacitance

kΩ

Pull

For pulldown: V = V

= V or V

NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t

is met. It may be set even with trigger signals

(int)

shorter than t

(int)

leakage current -- Ports Px

PARAMETER

TEST CONDITIONS

see Notes 1 and 2

NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.

MIN

TYP

MAX UNIT

±50 nA

High-impedance leakage current

3 V

lkg(Px.x)

2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is

disabled.

outputs -- Ports Px

PARAMETER

TEST CONDITIONS

MIN

TYP

-- 0 . 3

UNIT

High-level output voltage

Low-level output voltage

= --6 mA (see Notes 2)

= 6 mA (see Notes 2)

3 V

(OHmax)

(OLmax)

+0.3

NOTES: 1. The maximum total current, I

voltage drop specified.

and I

, for all outputs combined, should not exceed ±12 mA to hold the maximum

OHmax

OLmax

2. The maximum total current, I

voltage drop specified.

and I

, for all outputs combined, should not exceed ±48 mA to hold the maximum

OLmax

output frequency -- Ports Px

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Port output frequency

Px.y, C = 20 pF, R = 1 kOhm

3 V

MHz

Px.y

(with load)

(see Note 1 and 2)

Px.y, C = 20 pF

Clock output frequency

MHz

Port_CLK

(see Note 2)

NOTES: 1. A resistive divider with 2 times 0.5 kΩ between V and V is used as load. The output is connected to the center tap of the divider.

2. The output voltage reaches at least 10% and 90% V at the specified toggle frequency.

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MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical characteristics -- outputs

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

30.0

25.0

20.0

15.0

10.0

5.0

50.0

40.0

30.0

20.0

10.0

0.0

= 2.2 V

P1.7

= 3 V

P1.7

= 25°C

= 85°C

= 25°C

= 85°C

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-- Low-Level Output Voltage -- V

Figure 4

Figure 5

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

0.0

--10.0

--20.0

--30.0

--40.0

--50.0

0.0

-- 5 . 0

= 3 V

= 2.2 V

P1.7

--10.0

--15.0

--20.0

--25.0

= 85°C

= 25°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

-- High-Level Output Voltage -- V

Figure 6

Figure 7

NOTE: One output loaded at a time.

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MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

POR/brownout reset (BOR) (see Notes 1 and 2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(see Figure 8)

dV /dt ≤ 3 V/s

0.7 × V

(B_IT--)

CC(start)

(see Figure 8 through Figure 10)

(see Figure 8)

dV /dt ≤ 3 V/s

1.35

140

(B_IT--)

hys(B_IT--)

d(BOR)

dV /dt ≤ 3 V/s

µs

(see Figure 8)

2000

Pulse length needed at RST/NMI pin

to accepted reset internally

2.2 V/3 V

µs

(reset)

NOTES: 1. The current consumption of the brownout module is already included in the I current consumption data. The voltage level V

(B_IT--)

+ V

is ≤ 1.8V.

hys(B_IT--)

2. During power up, the CPU begins code execution following a period of t

after V = V

+ V

. The default

hys(B_IT--)

d(BOR)

(B_IT--)

DCO settings must not be changed until V ≥ V

, where V

is the minimum supply voltage for the desired

CC(min)

operating frequency.

hys(B_IT--)

(B_IT--)

CC(start)

d(BOR)

Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage

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MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

typical characteristics -- POR/brownout reset (BOR)

3 V

= 3 V

Typical Conditions

1.5

CC(drop)

0.5

0.001

1000

1 ns

-- Pulse Width -- µs

Figure 9. V_CC(drop)Level With a Square Voltage Drop to Generate a POR/Brownout Signal

1.5

3 V

= 3 V

Typical Conditions

CC(drop)

0.5

t = t

0.001

1000

-- Pulse Width -- µs

Figure 10. V_CC(drop)Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

main DCO characteristics

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

DCO control bits DCOx have a step size as defined by parameter S_DCO.

Modulation control bits MODx select how often f_{DCO(RSEL,DCO+1)}is used within the period of 32 DCOCLK

cycles. The frequency f_{DCO(RSEL,DCO)}is used for the remaining cycles. The frequency is an average equal

to:

32 × f_{DCO(RSEL,DCO)}× f_{DCO(RSEL,DCO+1)}

MOD × f_{DCO(RSEL,DCO)}+(32−MOD) × f_{DCO(RSEL,DCO+1)}

f_average

DCO frequency

PARAMETER

TEST CONDITIONS

MIN

1.8

TYP MAX UNIT

RSELx < 14

3.6

RSELx = 14

RSELx = 15

2.2

Vcc

Supply voltage range

3.0

DCO frequency (0, 0)

DCO frequency (0, 3)

DCO frequency (1, 3)

DCO frequency (2, 3)

DCO frequency (3, 3)

DCO frequency (4, 3)

DCO frequency (5, 3)

DCO frequency (6, 3)

DCO frequency (7, 3)

DCO frequency (8, 3)

DCO frequency (9, 3)

DCO frequency (10, 3)

DCO frequency (11, 3)

DCO frequency (12, 3)

DCO frequency (13, 3)

DCO frequency (14, 3)

DCO frequency (15, 3)

DCO frequency (15, 7)

RSELx = 0, DCOx = 0, MODx = 0

RSELx = 0, DCOx = 3, MODx = 0

RSELx = 1, DCOx = 3, MODx = 0

RSELx = 2, DCOx = 3, MODx = 0

RSELx = 3, DCOx = 3, MODx = 0

RSELx = 4, DCOx = 3, MODx = 0

RSELx = 5, DCOx = 3, MODx = 0

RSELx = 6, DCOx = 3, MODx = 0

RSELx = 7, DCOx = 3, MODx = 0

RSELx = 8, DCOx = 3, MODx = 0

RSELx = 9, DCOx = 3, MODx = 0

RSELx = 10, DCOx = 3, MODx = 0

RSELx = 11, DCOx = 3, MODx = 0

RSELx = 12, DCOx = 3, MODx = 0

RSELx = 13, DCOx = 3, MODx = 0

RSELx = 14, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 7, MODx = 0

3 V

0.06

0.14 MHz

MHz

DCO(0,0)

DCO(0,3)

DCO(1,3)

DCO(2,3)

DCO(3,3)

DCO(4,3)

DCO(5,3)

DCO(6,3)

DCO(7,3)

DCO(8,3)

DCO(9,3)

DCO(10,3)

DCO(11,3)

DCO(12,3)

DCO(13,3)

DCO(14,3)

DCO(15,3)

DCO(15,7)

0.12

0.15

0.21

0.30

0.41

0.58

0.80

MHz

0.80

1.50 MHz

MHz

1.60

2.30

3.40

4.25

MHz

4.30

8.60

7.30 MHz

MHz

7.80

13.9 MHz

MHz

15.25

21.00

MHz

Frequency step between

range RSEL and RSEL+1

= f /f

DCO(RSEL+1,DCO) DCO(RSEL,DCO)

3 V

1.35

RSEL

DCO

RSEL

DCO

ratio

Frequency step between

tap DCO and DCO+1

= f

3 V

1.08

DCO(RSEL,DCO+1) DCO(RSEL,DCO)

Duty Cycle

Measured at SMCLK output

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

calibrated DCO frequencies -- tolerance

PARAMETER

TEST CONDITIONS

MIN

-- 3

TYP

MAX UNIT

BCSCTL1= CALBC1_1MHz

DCOCTL = CALDCO_1MHz

calibrated at 30°C and 3.0V

1 MHz tolerance over temperature

(see Note 1)

0°C to 85°C

30°C

3.0 V

±0.5

BCSCTL1= CALBC1_1MHz

DCOCTL = CALDCO_1MHz

calibrated at 30°C and 3.0V

1 MHz tolerance over V

1.8 V -- 3.6 V

-- 3

-- 6

±2

±3

BCSCTL1= CALBC1_1MHz

DCOCTL = CALDCO_1MHz

calibrated at 30°C and 3.0V

-- 4 0 °C to

85°C

1 MHz tolerance overall

NOTES: 1. This is the frequency change from the measured frequency at 30°C over temperature.

wake-up from low-power modes (LPM3/4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DCO clock wake-up time from

LPM3/4

BCSCTL1= CALBC1_1MHz

DCOCTL = CALDCO_1MHz

3 V

1.5

µs

DCO,LPM3/4

CPU,LPM3/4

(see Note 1)

CPU wake-up time from LPM3/4

(see Note 2)

1/f

MCLK

Clock,LPM3/4

NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g. port interrupt) to the first clock edge

observable externally on a clock pin (MCLK or SMCLK).

2. Parameter applicable only if DCOCLK is used for MCLK.

typical characteristics -- DCO clock wake-up time from LPM3/4

10.00

RSELx = 0...11

1.00

RSELx = 12...15

0.10

1.00

DCO Frequency -- MHz

10.00

Figure 11. DCO wake-up time from LPM3 vs DCO frequency

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

crystal oscillator, LFXT1, low frequency modes (see Note 4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LFXT1 oscillator crystal

frequency, LF mode 0, 1

XTS = 0, LFXT1Sx = 0 or 1

1.8 V to 3.6 V

32768

LFXT1,LF

LFXT1 oscillator logic level

square wave input frequency,

LF mode

XTS = 0, XCAPx = 0,

LFXT1Sx = 3

1.8 V to 3.6 V

10000

32768

500

50000

LFXT1,LF,logic

XTS = 0, LFXT1Sx = 0,

= 32,768 kHz,

LFXT1,LF

L,eff

= 6 pF

Oscillation allowance for

LF crystals

kΩ

XTS = 0, LFXT1Sx = 0,

= 32,768 kHz,

200

LFXT1,LF

L,eff

= 12 pF

XTS = 0, XCAPx = 0

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

5.5

8.5

Integrated effective load

capacitance, LF mode

(see Note )

L,eff

XTS = 0,

Duty cycle

LF mode

Measured at P2.0/ACLK,

2.2 V

= 32,768Hz

LFXT1,LF

Oscillator fault frequency,

LF mode (see Note 3)

XTS = 0, XCAPx = 0.

LFXT1Sx = 3 (see Note 2)

10000

Fault,LF

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup the effective load capacitance should always match the specification of the used crystal.

2. Measured with logic level input frequency but also applies to operation with crystals.

3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and

frequencies in between might set the flag.

4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.

-- Keep the trace between the device and the crystal as short as possible.

-- Design a good ground plane around the oscillator pins.

-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other

documentation. This signal is no longer required for the serial programming adapter.

internal very low power, low frequency oscillator (VLO)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VLO frequency

-40 -- 85°C

3.0 V

kHz

VLO

VLO frequency

temperature drift

/dT

/dV

-40 -- 85°C

3.0 V

0.5

%/°C

VLO

VLO frequency supply

voltage drift

25°C

1.8 V -- 3.6 V

%/V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

Timer_A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK;

External: TACLK, INCLK;

Duty Cycle = 50% ±10%

Timer_A clock frequency

Timer_A, capture timing

MHz

SYSTEM

TA0, TA1

3.0 V

TA,cap

USI, Universal Serial Interface

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

External: SCLK;

Duty Cycle = 50% ±10%;

SPI Slave Mode

USI clock frequency

MHz

USI

SYSTEM

Low-level output voltage on SDA

and SCL

USI module in I2C mode

(OLmax)

3.0 V

V +0.4

OL,I2C

= 1.5 mA

typical characteristics -- USI low-level output voltage on SDA and SCL

5.0

4.0

3.0

2.0

1.0

0.0

5.0

4.0

3.0

2.0

1.0

0.0

T = 25°C

= 2.2 V

= 3 V

= 25°C

= 85°C

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

-- Low-Level Output Voltage -- V

Figure 12. USI Low-Level Output Voltage vs.

Output Current

Figure 13. USI Low-Level Output Voltage vs.

Output Current

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, power supply and input range conditions -- MSP430G2x31 only

PARAMETER

TEST CONDITIONS

MIN

2.2

TYP

MAX UNIT

Analog supply voltage

range

= 0 V

3.6

All Ax terminals.

Analog inputs selected in

ADC10AE register.

Analog input voltage range

(see Note 2)

3 V

= 5.0 MHz

ADC10CLK

ADC10ON = 1, REFON = 0

ADC10SHT0 = 1,

ADC10 supply current

(see Note 3)

25°C

0.6

ADC10

ADC10SHT1 = 0, ADC10DIV

= 0

= 5.0 MHz

ADC10CLK

ADC10ON = 0, REF2_5V = 0,

REFON = 1, REFOUT = 0

25°C

Reference supply current,

reference buffer disabled

(see Note 4)

3 V

0.25

1.1

REF+

= 5.0 MHz

ADC10CLK

ADC10ON = 0, REF2_5V = 1,

REFON = 1, REFOUT = 0

= 5.0 MHz

ADC10CLK

ADC10ON = 0,

Reference buffer supply

current with ADC10SR=0

(see Note 4)

REFON = 1, REF2_5V = 0,

REFOUT = 1,

ADC10SR=0

25°C

REFB,0

REFB,1

= 5.0 MHz

ADC10CLK

ADC10ON = 0,

REFON = 1,

Reference buffer supply

current with ADC10SR=1

(see Note 4)

0.5

REF2_5V = 0,

REFOUT = 1,

ADC10SR=1

Only one terminal Ax selected

at a time

Input capacitance

25°C

3 V

Input MUX ON resistance

0V ≤ V ≤ V

1000

Ω

NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.

2. The analog input voltage range must be within the selected reference voltage range V to V for valid conversion results.

R+

R--

3. The internal reference supply current is not included in current consumption parameter I

ADC10

4. The internal reference current is supplied via terminal V . Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, built-in voltage reference -- MSP430G2x31 only

PARAMETER

TEST CONDITIONS

≤ 1mA, REF2_5V=0

≤ 1mA, REF2_5V=1

MIN TYP

MAX UNIT

2.2

2.9

VREF+

Positive built-in reference analog

supply voltage range

CC,REF+

≤ I

max, REF2_5V = 0

VREF+

max, REF2_5V = 1

VREF+

3 V

1.41

2.35

1.5

2.5

1.59

2.65

±1

Positive built-in reference voltage

REF+

Maximum V

load current

REF+

LD,VREF+

= 500 µA +/-- 100 µA

VREF+

Analog input voltage V ≈ 0.75 V;

3 V

±2

LSB

REF2_5V = 0

load regulation

REF+

= 500 µA ± 100 µA

VREF+

Analog input voltage V ≈ 1.25 V;

REF2_5V = 1

VREF+

100µA→900µA,

≈ 0.5 x V

load regulation response time

ADC10SR = 0

3 V

400

100

REF+

Error of conversion

result ≤ 1 LSB

≤ ±1mA,

VREF+

Max. capacitance at pin V

Temperature coefficient

3 V

REF+

REFON = 1, REFOUT = 1

= const. with

VREF+

±100 ppm/°C

REF+

0 mA ≤ I

≤ 1 mA

Settling time of internal reference

voltage to 99.9% VREF

= 0.5 mA, REF2_5V=0

VREF+

3.6 V

3 V

µs

REFON

REFON = 0 → 1,

= 0.5 mA,

VREF+

Settling time of reference buffer to

99.9% VREF

REF2_5V=1,

REFON = 1,

ADC10SR = 0

REFBURST

REFBURST = 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, external reference -- MSP430G2x31 only

PARAMETER

TEST CONDITIONS

MIN

1.4

TYP

MAX UNIT

VEREF > VEREF

SREF1 = 1, SREF0 = 0

Positive external reference input

voltage range (see Note 2)

VEREF

VEREF ≤ VEREF ≤ V -- 0.15V

1.4

3.0

1.2

SREF1 = 1, SREF0 = 1 (see Note 3)

Negative external reference input

voltage range (see Note 4)

VEREF > VEREF

Differential external reference input

voltage range

∆VEREF

VEREF > VEREF (see Note 5)

1.4

∆VEREF = VEREF -- VEREF

0V ≤ VEREF ≤ V

3 V

±1

µA

SREF1 = 1, SREF0 = 0

Static input current into VEREF

VEREF+

VEREF--

0V ≤VEREF ≤ V -- 0.15V ≤ 3V

3 V

µA

SREF1 = 1, SREF0 = 1 (see Note 3)

0V ≤ VEREF ≤ V

±1

NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer

supply current I

. The current consumption can be limited to the sample and conversion period with REBURST = 1.

REFB

4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied

with reduced accuracy requirements.

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, timing parameters -- MSP430G2x31 only

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

For specified

ADC10SR = 0

ADC10SR = 1

3 V

0.45

6.3

MHz

1.5

performance of

ADC10 linearity

parameters

ADC10 input clock frequency

ADC10CLK

ADC10OSC

0.45

3.7

ADC10DIVx=0, ADC10SSELx = 0

= f

ADC10 built-in oscillator frequency

6.3 MHz

ADC10CLK

ADC10OSC

ADC10 built-in oscillator,

ADC10SSELx = 0

3 V

2.06

3.51

µs

= f

ADC10CLK

ADC10OSC

Conversion time

CONVERT

ADC10ON

13×

from ACLK, MCLK or

ADC10CLK

SMCLK: ADC10SSELx ≠ 0

ADC10DIV×

µs

1/f

ADC10CLK

Turn on settling time of the ADC

(see Note 1)

100

NOTES: 1. The condition is that the error in a conversion started after t

settled.

is less than ±0.5 LSB. The reference and input signal are already

ADC10ON

10-bit ADC, linearity parameters -- MSP430G2x31 only

PARAMETER

Integral linearity error

Differential linearity error

Offset error

TEST CONDITIONS

MIN

TYP

MAX UNIT

±1 LSB

±2 LSB

±5 LSB

3 V

Source impedance R < 100 Ω,

±1.1

±2

Gain error

Total unadjusted error

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

10-bit ADC, temperature sensor and built-in V_MID-- MSP430G2x31 only

PARAMETER

TEST CONDITIONS

MIN

TYP

3.55

MAX

UNIT

Temperature sensor supply

current (see Note 1)

REFON = 0, INCHx = 0Ah,

3 V

µA

SENSOR

= 25_C

ADC10ON = 1, INCHx = 0Ah

(see Note 2)

mV/°C

µs

SENSOR

Sensor(sample)

VMID

Sample time required if

channel 10 is selected (see

Note 4)

ADC10ON = 1, INCHx = 0Ah,

Error of conversion result ≤ 1 LSB

3 V

Current into divider at channel

11 (see Note 5)

ADC10ON = 1, INCHx = 0Bh,

3 V

µA

divider at channel 11

1.5

MID

is ≈0.5 x V

MID

Sample time required if

channel 11 is selected

(see Note 6)

ADC10ON = 1, INCHx = 0Bh,

Error of conversion result ≤ 1 LSB

3 V

1220

VMID(sample)

NOTES: 1. The sensor current I

is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal

SENSOR

is high). When REFON = 1, I

sensor input (INCH = 0Ah).

2. The following formula can be used to calculate the temperature sensor output voltage:

is included in I

. When REFON = 0, I

applies during conversion of the temperature

SENSOR

REF+

SENSOR

= TC

( 273 + T [°C] ) + V

[mV] or

Sensor,typ

Sensor

Offset,sensor

(T = 0°C) [mV]

T [°C] + V

Sensor

3. Values are not based on calculations using TC

or V

but on measurements.

Offset,sensor

Sensor

4. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t

SENSOR(on)

5. No additional current is needed. The V

is used during sampling.

MID

6. The on-time t

is included in the sampling time t

; no additional on time is needed.

VMID(on)

VMID(sample)

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

flash memory

PARAMETER

TEST CONDITIONS

MIN

2.2

TYP

MAX UNIT

CC(PGM/

ERASE)

Program and Erase supply voltage

Flash Timing Generator frequency

3.6

257

476

kHz

FTG

Supply current from V during program

2.2 V/3.6 V

PGM

Supply current from V during erase

ERASE

CPT

Cumulative program time (see Note 1)

Cumulative mass erase time

Program/Erase endurance

Data retention duration

CMErase

cycles

years

T = 25°C

100

Retention

Word or byte program time

Word

Block program time for 1 byte or word

Block, 0

Block program time for each additional byte or word

Block program end-sequence wait time

Mass erase time

Block, 1-63

Block, End

Mass Erase

Seg Erase

see Note 2

FTG

10593

4819

Segment erase time

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. These values are hardwired into the Flash Controller’s state machine (t

= 1/f

FTG

RAM

PARAMETER

TEST CONDITIONS

CPU halted

MIN

TYP

MAX UNIT

RAM retention supply voltage (see Note 1)

1.6

(RAMh)

NOTE 1: This parameter defines the minimum supply voltage V when the data in RAM remains unchanged. No program execution should

happen during this supply voltage condition.

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

JTAG and Spy-Bi-Wire interface

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

Spy-Bi-Wire input frequency

2.2 V / 3 V

MHz

SBW

Spy-Bi-Wire low clock pulse length

0.025

SBW,Low

Spy-Bi-Wire enable time

(TEST high to acceptance of first clock edge, see

Note 1)

2.2 V/ 3 V

SBW,En

Spy-Bi-Wire return to normal operation time

2.2 V/ 3 V

2.2 V

100

SBW,Ret

TCK

MHz

kΩ

TCK input frequency -- 4-wire JTAG (see Note 2)

Internal pull-down resistance on TEST

3 V

2.2 V/ 3 V

Internal

NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t

before applying the first SBWTCK clock edge.

time after pulling the TEST/SBWTCK pin high

SBW,En

may be restricted to meet the timing requirements of the module selected.

TCK

JTAG fuse (see Note 1)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

Supply voltage during fuse-blow condition

Voltage level on TEST for fuse-blow

Supply current into TEST during fuse blow

Time to blow fuse

= 25°C

2.5

CC(FB)

100

NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched

to bypass mode.

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

APPLICATION INFORMATION

Port P1 pin schematic: P1.0 -- P1.3, input/output with Schmitt trigger -- MSP430G2x21

PxSEL.y

PxDIR.y

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

PxSEL.y

PxOUT.y

From Timer

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

Port P1 (P1.0 to P1.3) pin functions -- MSP430G2x21

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

P1DIR.x

P1SEL.x

P1.0/

P1.x (I/O)

TA0.TACLK

ACLK

I: 0; O: 1

TA0CLK/

ACLK/

P1.1/

P1.x (I/O)

TA0.0

I: 0; O: 1

TA0.0/

TA0.CCI0A

P1.x (I/O)

TA0.1

P1.2/

I: 0; O: 1

TA0.1/

TA0.CCI1A

P1.x (I/O)

P1.3/

I: 0; O: 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.0 -- P1.3, input/output with Schmitt trigger -- MSP430G2x21

PxSEL.y

PxDIR.y

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

PxSEL.y

PxOUT.y

From Module

P1.4/SMCLK/TCK

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

From JTAG

To JTAG

Port P1 (P1.4) pin functions -- MSP430G2x21

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

JTAG

Mode

P1DIR.x

P1SEL.x

P1.4/

P1.x (I/O)

SMCLK

TCK

I: 0; O: 1

SMCLK/

TCK

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

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SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.5, input/output with Schmitt trigger -- MSP430G2x21

PxSEL.y

PxDIR.y

From USI

Direction

0: Input

1: Output

PxREN.y

PxSEL.y or

USIPE5

DV_SS

DV_CC

PxOUT.y

From USI

P1.5/TA0.0/SCLK/TMS

PxSEL.y

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

From JTAG

To JTAG

Port P1 (P1.5) pin functions -- MSP430G2x21

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

JTAG

Mode

P1DIR.x

P1SEL.x

USIP.x

P1.5/

P1.x (I/O)

TA0.0

I: 0; O: 1

TA0.0/

SCLK/

SIMO0/

TMS

SCLK

SIMO0

TMS

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.6, input/output with Schmitt trigger -- MSP430G2x21

PxSEL.y

PxDIR.y

Direction

0: Input

1: Output

PxREN.y

PxSEL.y or

USIPE6

DV_SS

DV_CC

PxOUT.y

From Module

P1.6/TA0.1/SDO/SCL/TDI

PxSEL.y

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

From JTAG

To JTAG

Port P1 (P1.6) pin functions -- MSP430G2x21

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

JTAG

Mode

P1DIR.x

P1SEL.x

USIP.x

P1.6/

P1.x (I/O)

TA0.1

I: 0; O: 1

TA0.1/

SDO/

SDO

TDI/TCLK

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MSP430G2x21, MSP430G2x31

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SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.7, input/output with Schmitt trigger -- MSP430G2x21

USIPE7

PxDIR.y

From USI

Direction

0: Input

1: Output

PxREN.y

PxSEL.y or

USIPE7

DV_SS

DV_CC

PxOUT.y

From USI

P1.7/SDI/SDA/TDO/TDI

PxSEL.y

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

From JTAG

To JTAG

From JTAG

To JTAG

Port P1 (P1.7) pin functions -- MSP430G2x21

P1.7/

P1.x (I/O)

SDI/SDO

TDO/TDI

I: 0; O: 1

SDI/SDO

TDO/TDI

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.0 -- P1.2, input/output with Schmitt trigger -- MSP430G2x31

To ADC10

INCHx

PxSEL.y

PxDIR.y

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

PxSEL.y

PxOUT.y

ACLK

P1.0/TA0CLK/ACLK/A0

P1.1/TA0.0/A1

Bus

Keeper

P1.2/TA0.1/A2

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 (P1.0 to P1.2) pin functions -- MSP430G2x31

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

ADC10AE.x

(INCH.y = 1)

P1DIR.x

P1SEL.x

P1.0/

P1.x (I/O)

TA0.TACLK

ACLK

I: 0; O: 1

TA0CLK/

ACLK/

A0/

1 (y = 0)

P1.1/

P1.x (I/O)

TA0.0

I: 0; O: 1

TA0.0/

TA0.CCI0A

A1/

1 (y = 1)

P1.2/

TA0.1/

P1.x (I/O)

TA0.1

I: 0; O: 1

TA0.CCI1A

A2/

1 (y = 2)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.3, input/output with Schmitt trigger -- MSP430G2x31

SREF2

VSS

To ADC10 VREF-

To ADC10

INCHx = y

ADC10AE0.y

PxDIR.y

PxSEL.y

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

PxSEL.y

PxOUT.y

ACLK

P1.3/ADC10CLK/A3/VREF-/VEREF-

Bus

Keeper

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

Port P1 (P1.3) pin functions -- MSP430G2x31

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

ADC10AE.x

(INCH.x = 1)

P1DIR.x

P1SEL.x

CAPD.y

P1.3/

P1.x (I/O)

ADC10CLK

I: 0; O: 1

ADC10CLK/

1 (y = 3)

VREF--/

VEREF--

CA3

VREF--

VEREF--

CA3

1 (y = 3)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.4, input/output with Schmitt trigger -- MSP430G2x31

To ADC10 VREF+

To ADC10

INCHx = y

ADC10AE0.y

PxSEL.y

PxDIR.y

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

PxSEL.y

PxOUT.y

ACLK

Bus

Keeper

P1.4/SMCLK/A4/VREF+/VEREF+/TCK

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

From JTAG

To JTAG

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 (P1.4) pin functions -- MSP430G2x31

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

ADC10AE.x

(INCH.x = 1)

JTAG

Mode

P1DIR.x

P1SEL.x

P1.4/

P1.x (I/O)

SMCLK

I: 0; O: 1

SMCLK/

A4/

1 (y = 4)

VREF+/

VEREF+/

CA4/

VREF+

VEREF+

CA4

TCK

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.5, input/output with Schmitt trigger -- MSP430G2x31

To ADC10

INCHx

ADC10EA.y

PxSEL.y

PxDIR.y

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

PxSEL.y

PxOUT.y

From Module

Bus

Keeper

P1.5/TA0.0/A5/TMS

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

From JTAG

To JTAG

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 (P1.5) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

ADC10AE.x

(INCH.x = 1)

JTAG

Mode

P1DIR.x

P1SEL.x

USIP.x

P1.5/

P1.x (I/O)

TA0.0

I: 0; O: 1

TA0.0/

A5/

1 (y = 5)

SCLK/

SIMO0/

TMS

SCLK

SIMO0

TMS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.6, input/output with Schmitt trigger -- MSP430G2x31

To ADC10

INCHx

ADC10EA.y

USIPE6

PxDIR.y

from USI

Direction

0: Input

1: Output

PxREN.y

PxSEL.y or

USIPE6

DV_SS

DV_CC

PxOUT.y

From USI

Bus

Keeper

P1.6/TA0.1/SDO/SCL/A6/TDI

PxSEL.y

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

From JTAG

To JTAG

USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 (P1.6) pin functions

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

ADC10AE.x

(INCH.x = 1)

JTAG

Mode

P1DIR.x

P1SEL.x

USIP.x

P1.6/

P1.x (I/O)

TA0.1

I: 0; O: 1

TA0.1/

A6/

1 (y = 6)

SDO/

SDO

TDI/TCLK

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 pin schematic: P1.7, input/output with Schmitt trigger -- MSP430G2x31

To ADC10

INCHx

ADC10EA.y

USIPE7

PxDIR.y

from USI

Direction

0: Input

1: Output

PxSEL.y

PxREN.y

PxSEL.y or

USIPE7

DV_SS

DV_CC

PxOUT.y

From USI

Bus

Keeper

P1.7/SDI/SDA/A7/TDO/TDI

PxSEL.y

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

From JTAG

To JTAG

From JTAG

To JTAG

USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P1 (P1.7) pin functions -- MSP430G2x31

CONTROL BITS / SIGNALS

PIN NAME (P1.X)

FUNCTION

ADC10AE.x

(INCH.x = 1)

JTAG

Mode

P1DIR.x

P1SEL.x

USIP.x

P1.7/

P1.x (I/O)

I: 0; O: 1

A7/

1 (y = 7)

SDI/SDO

TDO/TDI

SDI/SDO

TDO/TDI

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P2 pin schematic: P2.6, input/output with Schmitt trigger -- MSP430G2x21 and MSP430G2x31

XOUT/P2.7

LF off

PxSEL.6

PxSEL.7

BCSCTL3.LFXT1Sx = 11

LFXT1CLK

PxSEL.6

PxDIR.y

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

PxSEL.6

PxOUT.y

from Module

Bus

Keeper

XIN/P2.6/TA0.1

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

Port P2 (P2.6) pin functions -- MSP430G2x21 and MSP430G2x31

CONTROL BITS / SIGNALS

PIN NAME (P2.X)

FUNCTION

P2DIR.x

P2SEL.6

PSEL2.7

XIN

I: 0; O: 1

P2.6

P2.x (I/O)

Timer0_A3.TA1

TA0.1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P2 pin schematic: P2.7, input/output with Schmitt trigger -- MSP430G2x21 and MSP430G2x31

XIN/P2.6/TA0.1

LF off

PxSEL.6

PxSEL.7

BCSCTL3.LFXT1Sx = 11

LFXT1CLK

from P2.6/XIN

PxSEL.7

PxDIR.y

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

PxSEL.7

PxOUT.y

from Module

Bus

Keeper

XOUT/P2.7

PxIN.y

To Module

PxIRQ.y

PxIE.y

Set

PxIFG.y

Interrupt

Edge

PxSEL.y

PxIES.y

Select

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010

Port P2 (P2.7) pin functions -- MSP430G2x21 and MSP430G2x31

CONTROL BITS / SIGNALS

P2SEL.6

PIN NAME (P2.X)

FUNCTION

P2DIR.x

P2SEL.7

XOUT

P2.7

XOUT

P2.x (I/O)

I: 0; O: 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

26-May-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

Purchase Samples

MSP430G2121IN14

MSP430G2121IPW14

ACTIVE

PDIP

Pb-Free (RoHS)

CU NIPDAU Level-1-260C-UNLIM

TSSOP

Green (RoHS

& no Sb/Br)

MSP430G2121IPW14R

MSP430G2121IRSA16R

MSP430G2121IRSA16T

ACTIVE

TSSOP

QFN

RSA

2000

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

Purchase Samples

Green (RoHS

& no Sb/Br)

QFN

Green (RoHS

& no Sb/Br)

MSP430G2131IN14

MSP430G2131IPW14

ACTIVE

PDIP

Pb-Free (RoHS)

CU NIPDAU Level-1-260C-UNLIM

Purchase Samples

TSSOP

Green (RoHS

& no Sb/Br)

MSP430G2131IPW14R

MSP430G2131IRSA16R

MSP430G2131IRSA16T

MSP430G2221IN14

ACTIVE

TSSOP

QFN

RSA

2000

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

Purchase Samples

Green (RoHS

& no Sb/Br)

QFN

Green (RoHS

& no Sb/Br)

PDIP

Pb-Free (RoHS)

Contact TI Distributor

or Sales Office

MSP430G2221IPW14

MSP430G2221IPW14R

MSP430G2221IRSA16R

MSP430G2221IRSA16T

TSSOP

QFN

RSA

Green (RoHS

& no Sb/Br)

Purchase Samples

2000

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

QFN

Green (RoHS

& no Sb/Br)

MSP430G2231IN14

MSP430G2231IPW14

ACTIVE

PDIP

Pb-Free (RoHS)

CU NIPDAU Level-1-260C-UNLIM

Request Free Samples

Purchase Samples

TSSOP

Green (RoHS

& no Sb/Br)

MSP430G2231IPW14R

ACTIVE

TSSOP

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Contact TI Distributor

or Sales Office

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

26-May-2010

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

MSP430G2231IRSA16R

MSP430G2231IRSA16T

QFN

RSA

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Request Free Samples

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Purchase Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

0,10

0,65

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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MSP430G2231IRSA16T [TI]

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