MSP430G2231QPW1EP [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器型号: | MSP430G2231QPW1EP |
厂家: | TEXAS INSTRUMENTS |
描述: | MIXED SIGNAL MICROCONTROLLER |
文件: | 总43页 (文件大小:620K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MSP430G2231-EP
www.ti.com
SLAS862 –JUNE 2012
MIXED SIGNAL MICROCONTROLLER
1
FEATURES
•
Low Supply-Voltage Range: 1.8 V to 3.6 V
•
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
•
Ultra-Low Power Consumption
•
•
For Family Members Details, See Table 1 and
–
–
–
Active Mode: 220 µA at 1 MHz, 2.2 V
Standby Mode: 0.5 µA
Available in a 14-Pin Plastic Small-Outline Thin
Package (TSSOP) (PW)
Off Mode (RAM Retention): 0.1 µA
•
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
•
•
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
•
•
•
•
Controlled Baseline
Basic Clock Module Configurations
One Assembly/Test Site
One Fabrication Site
–
Internal Frequencies up to 16 MHz With
One Calibrated Frequency
Available in Extended (–40°C/125°C)
–
Internal Very Low Power Low-Frequency
(LF) Oscillator
(2)
Temperature Range
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
(1)
–
–
32-kHz Crystal
External Digital Clock Source
•
•
16-Bit Timer_A With Two Capture/Compare
Registers
Universal Serial Interface (USI) Supporting SPI
and I2C (See Table 1)
•
•
Brownout Detector
10-Bit 200-ksps A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
(See Table 1)
•
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
(1) Crystal oscillator cannot be operated beyond 105°C
(2) Custom temperature ranges available
DESCRIPTION
The MSP430G2231 is an ultra-low-power microcontroller consisting of several devices featuring different sets of
peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized
to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit
RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally
controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2231 has a 10-bit A/D converter and built-in communication capability using synchronous
protocols (SPI or I2C). For configuration details, see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430G2231-EP
SLAS862 –JUNE 2012
www.ti.com
Table 1. Available Options
Flash
(KB)
RAM
(B)
ADC10
Channel
Package
Type
Device
BSL
EEM
Timer_A
USI
Clock
I/O
MSP430G2231
-
1
2
128
1x TA2
1
8
LF, DCO, VLO
10
14-TSSOP
Table 2. ORDERING INFORMATION(1)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
G2231EP
VID NUMBER
–40°C to 125°C
TSSOP - PW
MSP430G2231QPW1EP
V62/12621-01XE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
2
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MSP430G2231-EP
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SLAS862 –JUNE 2012
Device Pinout
PW PACKAGE
(TOP VIEW)
14
13
12
11
10
9
DVSS
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
1
2
3
4
5
6
7
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREF-
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
P1.7/A7/SDI/SDA/TDO/TDI
8
P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
P1.5/TA0.0/A5/SCLK/TMS
NOTE: See port schematics in Application Information for detailed I/O information.
Functional Block Diagram
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
2
ACLK
Port P2
Port P1
ADC
Clock
System
SMCLK
Flash
RAM
128B
2 I/O
Interrupt
8 I/O
Interrupt
10-Bit
8 Ch.
2kB
1kB
capability
pull-up/down
resistors
capability
pull-up/down
resistors
Autoscan
1 ch DMA
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
USI
Watchdog Timer0_A2
WDT+
2 CC
Brownout
Protection
Universal
Serial
JTAG
Interface
15-Bit
Registers
Interface
SPI, I2C
Spy-Bi
Wire
RST/NMI
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Table 3. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
P1.0/
General-purpose digital I/O pin
TA0CLK/
ACLK/
A0
Timer0_A, clock signal TACLK input
ACLK signal output
2
I/O
ADC10 analog input A0(1)
P1.1/
TA0.0/
A1
General-purpose digital I/O pin
3
4
I/O
I/O
Timer0_A, capture: CCI0A input, compare: Out0 output
ADC10 analog input A1(1)
P1.2/
TA0.1/
A2
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A2(1)
P1.3/
ADC10CLK/
A3/
General-purpose digital I/O pin
ADC10, conversion clock output(1)
ADC10 analog input A3(1)
5
6
I/O
I/O
VREF-/VEREF
ADC10 negative reference voltage(1)
P1.4/
SMCLK/
A4/
VREF+/VEREF+/
TCK
General-purpose digital I/O pin
SMCLK signal output
ADC10 analog input A4(1)
ADC10 positive reference voltage(1)
JTAG test clock, input terminal for device programming and test
P1.5/
TA0.0/
A5/
SCLK/
TMS
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
7
8
9
I/O
I/O
I/O
ADC10 analog input A5(1)
USI: clock input in I2C mode; clock input/output in SPI mode
JTAG test mode select, input terminal for device programming and test
P1.6/
TA0.1/
A6/
SDO/
SCL/
TDI/TCLK
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A6(1)
USI: Data output in SPI mode
USI: I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
P1.7/
A7/
SDI/
General-purpose digital I/O pin
ADC10 analog input A7(1)
USI: Data input in SPI mode
SDA/
USI: I2C data in I2C mode
JTAG test data output terminal or test data input during programming and test
TDO/TDI(2)
XIN/
P2.6/
TA0.1
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
Output terminal of crystal oscillator(3)
General-purpose digital I/O pin
13
12
10
11
I/O
XOUT/
P2.7
I/O
RST/
NMI/
SBWTDIO
Reset
I
I
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
1
14
-
NA
NA
NA
Supply voltage
DVSS
Ground reference
QFN Pad
QFN package pad connection to VSS recommended.
(1) MSP430G2x31 only
(2) TDO or TDI is selected via JTAG instruction.
(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
4
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SLAS862 –JUNE 2012
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
R6
R7
R8
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
R9
R10
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
R11
R12
R13
Instruction Set
R14
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 4 shows examples of the three types of
instruction formats; Table 5 shows the address
modes.
R15
Table 4. Instruction Word Formats
INSTRUCTION FORMAT
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
SYNTAX
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 ---> R5
PC -->(TOS), R8--> PC
Jump-on-equal bit = 0
Table 5. Address Mode Descriptions(1)
ADDRESS MODE
Register
S
✓
✓
✓
✓
✓
D
✓
✓
✓
✓
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
R10 -- --> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
M(2+R5) -- --> M(6+R6)
M(EDE) -- --> M(TONI)
M(MEM) -- --> M(TCDAT)
M(R10) -- --> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) -- --> R11
R10 + 2-- --> R10
Indirect autoincrement
Immediate
✓
✓
MOV @Rn+,Rm
MOV #X,TONI
#45 -- --> M(TONI)
(1) S = source, D = destination
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Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
•
•
Low-power mode 1 (LPM1)
–
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
DCO's dc generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator remains enabled
ACLK remains active
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
–
–
–
–
–
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
Crystal oscillator is stopped
6
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SLAS862 –JUNE 2012
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 6. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range(1)
PORIFG
RSTIFG
WDTIFG
KEYV(2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
ACCVIFG(2)(3)
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Watchdog Timer+
Timer_A2
WDTIFG
TACCR0 CCIFG(4)
TACCR1 CCIFG, TAIFG(2)(4)
maskable
maskable
maskable
Timer_A2
ADC10
USI
ADC10IFG(4)
maskable
maskable
maskable
maskable
USIIFG, USISTTIFG(2)(4)
P2IFG.6 to P2IFG.7(2)(4)
P1IFG.0 to P1IFG.7(2)(4)
I/O Port P2 (two flags)
I/O Port P1 (eight flags)
(5)
See
0FFDEh to
0FFC0h
15 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 7. Interrupt Enable Register 1 and 2
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw-0
NMIIE
rw-0
OFIE
rw-0
WDTIE
rw-0
WDTIE
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
OFIE
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
Address
7
6
5
4
3
2
1
0
01h
Table 8. Interrupt Flag Register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw-0
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFG
rw-1
WDTIFG
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
PORIFG
RSTIFG
NMIIFG
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
Address
03h
7
6
5
4
3
2
1
0
8
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Memory Organization
Table 9. Memory Organization
MSP430G2231
Memory
Size
2kB
Main: interrupt vector
Main: code memory
Flash
Flash
0xFFFF to 0xFFC0
0xFFFF to 0xF800
Information memory
Size
256 Byte
Flash
010FFh to 01000h
RAM
Size
128B
027Fh to 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
•
Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1µs. The basic
clock module provides the following clock signals:
•
•
•
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 10. DCO Calibration Data
(Provided From Factory In Flash Information Memory Segment A)
CALIBRATION
REGISTER
DCO FREQUENCY
SIZE
ADDRESS
CALBC1_1MHZ
CALDCO_1MHZ
byte
byte
010FFh
010FEh
1 MHz
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull-up/pull-down resistor.
WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
10
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Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 11. Timer_A2 Signal Connections – Device With ADC10
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
INPUT PIN NUMBER
MODULE BLOCK
2 - P1.0
TACLK
ACLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
TA0
TA1
SMCLK
TACLK
TA0
2 - P1.0
3 - P1.1
3 - P1.1
7 - P1.5
ACLK (internal)
VSS
CCR0
CCR1
VCC
VCC
4 - P1.2
8 - P1.6
TA1
CCI1A
CCI1B
GND
4 - P1.2
8 - P1.6
13 - P2.6
TA1
VSS
VCC
VCC
USI
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430G2x31 only)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
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Peripheral File Map
Table 12. Peripherals With Word Access
REGISTER
NAME
MODULE
ADC10
REGISTER DESCRIPTION
OFFSET
ADC data transfer start address
ADC control 0
ADC10SA
ADC10CTL0
ADC10CTL0
ADC10MEM
TACCR1
TACCR0
TAR
1BCh
01B0h
01B2h
01B4h
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
012Ch
012Ah
0128h
0120h
ADC control 1
ADC memory
Timer_A
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Flash control 3
TAIV
Flash Memory
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
Watchdog Timer+
Watchdog/timer control
WDTCTL
Table 13. Peripherals With Byte Access
REGISTER
NAME
MODULE
ADC10
REGISTER DESCRIPTION
OFFSET
ADC analog enable
ADC data transfer control 1
ADC data transfer control 0
USI control 0
ADC10AE0
ADC10DTC1
ADC10DTC0
USICTL0
USICTL1
USICKCTL
USICNT
USISR
04Ah
049h
048h
078h
079h
07Ah
07Bh
07Ch
053h
058h
057h
056h
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
USI
USI control 1
USI clock control
USI bit counter
USI shift register
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P2 resistor enable
Port P2 selection
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P2REN
Port P2
P2SEL
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
P2IE
P2IES
P2IFG
P2DIR
Port P2 output
P2OUT
Port P2 input
P2IN
12
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Table 13. Peripherals With Byte Access (continued)
REGISTER
MODULE
REGISTER DESCRIPTION
OFFSET
NAME
P1REN
P1SEL
P1IE
Port P1
Port P1 resistor enable
Port P1 selection
027h
026h
025h
024h
023h
022h
021h
020h
003h
002h
001h
000h
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
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Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin(2)
–0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device pin
Unprogrammed device
Programmed device
–55°C to 150°C
–55°C to 150°C
(3)
Storage temperature range, Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
MIN NOM
MAX UNIT
During program execution
During flash programming
1.8
2.2
0
3.6
V
VCC
Supply voltage
3.6
VSS
TA
Supply voltage
V
Operating free-air temperature
–40
125
6
°C
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
dc
dc
VCC = 2.7 V,
Duty cycle = 50% ± 10%
fSYSTEM
Processor frequency (maximum MCLK frequency)(1)(2)
12 MHz
16
VCC = 3.3 V,
Duty cycle = 50% ± 10%
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
3.3 V 3.6 V
2.7 V
Supply Voltage - V
1.8 V
2.2 V
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
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A. See data sheet for absolute maximum and minimum recommended operating conditions.
B. Silicon operating life design goal is 10 years at 110°C junction temperature (does not include package interconnect
life).
C. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 2. Operating Life Derating Chart
THERMAL INFORMATION
MSP430G2231
THERMAL METRIC(1)
PW
14 PINS
102.5
31.4
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
45.0
°C/W
ψJT
1.8
ψJB
44.4
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
2.2 V
220
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (1 MHz)
IAM,1MHz
µA
3 V
300
390
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Typical Characteristics – Active Mode Supply Current (Into VCC)
4.0
5.0
4.0
3.0
2.0
1.0
0.0
f
= 16 MHz
DCO
T
= 85 °C
= 25 °C
A
3.0
2.0
1.0
0.0
T
A
V
= 3 V
CC
f
= 12 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
f
= 8 MHz
DCO
2.0
f
= 1 MHz
V
CC
= 2.2 V
DCO
1.5
2.5
3.0
3.5
4.0
0.0
4.0
8.0
12.0
16.0
V
CC
− Supply Voltage − V
f
DCO
− DCO Frequency − MHz
Figure 3. Active Mode Current vs VCC, TA = 25°C
Figure 4. Active Mode Current vs DCO Frequency
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Low-power mode 0
(LPM0) current(2)
ILPM0,1MHz
25°C
2.2 V
65
µA
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
25°C
22
fACLK = 32768 Hz,
Low-power mode 2
(LPM2) current(3)
ILPM2
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
2.2 V
µA
46
125°C
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
125°C
25°C
0.7
3
1.5
Low-power mode 3
(LPM3) current(3)
ILPM3,LFXT1
ILPM3,VLO
ILPM4
2.2 V
2.2 V
2.2 V
µA
21
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
0.5
2
0.7
Low-power mode 3
current, (LPM3)(3)
µA
125°C
9.3
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C
85°C
0.1
0.8
2
0.5
Low-power mode 4
(LPM4) current(4)
1.5
7.1
µA
125°C
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for brownout and WDT clocked by SMCLK included.
(3) Current for brownout and WDT clocked by ACLK included.
(4) Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
Vcc = 3.6 V
Vcc = 3 V
Vcc = 3.6 V
Vcc = 3 V
Vcc = 2.2 V
Vcc = 2.2 V
Vcc = 1.8 V
Vcc = 1.8 V
60 80
-40
-20
0
20
TA – Temperature – °C
Figure 6. LPM4 Current vs Temperature
40
-40
-20
0
20
40
60
80
TA – Temperature – °C
Figure 5. LPM3 Current vs Temperature
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Schmitt-Trigger Inputs – Ports Px
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45 VCC
1.35
TYP
MAX UNIT
0.75 VCC
VIT+
Positive-going input threshold voltage
V
V
3 V
2.25
0.55 VCC
1.65
0.25 VCC
0.75
VIT–
Negative-going input threshold voltage
3 V
3 V
Vhys
RPull
CI
Input voltage hysteresis (VIT+ – VIT–
Pullup/pulldown resistor
Input capacitance
)
0.3
1
V
For pullup: VIN = VSS
For pulldown: VIN = VCC
3 V
20
35
5
50
kΩ
pF
VIN = VSS or VCC
Leakage Current – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = -40°C to 105°C
TA = 125°C
VCC
3 V
3 V
MIN
MAX UNIT
±50
nA
Ilkg(Px.y)
High-impedance leakage current(1)(2)
±120
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –6 mA(1)
I(OLmax) = 6 mA(1)
VCC
3 V
3 V
MIN
TYP
VCC – 0.3
VSS + 0.3
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
V
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Px.y, CL = 20 pF, RL = 1 kΩ(1) (2)
Px.y, CL = 20 pF(2)
VCC
3 V
3 V
MIN
TYP
12
MAX UNIT
MHz
Port output frequency
(with load)
fPx.y
fPort_CLK
Clock output frequency
16
MHz
(1) A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
50
40
30
20
10
0
30
25
20
15
10
5
V
= 2.2 V
V
= 3 V
CC
CC
T
= 25°C
= 85°C
A
T
= 25°C
= 85°C
P1.7
A
P1.7
T
A
T
A
0
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 7.
Figure 8.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−5
0
−10
−20
−30
−40
−50
V
= 2.2 V
V
= 3 V
CC
CC
P1.7
P1.7
−10
−15
−20
−25
T
A
= 85°C
T
= 85°C
A
T
A
= 25°C
0.5
T
= 25°C
0.5
A
0
1
1.5
2
2.5
0
1
1.5
2
2.5
3
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 9.
Figure 10.
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POR/Brownout Reset (BOR)(1)
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
See Figure 11
TEST CONDITIONS
dVCC/dt ≤ 3 V/s
VCC
MIN
TYP
MAX UNIT
VCC(start)
V(B_IT–)
Vhys(B_IT–)
td(BOR)
0.7 × V(B_IT–)
1.35
V
V
See Figure 11 through Figure 13
See Figure 11
dVCC/dt ≤ 3 V/s
dVCC/dt ≤ 3 V/s
130
mV
See Figure 11
2000
µs
Pulse length needed at RST/NMI pin to
accepted reset internally
t(reset)
2.2 V/3 V
2
µs
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–)
+
Vhys(B_IT–)is ≤ 1.8 V.
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 11. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics – POR/Brownout Reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
Typical Conditions
CC
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 12. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(drop)
0.5
t = t
f
r
0
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 13. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
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Main DCO Characteristics
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
•
•
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × f
× f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
f
=
average
MOD × f
+ (32 – MOD) × f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.8
2.2
3
TYP
MAX UNIT
RSELx < 14
RSELx = 14
RSELx = 15
3.6
3.6
3.6
V
VCC
Supply voltage
V
V
fDCO(0,0)
fDCO(0,3)
fDCO(1,3)
fDCO(2,3)
fDCO(3,3)
fDCO(4,3)
fDCO(5,3)
fDCO(6,3)
fDCO(7,3)
fDCO(8,3)
fDCO(9,3)
fDCO(10,3)
fDCO(11,3)
fDCO(12,3)
fDCO(13,3)
fDCO(14,3)
fDCO(15,3)
fDCO(15,7)
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
0.096
0.12
0.15
0.21
0.30
0.41
0.58
0.80
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
0.8
1.5 MHz
MHz
1.6
2.3
MHz
3.4
MHz
4.25
MHz
4.3
8.6
7.3 MHz
MHz
7.8
13.9 MHz
MHz
15.25
21
MHz
Frequency step between
range RSEL and RSEL+1
SRSEL
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3 V
1.35
ratio
Frequency step between
tap DCO and DCO+1
SDCO
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
Measured at SMCLK output
3 V
3 V
1.08
50
ratio
%
Duty cycle
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Calibrated DCO Frequencies – Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
1-MHz tolerance over
temperature(1)
-40°C to 105°C
3 V
-3
±0.5
+3
+3
+6
%
%
%
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
1-MHz tolerance over VCC
1-MHz tolerance overall
30°C
1.8 V to 3.6 V
1.8 V to 3.6 V
-3
-6
±2
±3
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
-40°C to 105°C
(1) This is the frequency change from the measured frequency at 30°C over temperature.
Wake-Up From Lower-Power Modes (LPM3/4) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DCO clock wake-up time from
LPM3/4(1)
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
tDCO,LPM3/4
tCPU,LPM3/4
3 V
1.5
µs
1/fMCLK
+
CPU wake-up time from LPM3/4(2)
tClock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
DCO Frequency − MHz
Figure 14. DCO Wake-Up Time From LPM3 vs DCO Frequency
10.00
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Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32768
Hz
LFXT1 oscillator logic level
fLFXT1,LF,logic
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
1.8 V to 3.6 V 10000
1.8 V to 3.6 V
32768 50000
32768
Hz
Hz
LFXT1 oscillator logic level
XTS = 0, XCAPx = 0, LFXT1Sx = 3,
square wave input frequency,
TA = -40°C to 125°C
fLFXT1,LF,logic
LF mode
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
200
Oscillation allowance for
LF crystals
OALF
kΩ
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
8.5
11
Integrated effective load
capacitance, LF mode(2)
CL,eff
pF
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
Duty cycle, LF mode
2.2 V
2.2 V
30
10
50
70
%
Oscillator fault frequency,
LF mode(3)
fFault,LF
XTS = 0, XCAPx = 0, LFXT1Sx = 3(4)
10000
Hz
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TA
VCC
MIN
TYP
MAX UNIT
-40°C to 85°C
125°C
4
12
20
fVLO
3 V
kHz
23
dfVLO/dT
-40°C to 125°C
25°C
3 V
0.5
4
%/°C
%/V
dfVLO/dVCC VLO frequency supply voltage drift
1.8 V to 3.6 V
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
fTA
Timer_A input clock frequency
Timer_A capture timing
External: TACLK, INCLK
Duty cycle = 50% ± 10%
fSYSTEM
MHz
ns
tTA,cap
TA0, TA1
3 V
20
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USI, Universal Serial Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
USI clock frequency
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
External: SCLK,
Duty cycle = 50% ±10%,
SPI slave mode
fUSI
fSYSTEM
MHz
USI module in I2C mode,
I(OLmax) = 1.5 mA
VSS
V
VOL,I2C
Low-level output voltage on SDA and SCL
3 V
VSS
+ 0.4
Typical Characteristics – USI Low-Level Output Voltage on SDA and SCL
5.0
5.0
4.0
3.0
2.0
1.0
0.0
T
A
= 25°C
= 85°C
V
CC
= 2.2 V
V
CC
= 3 V
T
A
= 25°C
4.0
3.0
2.0
1.0
0.0
T
A
T
A
= 85°C
0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 15. USI Low-Level Output Voltage vs Output
Current
Figure 16. USI Low-Level Output Voltage vs Output
Current
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MAX UNIT
10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VSS = 0 V
TA
VCC
3 V
3 V
MIN
TYP
VCC
VAx
Analog supply voltage
2.2
3.6
V
V
All Ax terminals, Analog inputs
selected in ADC10AE register
Analog input voltage(2)
ADC10 supply current(3)
0
VCC
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
-40°C to
125°C
IADC10
0.6
1.64
mA
mA
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
0.25
0.84
0.84
Reference supply current,
reference buffer disabled(4)
-40°C to
125°C
IREF+
3 V
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
0.25
1.1
-40°C to
85°C
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
1.4
3.8
Reference buffer supply
IREFB,0
3 V
3 V
mA
mA
current with ADC10SR = 0(4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
-40°C to
125°C
-40°C to
85°C
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
0.5
0.7
Reference buffer supply
IREFB,1
current with ADC10SR = 1(4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
-40°C to
125°C
0.9
Only one terminal Ax can be selected -40°C to
CI
RI
Input capacitance
3 V
3 V
27
pF
at one time
125°C
-40°C to
125°C
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
1000
2000
Ω
(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC10
.
(4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
3
TYP
MAX UNIT
I
I
I
I
VREF+ ≤ 1 mA, REF2_5V = 0
Positive built-in reference
analog supply voltage range
VCC,REF+
V
VREF+ ≤ 1 mA, REF2_5V = 1
VREF+ ≤ IVREF+max, REF2_5V = 0
VREF+ ≤ IVREF+max, REF2_5V = 1
1.4
2.34
1.5
2.5
1.59
V
2.65
Positive built-in reference
voltage
VREF+
3 V
3 V
Maximum VREF+ load
current(1)(2)
ILD,VREF+
±1
±2
mA
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 0.75 V,
REF2_5V = 0
VREF+ load regulation(1)
3 V
3 V
LSB
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 1.25 V,
REF2_5V = 1
±2
IVREF+ = 100 µA→900 µA,
VAx ≉ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
VREF+ load regulation response
time(1)(2)
400
ns
ADC10SR = 0
Maximum capacitance at pin
VREF+(1)(2)
CVREF+
TCREF+
I
VREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3 V
3 V
100
pF
ppm/
°C
Temperature coefficient
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
±190
Settling time of internal
reference voltage to 99.9%
VREF(1)(2)
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
tREFON
3.6 V
3 V
30
2
µs
µs
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
Settling time of reference buffer
to 99.9% VREF(1)(2)
tREFBURST
(1) Minimum and maximum parameters are characterized up to TA = 105°C, unless otherwise noted.
(2) Characterized at TA = -40°C to 105°C only.
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10-Bit ADC, External Reference(1)
over recommended ranges of supply voltage and operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
1.4
VCC
Positive external reference input
voltage range
VEREF+
V
(2)
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1
1.4
0
3
(3)
Negative external reference input
VEREF–
VEREF+ > VEREF–
1.2
V
V
(4)
voltage range
Differential external reference
input voltage range,
(5)
ΔVEREF
VEREF+ > VEREF–
1.4
VCC
ΔVEREF = VEREF+ – VEREF–
0 V ≤ VEREF+ ≤ VCC
SREF1 = 1, SREF0 = 0
,
3 V
±1
IVEREF+
Static input current into VEREF+
Static input current into VEREF–
µA
µA
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
3 V
3 V
0
SREF1 = 1, SREF0 = 1(3)
IVEREF–
0 V ≤ VEREF– ≤ VCC
±1
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45
0.45
TYP
MAX UNIT
ADC10SR = 0
ADC10SR = 1
6.3
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10CLK
fADC10OSC
3 V
MHz
1.5
ADC10 built-in
ADC10DIVx = 0, ADC10SSELx = 0,
3 V
3 V
3.7
6.3 MHz
oscillator frequency fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
2.06
3.51
µs
tCONVERT
Conversion time
13 ×
fADC10CLK from ACLK, MCLK, or SMCLK,
ADC10SSELx ≠ 0
ADC10DIV ×
1/fADC10CLK
Turn-on settling time
of the ADC
(1)
tADC10ON
100
ns
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
Integral linearity error
Differential linearity error
Offset error
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
3 V
MIN
TYP
MAX UNIT
±1 LSB
±1 LSB
±1 LSB
±2 LSB
±5 LSB
EI
ED
EO
EG
ET
Source impedance RS < 100 Ω
Gain error
±1.1
±2
Total unadjusted error
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10-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
3 V
MIN
TYP
MAX UNIT
Temperature sensor supply
current(1)
REFON = 0, INCHx = 0Ah,
TA = 25°C
ISENSOR
TCSENSOR
tSensor(sample)
IVMID
60
µA
mV/°C
µs
(2)
ADC10ON = 1, INCHx = 0Ah
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3.55
Sample time required if channel
30
(3)
10 is selected
(4)
Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh
µA
ADC10ON = 1, INCHx = 0Bh,
VCC divider at channel 11
VMID
1.5
V
V
MID ≉ 0.5 × VCC
Sample time required if channel
11 is selected
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
3 V
1220
ns
(5)
(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
(2) The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
(4) No additional current is needed. The VMID is used during sampling.
.
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Flash Memory
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE) Program and erase supply voltage
2.2
3.6
476
5
V
fFTG
Flash timing generator frequency
Supply current from VCC during program
Supply current from VCC during erase
Cumulative program time(1)
257
kHz
mA
mA
ms
ms
IPGM
3 V
1
1
IERASE
tCPT
3 V
7
2.2 V/3.6 V
2.2 V/3.6 V
10
tCMErase
Cumulative mass erase time
20
104
15
-40°C ≤ TJ ≤
105°C
Program/erase endurance
105
cycles
tRetention
tWord
Data retention duration
TJ = 25°C
(2)
years
tFTG
Word or byte program time
30
25
(2)
(2)
tBlock, 0
Block program time for first byte or word
tFTG
Block program time for each additional byte or
word
tBlock, 1-63
18
tFTG
(2)
(2)
(2)
tBlock, End
tMass Erase
tSeg Erase
Block program end-sequence wait time
Mass erase time
6
10593
4819
tFTG
tFTG
tFTG
Segment erase time
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
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RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
(1)
V(RAMh)
RAM retention supply voltage
1.6
V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0
TYP
MAX
20
UNIT
MHz
µs
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
2.2 V/3 V
tSBW,Low Spy-Bi-Wire low clock pulse length
0.025
15
Spy-Bi-Wire enable time
tSBW,En
2.2 V/3 V
1
µs
(TEST high to acceptance of first clock edge(1)
)
tSBW,Ret
fTCK
Spy-Bi-Wire return to normal operation time
TCK input frequency(2)
TA = -40°C to 105°C
TA = -40°C to 105°C
2.2 V/3 V
2.2 V
15
0
100
5
µs
MHz
MHz
kΩ
3 V
0
10
90
RInternal
Internal pulldown resistance on TEST
2.2 V/3 V
25
60
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse(1)
TA = 25°C, over recommended ranges of supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.5
6
MAX
UNIT
V
VCC(FB)
VFB
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse blow
Supply current into TEST during fuse blow
Time to blow fuse
7
100
1
V
IFB
mA
ms
tFB
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
To ADC10
INCHx
ADC10AE0.y
PxSEL.y
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DV
SS
0
1
PxSEL.y
DV
CC
1
PxOUT.y
ACLK
0
1
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
Bus
Keeper
EN
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 14. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
ADC10AE.x
(INCH.y = 1)
P1DIR.x
P1SEL.x
P1.0/
P1.x (I/O)
TA0.TACLK
ACLK
I: 0; O: 1
0
1
1
X
0
1
1
X
0
TA0CLK/
ACLK/
A0
0
0
0
1
0
A0
X
1 (y = 0)
P1.1/
P1.x (I/O)
TA0.0
I: 0; O: 1
0
TA0.0/
1
0
X
0
0
1
TA0.CCI0A
A1
A1
1 (y = 1)
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Table 14. Port P1 (P1.0 to P1.2) Pin Functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
ADC10AE.x
(INCH.y = 1)
P1DIR.x
P1SEL.x
P1.2/
P1.x (I/O)
TA0.1
I: 0; O: 1
0
1
1
X
0
TA0.1/
1
0
X
0
0
2
TA0.CCI1A
A2
A2/
1 (y = 2)
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Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger
SREF2
VSS
0
To ADC10 VREF-
1
To ADC10
INCHx = y
ADC10AE0.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
DVSS
0
PxSEL.y
1
DVCC
1
PxOUT.y
0
1
ADC10CLK
P1.3/ADC10CLK/A3/VREF-/VEREF-
Bus
Keeper
EN
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 15. Port P1 (P1.3) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
P1.3/
x
FUNCTION
ADC10AE.x
(INCH.x = 1)
P1DIR.x
P1SEL.x
P1.x (I/O)
I: 0; O: 1
0
1
0
ADC10CLK/
A3/
ADC10CLK
A3
1
X
X
X
0
3
X
X
X
1 (y = 3)
VREF-/
VEREF-
VREF-
VEREF-
1
1
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Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger
ToADC10 VREF+
To ADC10
INCHx = y
ADC10AE0.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
DVSS
0
PxSEL.y
1
DVCC
1
PxOUT.y
SMCLK
0
1
Bus
Keeper
EN
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
Table 16. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
P1SEL.x
P1.4/
P1.x (I/O)
SMCLK
A4
I: 0; O: 1
0
1
0
0
0
0
0
0
1
SMCLK/
A4/
1
X
X
X
X
0
X
X
X
X
1 (y = 4)
4
VREF+/
VEREF+/
TCK
VREF+
VEREF+
TCK
1
1
0
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Port P1 Pin Schematic: P1.5, Input/Output With Schmitt Trigger
To ADC10
INCHx
ADC10AE0.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
DVSS
0
PxSEL.y
1
DVCC
1
PxOUT.y
0
1
From Module
Bus
Keeper
EN
P1.5/TA0.0/A5/TMS
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
Table 17. Port P1 (P1.5) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
P1.5/
x
FUNCTION
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
P1DIR.x
P1SEL.x
USIP.x
P1.x (I/O)
I: 0; O: 1
0
1
0
0
X
1
0
0
0
0
0
0
1
TA0.0/
A5/
TA0.0
A5
1
X
X
X
0
5
X
X
X
1 (y = 5)
SCLK/
TMS
SCLK
TMS
0
0
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MSP430G2231-EP
SLAS862 –JUNE 2012
www.ti.com
Port P1 Pin Schematic: P1.6, Input/Output With Schmitt Trigger
To ADC10
INCHx
ADC10AE0.y
USIPE6
PxDIR.y
1
from USI
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y or
USIPE6
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From USI
Bus
Keeper
EN
P1.6/TA0.1/SDO/SCL/A6/TDI
PxSEL.y
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
Table 18. Port P1 (P1.6) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
P1.6/
x
FUNCTION
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
P1DIR.x
P1SEL.x
USIP.x
P1.x (I/O)
TA0.1
I: 0; O: 1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
TA0.1/
1
0
0
TA0.CCR1B
A6
1
0
6
A6/
X
X
X
X
X
X
1 (y = 6)
SDO/
SDO
0
0
TDI/TCLK
TDI/TCLK
36
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MSP430G2231-EP
www.ti.com
SLAS862 –JUNE 2012
Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger
To ADC10
INCHx
ADC10AE0.y
USIPE7
PxDIR.y
1
0
Direction
0: Input
1: Output
from USI
PxSEL.y
PxREN.y
PxSEL.y or
USIPE7
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From USI
Bus
Keeper
EN
P1.7/SDI/SDA/A7/TDO/TDI
PxSEL.y
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
Table 19. Port P1 (P1.7) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
P1.7/
x
FUNCTION
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
P1DIR.x
P1SEL.x
USIP.x
P1.x (I/O)
A7
I: 0; O: 1
0
X
X
X
0
0
1
0
0
0
0
0
1
A7/
X
X
X
1 (y = 7)
7
SDI/SDO
TDO/TDI
SDI/SDO
TDO/TDI
0
0
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MSP430G2231-EP
SLAS862 –JUNE 2012
www.ti.com
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
XOUT/P2.7
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
PxSEL.6
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.6
1
PxOUT.y
0
1
from Module
Bus
Keeper
EN
XIN/P2.6/TA0.1
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 20. Port P2 (P2.6) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P2.x)
XIN
x
FUNCTION
P2DIR.x
P2SEL.6
P2SEL.7
XIN
0
I: 0; O: 1
1
1
0
1
1
X
X
P2.6
6
P2.x (I/O)
TA0.1(1)
TA0.1
(1) BCSCTL3.LFXT1Sx = 11 is required.
38
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MSP430G2231-EP
www.ti.com
SLAS862 –JUNE 2012
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
XIN/P2.6/TA0.1
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
from P2.6/XIN
PxSEL.7
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
0
1
PxSEL.7
1
PxOUT.y
0
1
from Module
Bus
Keeper
EN
XOUT/P2.7
PxIN.y
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 21. Port P2 (P2.7) Pin Functions
CONTROL BITS / SIGNALS
P2DIR.x P2SEL.6 P2SEL.7
PIN NAME (P2.x)
x
FUNCTION
XOUT
P2.7
XOUT
P2.x (I/O)
1
1
1
7
I: 0; O: 1
X
0
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2231QPW1EP
MSP430G2231QPW1REP
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
90
TBD
TBD
Call TI
Call TI
Call TI
Call TI
PREVIEW
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430G2231-EP :
Catalog: MSP430G2231
•
Automotive: MSP430G2231-Q1
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2012
Catalog - TI's standard catalog product
•
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
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