MSP430G2232IPW14 [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430G2232IPW14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总55页 (文件大小：908K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430G2x32
MSP430G2x02
www.ti.com
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
MIXED SIGNAL MICROCONTROLLER
1
FEATURES
•
Low Supply Voltage Range: 1.8 V to 3.6 V
•
•
Universal Serial Interface (USI) Supporting SPI
and I2C
•
Ultra-Low Power Consumption
10-Bit 200-ksps Analog-to-Digital (A/D)
Converter With Internal Reference,
Sample-and-Hold, and Autoscan
(MSP430G2x32 Only)
–
–
–
Active Mode: 220 µA at 1 MHz, 2.2 V
Standby Mode: 0.5 µA
Off Mode (RAM Retention): 0.1 µA
•
•
Five Power-Saving Modes
•
•
Brownout Detector
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
•
•
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
•
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
–
Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies
•
•
Family Members are Summarized in Table 1
Package Options
–
Internal Very-Low-Power Low-Frequency
(LF) Oscillator
–
–
–
TSSOP: 14 Pin, 20 Pin
PDIP: 20 Pin
–
–
32-kHz Crystal
External Digital Clock Source
QFN: 16 Pin
•
•
One 16-Bit Timer_A With Three
Capture/Compare Registers
•
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
Up to 16 Touch-Sense Enabled I/O Pins
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2x32 and MSP430G2x02 series of microcontrollers are ultra-low-power mixed signal
microcontrollers with built-in 16-bit timers, and up to 16 I/O touch sense enabled pins and built-in communication
capability using the universal serial communication interface. The MSP430G2x32 series have a 10-bit A/D
converter. For configuration details see Table 1. Typical applications include low-cost sensor systems that
capture analog signals, convert them to digital values, and then process the data for display or for transmission
to a host system.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
www.ti.com
Table 1. Available Options(1)
Flash
(KB)
RAM
(B)
ADC10
Channel
Package
Type(2)
Device
EEM
Timer_A
USI
CLOCK
I/O
MSP430G2432IN20
MSP430G2432IPW20
MSP430G2432IRSA16
MSP430G2432IPW14
MSP430G2332IN20
MSP430G2332IPW20
MSP430G2332IRSA16
MSP430G2332IPW14
MSP430G2232IN20
MSP430G2232IPW20
MSP430G2232IRSA16
MSP430G2232IPW14
MSP430G2132IN20
MSP430G2132IPW20
MSP430G2132IRSA16
MSP430G2132IPW14
MSP430G2402IN20
MSP430G2402IPW20
MSP430G2402IRSA16
MSP430G2402IPW14
MSP430G2302IN20
MSP430G2302IPW20
MSP430G2302IRSA16
MSP430G2302IPW14
MSP430G2202IN20
MSP430G2202IPW20
MSP430G2202IRSA16
MSP430G2202IPW14
MSP430G2102IN20
MSP430G2102IPW20
MSP430G2102IRSA16
MSP430G2102IPW14
16
16
10
10
16
16
10
10
16
16
10
10
16
16
10
10
16
16
10
10
16
16
10
10
16
16
10
10
16
16
10
10
20-PDIP
20-TSSOP
16-QFN
1
8
256
256
256
128
256
256
256
128
1x TA3
8
8
8
8
-
1
LF, DCO, VLO
14-TSSOP
20-PDIP
20-TSSOP
16-QFN
1
1
1
1
1
1
1
4
2
1
8
4
2
1
1x TA3
1x TA3
1x TA3
1x TA3
1x TA3
1x TA3
1x TA3
1
1
1
1
1
1
1
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
LF, DCO, VLO
14-TSSOP
20-PDIP
20-TSSOP
16-QFN
14-TSSOP
20-PDIP
20-TSSOP
16-QFN
14-TSSOP
20-PDIP
20-TSSOP
16-QFN
14-TSSOP
20-PDIP
20-TSSOP
16-QFN
-
14-TSSOP
20-PDIP
20-TSSOP
16-QFN
-
14-TSSOP
20-PDIP
20-TSSOP
16-QFN
-
14-TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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MSP430G2x32
MSP430G2x02
www.ti.com
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
Device Pinout
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
P1.2/TA0.1/A2
RST/NMI/SBWTDIO
P1.7/SDI/SDA/A7/TDO/TDI
P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK
P1.3/ADC10CLK/A3/VREF-/VEREF-
P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/SCLK/A5/TMS
8
NOTE: ADC10 pin functions are available only on MSP430G2x32.
NOTE: The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = 1.
RSA PACKAGE
(TOP VIEW)
16 15 14 13
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
1
2
3
4
12 XIN/P2.6/TA0.1
11 XOUT/P2.7
P1.2/TA0.1/A2
10 TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF-/VEREF-
9
RST/NMI/SBWTDIO
5
6 7 8
NOTE: ADC10 pin functions are available only on MSP430G2x32.
NOTE: The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = 1.
N OR PW PACKAGE
(TOP VIEW)
1
2
20
19
18
17
16
15
14
13
12
11
DVCC
DVSS
P1.0/TA0CLK/ACLK/A0
XIN/P2.6/TA0.1
3
P1.1/TA0.0/A1
XOUT/P2.7
4
P1.2/TA0.1/A2
TEST/SBWTCK
5
P1.3/ADC10CLK/VREF-/VEREF-/A3
RST/NMI/SBWTDIO
6
P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/TCK
P1.7/SDI/SDA/A7/TDO/TDI
7
P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK
P1.5/TA0.0/A5/TMS
8
P2.0
P2.1
P2.2
P2.5
P2.4
P2.3
9
10
NOTE: ADC10 pin functions are available only on MSP430G2x32.
Copyright © 2010–2011, Texas Instruments Incorporated
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
www.ti.com
Functional Block Diagram, MSP430G2x32
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
up to 8
ACLK
Port P2
Port P1
Flash
RAM
ADC
Clock
System
SMCLK
up to 8 I/O
Interrupt
8 I/O
Interrupt
8KB
4KB
2KB
1KB
256B
256B
256B
128B
10-Bit
8 Ch.
capability
pullup/down
resistors
capability
pullup/down
resistors
Autoscan
1 ch DMA
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
USI
Watchdog Timer0_A3
WDT+
3 CC
Brownout
Protection
Universal
Serial
JTAG
Interface
15-Bit
Registers
Interface
SPI, I2C
Spy-Bi
Wire
RST/NMI
Note: Port P2. Two pins are available on the 14/16-pin package options. Eight pins are available on the 20-pin package options.
Functional Block Diagram, MSP430G2x02
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
up to 8
ACLK
Port P2
Port P1
Flash
RAM
Clock
System
SMCLK
up to 8 I/O
Interrupt
8 I/O
Interrupt
8KB
4KB
2KB
1KB
256B
256B
256B
128B
capability
pull-up/down
resistors
capability
pull-up/down
resistors
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
USI
Watchdog Timer0_A3
WDT+
3 CC
Brownout
Protection
Universal
Serial
JTAG
Interface
15-Bit
Registers
Interface
SPI, I2C
Spy-Bi
Wire
RST/NMI
Note: Port P2. Two pins are available on the 14/16-pin package options. Eight pins are available on the 20-pin package options.
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MSP430G2x32
MSP430G2x02
www.ti.com
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
Table 2. Terminal Functions
TERMINAL
14
NO.
16
I/O
DESCRIPTION
NAME
20
N, PW RSA N, PW
P1.0/
General-purpose digital I/O pin
TA0CLK/
ACLK/
A0
Timer0_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0(1)
2
1
2
I/O
P1.1/
General-purpose digital I/O pin
TA0.0/
A1
3
4
2
3
3
4
I/O
I/O
Timer0_A, capture: CCI0A input, compare: Out0 output
ADC10 analog input A1(1)
P1.2/
General-purpose digital I/O pin
TA0.1/
A2
Timer0_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A2(1)
P1.3/
General-purpose digital I/O pin
ADC10CLK/
A3/
ADC10, conversion clock output(1)
ADC10 analog input A3(1)
ADC10 negative reference voltage(1)
5
6
4
5
5
6
I/O
I/O
VREF-/VEREF
P1.4/
General-purpose digital I/O pin
TA0.2/
SMCLK/
A4/
Timer0_A, capture: CCI2A input, compare: Out2 output
SMCLK signal output
ADC10 analog input A4(1)
VREF+/VEREF+/
TCK
ADC10 positive reference voltage(1)
JTAG test clock, input terminal for device programming and test
General-purpose digital I/O pin
P1.5/
TA0.0/
A5/
Timer0_A, compare: Out0 output
ADC10 analog input A5(1)
7
8
9
6
7
8
7
I/O
I/O
I/O
SCLK/
TMS
USI: clk input in I2C mode; clk in/output in SPI mode
JTAG test mode select, input terminal for device programming and test
General-purpose digital I/O pin
P1.6/
TA0.1/
A6/
Timer0_A, compare: Out1 output
ADC10 analog input A6(1)
SDO/
SCL/
14
15
USI: Data output in SPI mode
USI: I2C clock in I2C mode
TDI/
JTAG test data input or test clock input during programming and test
TCLK
P1.7/
General-purpose digital I/O pin
ADC10 analog input A7(1)
A7/
SDI/
USI: Data input in SPI mode
SDA/
USI: I2C data in I2C mode
TDO/TDI(2)
JTAG test data output terminal or test data input during programming and test
General-purpose digital I/O pin
P2.0
-
-
-
-
-
-
-
-
-
-
-
-
8
I/O
I/O
I/O
I/O
I/O
I/O
P2.1
9
General-purpose digital I/O pin
P2.2
10
11
12
13
General-purpose digital I/O pin
P2.3
General-purpose digital I/O pin
P2.4
General-purpose digital I/O pin
P2.5
General-purpose digital I/O pin
(1) Available only on MSP430G2x32 devices.
(2) TDO or TDI is selected via JTAG instruction.
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
14
NO.
16
I/O
DESCRIPTION
NAME
20
N, PW RSA N, PW
XIN/
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
Output terminal of crystal oscillator(3)
General-purpose digital I/O pin
Reset
P2.6/
TA0.1
XOUT/
P2.7
13
12
10
12
11
9
19
18
16
I/O
I/O
I
RST/
NMI/
Nonmaskable interrupt input
SBWTDIO/
TEST/
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
11
10
17
I
SBWTCK
DVCC
AVCC
DVSS
AVSS
Spy-Bi-Wire test clock input during programming and test
1
NA
14
NA
-
16
15
14
13
-
1
NA
20
NA
-
NA
NA
NA
NA
NA
NA
Supply voltage
Supply voltage
Ground reference
Ground reference
NC
Not connected
QFN Pad
-
Pad
-
QFN package pad connection to VSS recommended.
(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
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MSP430G2x32
MSP430G2x02
www.ti.com
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
SHORT-FORM DESCRIPTION
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
Stack Pointer
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Status Register
The CPU is integrated with 16 registers that provide
Constant Generator
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
R6
R7
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
R8
R9
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
R10
R11
R12
R13
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
R14
R15
Table 3. Instruction Word Formats
FORMAT
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
R4 + R5 —> R5
PC —>(TOS), R8—> PC
Jump-on-equal bit = 0
Table 4. Address Mode Descriptions(1)
ADDRESS MODE
Register
S
D
✓
✓
✓
✓
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
✓
✓
✓
✓
✓
R10 – –> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
M(2+R5) – –> M(6+R6)
M(EDE) – –> M(TONI)
M(MEM) – –> M(TCDAT)
M(R10) – –> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) – –> R11
R10 + 2 – –> R10
Indirect autoincrement
Immediate
✓
✓
MOV @Rn+,Rm
MOV #X,TONI
#45 – –> M(TONI)
(1) S = source, D = destination
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
www.ti.com
Operating Modes
The MSP430 devices have one active mode and five software selectable low-power modes of operation. An
interrupt event can wake up the device from any of the low-power modes, service the request, and restore back
to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
•
•
Low-power mode 1 (LPM1)
–
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
DCO's dc generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator remains enabled
ACLK remains active
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
–
–
–
–
–
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO's dc generator is disabled
Crystal oscillator is stopped
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MSP430G2x02
www.ti.com
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range(1)
PORIFG
RSTIFG
WDTIFG
KEYV(2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
ACCVIFG(2)(3)
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
29
28
27
26
25
Watchdog Timer+
Timer0_A3
WDTIFG
TACCR0 CCIFG(4)
maskable
maskable
Timer0_A3
TACCR2 TACCR1 CCIFG.
TAIFGTable 3(4)
maskable
0FFF0h
24
0FFEEh
0FFECh
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
23
22
21
20
19
18
17
16
ADC10(5)
USI
ADC10IFG(4)(5)
maskable
maskable
maskable
maskable
USIIFG, USISTTIFG(2)(4)
P2IFG.0 to P2IFG.7(2)(4)
P1IFG.0 to P1IFG.7(2)(4)
I/O Port P2 (up to eight flags)
I/O Port P1 (up to eight flags)
(6)
See
0FFDEh to
0FFC0h
15 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) MSP430G2x32 only
(6) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw-0
NMIIE
rw-0
OFIE
rw-0
WDTIE
rw-0
WDTIE
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
OFIE
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
Address
7
6
5
4
3
2
1
0
01h
Table 7. Interrupt Flag Register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw-0
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFG
rw-1
WDTIFG
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
PORIFG
RSTIFG
NMIIFG
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
Address
03h
7
6
5
4
3
2
1
0
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Memory Organization
Table 8. Memory Organization
MSP430G2102
MSP430G2132
MSP430G2202
MSP430G2232
MSP430G2302
MSP430G2332
MSP430G2402
MSP430G2432
Memory
Size
Flash
Flash
Size
1kB
2kB
4kB
8kB
Main: interrupt vector
Main: code memory
Information memory
0xFFFF to 0xFFC0
0xFFFF to 0xFC00
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xF800
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xF000
256 Byte
0xFFFF to 0xFFC0
0xFFFF to 0xE000
256 Byte
Flash
Size
010FFh to 01000h
128 B
010FFh to 01000h
256 B
010FFh to 01000h
256 B
010FFh to 01000h
256 B
RAM
0x027F to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
0x02FF to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
0x02FF to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
0x02FF to 0x0200
01FFh to 0100h
0FFh to 010h
0Fh to 00h
Peripherals
16-bit
8-bit
8-bit SFR
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
•
Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
•
•
•
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
Calibration Data Stored in Information Memory Segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.
Table 9. Tags Used by the ADC Calibration Tags
NAME
ADDRESS
0x10F6
0x10DA
-
VALUE
0x01
DESCRIPTION
DCO frequency calibration at VCC = 3 V and TA = 30°C at calibration
ADC10_1 calibration tag
TAG_DCO_30
TAG_ADC10_1
TAG_EMPTY
0x08
0xFE
Identifier for empty memory areas
Table 10. Labels Used by the ADC Calibration Tags
LABEL
CONDITION AT CALIBRATION / DESCRIPTION
SIZE
word
word
word
word
word
word
word
word
byte
byte
byte
byte
byte
byte
byte
byte
ADDRESS OFFSET
0x0010
CAL_ADC_25T85
CAL_ADC_25T30
INCHx = 0x1010, REF2_5 = 1, TA = 85°C
INCHx = 0x1010, REF2_5 = 1, TA = 30°C
0x000E
0x000C
0x000A
0x0008
CAL_ADC_25VREF_FACTOR
CAL_ADC_15T85
REF2_5 = 1, TA = 30°C, I(VREF+) = 1 mA
INCHx = 0x1010, REF2_5 = 0, TA = 85°C
CAL_ADC_15T30
INCHx = 0x1010, REF2_5 = 0, TA = 30°C
CAL_ADC_15VREF_FACTOR
CAL_ADC_OFFSET
CAL_ADC_GAIN_FACTOR
CAL_BC1_1MHz
REF2_5 = 0, TA = 30°C, I(VREF+) = 0.5 mA
0x0006
External VREF = 1.5 V, f(ADC10CLK) = 5 MHz
0x0004
External VREF = 1.5 V, f(ADC10CLK) = 5 MHz
0x0002
-
-
-
-
-
-
-
-
0x0009
CAL_DCO_1MHz
0x00008
0x0007
CAL_BC1_8MHz
CAL_DCO_8MHz
0x0006
CAL_BC1_12MHz
0x0005
CAL_DCO_12MHz
CAL_BC1_16MHz
0x0004
0x0003
CAL_DCO_16MHz
0x0002
12
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Main DCO Characteristics
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
•
•
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × f
× f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
f
=
average
MOD × f
+ (32 – MOD) × f
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are two 8-bit I/O ports implemented:
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition(port P1 and port P2 only) is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and port P2, if available.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
Each I/O has an individually programmable pin-oscillator enable bit to enable low-cost touch sensing.
WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
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Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 11. Timer0_A3 Signal Connections(1)
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
N20, PW20
PW14
RSA16
N20, PW20
PW14
RSA16
P1.0-2
P1.0-2
P1.0-1
TACLK
ACLK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
SMCLK
PinOsc
P1.1-3
PinOsc
P1.1-3
PinOsc
P1.1-2
TA0.0
ACLK
VSS
P1.2-4
P1.5-7
P1.1-3
P1.5-7
P1.1-2
P1.5-6
CCR0
CCR1
CCR2
TA0
TA1
TA2
VCC
VCC
P1.2-4
P1.2-4
P1.2-3
TA0.1
VSS
CCI1A
GND
P1.2-4
P1.2-4
P1.2-3
P2.6-19
P2.6-12
P2.6-12
VCC
VCC
P1.4-6
PinOsc
P1.4-6
PinOsc
P1.4-5
PinOsc
TA0.2
TA0.2
VSS
CCI2A
CCI2B
GND
P1.4-6
P1.4-6
P1.4-5
VCC
VCC
(1) Only one pin-oscillator must be enabled at a time.
USI
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430G2x32 only)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
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Peripheral File Map
Table 12. Peripherals With Word Access
REGISTER
NAME
MODULE
REGISTER DESCRIPTION
OFFSET
01BCh
ADC10 (MSP430G2x32 devices only) ADC data transfer start address
ADC10SA
ADC memory
ADC10MEM
ADC10CTL1
ADC10CTL0
TACCR2
TACCR1
TACCR0
TAR
01B4h
01B2h
01B0h
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
012Ch
012Ah
0128h
0120h
ADC control register 1
ADC control register 0
Timer0_A3
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
TACCTL2
TACCTL1
TACCTL0
TACTL
Timer_A interrupt vector
Flash control 3
TAIV
Flash Memory
FCTL3
Flash control 2
FCTL2
Flash control 1
FCTL1
Watchdog Timer+
Watchdog/timer control
WDTCTL
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Table 13. Peripherals With Byte Access
REGISTER
NAME
MODULE
REGISTER DESCRIPTION
OFFSET
04Ah
ADC10 (MSP430G2x32 devices only) Analog enable 0
ADC10AE0
ADC data transfer control register 1
ADC10DTC1
ADC10DTC0
USICTL0
USICTL1
USICKCTL
USICNT
USISR
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P2SEL2
P2REN
P2SEL
P2IE
049h
048h
078h
079h
07Ah
07Bh
07Ch
053h
058h
057h
056h
042h
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
041h
027h
026h
025h
024h
023h
022h
021h
020h
003h
002h
001h
000h
ADC data transfer control register 0
USI control 0
USI
USI control 1
USI clock control
USI bit counter
USI shift register
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P2 selection 2
Port P2 resistor enable
Port P2 selection
Port P2
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
P2IES
P2IFG
P2DIR
Port P2 output
P2OUT
P2IN
Port P2 input
Port P1
Port P1 selection 2
Port P1 resistor enable
Port P1 selection
P1SEL2
P1REN
P1SEL
P1IE
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1IES
P1IFG
P1DIR
Port P1 output
P1OUT
P1IN
Port P1 input
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
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Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS
Voltage applied to any pin(2)
–0.3 V to 4.1 V
–0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device pin
Unprogrammed device
Programmed device
–55°C to 150°C
–40°C to 85°C
(3)
Storage temperature range, Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
MIN NOM
MAX UNIT
During program execution
1.8
2.2
0
3.6
V
VCC
Supply voltage
During flash programming/erase
3.6
VSS
TA
Supply voltage
V
Operating free-air temperature
–40
85
6
°C
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
dc
dc
Processor frequency (maximum MCLK frequency VCC = 2.7 V,
using the USART module)(1)(2)
Duty cycle = 50% ± 10%
fSYSTEM
12 MHz
16
VCC = 3.3 V,
Duty cycle = 50% ± 10%
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
3.3 V 3.6 V
2.7 V
Supply Voltage - V
1.8 V
2.2 V
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
2.2 V
220
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (1 MHz)
IAM,1MHz
µA
3 V
320
400
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics – Active Mode Supply Current (Into VCC)
5.0
4.0
3.0
2.0
1.0
0.0
4.0
3.0
2.0
1.0
0.0
f
= 16 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
V
= 3 V
CC
f
= 12 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
f
= 8 MHz
DCO
2.0
f
= 1 MHz
V
CC
= 2.2 V
DCO
1.5
2.5
3.0
3.5
4.0
0.0
4.0
8.0
12.0
16.0
V
CC
− Supply Voltage − V
f
DCO
− DCO Frequency − MHz
Figure 2. Active Mode Current vs VCC, TA = 25°C
Figure 3. Active Mode Current vs DCO Frequency
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(2)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX UNIT
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Low-power mode 0
(LPM0) current(3)
ILPM0,1MHz
25°C
2.2 V
55
µA
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 2
(LPM2) current(4)
ILPM2
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
Low-power mode 3
(LPM3) current(4)
ILPM3,LFXT1
ILPM3,VLO
ILPM4
25°C
25°C
2.2 V
2.2 V
0.7
0.5
1.0
0.7
µA
µA
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
Low-power mode 3
current, (LPM3)(4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C
85°C
2.2 V
2.2 V
0.1
0.8
0.5
1.5
µA
µA
Low-power mode 4
(LPM4) current(5)
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VCC = 3.6 V
VCC = 3.6 V
VCC = 3 V
VCC = 3 V
VCC = 2.2 V
VCC = 2.2 V
VCC = 1.8 V
VCC = 1.8 V
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
− Temperature −
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
T
C
A
T
A
− Temperature − °C
Figure 4. LPM3 Current vs Temperature
Figure 5. LPM4 Current vs Temperature
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MAX UNIT
Schmitt-Trigger Inputs – Ports Px(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45 VCC
1.35
TYP
0.75 VCC
VIT+
Positive-going input threshold voltage
V
V
3 V
2.25
0.55 VCC
1.65
0.25 VCC
0.75
VIT–
Negative-going input threshold voltage
3 V
3 V
Vhys
RPull
CI
Input voltage hysteresis (VIT+ – VIT–
Pullup/pulldown resistor
Input capacitance
)
0.3
1
V
For pullup: VIN = VSS
For pulldown: VIN = VCC
3 V
20
35
5
50
kΩ
pF
VIN = VSS or VCC
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int)
.
Leakage Current – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
±50 nA
(1) (2)
Ilkg(Px.x)
High-impedance leakage current
3 V
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input, and the pullup/pulldown resistor is
disabled.
Outputs – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –6 mA(1)
I(OLmax) = 6 mA(1)
VCC
3 V
3 V
MIN
TYP
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
V
CC – 0.3
V
V
VSS + 0.3
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Px.y, CL = 20 pF, RL = 1 kΩ(1) (2)
Px.y, CL = 20 pF(2)
VCC
3 V
3 V
MIN
TYP
12
MAX UNIT
MHz
fPx.y
Port output frequency (with load)
Clock output frequency
fPort_CLK
16
MHz
(1) A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
40.0
30.0
20.0
10.0
0.0
30.0
25.0
20.0
15.0
10.0
5.0
V
= 2.2 V
V
= 3 V
CC
CC
T
= 25°C
= 85°C
A
T
= 25°C
= 85°C
P1.7
A
P1.7
T
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 6.
Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
V
= 2.2 V
V
= 3 V
CC
CC
P1.7
P1.7
−10.0
−15.0
−20.0
−25.0
T
A
= 85°C
T
= 85°C
A
T
A
= 25°C
0.5
T
= 25°C
0.5
A
0.0
1.0
1.5
2.0
2.5
0.0
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 8.
Figure 9.
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
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Pin-Oscillator Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
1400
900
MAX UNIT
P1.y, CL = 10 pF, RL = 100 kΩ(1)(2)
P1.y, CL = 20 pF, RL = 100 kΩ(1)(2)
P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ(1)(2)
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ(1)(2)
foP1.x
Port output oscillation frequency
3 V
kHz
1800
1000
foP2.x
Port output oscillation frequency
Port output oscillation frequency
3 V
3 V
kHz
kHz
P2.6 and P2.7, CL = 20 pF, RL = 100
foP2.6/7
700
kΩ(1)(2)
(1) A resistive divider with two 100-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage oscillates with a typical amplitude of 700 mV at the specified toggle frequency.
Typical Characteristics – Pin-Oscillator Frequency
TYPICAL OSCILLATING FREQUENCY
vs
LOAD CAPACITANCE
TYPICAL OSCILLATING FREQUENCY
vs
LOAD CAPACITANCE
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0.00
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0.00
V
CC
= 2.2 V
V
CC
= 3.0 V
P1.y
P1.y
P2.0 ... P2.5
P2.6, P2.7
P2.0 ... P2.5
P2.6, P2.7
10
50
100
10
50
100
C
LOAD
− External Capacitance − pF
C
LOAD
− External Capacitance − pF
Figure 10.
Figure 11.
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MSP430G2x02
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
POR/Brownout Reset (BOR)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
See Figure 12
TEST CONDITIONS
dVCC/dt ≤ 3 V/s
VCC
MIN
TYP
MAX UNIT
VCC(start)
V(B_IT–)
Vhys(B_IT–)
td(BOR)
0.7 × V(B_IT–)
1.40
V
V
See Figure 12 through Figure 14
See Figure 12
dVCC/dt ≤ 3 V/s
dVCC/dt ≤ 3 V/s
140
mV
See Figure 12
2000
µs
Pulse length needed at RST/NMI pin to
accepted reset internally
t(reset)
2.2 V
2
µs
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–)
+
Vhys(B_IT–)is ≤ 1.8 V.
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage
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MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
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Typical Characteristics – POR/Brownout Reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
Typical Conditions
CC
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
t
CC
pw
2
1.5
1
3 V
V
= 3 V
CC
Typical Conditions
V
CC(drop)
0.5
t = t
f
r
0
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.8
2.2
3
TYP
MAX UNIT
RSELx < 14
RSELx = 14
RSELx = 15
3.6
3.6
3.6
V
V
V
VCC
Supply voltage
fDCO(0,0)
fDCO(0,3)
fDCO(1,3)
fDCO(2,3)
fDCO(3,3)
fDCO(4,3)
fDCO(5,3)
fDCO(6,3)
fDCO(7,3)
fDCO(8,3)
fDCO(9,3)
fDCO(10,3)
fDCO(11,3)
fDCO(12,3)
fDCO(13,3)
fDCO(14,3)
fDCO(15,3)
fDCO(15,7)
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
0.06
0.07
0.14 MHz
0.17 MHz
MHz
0.15
0.21
0.30
0.41
0.58
MHz
MHz
MHz
MHz
0.54
0.80
1.06 MHz
1.50 MHz
MHz
1.6
2.3
MHz
3.4
MHz
4.25
MHz
4.30
6.00
8.60
12.0
16.0
7.30 MHz
9.60 MHz
13.9 MHz
18.5 MHz
26.0 MHz
Frequency step between
range RSEL and RSEL+1
SRSEL
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3 V
1.35
ratio
Frequency step between
tap DCO and DCO+1
SDCO
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
Measured at SMCLK output
3 V
3 V
1.08
50
ratio
%
Duty cycle
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MAX UNIT
Calibrated DCO Frequencies – Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
1-MHz tolerance over
temperature(1)
0°C to 85°C
3 V
-3
±0.5
+3
+3
+6
+3
+3
+6
+3
+3
+6
+3
+3
+6
%
%
%
%
%
%
%
%
%
%
%
%
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
1-MHz tolerance over VCC
1-MHz tolerance overall
30°C
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
-3
-6
-3
-3
-6
-3
-3
-6
-3
-3
-6
±2
±3
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
0°C to 85°C
30°C
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
8-MHz tolerance over
temperature(1)
±0.5
±2
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
8-MHz tolerance over VCC
8-MHz tolerance overall
2.2 V to 3.6 V
2.2 V to 3.6 V
3 V
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
0°C to 85°C
30°C
±3
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
12-MHz tolerance over
temperature(1)
±0.5
±2
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
12-MHz tolerance over VCC
12-MHz tolerance overall
2.7 V to 3.6 V
2.7 V to 3.6 V
3.3 V
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
0°C to 85°C
30°C
±3
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
16-MHz tolerance over
temperature(1)
±0.5
±2
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
16-MHz tolerance over VCC
16-MHz tolerance overall
3.3 V to 3.6 V
3.3 V to 3.6 V
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
±3
(1) This is the frequency change from the measured frequency at 30°C over temperature.
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DCO clock wake-up time from
LPM3/4(1)
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
tDCO,LPM3/4
tCPU,LPM3/4
3 V
1.5
µs
1/fMCLK
+
CPU wake-up time from LPM3/4(2)
tClock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
DCO Frequency − MHz
Figure 15. DCO Wake-Up Time From LPM3 vs DCO Frequency
10.00
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
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Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32768
Hz
LFXT1 oscillator logic level
fLFXT1,LF,logic
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
1.8 V to 3.6 V 10000
32768 50000
Hz
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
200
Oscillation allowance for
LF crystals
OALF
kΩ
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
8.5
11
Integrated effective load
capacitance, LF mode(2)
CL,eff
pF
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
Duty cycle
fFault,LF
LF mode
2.2 V
2.2 V
30
10
50
70
%
Oscillator fault frequency,
LF mode(3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3(4)
10000
Hz
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
TA
VCC
3 V
MIN
TYP
12
MAX UNIT
20 kHz
%/°C
fVLO
-40°C to 85°C
-40°C to 85°C
25°C
4
dfVLO/dT
dfVLO/dVCC
VLO frequency temperature drift
VLO frequency supply voltage drift
3 V
0.5
4
1.8 V to 3.6 V
%/V
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
SMCLK
Duty cycle = 50% ± 10%
fTA
Timer_A input clock frequency
Timer_A capture timing
fSYSTEM
MHz
ns
tTA,cap
TA0, TA1
3 V
20
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
USI, Universal Serial Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
External: SCLK,
Duty cycle = 50% ± 10%
fUSI
USI module clock frequency
fSYSTEM
MHz
f(SCLK)
VOL,I2C
Serial clock frequency, slave mode
Low-level output voltage on SDA and SCL
SPI slave mode
3 V
3 V
6
MHz
V
USI module in I2C mode,
I(OLmax) = 1.5 mA
VSS
+ 0.4
VSS
Typical Characteristics – USI Low-Level Output Voltage on SDA and SCL
5.0
5.0
4.0
3.0
2.0
1.0
0.0
V
CC
= 2.2 V
V
CC
= 3 V
T
= 25°C
A
4.0
3.0
2.0
1.0
0.0
T
= 25°C
A
T
= 85°C
A
T
= 85°C
A
0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 16. USI Low-Level Output Voltage vs Output
Current
Figure 17. USI Low-Level Output Voltage vs Output
Current
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
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MAX UNIT
10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x32 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VSS = 0 V
TA
VCC
3 V
3 V
MIN
TYP
VCC
VAx
Analog supply voltage
2.2
3.6
V
V
All Ax terminals, Analog inputs
selected in ADC10AE register
Analog input voltage(2)
ADC10 supply current(3)
0
VCC
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
IADC10
25°C
25°C
0.6
mA
mA
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
0.25
0.25
Reference supply current,
reference buffer disabled(4)
IREF+
3 V
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,
Reference buffer supply
ADC10ON = 0, REFON = 1,
IREFB,0
25°C
25°C
3 V
3 V
1.1
0.5
mA
mA
current with ADC10SR = 0(4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
Reference buffer supply
IREFB,1
current with ADC10SR = 1(4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
Only one terminal Ax can be selected
CI
RI
Input capacitance
at one time
25°C
25°C
3 V
3 V
27
pF
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
1000
Ω
(1) The leakage current is defined in the leakage current table with Px.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC10
.
(4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
10-Bit ADC, Built-In Voltage Reference (MSP430G2x32 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF+ ≤ 1 mA, REF2_5V = 0
VCC
MIN
2.2
TYP
MAX UNIT
I
I
I
I
Positive built-in reference
analog supply voltage range
VCC,REF+
V
VREF+ ≤ 1 mA, REF2_5V = 1
2.9
VREF+ ≤ IVREF+max, REF2_5V = 0
VREF+ ≤ IVREF+max, REF2_5V = 1
1.41
2.35
1.5
2.5
1.59
V
Positive built-in reference
voltage
VREF+
3 V
3 V
2.65
Maximum VREF+ load
current
ILD,VREF+
±1
±2
mA
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 0.75 V,
REF2_5V = 0
VREF+ load regulation
3 V
3 V
LSB
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 1.25 V,
REF2_5V = 1
±2
IVREF+ = 100 µA→900 µA,
VAx ≉ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
VREF+ load regulation
response time
400
ns
ADC10SR = 0
Maximum capacitance at
pin VREF+
CVREF+
TCREF+
I
VREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3 V
3 V
100
pF
ppm/
°C
Temperature coefficient
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
±100
Settling time of internal
reference voltage to 99.9%
VREF
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
tREFON
3.6 V
3 V
30
2
µs
µs
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
Settling time of reference
buffer to 99.9% VREF
tREFBURST
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MAX UNIT
10-Bit ADC, External Reference(1) (MSP430G2x32 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
1.4
VCC
Positive external reference input
voltage range(2)
VEREF+
V
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1
1.4
0
3
(3)
Negative external reference input
voltage range(4)
VEREF–
ΔVEREF
VEREF+ > VEREF–
1.2
V
V
Differential external reference
input voltage range,
(5)
VEREF+ > VEREF–
1.4
VCC
ΔVEREF = VEREF+ – VEREF–
0 V ≤ VEREF+ ≤ VCC
SREF1 = 1, SREF0 = 0
,
±1
IVEREF+
Static input current into VEREF+
3 V
3 V
µA
µA
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
0
SREF1 = 1, SREF0 = 1(3)
IVEREF–
Static input current into VEREF–
0 V ≤ VEREF– ≤ VCC
±1
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters (MSP430G2x32 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45
0.45
TYP
MAX
6.3
UNIT
ADC10SR = 0
ADC10SR = 1
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10CLK
fADC10OSC
3 V
MHz
1.5
ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,
3 V
3 V
3.7
6.3
MHz
µs
frequency
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
2.06
3.51
tCONVERT
Conversion time
13 ×
fADC10CLK from ACLK, MCLK, or SMCLK:
ADC10DIV ×
1/fADC10CLK
ADC10SSELx ≠ 0
Turn-on settling time of
the ADC
(1)
tADC10ON
100
ns
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
10-Bit ADC, Linearity Parameters (MSP430G2x32 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integral linearity error
Differential linearity error
Offset error
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
3 V
MIN
TYP
MAX UNIT
±1 LSB
±1 LSB
±1 LSB
±2 LSB
±5 LSB
EI
ED
EO
EG
ET
Source impedance RS < 100 Ω
Gain error
±1.1
±2
Total unadjusted error
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MSP430G2x02
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x32 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
3 V
3 V
MIN
TYP
60
MAX UNIT
Temperature sensor supply
current(1)
REFON = 0, INCHx = 0Ah,
TA = 25°C
ISENSOR
TCSENSOR
tSensor(sample)
IVMID
µA
mV/°C
µs
(2)
ADC10ON = 1, INCHx = 0Ah
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3.55
Sample time required if channel
30
(3)
10 is selected
(4)
Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh
µA
ADC10ON = 1, INCHx = 0Bh,
VCC divider at channel 11
VMID
1.5
V
V
MID ≉ 0.5 × VCC
Sample time required if channel
11 is selected
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
3 V
1220
ns
(5)
(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
(2) The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
(4) No additional current is needed. The VMID is used during sampling.
.
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
TYP
MAX UNIT
3.6
476 kHz
VCC(PGM/ERASE)
fFTG
Program and erase supply voltage
Flash timing generator frequency
Supply current from VCC during program
Supply current from VCC during erase
Cumulative program time(1)
V
257
IPGM
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
1
1
5
7
mA
mA
IERASE
tCPT
10
ms
tCMErase
Cumulative mass erase time
Program/erase endurance
20
104
100
ms
105
cycles
years
tFTG
tFTG
tRetention
tWord
Data retention duration
TJ = 25°C
(2)
Word or byte program time
30
25
(2)
(2)
tBlock, 0
Block program time for first byte or word
Block program time for each additional
byte or word
tBlock, 1-63
18
tFTG
(2)
(2)
(2)
tBlock, End
tMass Erase
tSeg Erase
Block program end-sequence wait time
Mass erase time
6
10593
4819
tFTG
tFTG
tFTG
Segment erase time
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
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MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
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RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
(1)
V(RAMh)
RAM retention supply voltage
1.6
V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0
TYP
MAX
20
UNIT
MHz
µs
fSBW
Spy-Bi-Wire input frequency
2.2 V
2.2 V
tSBW,Low Spy-Bi-Wire low clock pulse length
0.025
15
Spy-Bi-Wire enable time
tSBW,En
2.2 V
1
µs
(TEST high to acceptance of first clock edge(1)
)
tSBW,Ret
fTCK
Spy-Bi-Wire return to normal operation time
TCK input frequency(2)
2.2 V
2.2 V
2.2 V
15
0
100
5
µs
MHz
kΩ
RInternal
Internal pulldown resistance on TEST
25
60
90
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
2.5
6
MAX
UNIT
V
VCC(FB)
VFB
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse blow
Supply current into TEST during fuse blow
Time to blow fuse
7
100
1
V
IFB
mA
ms
tFB
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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MSP430G2x02
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
PIN SCHEMATICS
Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
0
2
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Module
2
3
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/A0*
P1.1/TA0.0/A1*
P1.2/TA0.1/A2*
0
TAx.y
TAxCLK
PxIN.y
EN
To Module
PxIRQ.y
D
PxIE.y
EN
Set
Q
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
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Table 14. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P1.x)
x
FUNCTION
ADC10AE.x
(INCH.y=1)(2)
P1DIR.x
P1SEL.x
P1SEL2.x
P1.0/
P1.x (I/O)
TA0.TACLK
ACLK
I: 0; O: 1
0
1
1
X
0
0
1
1
X
0
0
1
1
X
0
0
0
0
X
1
0
0
0
X
1
0
0
0
X
1
0
TA0CLK/
ACLK/
0
0
0
1
0
A0(2)
/
A0
X
1 (y = 0)
Pin Osc
P1.1/
Capacitive sensing
P1.x (I/O)
TA0.0
x
0
I: 0; O: 1
0
TA0.0/
1
0
1
2
TA0.CCI0A
A1
0
0
A1(2)
/
X
1 (y = 1)
Pin Osc
P1.2/
Capacitive sensing
P1.x (I/O)
TA0.1
X
0
I: 0; O: 1
0
TA0.1/
1
0
0
TA0.CCI1A
A2
0
1 (y = 2)
0
A2(2)
Pin Osc
/
X
X
Capacitive sensing
(1) X = don't care
(2) MSP430G2x32 devices only
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MSP430G2x02
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger
SREF2 *
VSS
0
1
To ADC10 VREF- *
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxDIR.y
PxSEL2.y PxSEL.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From ADC10 *
2
3
Bus
Keeper
EN
P1.3/ADC10CLK*/A3*/VREF-*/VEREF-*
TAx.y
TAxCLK
PxIN.y
EN
To Module
PxIRQ.y
D
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
Table 15. Port P1 (P1.3) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P1.x)
x
FUNCTION
P1DIR.x
ADC10AE.x
(INCH.x=1)(2)
P1SEL.x
P1SEL2.x
P1.3/
ADC10CLK(2)
A3(2)
VREF-(2)
P1.x (I/O)
ADC10CLK
A3
I: 0; O: 1
0
1
0
0
0
/
1
X
X
X
X
0
/
X
X
X
0
X
X
X
1
1 (y = 3)
3
/
VREF-
1
1
0
VEREF-(2)
/
VEREF-
Pin Osc
Capacitive sensing
(1) X = don't care
(2) MSP430G2x32 devices only
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
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Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger
From/To ADC10 Ref+ *
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
SMCLK
0
1
2
3
Bus
Keeper
EN
P1.4/SMCLK/TA0.2/A4*/VREF+*/VEREF+*/TCK
from Timer
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
Table 16. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P1.x)
x
FUNCTION
ADC10AE.x
(INCH.x=1)(2)
P1DIR.x
P1SEL.x
P1SEL2.x
JTAG Mode
CAPD.y
P1.4/
P1.x (I/O)
I: 0; O: 1
0
1
1
1
X
X
X
X
0
0
0
1
1
X
X
X
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
SMCLK/
TA0.2/
SMCLK
TA0.2
1
1
0
0
TA0.CCI2A
VREF+
0
0
VREF+(2)
/
4
X
X
X
X
X
1
VEREF+(2)
A4(2)
/
VEREF+
A4
1
/
1 (y = 4)
TCK/
TCK
0
0
Pin Osc
Capacitive sensing
(1) X = don't care
(2) MSP430G2x32 devices only
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MSP430G2x02
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Module
2
3
Bus
Keeper
EN
P1.5/TA0.0/SCLK/A5*/TMS
P1.6/TA0.1/SDO/SCL/A6*/TDI/TCLK
P1.7//SDI/SDA/A7*/TDO/TDI
0
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
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MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
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Table 17. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P1.x)
x
FUNCTION
ADC10AE.x
(INCH.x=1)(2)
P1DIR.x
P1SEL.x
P1SEL2.x
USIP.x
JTAG Mode
P1.5/
P1.x (I/O)
I: 0; O: 1
0
1
1
X
X
0
0
1
1
1
X
X
0
0
1
1
X
X
0
0
0
0
X
X
1
0
0
0
0
X
X
1
0
0
0
X
X
1
0
0
1
0
0
0
0
0
!
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
TA0.0/
SCLK/
TA0.0
1
0
SPI mode
A5
from USI
0
5
A5(2)
/
X
1 (y = 5)
TMS/
TMS
X
0
Pin Osc
P1.6/
Capacitive sensing
P1.x (I/O)
TA0.1
X
0
I: 0; O: 1
0
TA0.1/
SDO/
SCL/
1
0
SPI mode
I2C mode
A6
from USI
0
6
from USI
!
0
A6(2)
/
X
0
0
0
0
1
1
0
0
0
1 (y = 6)
TDI/TCLK/
Pin Osc
P1.7/
TDI/TCLK
Capacitive sensing
P1.x (I/O)
SPI mode
SPI mode
A7
X
0
X
0
I: 0; O: 1
0
SDI/
from USI
0
SDO/
from USI
0
7
A7(2)
/
X
X
X
1 (y = 7)
TDO/TDI/
Pin Osc
TDO/TDI
Capacitive sensing
0
0
(1) X = don't care
(2) MSP430G2x32 devices only
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MSP430G2x02
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SLAS723B –DECEMBER 2010–REVISED MARCH 2011
Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
0
2
3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
0
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 18. Port P2 (P2.0 to P2.5) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P2.x)
x
0
1
2
3
4
5
FUNCTION
P2DIR.x
I: 0; O: 1
P2SEL.x
P2SEL2.x
P2.0/
P2.x (I/O)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Pin Osc
P2.1/
Capacitive sensing
P2.x (I/O)
X
I: 0; O: 1
Pin Osc
P2.2/
Capacitive sensing
P2.x (I/O)
X
I: 0; O: 1
Pin Osc
P2.3/
Capacitive sensing
P2.x (I/O)
X
I: 0; O: 1
Pin Osc
P2.4/
Capacitive sensing
P2.x (I/O)
X
I: 0; O: 1
X
Pin Osc
P2.5/
Capacitive sensing
P2.x (I/O)
I: 0; O: 1
X
Pin Osc
Capacitive sensing
(1) X = don't care
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MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
XOUT/P2.7
LF off
PxSEL.6 & PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
LFXT1CLK
1
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Module
2
3
XIN/P2.6/TA0.1
0
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 19. Port P2 (P2.6) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P2.x)
x
FUNCTION
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
P2DIR.x
1
1
0
0
XIN/
XIN
0
0
X
0
0
P2.6/
P2.x (I/O)
I: 0; O: 1
6
1
0
0
0
TA0.1/
Timer0_A3.TA1
Capacitive sensing
1
0
X
1
X
Pin Osc
X
(1) X = don't care
42
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Copyright © 2010–2011, Texas Instruments Incorporated
MSP430G2x32
MSP430G2x02
www.ti.com
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
XIN/P2.6/TA0.1
LF off
PxSEL.6 & PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
LFXT1CLK
1
from P2.6
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
0
1
1
PxOUT.y
0
1
From Module
2
3
XOUT/P2.7
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIRQ.y
PxIE.y
EN
Set
Q
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 20. Port P2 (P2.7) Pin Functions
CONTROL BITS / SIGNALS(1)
PIN NAME
(P2.x)
x
FUNCTION
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
P2DIR.x
1
1
0
0
XOUT/
XOUT
X
I: 0; O: 1
X
0
X
0
0
P2.7/
7
P2.x (I/O)
0
X
1
X
Pin Osc
Capacitive sensing
(1) X = don't care
Copyright © 2010–2011, Texas Instruments Incorporated
Submit Documentation Feedback
43
MSP430G2x32
MSP430G2x02
SLAS723B –DECEMBER 2010–REVISED MARCH 2011
www.ti.com
REVISION HISTORY
REVISION
DESCRIPTION
SLAS723
Initial release
Page 1, Changed Internal Frequencies up to 16 MHz With One Calibrated Frequency to Internal Frequencies up
to 16 MHz With Four Calibrated Frequencies
SLAS723A
Added note concerning pulldown resistor to PW14 and RSA16 pinout drawings.
Removed reference to CAOUT from N20, PW20 pinout drawing and Table 11 (there is no comparator module on
this device).
SLAS723B
Added "N20, PW20" to Input Pin Number and Output Pin Number columns in Table 11.
Corrected pin numbers for P1.0 to P1.3 for PW14 package in Table 2.
44
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Copyright © 2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2102IN20
MSP430G2102IPW14
ACTIVE
ACTIVE
PDIP
N
20
14
20
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2102IPW14R
MSP430G2102IPW20
MSP430G2102IPW20R
MSP430G2102IRSA16R
MSP430G2102IRSA16T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
14
20
20
16
16
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RSA
RSA
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2132IN20
MSP430G2132IPW14
ACTIVE
ACTIVE
PDIP
N
20
14
20
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2132IPW14R
MSP430G2132IPW20
MSP430G2132IPW20R
MSP430G2132IRSA16R
MSP430G2132IRSA16T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
14
20
20
16
16
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RSA
RSA
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2202IN20
MSP430G2202IPW14
ACTIVE
ACTIVE
PDIP
N
20
14
20
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2202IPW14R
MSP430G2202IPW20
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
14
20
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2202IPW20R
MSP430G2202IRSA16R
MSP430G2202IRSA16T
TSSOP
QFN
PW
RSA
RSA
20
16
16
2000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
QFN
Green (RoHS
& no Sb/Br)
MSP430G2232IN20
MSP430G2232IPW14
ACTIVE
ACTIVE
PDIP
N
20
14
20
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2232IPW14R
MSP430G2232IPW20
MSP430G2232IPW20R
MSP430G2232IRSA16R
MSP430G2232IRSA16T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
14
20
20
16
16
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RSA
RSA
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2302IN20
MSP430G2302IPW14
ACTIVE
ACTIVE
PDIP
N
20
14
20
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2302IPW14R
MSP430G2302IPW20
MSP430G2302IPW20R
MSP430G2302IRSA16R
MSP430G2302IRSA16T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
14
20
20
16
16
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RSA
RSA
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2332IN20
MSP430G2332IPW14
ACTIVE
ACTIVE
PDIP
N
20
14
20
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
MSP430G2332IPW14R
MSP430G2332IPW20
MSP430G2332IPW20R
MSP430G2332IRSA16R
MSP430G2332IRSA16T
TSSOP
TSSOP
TSSOP
QFN
PW
PW
14
20
20
16
16
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RSA
RSA
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2402IN20
MSP430G2402IPW14
ACTIVE
ACTIVE
PDIP
N
20
14
20
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2402IPW14R
MSP430G2402IPW20
MSP430G2402IPW20R
MSP430G2402IRSA16R
MSP430G2402IRSA16T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
14
20
20
16
16
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RSA
RSA
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
MSP430G2432IN20
MSP430G2432IPW14
ACTIVE
ACTIVE
PDIP
N
20
14
20
90
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
MSP430G2432IPW14R
MSP430G2432IPW20
MSP430G2432IPW20R
MSP430G2432IRSA16R
MSP430G2432IRSA16T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
PW
PW
14
20
20
16
16
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RSA
RSA
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2011
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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