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MSP430G2553-Q1, MSP430G2453-Q1

SLAS966 –MARCH 2014

MSP430G2x53 Automotive Mixed-Signal Microcontrollers

1 Features

•

Package Options

TSSOP: 20 Pin or 28 Pin

–

1

•

Qualified for Automotive Applications

Low Supply-Voltage Range: 1.8 V to 3.6 V

Ultra-Low-Power Consumption

•

For Complete Module Descriptions, See the

MSP430x2xx Family User’s Guide (SLAU144)

–

Active Mode: 230 µA at 1 MHz, 2.2 V

Standby Mode: 0.5 µA

2 Applications

•

Power Management

Sensor Interface

Capacitive Touch

Off Mode (RAM Retention): 0.1 µA

•

Five Power-Saving Modes

Ultra-Fast Wakeup From Standby Mode in Less

Than 1 µs

3 Description

•

16-Bit RISC Architecture, 62.5-ns Instruction

Cycle Time

The Texas Instruments MSP430™ family of ultra-low-

power microcontrollers consists of several devices

featuring different sets of peripherals targeted for

various applications. The architecture, combined with

five low-power modes, is optimized to achieve

extended battery life in portable measurement

applications. The device features a powerful 16-bit

RISC CPU, 16-bit registers, and constant generators

that contribute to maximum code efficiency. The

digitally controlled oscillator (DCO) allows the device

to wake up from low-power modes to active mode in

less than 1 µs.

Basic Clock Module Configurations

–

Internal Frequencies up to 16 MHz With Four

Calibrated Frequency

–

Internal Very-Low-Power Low-Frequency (LF)

Oscillator

–

32-kHz Crystal

External Digital Clock Source

•

Two 16-Bit Timer_A With Three Capture/Compare

Registers

The MSP430G2x53 series are ultra-low-power mixed

signal microcontrollers with built-in 16-bit timers, up to

24 I/O capacitive-touch enabled pins, a versatile

analog comparator, a 10-bit analog-to-digital (A/D)

converter, and built-in communication capability using

the universal serial communication interface. For

configuration details, see Table 1.

•

Up to 24 Capacitive-Touch Enabled I/O Pins

Universal Serial Communication Interface (USCI)

–

Enhanced UART Supports Automatic Baud-

Rate Detection (LIN)

–

IrDA Encoder and Decoder

Synchronous SPI

I²C

Typical applications include low-cost sensor systems

that capture analog signals, convert them to digital

values, and then process the data for display or for

transmission to a host system.

•

On-Chip Comparator for Analog Signal Compare

Function or Slope Analog-to-Digital (A/D)

Conversion

Device Information⁽¹⁾

10-Bit 200-ksps Analog-to-Digital Converter (ADC)

With Internal Reference, Sample-and-Hold, and

Autoscan

PACKAGE

(PIN)

ORDER NUMBER

BODY SIZE

MSP430G2553IPW8RQ1

MSP430G2553IPW0RQ1

PW (28)

PW (20)

9.7 mm x 4.4 mm

6.5 mm x 4.4 mm

•

Brownout Detector

Serial Onboard Programming,

No External Programming Voltage Needed,

Programmable Code Protection by Security Fuse

•

On-Chip Emulation Logic With Spy-Bi-Wire

Interface

(1) For the most current part, package, and ordering information,

see the Package Option Addendum at the end of this

document, or see the TI web site at www.ti.com.

Family Members are Summarized in Table 1

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

MSP430G2553-Q1, MSP430G2453-Q1

SLAS966 –MARCH 2014

www.ti.com

4 Functional Block Diagram

XIN XOUT

DVCC

Flash

DVSS

P1.x

8

P2.x

P3.x

8

ACLK

Clock

Port P3

8 I/O

Pullup or

pulldown

resistors

Port P1

8 I/O

Port P2

8 I/O

RAM

512B

ADC

SMCLK

System

Interrupt

capability,

pullup or

pulldown

resistors

Interrupt

capability,

pullup or

pulldown

resistors

16KB

8KB

10-Bit

8 Ch.

Autoscan

1 ch DMA

MCLK

16-MHz

CPU

MAB

MDB

Includes

16 registers

USCI A0

UART, LIN,

IrDA, SPI

Emulation

2BP

Timer0_A3 Timer1_A3

Watchdog

WDT+

Comp_A+

Brownout

Protection

3 CC

Registers

3 CC

Registers

JTAG

Interface

USCI B0

SPI, I2C

8 Channels

15-Bit

Spy-Bi-

Wire

RST/NMI

NOTE: Port P3 is available on 28-pin devices only.

Figure 1. Functional Block Diagram, MSP430G2x53

2

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SLAS966 –MARCH 2014

Table of Contents

9.20 Internal Very-Low-Power Low-Frequency Oscillator

(VLO) ...................................................................... 33

1

2

3

4

5

6

7

Features ................................................................. 1

Applications .......................................................... 1

Description ............................................................ 1

Functional Block Diagram ................................... 2

Revision History ................................................... 3

Device Characteristics ......................................... 4

Terminal Configuration and Functions ............... 5

7.1 20-Pin PW Package (Top View) .............................. 5

7.2 28-Pin PW Package (Top View) .............................. 5

7.3 Terminal Functions .................................................. 6

Detailed Description ............................................. 9

8.1 CPU .......................................................................... 9

8.2 Instruction Set .......................................................... 9

8.3 Operating Modes ................................................... 10

8.4 Interrupt Vector Addresses .................................... 11

8.5 Special Function Registers (SFRs) ........................ 12

8.6 Memory Organization ............................................. 13

8.7 Bootstrap Loader (BSL) ......................................... 13

8.8 Flash Memory ........................................................ 13

8.9 Peripherals ............................................................. 14

Specifications ...................................................... 21

9.1 Absolute Maximum Ratings ................................... 21

9.2 Recommended Operating Conditions .................... 21

9.21 Timer_A ................................................................ 33

9.22 USCI (UART Mode) ............................................. 34

9.23 USCI (SPI Master Mode) ..................................... 34

9.24 USCI (SPI Slave Mode) ....................................... 35

9.25 USCI (I²C Mode) .................................................. 36

9.26 Comparator_A+ .................................................... 36

9.27 Typical Characteristics – Comparator_A+ ........... 37

9.28 10-Bit ADC, Power Supply and Input Range

Conditions ............................................................... 38

9.29 10-Bit ADC, Built-In Voltage Reference ............... 39

9.30 10-Bit ADC, External Reference .......................... 40

9.31 10-Bit ADC, Timing Parameters ........................... 40

9.32 10-Bit ADC, Linearity Parameters ........................ 40

8

9.33 10-Bit ADC, Temperature Sensor and Built-In V_MID

................................................................................. 41

9.34 Flash Memory ...................................................... 41

9.35 RAM ..................................................................... 42

9.36 JTAG and Spy-Bi-Wire Interface .......................... 42

9.37 JTAG Fuse ........................................................... 42

10 I/O Port Schematics ........................................... 43

9

10.1 Port P1 Pin Schematic: P1.0 to P1.2, Input/Output

With Schmitt Trigger ............................................... 43

10.2 Port P1 Pin Schematic: P1.3, Input/Output With

Schmitt Trigger ........................................................ 45

9.3 Active Mode Supply Current Into V_CCExcluding

External Current ...................................................... 22

10.3 Port P1 Pin Schematic: P1.4, Input/Output With

Schmitt Trigger ........................................................ 47

9.4 Typical Characteristics, Active Mode Supply Current

(Into V_CC) ................................................................ 22

10.4 Port P1 Pin Schematic: P1.5 to P1.7, Input/Output

With Schmitt Trigger ............................................... 49

9.5 Low-Power Mode Supply Currents (Into V_CC

)

Excluding External Current ..................................... 23

10.5 Port P2 Pin Schematic: P2.0 to P2.5, Input/Output

With Schmitt Trigger ............................................... 51

9.6 Typical Characteristics, Low-Power Mode Supply

Currents .................................................................. 24

10.6 Port P2 Pin Schematic: P2.6, Input/Output With

Schmitt Trigger ........................................................ 53

9.7 Schmitt-Trigger Inputs, Ports Px ............................ 25

9.8 Leakage Current, Ports Px ..................................... 25

9.9 Outputs, Ports Px ................................................... 25

9.10 Output Frequency, Ports Px ................................. 25

9.11 Typical Characteristics, Outputs .......................... 26

9.12 Pin-Oscillator Frequency – Ports Px .................... 27

10.7 Port P2 Pin Schematic: P2.7, Input/Output With

Schmitt Trigger ........................................................ 55

10.8 Port P3 Pin Schematic: P3.0 to P3.7, Input/Output

With Schmitt Trigger (28-Pin PW and 32-Pin RHB

Packages Only) ....................................................... 57

11 Device and Documentation Support ................ 59

11.1 Device Support .................................................... 59

11.2 Documentation Support ....................................... 62

11.3 Related Links ....................................................... 62

11.4 Community Resources ......................................... 62

11.5 Trademarks .......................................................... 62

11.6 Electrostatic Discharge Caution ........................... 62

11.7 Glossary ............................................................... 62

9.13 Typical Characteristics, Pin-Oscillator Frequency

................................................................................. 27

9.14 POR, BOR ........................................................... 28

9.15 DCO Frequency ................................................... 30

9.16 Calibrated DCO Frequencies, Tolerance ............. 31

9.17 Wakeup From Lower-Power Modes (LPM3 or

LPM4) ..................................................................... 32

9.18 Typical Characteristics, DCO Clock Wakeup Time

From LPM3 or LPM4 .............................................. 32

12 Mechanical, Packaging, and Orderable

9.19 Crystal Oscillator, XT1, Low-Frequency Mode .... 33

Information .......................................................... 62

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Date

Revision

Notes

February 2014

*

Initial release.

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SLAS966 –MARCH 2014

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6 Device Characteristics

Table 1. Family Members⁽¹⁾⁽²⁾

Flash

(KB)

RAM

(B)

COMP_A+

Channel

ADC10

Channel

USCI_A0,

USCI_B0

Package

Type

Device

BSL

EEM

Timer_A

Clock

I/O

LF,

DCO,

VLO

24

16

24

16

28-TSSOP

20-TSSOP

28-TSSOP

20-TSSOP

MSP430G2553

1

16

8

512

2x TA3

8

1

LF,

DCO,

VLO

MSP430G2453

1

2x TA3

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

4

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SLAS966 –MARCH 2014

7 Terminal Configuration and Functions

7.1 20-Pin PW Package (Top View)

DVCC

P1.0/TA0CLK/ACLK/A0/CA0

1

2

20

19

18

17

16

15

14

13

12

11

DVSS

XIN/P2.6/TA0.1

XOUT/P2.7

TEST/SBWTCK

P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1

P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2

P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3

P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK

P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS

P2.0/TA1.0

3

4

PW20

(TOP VIEW)

5

RST/NMI/SBWTDIO

6

P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI

P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK

7

8

P2.5/TA1.2

P2.4/TA1.2

P2.3/TA1.0

P2.1/TA1.1

9

P2.2/TA1.1

10

NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.

7.2 28-Pin PW Package (Top View)

DVCC

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DVSS

P1.0/TA0CLK/ACLK/A0/CA0

XIN/P2.6/TA0.1

P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1

3

XOUT/P2.7

P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2

4

TEST/SBWTCK

P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3

5

RST/NMI/SBWTDIO

P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK

6

P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI

PW28

(TOP VIEW)

P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK

P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS

7

8

P3.7/TA1CLK/CAOUT

P3.6/TA0.2

P3.1/TA1.0

P3.0/TA0.2

P2.0/TA1.0

P2.1/TA1.1

P2.2/TA1.1

P3.2/TA1.1

P3.3/TA1.2

9

10

11

12

13

14

P3.5/TA0.1

P2.5/TA1.2

P2.4/TA1.2

P2.3/TA1.0

P3.4/TA0.0

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7.3 Terminal Functions

Table 2. Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

PW20

PW28

P1.0/

General-purpose digital I/O pin

TA0CLK/

ACLK/

Timer0_A, clock signal TACLK input

ACLK signal output

2

I/O

A0

ADC10 analog input A0

CA0

Comparator_A+, CA0 input

P1.1/

General-purpose digital I/O pin

TA0.0/

Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit

USCI_A0 UART mode: receive data input

USCI_A0 SPI mode: slave data out/master in

ADC10 analog input A1

UCA0RXD/

UCA0SOMI/

A1/

3

4

5

3

I/O

CA1

Comparator_A+, CA1 input

P1.2/

General-purpose digital I/O pin

TA0.1/

Timer0_A, capture: CCI1A input, compare: Out1 output

USCI_A0 UART mode: transmit data output

USCI_A0 SPI mode: slave data in/master out

ADC10 analog input A2

UCA0TXD/

UCA0SIMO/

A2/

4

5

CA2

Comparator_A+, CA2 input

P1.3/

General-purpose digital I/O pin

ADC10CLK/

A3/

ADC10, conversion clock output

ADC10 analog input A3

VREF-/VEREF-/

CA3/

ADC10 negative reference voltage

Comparator_A+, CA3 input

CAOUT

P1.4/

Comparator_A+, output

General-purpose digital I/O pin

SMCLK/

UCB0STE/

UCA0CLK/

A4/

SMCLK signal output

USCI_B0 slave transmit enable

USCI_A0 clock input/output

6

I/O

ADC10 analog input A4

VREF+/VEREF+/

CA4/

ADC10 positive reference voltage

Comparator_A+, CA4 input

TCK

JTAG test clock, input terminal for device programming and test

General-purpose digital I/O pin

P1.5/

TA0.0/

Timer0_A, compare: Out0 output / BSL receive

USCI_B0 clock input/output

UCB0CLK/

UCA0STE/

A5/

7

I/O

USCI_A0 slave transmit enable

ADC10 analog input A5

CA5/

Comparator_A+, CA5 input

TMS

JTAG test mode select, input terminal for device programming and test

6

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SLAS966 –MARCH 2014

Terminal Functions (continued)

Table 2. Terminal Functions (continued)

TERMINAL

NO.

I/O

DESCRIPTION

NAME

PW20

PW28

P1.6/

General-purpose digital I/O pin

Timer0_A, compare: Out1 output

ADC10 analog input A6

TA0.1/

A6/

CA6/

14

22

I/O

Comparator_A+, CA6 input

UCB0SOMI/

UCB0SCL/

TDI/TCLK

P1.7/

USCI_B0 SPI mode: slave out master in

USCI_B0 I²C mode: SCL I²C clock

JTAG test data input or test clock input during programming and test

General-purpose digital I/O pin

A7/

ADC10 analog input A7

CA7/

Comparator_A+, CA7 input

CAOUT/

UCB0SIMO/

UCB0SDA/

TDO/TDI

P2.0/

15

23

I/O

Comparator_A+, output

USCI_B0 SPI mode: slave in master out

USCI_B0 I²C mode: SDA I²C data

JTAG test data output terminal or test data input during programming and test

General-purpose digital I/O pin

8

10

11

12

16

17

18

I/O

TA1.0

P2.1/

Timer1_A, capture: CCI0A input, compare: Out0 output

General-purpose digital I/O pin

9

TA1.1

P2.2/

Timer1_A, capture: CCI1A input, compare: Out1 output

General-purpose digital I/O pin

10

11

12

13

TA1.1

P2.3/

Timer1_A, capture: CCI1B input, compare: Out1 output

General-purpose digital I/O pin

TA1.0

P2.4/

Timer1_A, capture: CCI0B input, compare: Out0 output

General-purpose digital I/O pin

TA1.2

P2.5/

Timer1_A, capture: CCI2A input, compare: Out2 output

General-purpose digital I/O pin

TA1.2

XIN/

Timer1_A, capture: CCI2B input, compare: Out2 output

Input terminal of crystal oscillator

P2.6/

19

27

I/O

General-purpose digital I/O pin

TA0.1

XOUT/

P2.7

Timer0_A, compare: Out1 output

Output terminal of crystal oscillator⁽¹⁾

18

-

26

9

I/O

General-purpose digital I/O pin

P3.0/

General-purpose digital I/O pin

TA0.2

P3.1/

Timer0_A, capture: CCI2A input, compare: Out2 output

General-purpose digital I/O pin

-

8

TA1.0

P3.2/

Timer1_A, compare: Out0 output

General-purpose digital I/O pin

-

13

14

15

TA1.1

P3.3/

Timer1_A, compare: Out1 output

General-purpose digital I/O

-

TA1.2

P3.4/

Timer1_A, compare: Out2 output

General-purpose digital I/O

-

TA0.0

Timer0_A, compare: Out0 output

(1) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

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Terminal Functions (continued)

Table 2. Terminal Functions (continued)

TERMINAL

NO.

I/O

DESCRIPTION

NAME

PW20

PW28

P3.5/

General-purpose digital I/O

-

19

I/O

TA0.1

P3.6/

Timer0_A, compare: Out1 output

General-purpose digital I/O

-

20

21

TA0.2

P3.7/

Timer0_A, compare: Out2 output

General-purpose digital I/O

TA1CLK/

CAOUT

RST/

I/O

Timer1_A, clock signal TACLK input

Comparator_A+, output

Reset

NMI/

16

17

24

25

I

Nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

SBWTDIO

TEST/

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to

TEST.

SBWTCK

AVCC

DVCC

DVSS

Spy-Bi-Wire test clock input during programming and test

Analog supply voltage

NA

1

NA

1

NA

Digital supply voltage

20

NA

28

NA

Ground reference

NC

Not connected

QFN Pad

QFN package pad. Connection to VSS is recommended.

8

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SLAS966 –MARCH 2014

8 Detailed Description

8.1 CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions, are

performed as register operations in conjunction with

seven addressing modes for source operand and four

addressing modes for destination operand.

Instruction Set (continued)

Program Counter

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Stack Pointer

Status Register

The CPU is integrated with 16 registers that provide

reduced instruction execution time. The register-to-

register operation execution time is one cycle of the

CPU clock.

Constant Generator

General-Purpose Register

R5

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register, and

constant generator, respectively. The remaining

registers are general-purpose registers.

R6

R7

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled with

all instructions.

R8

R9

The instruction set consists of the original 51

instructions with three formats and seven address

modes and additional instructions for the expanded

address range. Each instruction can operate on word

and byte data.

R10

R11

R12

R13

8.2 Instruction Set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 3 shows examples of the three types of

instruction formats; Table 4 shows the address

modes.

R14

R15

Table 3. Instruction Word Formats

INSTRUCTION FORMAT

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

EXAMPLE

ADD R4,R5

CALL R8

JNE

OPERATION

R4 + R5 ---> R5

PC -->(TOS), R8--> PC

Jump-on-equal bit = 0

Table 4. Address Mode Descriptions⁽¹⁾

ADDRESS MODE

Register

S

✓

D

✓

SYNTAX

MOV Rs,Rd

EXAMPLE

MOV R10,R11

MOV 2(R5),6(R6)

OPERATION

R10 -- --> R11

Indexed

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM,&TCDAT

MOV @Rn,Y(Rm)

M(2+R5) -- --> M(6+R6)

M(EDE) -- --> M(TONI)

M(MEM) -- --> M(TCDAT)

M(R10) -- --> M(Tab+R6)

Symbolic (PC relative)

Absolute

Indirect

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

M(R10) -- --> R11

R10 + 2-- --> R10

Indirect autoincrement

Immediate

✓

MOV @Rn+,Rm

MOV #X,TONI

#45 -- --> M(TONI)

(1) S = source, D = destination

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8.3 Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the low-power modes, service the request, and restore back to the

low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

•

Active mode (AM)

All clocks are active

Low-power mode 0 (LPM0)

–

•

–

CPU is disabled

ACLK and SMCLK remain active, MCLK is disabled

•

Low-power mode 1 (LPM1)

–

CPU is disabled

ACLK and SMCLK remain active, MCLK is disabled

DCO's dc generator is disabled if DCO not used in active mode

Low-power mode 2 (LPM2)

–

CPU is disabled

MCLK and SMCLK are disabled

DCO's dc generator remains enabled

ACLK remains active

•

Low-power mode 3 (LPM3)

–

CPU is disabled

MCLK and SMCLK are disabled

DCO's dc generator is disabled

ACLK remains active

Low-power mode 4 (LPM4)

–

CPU is disabled

ACLK is disabled

MCLK and SMCLK are disabled

DCO's dc generator is disabled

Crystal oscillator is stopped

10

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8.4 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the

CPU goes into LPM4 immediately after power-up.

Table 5. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

Power-Up

External Reset

Watchdog Timer+

Flash key violation

PC out-of-range⁽¹⁾

PORIFG

RSTIFG

WDTIFG

KEYV⁽²⁾

Reset

0FFFEh

31, highest

NMI

Oscillator fault

Flash memory access violation

NMIIFG

OFIFG

(non)-maskable

0FFFCh

30

ACCVIFG⁽²⁾⁽³⁾

Timer1_A3

TA1CCR0 CCIFG⁽⁴⁾

maskable

0FFFAh

0FFF8h

29

28

TA1CCR2 TA1CCR1 CCIFG,

TAIFG⁽²⁾⁽⁴⁾

maskable

Comparator_A+

Watchdog Timer+

Timer0_A3

CAIFG⁽⁴⁾

maskable

0FFF6h

0FFF4h

0FFF2h

27

26

25

WDTIFG

TA0CCR0 CCIFG⁽⁴⁾

Timer0_A3

TA0CCR2 TA0CCR1 CCIFG, TAIFG

maskable

0FFF0h

0FFEEh

0FFECh

0FFEAh

24

23

22

21

(5)(4)

USCI_A0/USCI_B0 receive

USCI_B0 I²C status

UCA0RXIFG, UCB0RXIFG⁽²⁾⁽⁵⁾

UCA0TXIFG, UCB0TXIFG⁽²⁾⁽⁶⁾

ADC10IFG⁽⁴⁾

USCI_A0/USCI_B0 transmit

USCI_B0 I²C receive/transmit

ADC10

(MSP430G2x53 only)

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

0FFDEh

20

19

18

17

16

15

I/O Port P2 (up to eight flags)

I/O Port P1 (up to eight flags)

P2IFG.0 to P2IFG.7⁽²⁾⁽⁴⁾

P1IFG.0 to P1IFG.7⁽²⁾⁽⁴⁾

maskable

(7)

See

(8)

See

0FFDEh to

0FFC0h

14 to 0, lowest

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address ranges.

(2) Multiple source flags

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4) Interrupt flags are located in the module.

(5) In SPI mode: UCB0RXIFG. In I²C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

(6) In UART or SPI mode: UCB0TXIFG. In I²C mode: UCB0RXIFG, UCB0TXIFG.

(7) This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)

disables the erasure of the flash if an invalid password is supplied.

(8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

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8.5 Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend

rw:

Bit can be read and written.

rw-0,1:

rw-(0,1):

Bit can be read and written. It is reset or set by PUC.

Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

Address

00h

7

6

5

4

3

2

1

0

ACCVIE

rw-0

NMIIE

rw-0

OFIE

rw-0

WDTIE

rw-0

WDTIE

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in

interval timer mode.

OFIE

Oscillator fault interrupt enable

(Non)maskable interrupt enable

Flash access violation interrupt enable

NMIIE

ACCVIE

Address

7

6

5

4

3

2

1

0

01h

UCB0TXIE

rw-0

UCB0RXIE

rw-0

UCA0TXIE

rw-0

UCA0RXIE

rw-0

UCA0RXIE

UCA0TXIE

UCB0RXIE

UCB0TXIE

USCI_A0 receive interrupt enable

USCI_A0 transmit interrupt enable

USCI_B0 receive interrupt enable

USCI_B0 transmit interrupt enable

Table 7. Interrupt Flag Register 1 and 2

Address

02h

7

6

5

4

3

2

1

0

NMIIFG

rw-0

RSTIFG

rw-(0)

PORIFG

rw-(1)

OFIFG

rw-1

WDTIFG

rw-(0)

WDTIFG

Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V_CCpower-on or a reset condition at the RST/NMI pin in reset mode.

OFIFG

Flag set on oscillator fault.

PORIFG

RSTIFG

NMIIFG

Power-On Reset interrupt flag. Set on V_CCpower-up.

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V_CCpower-up.

Set via RST/NMI pin

Address

03h

7

6

5

4

3

2

1

0

UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

rw-1 rw-0 rw-1 rw-0

UCA0RXIFG

UCA0TXIFG

UCB0RXIFG

UCB0TXIFG

USCI_A0 receive interrupt flag

USCI_A0 transmit interrupt flag

USCI_B0 receive interrupt flag

USCI_B0 transmit interrupt flag

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8.6 Memory Organization

Table 8. Memory Organization

MSP430G2453

MSP430G2553

16kB

Memory

Size

Flash

Size

8kB

Main: interrupt vector

Main: code memory

Information memory

0xFFFF to 0xFFC0

0xFFFF to 0xE000

256 Byte

0xFFFF to 0xFFC0

0xFFFF to 0xC000

256 Byte

Flash

Size

010FFh to 01000h

512 Byte

010FFh to 01000h

512 Byte

RAM

0x03FF to 0x0200

01FFh to 0100h

0FFh to 010h

0Fh to 00h

0x03FF to 0x0200

01FFh to 0100h

0FFh to 010h

0Fh to 00h

Peripherals

16-bit

8-bit

8-bit SFR

8.7 Bootstrap Loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to

the MSP430 memory via the BSL is protected by user-defined password. For complete description of the

features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's

Guide (SLAU319).

Table 9. BSL Function Pins

BSL FUNCTION

Data transmit

Data receive

20-PIN PW PACKAGE

3 - P1.1

28-PIN PW PACKAGE

3 - P1.1

7 - P1.5

8.8 Flash Memory

The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can

perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also

called information memory.

•

Segment A contains calibration data. After reset segment A is protected against programming and erasing. It

can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is

required.

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8.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

8.9.1 Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).

The basic clock module is designed to meet the requirements of both low system cost and low power

consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic

clock module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

8.9.2 Main DCO Characteristics

•

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

•

DCO control bits DCOx have a step size as defined by parameter S_DCO.

Modulation control bits MODx select how often f_{DCO(RSEL,DCO+1)}is used within the period of 32 DCOCLK

cycles. The frequency f_{DCO(RSEL,DCO)}is used for the remaining cycles. The frequency is an average equal to:

32 × f

× f

DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

f

=

average

MOD × f

+ (32 – MOD) × f

DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

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Peripherals (continued)

8.9.3 Calibration Data Stored in Information Memory Segment A

Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.

Table 10. Tags Used by the ADC Calibration Tags

NAME

ADDRESS

0x10F6

0x10DA

-

VALUE

0x01

DESCRIPTION

DCO frequency calibration at V_CC= 3 V and T_A= 30°C at calibration

ADC10_1 calibration tag

TAG_DCO_30

TAG_ADC10_1

TAG_EMPTY

0x10

0xFE

Identifier for empty memory areas

Table 11. Labels Used by the ADC Calibration Tags

ADDRESS

LABEL

SIZE

CONDITION AT CALIBRATION AND DESCRIPTION

OFFSET

0x0010

0x000E

0x000C

0x000A

0x0008

0x0006

0x0004

0x0002

0x0009

0x0008

0x0007

0x0006

0x0005

0x0004

0x0003

0x0002

CAL_ADC_25T85

CAL_ADC_25T30

word

byte

INCHx = 0x1010, REF2_5 = 1, T_A= 85°C

INCHx = 0x1010, REF2_5 = 1, T_A= 30°C

CAL_ADC_25VREF_FACTOR

CAL_ADC_15T85

REF2_5 = 1, T_A= 30°C, I_VREF+= 1 mA

INCHx = 0x1010, REF2_5 = 0, T_A= 85°C

CAL_ADC_15T30

INCHx = 0x1010, REF2_5 = 0, T_A= 30°C

CAL_ADC_15VREF_FACTOR

CAL_ADC_OFFSET

CAL_ADC_GAIN_FACTOR

CAL_BC1_1MHZ

REF2_5 = 0, T_A= 30°C, I_VREF+= 0.5 mA

External VREF = 1.5 V, f_ADC10CLK= 5 MHz

-

CAL_DCO_1MHZ

CAL_BC1_8MHZ

CAL_DCO_8MHZ

CAL_BC1_12MHZ

CAL_DCO_12MHZ

CAL_BC1_16MHZ

CAL_DCO_16MHZ

8.9.4 Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and

power off.

8.9.5 Digital I/O

Up to three 8-bit I/O ports are implemented:

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.

Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available).

Read/write access to port-control registers is supported by all instructions.

Each I/O has an individually programmable pullup or pulldown resistor.

Each I/O has an individually programmable pin oscillator enable bit to enable low-cost capacitive touch

detection.

8.9.6 Watchdog Timer (WDT+)

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be disabled or configured as an interval timer and can

generate interrupts at selected time intervals.

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8.9.7 Timer_A3 (TA0, TA1)

Timer0/1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Table 12. Timer0_A3 Signal Connections

INPUT PIN NUMBER

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

DEVICE INPUT

SIGNAL

MODULE

INPUT NAME

MODULE

BLOCK

PW20

PW28

PW20

PW28

P1.0-2

TACLK

ACLK

SMCLK

TACLK

TA0.0

ACLK

V_SS

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

CCR1

CCR2

NA

PinOsc

P1.1-3

PinOsc

P1.1-3

P1.5-7

P1.1-3

P1.5-7

P3.4-15

TA0

TA1

TA2

V_CC

P1.2-4

PinOsc

P1.2-4

TA0.1

CAOUT

V_SS

CCI1A

CCI1B

GND

P1.2-4

P1.6-14

P2.6-19

P1.2-4

P1.6-22

P2.6-27

P3.5-19

P3.0-9

V_CC

P3.0-9

PinOsc

TA0.2

V_SS

CCI2A

CCI2B

GND

P3.6-20

V_CC

Table 13. Timer1_A3 Signal Connections

INPUT PIN NUMBER

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

DEVICE INPUT

SIGNAL

MODULE

INPUT NAME

MODULE

BLOCK

PW20

PW28

PW20

PW28

-

P3.7-21

TACLK

ACLK

SMCLK

TACLK

TA1.0

V_SS

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

CCR1

CCR2

NA

-

P3.7-21

P2.0-10

P2.3-16

P2.0-8

P2.3-11

P2.0-8

P2.0-10

P2.3-16

P3.1-8

P2.3-11

TA0

TA1

TA2

V_CC

P2.1-9

P2.1-11

P2.2-12

TA1.1

V_SS

CCI1A

CCI1B

GND

P2.1-9

P2.1-11

P2.2-12

P3.2-13

P2.2-10

V_CC

P2.4-12

P2.5-13

P2.4-17

P2.5-18

TA1.2

V_SS

CCI2A

CCI2B

GND

P2.4-12

P2.5-13

P2.4-17

P2.5-18

P3.3-14

V_CC

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8.9.8 Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I²C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the USCI

functionality.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I²C.

8.9.9 Comparator_A+

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,

battery-voltage supervision, and monitoring of external analog signals.

8.9.10 ADC10

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion

result handling, allowing ADC samples to be converted and stored without any CPU intervention.

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8.9.11 Peripheral File Map

Table 14. Peripherals With Word Access

REGISTER

NAME

MODULE

REGISTER DESCRIPTION

OFFSET

ADC10

ADC data transfer start address

ADC memory

ADC10SA

ADC10MEM

ADC10CTL1

ADC10CTL0

TA1CCR2

TA1CCR1

TA1CCR0

TA1R

1BCh

1B4h

ADC control register 1

ADC control register 0

Capture/compare register

Timer_A register

1B2h

1B0h

Timer1_A3

0196h

0194h

0192h

0190h

0186h

0184h

0182h

0180h

011Eh

0176h

0174h

0172h

0170h

0166h

0164h

0162h

0160h

012Eh

012Ch

012Ah

0128h

0120h

Capture/compare control

Timer_A control

TA1CCTL2

TA1CCTL1

TA1CCTL0

TA1CTL

Timer_A interrupt vector

Capture/compare register

Timer_A register

TA1IV

Timer0_A3

TA0CCR2

TA0CCR1

TA0CCR0

TA0R

Capture/compare control

Timer_A control

TA0CCTL2

TA0CCTL1

TA0CCTL0

TA0CTL

Timer_A interrupt vector

Flash control 3

TA0IV

Flash Memory

FCTL3

Flash control 2

FCTL2

Flash control 1

FCTL1

Watchdog Timer+

Watchdog/timer control

WDTCTL

18

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Table 15. Peripherals With Byte Access

REGISTER

OFFSET

NAME

MODULE

REGISTER DESCRIPTION

USCI_B0

USCI_B0 transmit buffer

USCI_B0 receive buffer

USCI_B0 status

USCI B0 I²C Interrupt enable

USCI_B0 bit rate control 1

USCI_B0 bit rate control 0

USCI_B0 control 1

UCB0TXBUF

UCB0RXBUF

UCB0STAT

UCB0CIE

UCB0BR1

UCB0BR0

UCB0CTL1

UCB0CTL0

UCB0SA

UCB0OA

UCA0TXBUF

UCA0RXBUF

UCA0STAT

UCA0MCTL

UCA0BR1

UCA0BR0

UCA0CTL1

UCA0CTL0

UCA0IRRCTL

UCA0IRTCTL

UCA0ABCTL

ADC10AE0

ADC10AE1

ADC10DTC1

ADC10DTC0

CAPD

06Fh

06Eh

06Dh

06Ch

06Bh

06Ah

069h

068h

011Ah

0118h

067h

066h

065h

064h

063h

062h

061h

060h

05Fh

05Eh

05Dh

04Ah

04Bh

049h

048h

05Bh

05Ah

059h

053h

058h

057h

056h

043h

010h

01Bh

01Ah

019h

018h

042h

02Fh

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

USCI_B0 control 0

USCI_B0 I²C slave address

USCI_B0 I²C own address

USCI_A0 transmit buffer

USCI_A0 receive buffer

USCI_A0 status

USCI_A0

USCI_A0 modulation control

USCI_A0 baud rate control 1

USCI_A0 baud rate control 0

USCI_A0 control 1

USCI_A0 control 0

USCI_A0 IrDA receive control

USCI_A0 IrDA transmit control

USCI_A0 auto baud rate control

ADC analog enable 0

ADC analog enable 1

ADC data transfer control register 1

ADC data transfer control register 0

Comparator_A+ port disable

Comparator_A+ control 2

Comparator_A+ control 1

Basic clock system control 3

Basic clock system control 2

Basic clock system control 1

DCO clock frequency control

Port P3 selection 2. pin

Port P3 resistor enable

Port P3 selection

ADC10

Comparator_A+

CACTL2

CACTL1

Basic Clock System+

BCSCTL3

BCSCTL2

BCSCTL1

DCOCTL

P3SEL2

Port P3

(28-pin PW only)

P3REN

P3SEL

Port P3 direction

P3DIR

Port P3 output

P3OUT

Port P3 input

P3IN

Port P2

Port P2 selection 2

P2SEL2

Port P2 resistor enable

Port P2 selection

P2REN

P2SEL

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

P2IE

P2IES

P2IFG

Port P2 direction

P2DIR

Port P2 output

P2OUT

Port P2 input

P2IN

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Table 15. Peripherals With Byte Access (continued)

REGISTER

NAME

MODULE

REGISTER DESCRIPTION

OFFSET

Port P1

Port P1 selection 2

Port P1 resistor enable

Port P1 selection

P1SEL2

P1REN

P1SEL

P1IE

041h

027h

026h

025h

024h

023h

022h

021h

020h

003h

002h

001h

000h

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

P1IES

P1IFG

P1DIR

P1OUT

P1IN

Port P1 output

Port P1 input

Special Function

SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

IFG2

IFG1

IE2

IE1

20

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9 Specifications

9.1 Absolute Maximum Ratings⁽¹⁾

Voltage applied at V_CCto V_SS

Voltage applied to any pin⁽²⁾

–0.3 V to 4.1 V

–0.3 V to V_CC+ 0.3 V

±2 mA

Diode current at any device pin

Unprogrammed device

Programmed device

–55°C to 150°C

(3)

Storage temperature range, T_stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

9.2 Recommended Operating Conditions

Typical values are specified at V_CC= 3.3 V and T_A= 25°C (unless otherwise noted)

MIN NOM

MAX UNIT

During program execution

1.8

3.6

V_CC

Supply voltage

V

During flash programming

or erase

2.2

3.6

V_SS

T_A

Supply voltage

0

V

Operating free-air temperature

I version

–40

85

6

°C

V_CC= 1.8 V,

Duty cycle = 50% ± 10%

dc

V_CC= 2.7 V,

Duty cycle = 50% ± 10%

f_SYSTEM

Processor frequency (maximum MCLK frequency)⁽¹⁾⁽²⁾

12 MHz

16

V_CC= 3.3 V,

Duty cycle = 50% ± 10%

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Legend:

16 MHz

Supply voltage range,

during flash memory

programming

12 MHz

Supply voltage range,

during program execution

6 MHz

3.3 V 3.6 V

2.7 V

Supply Voltage - V

1.8 V

2.2 V

Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V_CC

of 2.2 V.

Figure 2. Safe Operating Area

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9.3 Active Mode Supply Current Into V_CCExcluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

f_DCO= f_MCLK= f_SMCLK= 1 MHz,

f_ACLK= 0 Hz,

2.2 V

230

Program executes in flash,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

Active mode (AM)

current at 1 MHz

I_AM,1MHz

µA

3 V

330

420

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

9.4 Typical Characteristics, Active Mode Supply Current (Into V_CC)

5.0

4.0

3.0

2.0

1.0

0.0

4.0

3.0

2.0

1.0

0.0

f

= 16 MHz

DCO

T

= 85 °C

= 25 °C

A

T

A

V

= 3 V

CC

f

= 12 MHz

DCO

T

= 85 °C

= 25 °C

A

T

A

f

= 8 MHz

DCO

2.0

f

= 1 MHz

V

CC

= 2.2 V

DCO

1.5

2.5

3.0

3.5

4.0

0.0

4.0

8.0

12.0

16.0

V

CC

− Supply Voltage − V

f

DCO

− DCO Frequency − MHz

Figure 3. Active Mode Current vs V_CC, T_A= 25°C

Figure 4. Active Mode Current vs DCO Frequency

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9.5 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

(2)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

f_MCLK= 0 MHz,

f_SMCLK= f_DCO= 1 MHz,

f_ACLK= 32768 Hz,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

Low-power mode 0

(LPM0) current⁽³⁾

I_LPM0,1MHz

25°C

2.2 V

56

µA

f_MCLK= f_SMCLK= 0 MHz,

f_DCO= 1 MHz,

f_ACLK= 32768 Hz,

Low-power mode 2

(LPM2) current⁽⁴⁾

I_LPM2

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 1,

OSCOFF = 0

25°C

2.2 V

22

µA

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLK= 32768 Hz,

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

Low-power mode 3

(LPM3) current⁽⁴⁾

I_LPM3,LFXT1

I_LPM3,VLO

I_LPM4

25°C

2.2 V

0.7

0.5

1.5

0.7

µA

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLKfrom internal LF oscillator (VLO),

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

Low-power mode 3

current, (LPM3)⁽⁴⁾

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLK= 0 Hz,

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 1

25°C

85°C

0.1

0.8

0.5

1.7

Low-power mode 4

(LPM4) current⁽⁵⁾

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

(3) Current for brownout and WDT clocked by SMCLK included.

(4) Current for brownout and WDT clocked by ACLK included.

(5) Current for brownout included.

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9.6 Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

Vcc = 3.6 V

Vcc = 3 V

Vcc = 3.6 V

Vcc = 3 V

Vcc = 2.2 V

Vcc = 1.8 V

60 80

-40

-20

0

20

40

-40

-20

0

20

40

60

80

T_A– Temperature – °C

Figure 6. LPM4 Current vs Temperature

T_A– Temperature – °C

Figure 5. LPM3 Current vs Temperature

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9.7 Schmitt-Trigger Inputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0.45 V_CC

1.35

TYP

MAX UNIT

0.75 V_CC

V_IT+

Positive-going input threshold voltage

V

3 V

2.25

0.55 V_CC

1.65

0.25 V_CC

0.75

V_IT–

Negative-going input threshold voltage

3 V

V_hys

R_Pull

C_I

Input voltage hysteresis (V_IT+– V_IT–

Pullup/pulldown resistor

Input capacitance

)

0.3

1

V

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

3 V

20

35

5

50

kΩ

pF

V_IN= V_SSor V_CC

9.8 Leakage Current, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

±50 nA

(1) (2)

I_lkg(Px.y)

High-impedance leakage current

3 V

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

9.9 Outputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –6 mA⁽¹⁾

I_(OLmax)= 6 mA⁽¹⁾

V_CC

3 V

MIN

TYP

V_CC– 0.3

V_SS+ 0.3

MAX UNIT

V_OH

V_OL

High-level output voltage

Low-level output voltage

V

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

9.10 Output Frequency, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Px.y, C_L= 20 pF, R_L= 1 kΩ^{(1) (2)}

Px.y, C_L= 20 pF⁽²⁾

V_CC

3 V

MIN

TYP

12

MAX UNIT

MHz

Port output frequency

(with load)

f_Px.y

f_{Port_CLK}

Clock output frequency

16

MHz

(1) A resistive divider with two 0.5-kΩ resistors between V_CCand V_SSis used as load. The output is connected to the center tap of the

divider.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

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9.11 Typical Characteristics, Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

50

40

30

20

10

0

30

25

20

15

10

5

V

= 2.2 V

V

= 3 V

CC

T

= 25°C

A

T

= 25°C

= 85°C

P1.7

A

P1.7

T

A

T

A

= 85°C

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

3

3.5

V

OL

− Low-Level Output Voltage − V

V

OL

− Low-Level Output Voltage − V

Figure 7. Typical Low-Level Output Current vs Low-Level

Output Voltage

Figure 8. Typical Low-Level Output Current vs Low-Level

Output Voltage

0

V

CC

= 2.2 V

V

CC

= 3 V

P1.7

−5

−10

−15

−20

−25

−10

−20

−30

−40

−50

T

= 85°C

A

T

= 85°C

A

T

A

= 25°C

0.5

T

A

= 25°C

0.5

0

1

1.5

2

2.5

0

1

1.5

2

2.5

3

3.5

V

OH

− High-Level Output Voltage − V

V

OH

− High-Level Output Voltage − V

Figure 9. Typical High-Level Output Current vs High-Level

Output Voltage

Figure 10. Typical High-Level Output Current vs High-Level

Output Voltage

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9.12 Pin-Oscillator Frequency – Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

1400

900

MAX UNIT

P1.y, C_L= 10 pF, R_L= 100 kΩ⁽¹⁾⁽²⁾

P1.y, C_L= 20 pF, R_L= 100 kΩ⁽¹⁾⁽²⁾

P2.0 to P2.5, C_L= 10 pF, R_L= 100 kΩ⁽¹⁾⁽²⁾

P2.0 to P2.5, C_L= 20 pF, R_L= 100 kΩ⁽¹⁾⁽²⁾

fo_P1.x

Port output oscillation frequency

3 V

kHz

1800

1000

fo_P2.x

fo_P2.6/7

fo_P3.x

Port output oscillation frequency

kHz

3 V

P2.6 and P2.7, C_L= 20 pF, R_L= 100

700

kΩ⁽¹⁾⁽²⁾

P3.y, C_L= 10 pF, R_L= 100 kΩ⁽¹⁾⁽²⁾

P3.y, C_L= 20 pF, R_L= 100 kΩ⁽¹⁾⁽²⁾

1800

1000

(1) A resistive divider with two 50-kΩ resistors between V_CCand V_SSis used as load. The output is connected to the center tap of the

divider.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

9.13 Typical Characteristics, Pin-Oscillator Frequency

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0.00

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0.00

V

CC

= 3.0 V

V

CC

= 2.2 V

P1.y

P2.0 ... P2.5

P2.6, P2.7

P2.0 ... P2.5

P2.6, P2.7

10

50

100

10

50

100

C

LOAD

− External Capacitance − pF

C

LOAD

− External Capacitance − pF

One output active at a time.

Figure 11. Typical Oscillating Frequency vs Load

Capacitance

Figure 12. Typical Oscillating Frequency vs Load

Capacitance

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9.14 POR, BOR⁽¹⁾⁽²⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

0.7 ×

V_{(B_IT--)}

V_CC(start)

See Figure 13

dV_CC/dt ≤ 3 V/s

V

V_{(B_IT–)}

V_{hys(B_IT–)}

t_d(BOR)

See Figure 13 through Figure 15

See Figure 13

dV_CC/dt ≤ 3 V/s

1.35

140

V

mV

µs

See Figure 13

2000

Pulse duration needed at RST/NMI pin to

accepted reset internally

t_(reset)

2.2 V

2

µs

(1) The current consumption of the brownout module is already included in the I_CCcurrent consumption data. The voltage level V_{(B_IT–)}

+

V_{hys(B_IT–)}is ≤ 1.8 V.

(2) During power up, the CPU begins code execution following a period of t_d(BOR)after V_CC= V_{(B_IT–)}+ V_{hys(B_IT–)}. The default DCO settings

must not be changed until V_CC≥ V_CC(min), where V_CC(min)is the minimum supply voltage for the desired operating frequency.

V

CC

V

hys(B_IT−)

V

(B_IT−)

V

CC(start)

1

0

t

d(BOR)

Figure 13. POR and BOR vs Supply Voltage

V

t

CC

pw

2

3 V

V

= 3 V

Typical Conditions

CC

1.5

1

V

CC(drop)

0.5

0

0.001

1

1000

1 ns

− Pulse Width − µs

t

− Pulse Width − µs

t

pw

Figure 14. V_CC(drop)Level With a Square Voltage Drop to Generate a POR or BOR Signal

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V

t

CC

pw

2

3 V

V

CC

= 3 V

1.5

1

Typical Conditions

V

CC(drop)

0.5

0

t = t

f

r

0.001

1

1000

t

r

f

t

− Pulse Width − µs

t

− Pulse Width − µs

pw

Figure 15. V_CC(drop)Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

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9.15 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

1.8

TYP

MAX UNIT

RSELx < 14

RSELx = 14

RSELx = 15

3.6

V_CC

Supply voltage

2.2

3.6

V

3

f_DCO(0,0)

f_DCO(0,3)

f_DCO(1,3)

f_DCO(2,3)

f_DCO(3,3)

f_DCO(4,3)

f_DCO(5,3)

f_DCO(6,3)

f_DCO(7,3)

f_DCO(8,3)

f_DCO(9,3)

f_DCO(10,3)

f_DCO(11,3)

f_DCO(12,3)

f_DCO(13,3)

f_DCO(14,3)

f_DCO(15,3)

f_DCO(15,7)

DCO frequency (0, 0)

DCO frequency (0, 3)

DCO frequency (1, 3)

DCO frequency (2, 3)

DCO frequency (3, 3)

DCO frequency (4, 3)

DCO frequency (5, 3)

DCO frequency (6, 3)

DCO frequency (7, 3)

DCO frequency (8, 3)

DCO frequency (9, 3)

DCO frequency (10, 3)

DCO frequency (11, 3)

DCO frequency (12, 3)

DCO frequency (13, 3)

DCO frequency (14, 3)

DCO frequency (15, 3)

DCO frequency (15, 7)

RSELx = 0, DCOx = 0, MODx = 0

RSELx = 0, DCOx = 3, MODx = 0

RSELx = 1, DCOx = 3, MODx = 0

RSELx = 2, DCOx = 3, MODx = 0

RSELx = 3, DCOx = 3, MODx = 0

RSELx = 4, DCOx = 3, MODx = 0

RSELx = 5, DCOx = 3, MODx = 0

RSELx = 6, DCOx = 3, MODx = 0

RSELx = 7, DCOx = 3, MODx = 0

RSELx = 8, DCOx = 3, MODx = 0

RSELx = 9, DCOx = 3, MODx = 0

RSELx = 10, DCOx = 3, MODx = 0

RSELx = 11, DCOx = 3, MODx = 0

RSELx = 12, DCOx = 3, MODx = 0

RSELx = 13, DCOx = 3, MODx = 0

RSELx = 14, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 7, MODx = 0

3 V

0.06

0.07

0.14 MHz

0.17 MHz

MHz

0.15

0.21

0.30

0.41

0.58

MHz

0.54

0.80

1.06 MHz

1.50 MHz

MHz

1.6

2.3

MHz

3.4

MHz

4.25

MHz

4.30

6.00

8.60

12.0

16.0

7.30 MHz

9.60 MHz

13.9 MHz

18.5 MHz

26.0 MHz

7.8

Frequency step between

range RSEL and RSEL+1

S_RSEL

S_DCO

S_RSEL= f_{DCO(RSEL+1,DCO)}/f_{DCO(RSEL,DCO)}

3 V

1.35

ratio

Frequency step between

tap DCO and DCO+1

S_DCO= f_{DCO(RSEL,DCO+1)}/f_{DCO(RSEL,DCO)}

Measured at SMCLK output

3 V

1.08

50

ratio

%

Duty cycle

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9.16 Calibrated DCO Frequencies, Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

calibrated at 30°C and 3 V

1-MHz tolerance over

temperature⁽¹⁾

0°C to 85°C

3 V

-3

±0.5

+3

+6

+3

+6

+3

+6

+3

+6

%

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

calibrated at 30°C and 3 V

1-MHz tolerance over V_CC

1-MHz tolerance overall

30°C

1.8 V to 3.6 V

3 V

-3

-6

-3

-6

-3

-6

-3

-6

±2

±3

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

calibrated at 30°C and 3 V

-40°C to 85°C

0°C to 85°C

30°C

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

calibrated at 30°C and 3 V

8-MHz tolerance over

temperature⁽¹⁾

±0.5

±2

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

calibrated at 30°C and 3 V

8-MHz tolerance over V_CC

8-MHz tolerance overall

2.2 V to 3.6 V

3 V

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

calibrated at 30°C and 3 V

-40°C to 85°C

0°C to 85°C

30°C

±3

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

calibrated at 30°C and 3 V

12-MHz tolerance over

temperature⁽¹⁾

±0.5

±2

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

calibrated at 30°C and 3 V

12-MHz tolerance over V_CC

12-MHz tolerance overall

2.7 V to 3.6 V

3 V

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

calibrated at 30°C and 3 V

-40°C to 85°C

0°C to 85°C

30°C

±3

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

calibrated at 30°C and 3 V

16-MHz tolerance over

temperature⁽¹⁾

±0.5

±2

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

calibrated at 30°C and 3 V

16-MHz tolerance over V_CC

16-MHz tolerance overall

3.3 V to 3.6 V

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

calibrated at 30°C and 3 V

-40°C to 85°C

±3

(1) This is the frequency change from the measured frequency at 30°C over temperature.

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9.17 Wakeup From Lower-Power Modes (LPM3 or LPM4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

DCO clock wake-up time from LPM3 BCSCTL1 = CALBC1_1MHz,

t_DCO,LPM3/4

t_CPU,LPM3/4

3 V

1.5

µs

or LPM4⁽¹⁾

DCOCTL = CALDCO_1MHz

CPU wake-up time from LPM3 or

LPM4⁽²⁾

1/f_MCLK+

t_Clock,LPM3/4

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge

observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

9.18 Typical Characteristics, DCO Clock Wakeup Time From LPM3 or LPM4

10.00

RSELx = 0...11

RSELx = 12...15

1.00

0.10

1.00

DCO Frequency − MHz

Figure 16. DCO Wakeup Time From LPM3 vs DCO Frequency

10.00

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9.19 Crystal Oscillator, XT1, Low-Frequency Mode⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

LFXT1 oscillator crystal

frequency, LF mode 0, 1

f_LFXT1,LF

XTS = 0, LFXT1Sx = 0 or 1

1.8 V to 3.6 V

32768

Hz

LFXT1 oscillator logic level

f_{LFXT1,LF,logic}

square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3

LF mode

1.8 V to 3.6 V 10000

32768 50000

Hz

XTS = 0, LFXT1Sx = 0,

f_LFXT1,LF= 32768 Hz, C_L,eff= 6 pF

500

200

Oscillation allowance for

LF crystals

OA_LF

kΩ

XTS = 0, LFXT1Sx = 0,

f_LFXT1,LF= 32768 Hz, C_L,eff= 12 pF

XTS = 0, XCAPx = 0

XTS = 0, XCAPx = 1

XTS = 0, XCAPx = 2

XTS = 0, XCAPx = 3

1

5.5

8.5

11

Integrated effective load

capacitance, LF mode⁽²⁾

C_L,eff

pF

XTS = 0, Measured at P2.0/ACLK,

f_LFXT1,LF= 32768 Hz

Duty cycle, LF mode

2.2 V

30

10

50

70

%

Oscillator fault frequency,

LF mode⁽³⁾

f_Fault,LF

XTS = 0, XCAPx = 0, LFXT1Sx = 3⁽⁴⁾

10000

Hz

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If a conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(4) Measured with logic-level input frequency but also applies to operation with crystals.

9.20 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

T_A

V_CC

3 V

MIN

TYP

12

MAX UNIT

20 kHz

%/°C

f_VLO

-40°C to 85°C

25°C

4

df_VLO/d_T

3 V

0.5

4

df_VLO/dV_CCVLO frequency supply voltage drift

1.8 V to 3.6 V

%/V

9.21 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SMCLK, duty cycle = 50% ± 10%

TA0, TA1

V_CC

MIN

TYP

f_SYSTEM

MAX UNIT

f_TA

Timer_A input clock frequency

Timer_A capture timing

MHz

ns

t_TA,cap

3 V

20

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9.22 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_USCI

USCI input clock frequency

SMCLK, duty cycle = 50% ± 10%

f_SYSTEM

MHz

Maximum BITCLK clock frequency

(equals baudrate in MBaud)⁽¹⁾

UART receive deglitch time⁽²⁾

f_max,BITCLK

t_τ

3 V

2

MHz

50

100

600

ns

(1) The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.

(2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

9.23 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17 and

Figure 18)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_USCI

USCI input clock frequency

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time

SMCLK, duty cycle = 50% ± 10%

f_SYSTEMMHz

t_SU,MI

3 V

75

0

ns

t_HD,MI

t_VALID,MO

UCLK edge to SIMO valid, C_L= 20 pF

20

ns

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LO/HI

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 17. SPI Master Mode, CKPH = 0

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LO/HI

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

Figure 18. SPI Master Mode, CKPH = 1

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9.24 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 19 and

Figure 20)

PARAMETER

TEST CONDITIONS

V_CC

3 V

MIN

TYP

MAX UNIT

t_STE,LEAD

t_STE,LAG

t_STE,ACC

STE lead time, STE low to clock

STE lag time, Last clock to STE high

STE access time, STE low to SOMI data out

50

ns

10

50

STE disable time, STE high to SOMI high

impedance

t_STE,DIS

3 V

ns

t_SU,SI

t_HD,SI

SIMO input data setup time

SIMO input data hold time

3 V

15

10

ns

UCLK edge to SOMI valid,

C_L= 20 pF

t_VALID,SO

SOMI output data valid time

3 V

50

75

ns

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_SU,SI

t_LO/HI

t_HD,SI

SIMO

SOMI

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 19. SPI Slave Mode, CKPH = 0

t_STE,LEAD

t_STE,LAG

STE

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LO/HI

t_HD,SI

t_SU,SI

SIMO

SOMI

t_HD,MO

t_VALID,SO

t_STE,ACC

t_STE,DIS

Figure 20. SPI Slave Mode, CKPH = 1

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9.25 USCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 21)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_SYSTEMMHz

400 kHz

f_USCI

f_SCL

USCI input clock frequency

SCL clock frequency

SMCLK, duty cycle = 50% ± 10%

3 V

0

4.0

0.6

4.7

0.6

0

f

_SCL≤ 100 kHz

f_SCL> 100 kHz

_SCL≤ 100 kHz

t_HD,STA

Hold time (repeated) START

µs

f

t_SU,STA

Setup time for a repeated START

3 V

f_SCL> 100 kHz

t_HD,DAT

t_SU,DAT

t_SU,STO

Data hold time

3 V

ns

µs

Data setup time

Setup time for STOP

250

4.0

Pulse width of spikes suppressed by

input filter

t_SP

3 V

50

100

600

ns

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

Figure 21. I²C Mode Timing

9.26 Comparator_A+

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

(1)

I_(DD)

CAON = 1, CARSEL = 0, CAREF = 0

3 V

45

µA

CAON = 1, CARSEL = 0,

CAREF = 1, 2, or 3,

No load at CA0 and CA1

I_(Refladder/

RefDiode)

3 V

45

µA

V_(IC)

Common–mode input voltage

CAON = 1

3 V

0

V_CC-1

V

PCA0 = 1, CARSEL = 1, CAREF = 1,

No load at CA0 and CA1

V_(Ref025)

(Voltage at 0.25 V_CCnode) / V_CC

0.24

0.48

490

PCA0 = 1, CARSEL = 1, CAREF = 2,

No load at CA0 and CA1

V_(Ref050)

V_(RefVT)

(Voltage at 0.5 V_CCnode) / V_CC

3 V

PCA0 = 1, CARSEL = 1, CAREF = 3,

No load at CA0 and CA1, TA = 85°C

See Figure 22 and Figure 23

mV

V_(offset)

V_hys

Offset voltage⁽²⁾

Input hysteresis

3 V

±10

0.7

mV

CAON = 1

T_A= 25°C, Overdrive 10 mV,

Without filter: CAF = 0

120

1.5

ns

µs

Response time

(low-high and high-low)

t_(response)

3 V

T_A= 25°C, Overdrive 10 mV,

With filter: CAF = 1

(1) The leakage current for the Comparator_A+ terminals is identical to I_lkg(Px.y)specification.

(2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The

two successive measurements are then summed together.

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9.27 Typical Characteristics – Comparator_A+

650

600

550

500

450

400

V_CC= 3 V

V_CC= 2.2 V

600

Typical

550

500

450

400

-45

-25

-5

15

35

55

75

95

115

-45

-25

-5

15

35

55

75

95

115

T_A– Free-Air Temperature – °C

Figure 22. V_(RefVT)vs Temperature, V_CC= 3 V

Figure 23. V_(RefVT)vs Temperature, V_CC= 2.2 V

100

V_CC= 1.8 V

V_CC= 2.2 V

V_CC= 3 V

10

V_CC= 3.6 V

1

0

0.4

0.6

0.8

1

0.2

V_IN/V_CC– Normalized Input Voltage – V/V

Figure 24. Short Resistance vs V_IN/V_CC

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9.28 10-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_SS= 0 V

T_A

V_CC

3 V

MIN

TYP

MAX UNIT

V_CC

V_Ax

Analog supply voltage

2.2

3.6

V

All Ax terminals, Analog inputs

selected in ADC10AE register

Analog input voltage⁽²⁾

ADC10 supply current⁽³⁾

0

V_CC

V

f_ADC10CLK= 5.0 MHz,

ADC10ON = 1, REFON = 0,

ADC10SHT0 = 1, ADC10SHT1 = 0,

ADC10DIV = 0

I_ADC10

25°C

0.6

mA

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REF2_5V = 0,

REFON = 1, REFOUT = 0

0.25

Reference supply current,

reference buffer disabled⁽⁴⁾

I_REF+

3 V

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REF2_5V = 1,

REFON = 1, REFOUT = 0

f_ADC10CLK= 5.0 MHz,

Reference buffer supply

ADC10ON = 0, REFON = 1,

I_REFB,0

25°C

3 V

1.1

0.5

mA

current with ADC10SR = 0⁽⁴⁾REF2_5V = 0, REFOUT = 1,

ADC10SR = 0

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REFON = 1,

Reference buffer supply

I_REFB,1

current with ADC10SR = 1⁽⁴⁾REF2_5V = 0, REFOUT = 1,

ADC10SR = 1

Only one terminal Ax can be selected

C_I

R_I

Input capacitance

at one time

25°C

3 V

27

pF

Input MUX ON resistance

0 V ≤ V_Ax≤ V_CC

1000

Ω

(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results.

(3) The internal reference supply current is not included in current consumption parameter I_ADC10

.

(4) The internal reference current is supplied via terminal V_CC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

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9.29 10-Bit ADC, Built-In Voltage Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_VREF+≤ 1 mA, REF2_5V = 0

I_VREF+≤ 1 mA, REF2_5V = 1

I_VREF+≤ I_VREF+max, REF2_5V = 0

I_VREF+≤ I_VREF+max, REF2_5V = 1

V_CC

MIN

2.2

TYP

MAX UNIT

Positive built-in reference

analog supply voltage range

V_CC,REF+

V

2.9

1.41

2.35

1.5

2.5

1.59

V

Positive built-in reference

voltage

V_REF+

3 V

2.65

Maximum VREF+ load

current

I_LD,VREF+

±1

±2

mA

I_VREF+= 500 µA ± 100 µA,

Analog input voltage V_Ax≉ 0.75 V,

REF2_5V = 0

VREF+ load regulation

3 V

LSB

I_VREF+= 500 µA ± 100 µA,

Analog input voltage V_Ax≉ 1.25 V,

REF2_5V = 1

±2

I_VREF+= 100 µA→900 µA,

V_Ax≉ 0.5 × VREF+,

Error of conversion result ≤ 1 LSB,

ADC10SR = 0

V_REF+load regulation

response time

400

ns

Maximum capacitance at

pin VREF+

C_VREF+

TC_REF+

I_VREF+≤ ±1 mA, REFON = 1, REFOUT = 1

I_VREF+= const with 0 mA ≤ I_VREF+≤ 1 mA

3 V

100

pF

ppm/

°C

Temperature coefficient⁽¹⁾

±100

Settling time of internal

reference voltage to 99.9%

VREF

I_VREF+= 0.5 mA, REF2_5V = 0,

REFON = 0 → 1

t_REFON

3.6 V

3 V

30

2

µs

I_VREF+= 0.5 mA,

REF2_5V = 1, REFON = 1,

REFBURST = 1, ADC10SR = 0

Settling time of reference

buffer to 99.9% VREF

t_REFBURST

(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))

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9.30 10-Bit ADC, External Reference⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_CC

VEREF+ > VEREF–,

SREF1 = 1, SREF0 = 0

1.4

Positive external reference input

VEREF+

V

(2)

voltage range

VEREF– ≤ VEREF+ ≤ V_CC– 0.15 V,

1.4

0

3

(3)

SREF1 = 1, SREF0 = 1

Negative external reference input

VEREF–

VEREF+ > VEREF–

1.2

V

(4)

voltage range

Differential external reference

input voltage range,

(5)

ΔVEREF

VEREF+ > VEREF–

1.4

V_CC

ΔVEREF = VEREF+ – VEREF–

0 V ≤ VEREF+ ≤ V_CC

SREF1 = 1, SREF0 = 0

,

3 V

±1

I_VEREF+

Static input current into VEREF+

Static input current into VEREF–

µA

0 V ≤ VEREF+ ≤ V_CC– 0.15 V ≤ 3 V,

3 V

0

SREF1 = 1, SREF0 = 1⁽³⁾

I_VEREF–

0 V ≤ VEREF– ≤ V_CC

±1

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply

current I_REFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.

(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

9.31 10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0.45

TYP

MAX

6.3

UNIT

ADC10SR = 0

ADC10SR = 1

ADC10 input clock

frequency

For specified performance of

ADC10 linearity parameters

f_ADC10CLK

f_ADC10OSC

3 V

MHz

1.5

ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,

3 V

3.7

6.3

MHz

µs

frequency

f_ADC10CLK= f_ADC10OSC

ADC10 built-in oscillator, ADC10SSELx = 0,

f_ADC10CLK= f_ADC10OSC

2.06

3.51

t_CONVERT

Conversion time

13 ×

f_ADC10CLKfrom ACLK, MCLK, or SMCLK:

ADC10DIV ×

1/f_ADC10CLK

ADC10SSELx ≠ 0

Turn-on settling time of

the ADC

(1)

t_ADC10ON

100

ns

(1) The condition is that the error in a conversion started after t_ADC10ONis less than ±0.5 LSB. The reference and input signal are already

settled.

9.32 10-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Integral linearity error

Differential linearity error

Offset error

TEST CONDITIONS

V_CC

3 V

MIN

TYP

MAX UNIT

±1 LSB

±2 LSB

±5 LSB

E_I

E_D

E_O

E_G

E_T

Source impedance R_S< 100 Ω

Gain error

±1.1

±2

Total unadjusted error

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9.33 10-Bit ADC, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

3 V

MIN

TYP

60

MAX UNIT

Temperature sensor supply

current⁽¹⁾

REFON = 0, INCHx = 0Ah,

T_A= 25°C

I_SENSOR

TC_SENSOR

t_{Sensor(sample)}

I_VMID

µA

mV/°C

µs

(2)

ADC10ON = 1, INCHx = 0Ah

ADC10ON = 1, INCHx = 0Ah,

Error of conversion result ≤ 1 LSB

3.55

Sample time required if channel

30

(3)

10 is selected

(4)

Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh

µA

ADC10ON = 1, INCHx = 0Bh,

V_CCdivider at channel 11

V_MID

1.5

V

_MID≉ 0.5 × V_CC

Sample time required if channel

11 is selected

ADC10ON = 1, INCHx = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

3 V

1220

ns

(5)

(1) The sensor current I_SENSORis consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is

high). When REFON = 1, I_SENSORis included in I_REF+. When REFON = 0, I_SENSORapplies during conversion of the temperature sensor

input (INCH = 0Ah).

(2) The following formula can be used to calculate the temperature sensor output voltage:

V_Sensor,typ= TC_Sensor(273 + T [°C] ) + V_{Offset,sensor}[mV] or

V_Sensor,typ= TC_SensorT [°C] + V_Sensor(T_A= 0°C) [mV]

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

.

(4) No additional current is needed. The V_MIDis used during sampling.

(5) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

9.34 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST

CONDITIONS

V_CC

MIN

TYP

MAX

UNIT

V_{CC(PGM/ERASE)}Program and erase supply voltage

2.2

3.6

476

5

V

kHz

mA

f_FTG

Flash timing generator frequency

Supply current from V_CCduring program

Supply current from V_CCduring erase

Cumulative program time⁽¹⁾

257

I_PGM

2.2 V, 3.6 V

1

I_ERASE

t_CPT

7

mA

10

ms

t_CMErase

Cumulative mass erase time

20

10⁴

100

ms

Program/erase endurance

10⁵

cycles

years

t_FTG

t_Retention

t_Word

Data retention duration

T_J= 25°C

(2)

Word or byte program time

30

25

(2)

t_{Block, 0}

Block program time for first byte or word

Block program time for each additional byte or

word

t_{Block, 1-63}

18

t_FTG

(2)

t_{Block, End}

t_{Mass Erase}

t_{Seg Erase}

Block program end-sequence wait time

Mass erase time

6

10593

4819

t_FTG

Segment erase time

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word write, individual byte write, and block write modes.

(2) These values are hardwired into the Flash Controller's state machine (t_FTG= 1/f_FTG).

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9.35 RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

CPU halted

MIN

MAX

UNIT

(1)

V_(RAMh)

RAM retention supply voltage

1.6

V

(1) This parameter defines the minimum supply voltage V_CCwhen the data in RAM remains unchanged. No program execution should

happen during this supply voltage condition.

9.36 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0

TYP

MAX

20

UNIT

MHz

µs

f_SBW

Spy-Bi-Wire input frequency

2.2 V

t_SBW,LowSpy-Bi-Wire low clock pulse duration

0.025

15

Spy-Bi-Wire enable time

t_SBW,En

2.2 V

1

µs

(TEST high to acceptance of first clock edge⁽¹⁾

)

t_SBW,Ret

f_TCK

Spy-Bi-Wire return to normal operation time

TCK input frequency⁽²⁾

2.2 V

15

0

100

5

µs

MHz

kΩ

R_Internal

Internal pulldown resistance on TEST

25

60

90

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t_SBW,Entime after pulling the TEST/SBWTCK pin high before

applying the first SBWTCK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

9.37 JTAG Fuse⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A= 25°C

MIN

2.5

6

MAX

UNIT

V

V_CC(FB)

V_FB

Supply voltage during fuse-blow condition

Voltage level on TEST for fuse blow

Supply current into TEST during fuse blow

Time to blow fuse

7

100

1

V

I_FB

mA

ms

t_FB

(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to

bypass mode.

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10 I/O Port Schematics

10.1 Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger

To Comparator

From Comparator

To ADC10

INCHx = y

CAPD.y

or ADC10AE0.y

PxSEL2.y

PxSEL.y

PxDIR.y

0

From Timer

1

Direction

0: Input

1: Output

1

2

3

From USCI

PxSEL2.y

PxSEL.y

PxREN.y

0

1

0

1

PxSEL2.y

PxSEL.y

DVSS

DVCC

0

1

PxOUT.y

0

1

From Timer

2

3

Bus

Keeper

EN

P1.0/TA0CLK/ACLK/

A0/CA0

0

P1.1/TA0.0/UCA0RXD/

UCA0SOMI/A1/CA1

P1.2/TA0.1/UCA0TXD/

UCA0SIMO/A2/CA2

TAx.y

TAxCLK

PxIN.y

EN

To Module

PxIRQ.y

D

PxIE.y

EN

Set

Q

PxIFG.y

PxSEL.y

PxIES.y

Interrupt

Edge

Select

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Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger (continued)

Table 16. Port P1 (P1.0 to P1.2) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P1.x)

x

FUNCTION

ADC10AE.x

INCH.x=1

P1DIR.x

P1SEL.x

P1SEL2.x

CAPD.y

P1.0/

P1.x (I/O)

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

X

1

0

1

X

1

0

1

X

1

0

TA0CLK/

ACLK/

A0/

TA0.TACLK

ACLK

0

1

0

A0

X

1 (y = 0)

0

CA0/

CA0

X

0

1 (y = 0)

Pin Osc

P1.1/

Capacitive sensing

P1.x (I/O)

TA0.0

X

0

I: 0; O: 1

0

TA0.0/

1

0

TA0.CCI0A

UCA0RXD

UCA0SOMI

A1

0

UCA0RXD/

UCA0SOMI/

A1/

from USCI

0

1

from USCI

0

X

1 (y = 1)

0

CA1/

CA1

X

0

1 (y = 1)

Pin Osc

P1.2/

Capacitive sensing

P1.x (I/O)

TA0.1

X

0

I: 0; O: 1

0

TA0.1/

1

0

TA0.CCI1A

UCA0TXD

UCA0SIMO

A2

0

UCA0TXD/

UCA0SIMO/

A2/

from USCI

0

2

from USCI

0

X

1 (y = 2)

0

1 (y = 2)

0

CA2/

CA2

0

Pin Osc

Capacitive sensing

(1) X = don't care

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10.2 Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger

SREF2

VSS

0

1

To ADC10 VREF-

To Comparator

from Comparator

To ADC10

INCHx = y

CAPD.y

or ADC10AE0.y

PxSEL2.y PxSEL.y

PxDIR.y

0,2,3

1

Direction

0: Input

1: Output

PxSEL2.y

PxSEL.y

PxREN.y

0

1

0

1

PxSEL2.y

PxSEL.y

DVSS

DVCC

0

1

PxOUT.y

0

1

From ADC10

2

3

Bus

Keeper

EN

P1.3/ADC10CLK/CAOUT/

A3/VREF-/VEREF-/CA3

From Comparator

TAx.y

TAxCLK

PxIN.y

EN

D

To Module

PxIRQ.y

PxIE.y

EN

Set

Q

PxIFG.y

PxSEL.y

PxIES.y

Interrupt

Edge

Select

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Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger (continued)

Table 17. Port P1 (P1.3) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P1.x)

x

FUNCTION

ADC10AE.x

INCH.x=1

P1DIR.x

P1SEL.x

P1SEL2.x

CAPD.y

P1.3/

P1.x (I/O)

I: 0; O: 1

0

1

0

ADC10CLK/

CAOUT/

A3/

ADC10CLK

CAOUT

A3

1

0

1

0

X

0

X

1

1 (y = 3)

0

3

VREF-/

VEREF-/

CA3/

VREF-

1

0

VEREF-

CA3

0

1 (y = 3)

0

Pin Osc

Capacitive sensing

(1) X = don't care

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10.3 Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger

From/To ADC10 Ref+

To Comparator

from Comparator

To ADC10

INCHx = y

CAPD.y

or ADC10AE0.y

PxSEL.y

PxDIR.y

0

1

Direction

0: Input

1: Output

PxSEL2.y

PxSEL.y

PxREN.y

0

1

0

1

PxSEL2.y

PxSEL.y

DVSS

DVCC

0

1

PxOUT.y

SMCLK

0

1

2

3

Bus

Keeper

EN

P1.4/SMCLK/UCB0STE/UCA0CLK/

A4/VREF+/VEREF+/CA4/TCK

From Module

TAx.y

TAxCLK

PxIN.y

EN

D

To Module

PxIRQ.y

PxIE.y

EN

Q

Set

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

From JTAG

To JTAG

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Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger (continued)

Table 18. Port P1 (P1.4) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P1.x)

x

FUNCTION

ADC10AE.x

INCH.x=1

P1DIR.x

P1SEL.x

P1SEL2.x

JTAG Mode

CAPD.y

P1.4/

P1.x (I/O)

SMCLK

UCB0STE

UCA0CLK

VREF+

VEREF+

A4

I: 0; O: 1

0

1

0

1

0

SMCLK/

UCB0STE/

UCA0CLK/

VREF+/

VEREF+/

A4/

1

0

from USCI

1

0

from USCI

1

0

X

1

0

4

1

0

1 (y = 4)

0

1 (y = 4)

0

CA4

0

TCK/

TCK

Capacitive

sensing

Pin Osc

X

0

1

0

(1) X = don't care

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10.4 Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger

To Comparator

From Comparator

To ADC10

INCHx = y

CAPD.y

ADC10AE0.y

PxSEL2.y

PxSEL.y

PxDIR.y

0

1

From Module

Direction

0: Input

1: Output

2

3

From Module

PxSEL2.y

PxSEL.y

PxREN.y

0

1

0

1

PxSEL2.y

PxSEL.y

DVSS

DVCC

0

1

PxOUT.y

0

1

From Module

2

3

Bus

Keeper

EN

From Module

P1.5/TA0.0/UCB0CLK/UCA0STE/

A5/CA5/TMS

P1.6/TA0.1/UCB0SOMI/UCB0SCL/

A6/CA6/TDI/TCLK

P1.7/CAOUT/UCB0SIMO/UCB0SDA/

A7/CA7/TDO/TDI

TAx.y

TAxCLK

PxIN.y

EN

D

To Module

PxIRQ.y

PxIE.y

EN

Set

Q

PxIFG.y

PxSEL.y

PxIES.y

Interrupt

Edge

Select

From JTAG

To JTAG

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Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger (continued)

Table 19. Port P1 (P1.5 to P1.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P1.x)

x

FUNCTION

ADC10AE.x

INCH.x=1

P1DIR.x

P1SEL.x

P1SEL2.x

JTAG Mode

CAPD.y

P1.5/

P1.x (I/O)

TA0.0

I: 0; O: 1

0

1

0

1

0

TA0.0/

UCB0CLK/

UCA0STE/

A5/

1

0

UCB0CLK

UCA0STE

A5

from USCI

1

0

from USCI

1

0

5

X

1 (y = 5)

0

1 (y = 5)

0

CA5

0

TMS

Capacitive

sensing

Pin Osc

X

0

1

0

P1.6/

P1.x (I/O)

TA0.1

I: 0; O: 1

0

1

0

1

0

TA0.1/

1

0

UCB0SOMI/

UCB0SCL/

A6/

UCB0SOMI

UCB0SCL

A6

from USCI

1

0

from USCI

1

0

6

X

1 (y = 6)

0

1 (y = 6)

0

CA6

0

TDI/TCLK/

TDI/TCLK

Capacitive

sensing

Pin Osc

X

0

1

0

P1.7/

P1.x (I/O)

UCB0SIMO

UCB0SDA

A7

I: 0; O: 1

0

1

0

1

0

1

0

UCB0SIMO/

UCB0SDA/

A7/

from USCI

0

from USCI

1

0

X

1

X

1

X

0

1 (y = 7)

0

7

CA7

0

1 (y = 7)

CAOUT

TDO/TDI/

CAOUT

TDO/TDI

0

X

Capacitive

sensing

Pin Osc

X

0

1

0

(1) X = don't care

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10.5 Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger

PxSEL.y

PxDIR.y

0

1

Direction

0: Input

1: Output

PxSEL2.y

PxSEL.y

PxREN.y

0

1

0

1

PxSEL2.y

PxSEL.y

DVSS

DVCC

0

1

PxOUT.y

0

From Timer

1

2

3

P2.0/TA1.0

P2.1/TA1.1

P2.2/TA1.1

P2.3/TA1.0

P2.4/TA1.2

P2.5/TA1.2

0

TAx.y

TAxCLK

PxIN.y

EN

D

To Module

PxIRQ.y

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

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Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger (continued)

Table 20. Port P2 (P2.0 to P2.5) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P2.x)

x

FUNCTION

P2DIR.x

P2SEL.x

P2SEL2.x

P2.0/

P2.x (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

TA1.0/

Timer1_A3.CCI0A

Timer1_A3.TA0

Capacitive sensing

P2.x (I/O)

0

1

Pin Osc

P2.1/

X

I: 0; O: 1

TA1.1/

Timer1_A3.CCI1A

Timer1_A3.TA1

Capacitive sensing

P2.x (I/O)

0

1

2

3

4

5

1

Pin Osc

P2.2/

X

I: 0; O: 1

TA1.1/

Timer1_A3.CCI1B

Timer1_A3.TA1

Capacitive sensing

P2.x (I/O)

0

1

Pin Osc

P2.3/

X

I: 0; O: 1

TA1.0/

Timer1_A3.CCI0B

Timer1_A3.TA0

Capacitive sensing

P2.x (I/O)

0

1

Pin Osc

P2.4/

X

I: 0; O: 1

TA1.2/

Timer1_A3.CCI2A

Timer1_A3.TA2

Capacitive sensing

P2.x (I/O)

0

1

Pin Osc

P2.5/

X

I: 0; O: 1

TA1.2/

Timer1_A3.CCI2B

Timer1_A3.TA2

Capacitive sensing

0

1

Pin Osc

X

(1) X = don't care

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10.6 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger

XOUT/P2.7

LF off

PxSEL.6 and PxSEL.7

BCSCTL3.LFXT1Sx = 11

0

LFXT1CLK

1

PxSEL.y

PxDIR.y

0

1

Direction

0: Input

1: Output

PxSEL2.y

PxSEL.y

PxREN.y

0

1

0

1

PxSEL2.y

PxSEL.y

DVSS

DVCC

0

1

PxOUT.y

0

1

From Module

2

3

XIN/P2.6/TA0.1

TAx.y

TAxCLK

PxIN.y

EN

D

To Module

PxIRQ.y

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

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Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger (continued)

Table 21. Port P2 (P2.6) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P2.x)

x

FUNCTION

P2SEL.6

P2SEL.7

P2SEL2.6

P2SEL2.7

P2DIR.x

1

0

XIN

0

X

0

P2.6

P2.x (I/O)

I: 0; O: 1

6

1

0

TA0.1

Pin Osc

Timer0_A3.TA1

Capacitive sensing

1

0

X

1

X

(1) X = don't care

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10.7 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger

XIN

LF off

PxSEL.6 and PxSEL.7

BCSCTL3.LFXT1Sx = 11

LFXT1CLK

PxDIR.y

0

1

from P2.6

PxSEL.y

0

1

Direction

0: Input

1: Output

PxSEL2.y

PxSEL.y

PxREN.y

0

1

0

1

PxSEL2.y

PxSEL.y

DVSS

DVCC

0

1

PxOUT.y

0

1

From Module

2

3

XOUT/P2.7

TAx.y

TAxCLK

PxIN.y

EN

To Module

PxIRQ.y

D

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

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Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger (continued)

Table 22. Port P2 (P2.7) Pin Functions

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P2.x)

x

FUNCTION

P2SEL.6

P2SEL.7

P2SEL2.6

P2SEL2.7

P2DIR.x

1

0

XOUT/

XOUT

1

I: 0; O: 1

X

0

X

0

P2.7/

7

P2.x (I/O)

0

X

1

X

Pin Osc

Capacitive sensing

(1) X = don't care

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10.8 Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger (28-Pin PW and

32-Pin RHB Packages Only)

PxSEL.y

PxDIR.y

0

1

Direction

0: Input

1: Output

PxSEL2.y

PxSEL.y

PxREN.y

0

1

0

1

PxSEL2.y

PxSEL.y

DVSS

DVCC

0

1

PxOUT.y

0

1

From Module

2

3

P3.0/TA0.2

P3.1/TA1.0

P3.2/TA1.1

P3.3/TA1.2

P3.4/TA0.0

P3.5/TA0.1

TAx.y

TAxCLK

P3.6/TA0.2

P3.7/TA1CLK/CAOUT

PxIN.y

EN

D

To Module

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Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger (28-Pin PW and 32-Pin

RHB Packages Only) (continued)

Table 23. Port P3 (P3.0 to P3.7) Pin Functions (28-Pin PW and 32-Pin RHB Packages Only)

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

P3SEL2.x

P3.0/

P3.x (I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

TA0.2/

Timer0_A3.CCI2A

Timer0_A3.TA2

Capacitive sensing

P3.x (I/O)

0

1

Pin Osc

P3.1/

X

I: 0; O: 1

TA1.0/

Pin Osc

P3.2/

1

2

3

4

5

6

Timer1_A3.TA0

Capacitive sensing

P3.x (I/O)

1

X

I: 0; O: 1

TA1.1/

Pin Osc

P3.3/

Timer1_A3.TA1

Capacitive sensing

P3.x (I/O)

1

X

I: 0; O: 1

TA1.2/

Pin Osc

P3.4/

Timer1_A3.TA2

Capacitive sensing

P3.x (I/O)

1

X

I: 0; O: 1

TA0.0/

Pin Osc

P3.5/

Timer0_A3.TA0

Capacitive sensing

P3.x (I/O)

1

X

I: 0; O: 1

TA0.1/

Pin Osc

P3.6/

Timer0_A3.TA1

Capacitive sensing

P3.x (I/O)

1

X

I: 0; O: 1

TA0.2/

Pin Osc

P3.7/

Timer0_A3.TA2

Capacitive sensing

P3.x (I/O)

1

X

I: 0; O: 1

TA1CLK/

CAOUT/

Pin Osc

Timer1_A3.TACLK

Comparator output

Capacitive sensing

0

1

7

X

(1) X = don't care

58

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SLAS966 –MARCH 2014

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Tools Support

All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools.

Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.

11.1.1.1 Hardware Features

See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.

Break-

points

(N)

Range

Break-

points

LPMx.5

Debugging

Support

MSP430

Architecture

4-Wire

JTAG

2-Wire

JTAG

Clock

Control

State

Sequencer

Trace

Buffer

MSP430

Yes

2

No

Yes

No

11.1.1.2 Recommended Hardware Options

11.1.1.2.1 Target Socket Boards

The target socket boards allow easy programming and debugging of the device using JTAG. They also feature

header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG

programmer and debugger included. The following table shows the compatible target boards and the supported

packages.

Package

Target Board and Programmer Bundle

Target Board Only

28-pin TSSOP (PW)

MSP-FET430U28A

MSP-TS430PW28A

11.1.1.2.2 Experimenter Boards

Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional

hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools

for details.

11.1.1.2.3 Debugging and Programming Tools

Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full

list of available tools at www.ti.com/msp430tools.

11.1.1.2.4 Production Programmers

The production programmers expedite loading firmware to devices by programming several devices

simultaneously.

Part Number

PC Port

Features

Provider

MSP-GANG

Serial and USB

Program up to eight devices at a time. Works with PC or standalone.

Texas Instruments

11.1.1.3 Recommended Software Options

11.1.1.3.1 Integrated Development Environments

Software development tools are available from TI or from third parties. Open source solutions are also available.

This device is supported by Code Composer Studio™ IDE (CCS).

11.1.1.3.2 MSP430Ware

MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices

delivered in a convenient package. MSP430Ware is available as a component of CCS or as a standalone

package.

Submit Documentation Feedback

59

Product Folder Links: MSP430G2553-Q1 MSP430G2453-Q1

MSP430G2553-Q1, MSP430G2453-Q1

SLAS966 –MARCH 2014

www.ti.com

11.1.1.3.3 Command-Line Programmer

MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a

FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to

download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for an IDE.

11.1.1.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you

can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.

TI Embedded Processors Wiki

Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded

processors from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

11.1.2 Device and Development Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

MSP430™ MCU devices and support tools. Each MSP430™ MCU commercial family member has one of three

prefixes: MSP, PMS, or XMS (for example, MSP430F5259). Texas Instruments recommends two of three

possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of

product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully

qualified production devices and tools (with MSP for devices and MSP for tools).

Device development evolutionary flow:

XMS – Experimental device that is not necessarily representative of the final device's electrical specifications

PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality and

reliability verification

MSP – Fully qualified production device

Support tool development evolutionary flow:

MSPX – Development-support product that has not yet completed Texas Instruments internal qualification

testing.

MSP – Fully-qualified development-support product

XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of

the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, PZP) and temperature range (for example, T). Figure 25 provides a legend for reading the

complete device name for any family member.

60

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Product Folder Links: MSP430G2553-Q1 MSP430G2453-Q1

MSP430G2553-Q1, MSP430G2453-Q1

www.ti.com

SLAS966 –MARCH 2014

MSP 430 F 5 438 A I ZQW T XX

Processor Family

430 MCU Platform

Device Type

Series

Feature Set

Optional: Additional Features

Optional: Tape and Reel

Packaging

Optional: Temperature Range

Optional: A = Revision

Processor Family

CC = Embedded RF Radio

MSP = Mixed Signal Processor

XMS = Experimental Silicon

PMS = Prototype Device

430 MCU Platform

Device Type

TI’s Low Power Microcontroller Platform

Memory Type

C = ROM

F = Flash

Specialized Application

AFE = Analog Front End

BT = Preprogrammed with Bluetooth

BQ = Contactless Power

FR = FRAM

G = Flash or FRAM (Value Line) CG = ROM Medical

L = No Nonvolatile Memory

FE = Flash Energy Meter

FG = Flash Medical

FW = Flash Electronic Flow Meter

Series

1 Series = Up to 8 MHz

2 Series = Up to 16 MHz

3 Series = Legacy

5 Series = Up to 25 MHz

6 Series = Up to 25 MHz w/ LCD

0 = Low Voltage Series

4 Series = Up to 16 MHz w/ LCD

Feature Set

Various Levels of Integration Within a Series

N/A

Optional: A = Revision

Optional: Temperature Range S = 0°C to 50°C

C = 0°C to 70°C

I = -40°C to 85°C

T = -40°C to 105°C

Packaging

www.ti.com/packaging

Optional: Tape and Reel

T = Small Reel (7 inch)

R = Large Reel (11 inch)

No Markings = Tube or Tray

Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)

-HT = Extreme Temperature Parts (-55°C to 150°C)

-Q1 = Automotive Q100 Qualified

Figure 25. Device Nomenclature

Submit Documentation Feedback

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Product Folder Links: MSP430G2553-Q1 MSP430G2453-Q1

MSP430G2553-Q1, MSP430G2453-Q1

SLAS966 –MARCH 2014

www.ti.com

11.2 Documentation Support

11.2.1 Related Documents

The following documents describe the MSP430G2x53 devices. Copies of these documents are available on the

Internet at www.ti.com.

SLAU144 MSP430x2xx Family User's Guide. Detailed information on the modules and peripherals available in

this device family.

SLAZ440 MSP430G2553 Device Erratasheet. Describes the known exceptions to the functional specifications

for the MSP430G2553 device.

SLAZ437 MSP430G2453 Device Erratasheet. Describes the known exceptions to the functional specifications

for the MSP430G2453 device.

11.3 Related Links

Table 24 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 24. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

MSP430G2553-Q1

MSP430G2453-Q1

Click here

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you

can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.

TI Embedded Processors Wiki

Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded

processors from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

11.5 Trademarks

MSP430, Code Composer Studio are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

62

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Product Folder Links: MSP430G2553-Q1 MSP430G2453-Q1

PACKAGE OUTLINE

PW0020A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

5

0

SMALL OUTLINE PACKAGE

SEATING

PLANE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX AREA

18X 0.65

20

1

2X

5.85

6.6

6.4

NOTE 3

10

B

11

0.30

20X

4.5

4.3

NOTE 4

0.19

1.2 MAX

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

A

20

0 -8

DETAIL A

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0020A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

20X (1.5)

(R0.05) TYP

20

1

20X (0.45)

SYMM

18X (0.65)

11

10

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220206/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0020A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

20X (1.5)

SYMM

(R0.05) TYP

20

1

20X (0.45)

SYMM

18X (0.65)

10

11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220206/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430G2553IPW8RQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 16KB 闪存、512B SRAM、10 位 ADC、比较器、UART/SPI/I2C 和计时器的汽车类 16MHz MCU \| PW \| 28 \| -40 to 85 静态存储器比较器闪存
文件：	总73页 (文件大小：1065K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430G2553IPW8RQ1 [TI]

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