MSP430I2041 [TI]
具有 4 个 24 位 Σ-Δ ADC、2 个 16 位计时器、32KB 闪存和 2KB RAM 的 16MHz 计量 AFE;
| 型号： | MSP430I2041 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 4 个 24 位 Σ-Δ ADC、2 个 16 位计时器、32KB 闪存和 2KB RAM 的 16MHz 计量 AFE 闪存 |
| 文件： | 总81页 (文件大小：3119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
ZHCSI49C –SEPTEMBER 2014 –REVISED MARCH 2021
MSP430i204x、MSP430i203x、MSP430i202x 混合信号微控制器内部版本
– 具有可编程电平检测功能的电源电压监控器
– 欠压检测器
1 特性
– 内置的电压基准
– 温度传感器
• 电源电压范围：2.2V 至3.6V
• 高性能模拟
• 时钟系统
– MSP430i204x：四个具有差分PGA 输入的24
位Σ-Δ模数转换器(ADC)
– MSP430I203x：三个具有差分PGA 输入的24
位Σ-Δ模数转换器(ADC)
– MSP430I202x：两个具有差分PGA 输入的24
位Σ-Δ模数转换器(ADC)
– 16.384MHz 内部数控振荡器(DCO)
– 采用内部或外部电阻器的DCO 运行
– 外部数字时钟源
• 节11.3 开发工具与软件（另请参阅工具与软件）
– EVM430-I2040S 评估模块(EVM)，用于计量
– MSP-TS430RHB32A 100 引脚目标开发板
– MSP430Ware 代码示例
• 超低功耗
– 激活模式(AM)：
• 在1µs 内从待机模式唤醒
所有系统时钟激活在16.384MHz、3.0V 且闪存
程序执行时为275µA/MHz（典型值）
– 待机模式(LPM3)：
看门狗计时器激活，完全RAM 保持3.0V 时为
210µA（典型值）
– 关闭模式(LPM4)：
• 16 位RISC 架构, 高达16.384MHz 系统时钟
• 串行板上编程，无需外部编程电压
• 提供28 引脚TSSOP (PW) 封装和32 引脚VQFN
(RHB) 封装
• 节6 器件比较汇总了可用的产品系列成员
• 特色软件和参考设计
完全RAM 保持3.0V 时为70µA（典型值）
– 关断模式(LPM4.5)：
– 适用于MSP430 MCU 应用软件和框架的电能测
量设计中心
– 适用于MSP430 微控制器软件库的数字信号处
理(DSP) 库
– 单相和直流嵌入式计量参考设计
– 三路输出智能电源板参考设计
3.0V 时为75nA（典型值）
• 智能数字外设
– 两个16 位计时器，每个计时器具有三个捕捉/比
较寄存器
– 硬件乘法器支持16 位运算
• 增强型通用串行通信接口(eUSCI)
2 应用
– eUSCI_A0
• 计量
• 分项计量
• 电源监控和控制
• 工业传感器
• 单相交流和直流电源监控
• 两相电子计量表
• 智能插头
• 智能电源板
• 医疗–多参数患者监护
• 具有自动波特率检测功能的增强型通用异步
收发器(UART)
• 红外数据通讯(IrDA) 编码器和解码器
• 同步SPI
– eUSCI_B0
• 同步串行外设接口(SPI)
• I2C
• 灵活的电源管理系统
– 具有1.8V 稳压内核电源电压的集成式LDO
3 说明
™德州仪器 (TI) MSP430i204x、MSP430I203x 和 MSP430I202x 微控制器 (MCU) 属于 MSP430 计量和监控产品
系列。该架构和集成外设与五种低功耗模式相结合并经过优化，可在便携式和电池供电测量应用中延长电池寿
命。该器件具有功能强大的 16 位 RISC CPU、16 位寄存器和常数发生器，有助于实现最大编码效率。数控振荡
器(DCO) 可以让器件在不到5µs 的时间内从低功耗模式唤醒至激活模式。
MSP430i204x MCU 包括四个高性能 24 位 Σ-Δ ADC，两个 eUSCI（一个 eUSCI_A 模块和一个 eUSCI_B 模
块），两个16 位计时器，一个硬件乘法器和多达16 个I/O 引脚。
MSP430I203x MCU 包括三个高性能 24 位 Σ-Δ ADC，两个 eUSCI（一个 eUSCI_A 模块和一个 eUSCI_B 模
块），两个16 位计时器，一个硬件乘法器和多达16 个I/O 引脚。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLAS887
MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
ZHCSI49C –SEPTEMBER 2014 –REVISED MARCH 2021
www.ti.com.cn
MSP430I202x MCU 包括两个高性能 24 位 Σ-Δ ADC，两个 eUSCI（一个 eUSCI_A 模块和一个 eUSCI_B 模
块），两个16 位计时器，一个硬件乘法器和多达16 个I/O 引脚。
这些器件的典型应用包括：电能测量、模拟和数字传感器系统、LED 照明、数字电源、电机控制、远程控制、温
度调节装置、数字计时器和手持式仪表。
MSP430i204x、MSP430I203x 和 MSP430I202x MCU 由广泛的硬件和软件生态系统提供支持，随附参考设计和
代码示例，便于您快速开始设计。 开发套件包括用于计量的 EVM430-I2040S 评估模块 (EVM) 和 MSP-
TS430RHB32A 100 引脚目标开发板。提供适用于 MSP430 MCU 的电能测量设计中心作为快速开发工具，可测
量这些器件的电能。™ ™ TI 还提供免费的MSP430Ware 软件，该软件以Code Composer Studio IDE 桌面和云版
本组件的形式提供（位于 TI Resource Explorer 中）。™TI E2E 支持论坛还为 MSP430 MCU 提供广泛的在线配
套资料、培训和在线支持。
SLAU335 如需完整的模块说明，请参阅《MSP430i2xx 系列用户指南》。
器件信息
封装
器件型号
MSP430i2041TPW
封装尺寸
9.7mm x 4.4mm
5mm x 5mm
TSSOP (28)
VQFN (32)
MSP430i2041TRHB
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ZHCSI49C –SEPTEMBER 2014 –REVISED MARCH 2021
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4 Functional Block Diagram
图 4-1 shows the functional block diagram for the MSP430i204x devices in the RHB package. For the functional
block diagrams of all device variants and packages, see 节9.2.
ROSC
VCC DVSS AVSS VCORE RST/NMI
P1.x
P2.x
8
8
ACLK
Clock
System
TA0
TA1
Port P1
Port P2
RAM
Flash
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/Os,
Interrupt
capability
8 I/Os,
Interrupt
capability
SMCLK
2KB
1KB
32KB
16KB
MCLK
MAB
MDB
16.384-MHz
CPU
with 16
registers
Emulation
2BP
Hardware
Multiplier
(16x16)
SD24
Power
Management
JTAG
Interface
eUSCI_A0
Watchdog
WDT
eUSCI_B0
SPI, I2C
4
Sigma-Delta
Analog-to-
Digital
LDO
REF
VMON
Brownout
MPY,
MPYS,
MAC,
UART,
IrDA, SPI
15 or 16 bit
Spy-Bi-
Wire
Converters
MACS
图4-1. Functional Block Diagram –RHB Package –MSP430i204x
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Table of Contents
9.3 CPU.......................................................................... 38
9.4 Instruction Set...........................................................39
9.5 Operating Modes...................................................... 40
9.6 Interrupt Vector Addresses....................................... 41
9.7 Special Function Registers....................................... 42
9.8 Flash Memory........................................................... 42
9.9 JTAG Operation........................................................ 43
9.10 Peripherals..............................................................45
9.11 Input/Output Diagrams............................................49
9.12 Device Descriptor....................................................56
9.13 Memory...................................................................57
9.14 Identification............................................................60
10 Applications, Implementation, and Layout............... 61
11 Device and Documentation Support..........................62
11.1 Getting Started and Next Steps.............................. 62
11.2 Device Nomenclature..............................................62
11.3 Tools and Software..................................................63
11.4 Documentation Support.......................................... 64
11.5 支持资源..................................................................65
11.6 Trademarks............................................................. 65
11.7 静电放电警告...........................................................65
11.8 术语表..................................................................... 66
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................6
6.1 Related Products........................................................ 6
7 Terminal Configuration and Functions..........................7
7.1 Pin Diagrams.............................................................. 7
7.2 Signal Descriptions................................................... 10
7.3 Pin Multiplexing.........................................................12
7.4 Connection of Unused Pins...................................... 12
8 Specifications................................................................ 13
8.1 Absolute Maximum Ratings...................................... 13
8.2 ESD Ratings............................................................. 13
8.3 Recommended Operating Conditions.......................13
8.4 Active Mode Supply Current (Into VCC
Excluding External Current .........................................14
8.5 Low-Power Mode Supply Currents (Into VCC
)
)
Excluding External Current .........................................15
8.6 Thermal Resistance Characteristics......................... 15
8.7 Timing and Switching Characteristics....................... 16
9 Detailed Description......................................................32
9.1 Overview...................................................................32
9.2 Functional Block Diagrams....................................... 32
Information.................................................................... 67
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ZHCSI49C –SEPTEMBER 2014 –REVISED MARCH 2021
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5 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from revision B to revision C
Changes from March 4, 2020 to March 16, 2021
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• 节1 更新了特性中的“精选软件和参考设计”..................................................................................................1
Changes from revision A to revision B
Changes from May 3, 2018 to March 3, 2020
Page
• 更新了特性.........................................................................................................................................................1
• 更新了说明.........................................................................................................................................................1
• Added 2 and 4 to the SD24GAINx options in the test conditions of the "Gain error" parameter in 节8.7.7.5,
SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256) ................................................23
• Added 2 and 4 to the SD24GAINx options in the test conditions of the "Gain error" parameter in 节8.7.7.6,
SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256) ...............................................24
• Changed the MIN values for the tHD,STA, tSU,STA, tHD,DAT, tSU,DAT, and tSU,STO parameters in 节8.7.8.6, eUSCI
(I2C Mode) Timing ............................................................................................................................................30
• Updated descriptions and links in 节10, Applications, Implementation, and Layout .......................................61
Changes from the initial release to revision A
Changes from August 31, 2014 to May 2, 2018
Page
• 节2 更改了应用中的应用列表...........................................................................................................................1
• Added 节6.1, Related Products ........................................................................................................................ 6
• Added typical conditions statements at the beginning of 节8, Specifications .................................................13
• Added SD24 input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and
added SD24 input pin limits in "Diode current at pins" parameter in 节8.1, Absolute Maximum Ratings .......13
• Added 节8.2, ESD Ratings ............................................................................................................................. 13
• Added 节8.6, Thermal Resistance Characteristics .........................................................................................15
• Changed the MAX value of the tWAKE-UP-LPM4 parameter from 35 µs to 45 µs in 节8.7.3.1, Wake-up Times
From Low Power Modes ..................................................................................................................................17
• Added the CAUTION that begins "The CPU will lock up if..." in 节9.3, CPU .................................................. 38
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6 Device Comparison
表6-1 summarizes the available family members.
表6-1. Device Comparison
eUSCI_A:
UART, IrDA,
SPI
FLASH
(KB)
SRAM
(KB)
SD24
CONVERTERS
eUSCI_B:
SPI, I2C
DEVICE(1)
MULTIPLIER
Timer_A(2)
I/O
PACKAGE
16
12
16
12
16
12
16
12
16
12
16
12
32 RHB
28 PW
32 RHB
28 PW
32 RHB
28 PW
32 RHB
28 PW
32 RHB
28 PW
32 RHB
28 PW
MSP430i2041
MSP430i2040
MSP430i2031
MSP430i2030
MSP430i2021
MSP430i2020
32
16
32
16
32
16
2
1
2
1
2
1
4
4
3
3
2
2
1
1
1
1
1
1
3, 3
3, 3
3, 3
3, 3
3, 3
3, 3
1
1
1
1
1
1
1
1
1
1
1
1
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in 节12, or
see the TI website at www.ti.com.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
MSP430 ultra-low-power sensing and measurement microcontrollers
One platform. One ecosystem. Endless possibilities.
Reference designs for MSP430i2041
Find reference designs leveraging the best in TI technology to solve your system-level challenges. All designs
include a schematic, test data and design files.
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7 Terminal Configuration and Functions
7.1 Pin Diagrams
32-Pin RHB Package (Top View) – MSP430i2041, MSP430i2040 shows the pin assignments for the
MSP430i2041 and MSP430i2040 devices in the RHB package.
32 31 30 29 28 27 26 25
A0.0+
A0.0-
A1.0+
A1.0-
A2.0+
A2.0-
A3.0+
A3.0-
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
P1.6/UCB0SCL/UCB0SOMI/TA0.2
P1.5/UCB0CLK/TA0.1
MSP430i2041TRHB
MSP430i2040TRHB
P1.4/UCB0STE/TA0.0
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
P1.1/UCA0CLK/SMCLK/TMS
P1.0/UCA0STE/MCLK/TCK
9
10 11 12 13 14 15 16
NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.
图7-1. 32-Pin RHB Package (Top View) –MSP430i2041, MSP430i2040
图7-2 shows the pin assignments for the MSP430i2041 and MSP430i2040 devices in the PW package.
A0.0+
A0.0-
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P2.3/VMONIN
P2.2/TA1.2
A1.0+
A1.0-
3
P2.1/TA1.1
4
P2.0/TA1.0/CLKIN
A2.0+
A2.0-
5
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
P1.6/UCB0SCL/UCB0SOMI/TA0.2
P1.5/UCB0CLK/TA0.1
6
MSP430i2041TPW
MSP430i2040TPW
A3.0+
A3.0-
7
8
P1.4/UCB0STE/TA0.0
VREF
AVSS
ROSC
DVSS
VCC
9
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
P1.1/UCA0CLK/SMCLK/TMS
P1.0/UCA0STE/MCLK/TCK
TEST/SBWTCK
10
11
12
13
14
VCORE
RST/NMI/SBWTDIO
图7-2. 28-Pin PW Package (Top View) –MSP430i2041, MSP430i2040
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32-Pin RHB Package (Top View) – MSP430i2031, MSP430i2030 shows the pin assignments for the
MSP430i2031 and MSP430i2030 devices in the RHB package.
32 31 30 29 28 27 26 25
A0.0+
A0.0-
A1.0+
A1.0-
A2.0+
A2.0-
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
P1.6/UCB0SCL/UCB0SOMI/TA0.2
P1.5/UCB0CLK/TA0.1
MSP430i2031TRHB
MSP430i2030TRHB
P1.4/UCB0STE/TA0.0
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
P1.1/UCA0CLK/SMCLK/TMS
NC
P1.0/UCA0STE/MCLK/TCK
9
10 11 12 13 14 15 16
NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.
NOTE: TI recommends connecting NC pins to AVSS.
图7-3. 32-Pin RHB Package (Top View) –MSP430i2031, MSP430i2030
28-Pin PW Package (Top View) – MSP430i2031, MSP430i2030 shows the pin assignments for the
MSP430i2031 and MSP430i2030 devices in the PW package.
A0.0+
A0.0-
A1.0+
A1.0-
A2.0+
A2.0-
NC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P2.3/VMONIN
P2.2/TA1.2
3
P2.1/TA1.1
4
P2.0/TA1.0/CLKIN
5
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
P1.6/UCB0SCL/UCB0SOMI/TA0.2
P1.5/UCB0CLK/TA0.1
6
MSP430i2031TPW
MSP430i2030TPW
7
NC
8
P1.4/UCB0STE/TA0.0
VREF
AVSS
ROSC
DVSS
VCC
9
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
P1.1/UCA0CLK/SMCLK/TMS
P1.0/UCA0STE/MCLK/TCK
TEST/SBWTCK
10
11
12
13
14
VCORE
RST/NMI/SBWTDIO
NOTE: TI recommends connecting NC pins to AVSS.
图7-4. 28-Pin PW Package (Top View) –MSP430i2031, MSP430i2030
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32-Pin RHB Package (Top View) – MSP430i2021, MSP430i2020 shows the pin assignments for the
MSP430i2021 and MSP430i2020 devices in the RHB package.
32 31 30 29 28 27 26 25
A0.0+
A0.0-
A1.0+
A1.0-
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
P1.6/UCB0SCL/UCB0SOMI/TA0.2
P1.5/UCB0CLK/TA0.1
P1.4/UCB0STE/TA0.0
MSP430i2021TRHB
MSP430i2020TRHB
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
P1.1/UCA0CLK/SMCLK/TMS
NC
NC
NC
P1.0/UCA0STE/MCLK/TCK
9
10 11 12 13 14 15 16
NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.
TI recommends connecting NC pins to AVSS.
图7-5. 32-Pin RHB Package (Top View) –MSP430i2021, MSP430i2020
28-Pin PW Package (Top View) – MSP430i2021, MSP430i2020 shows the pin assignments for the
MSP430i2021 and MSP430i2020 devices in the PW package.
A0.0+
A0.0-
A1.0+
A1.0-
NC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P2.3/VMONIN
P2.2/TA1.2
3
P2.1/TA1.1
4
P2.0/TA1.0/CLKIN
5
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
P1.6/UCB0SCL/UCB0SOMI/TA0.2
P1.5/UCB0CLK/TA0.1
NC
6
NC
7
MSP430i2021TPW
MSP430i2020TPW
NC
8
P1.4/UCB0STE/TA0.0
VREF
AVSS
ROSC
DVSS
VCC
9
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
P1.1/UCA0CLK/SMCLK/TMS
P1.0/UCA0STE/MCLK/TCK
TEST/SBWTCK
10
11
12
13
14
VCORE
RST/NMI/SBWTDIO
TI recommends connecting NC pins to AVSS.
图7-6. 28-Pin PW Package (Top View) –MSP430i2021, MSP430i2020
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7.2 Signal Descriptions
节7.2 describes the signals for all device variants and package options.
表7-1. Signal Descriptions
TERMINAL
NO.(2)
I/O(1)
DESCRIPTION
NAME
PW
RHB
1
A0.0+
A0.0-
1
2
I
I
I
I
I
I
I
I
I
SD24 positive analog input A0.0(3)
2
SD24 negative analog input A0.0(3)
SD24 positive analog input A1.0(3)
SD24 negative analog input A1.0(3)
SD24 positive analog input A2.0(3) (4)
SD24 negative analog input A2.0(3) (4)
SD24 positive analog input A3.0 (3) (4) (5)
SD24 negative analog input A3.0 (3) (4) (5)
SD24 external reference voltage input
Analog supply voltage, negative terminal
External resistor pin for DCO.
A1.0+
A1.0-
3
3
4
4
A2.0+
A2.0-
5
5
6
6
A3.0+
A3.0-
7
7
8
8
VREF(6)
9
9
AVSS
10
10
Connect recommended resistor between ROSC and AVSS for DCO operation
in external resistor mode. Connect ROSC to AVSS while operating DCO in
internal resistor mode.
ROSC
11
11
DVSS
12
13
14
12
13
14
Digital supply voltage, negative terminal
VCC
Analog and digital supply voltage, positive terminal
Regulated core power supply (internal use only, no external current loading)
VCORE (7)
Reset or nonmaskable interrupt input.
Spy-Bi-Wire test data input/output for device programming and test.
RST/NMI/SBWTDIO
TEST/SBWTCK
15
16
15
16
I/O
I
Selects test mode for JTAG pins on P1.0 to P1.3.
Spy-Bi-Wire test clock input for device programming and test.
General-purpose digital I/O pin.
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI).
P1.0/UCA0STE/MCLK/TCK
P1.1/UCA0CLK/SMCLK/TMS
17
18
17
18
I/O
I/O
MCLK output.
JTAG test clock. TCK is the clock input port for device programming and test.
General-purpose digital I/O pin.
eUSCI_A0 clock input/output (direction controlled by eUSCI).
SMCLK output.
JTAG test mode select. TMS is used as an input port for device programming
and test.
General-purpose digital I/O pin.
eUSCI_A0 UART receive data or eUSCI_A0 SPI slave out/master in (direction
P1.2/UCA0RXD/UCA0SOMI/
ACLK/TDI/TCLK
controlled by eUSCI).
19
19
I/O
ACLK output.
JTAG test data input or test clock input for device programming and test.
General-purpose digital I/O pin.
eUSCI_A0 UART transmit data or eUSCI_A0 SPI slave in/master out (direction
controlled by eUSCI).
P1.3/UCA0TXD/UCA0SIMO/
TA0CLK/TDO/TDI
20
21
20
21
I/O
I/O
Timer external clock input TACLK for TA0.
JTAG test data output port. TDO/TDI data output or programming data input
terminal.
General-purpose digital I/O pin.
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI).
P1.4/UCB0STE/TA0.0
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output.
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表7-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.(2)
I/O(1)
DESCRIPTION
PW
RHB
General-purpose digital I/O pin.
eUSCI_B0 clock input/output (direction controlled by eUSCI).
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output.
P1.5/UCB0CLK/TA0.1
22
22
I/O
General-purpose digital I/O pin.
eUSCI_B0 I2C clock or eUSCI_B0 SPI slave out/master in (direction controlled
P1.6/UCB0SCL/UCB0SOMI/
TA0.2
23
23
I/O
by eUSCI).
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output.
General-purpose digital I/O pin.
eUSCI_B0 I2C data or eUSCI_B0 slave input/master output (direction
P1.7/UCB0SDA/UCB0SIMO/
TA1CLK
24
25
24
25
I/O
I/O
controlled by eUSCI).
Timer external clock input TACLK for TA1.
General-purpose digital I/O pin.
Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output.
P2.0/TA1.0/CLKIN
DCO bypass clock input.
General-purpose digital I/O pin.
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output.
P2.1/TA1.1
26
27
26
27
28
29
30
31
32
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O pin.
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 output.
P2.2/TA1.2
General-purpose digital I/O pin.
Voltage monitor input.
P2.3/VMONIN
P2.4/TA1.0(8)
P2.5/TA0.0(8)
P2.6/TA0.1(8)
P2.7/TA0.2(8)
28
General-purpose digital I/O pin.
Timer TA1 CCR0 capture: CCI0B input, compare: Out0 output.
N/A
N/A
N/A
N/A
General-purpose digital I/O pin.
Timer TA0 CCR0 capture: CCI0B input, compare: Out0 output.
General-purpose digital I/O pin.
Timer TA0 CCR1 compare: Out1 output.
General-purpose digital I/O pin.
Timer TA0 CCR2 compare: Out2 output.
(1) I = input, O = output
(2) N/A = not available
(3) Short unused analog input pairs and connect them to analog ground (see 节7.4 for recommendations on all unused pins).
(4) Not available on MSP430i2021 and MSP430i2020 devices.
(5) Not available on MSP430i2031 and MSP430i2030 devices.
(6) When the SD24 operates with the internal reference (SD24REFS = 1), the VREF pin must not be loaded externally. Connect only the
recommended capacitor value (CVREF) from the VREF pin to AVSS (see 节8.7.7.2).
(7) VCORE is for internal use only. No external current loading is possible. Connect VCORE to only the recommended capacitor value
(CVCORE) (see 节8.3).
(8) These pins are not available on the 28-pin PW package. Program these four pins to output direction and drive value 0 in software.
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7.3 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the
device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see 节
9.11.
7.4 Connection of Unused Pins
表7-2 lists the correct termination of all unused pins.
表7-2. Connection of Unused Pins
PIN(1)
AVCC
POTENTIAL
DVCC
COMMENT
AVSS
DVSS
VREF
Open
ROSC
AVSS
Connect the ROSC pin to AVSS when the DCO is used in internal resistor mode.
Set to port function, output direction.
Px.0 to Px.7
Ax.0+ and Ax.0-
RST/NMI
TEST
Open
AVSS
Short unused analog input pairs and connect them to analog ground.
47-kΩpullup with 10 nF (or 2.2 nF(2)) pulldown
DVCC or VCC
Open
This pin always has an internal pulldown enabled.
P1.3/TDO
P1.2/TDI
P1.1/TMS
P1.0/TCK
The JTAG pins are shared with general-purpose I/O function (P1.x). If these pins are not
used, set them to port function and output direction. When used as JTAG pins, leave these
pins open.
Open
(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 unused
pin connection.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.
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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
Supply voltage applied at VCC
Voltage applied to pins
4.1
V
–0.3
–0.3
All pins except VCORE(3), ROSC(4), and SD24 input pins
(A0.0+, A0.0-, A1.0+, A1.0-, A2.0+, A2.0-, A3.0+, A3.0-)(5)
VCC + 0.3
±2
V
All pins except SD24 input pins (A0.0+, A0.0-, A1.0+, A1.0-,
A2.0+, A2.0-, A3.0+, A3.0-)
Diode current at pins
mA
A0.0+, A0.0-, A1.0+, A1.0-, A2.0+, A2.0-, A3.0+, A3.0-(6)
2
115
150
Maximum junction temperature, TJ,MAX
°C
°C
(7)
Storage temperature, Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are referenced to VSS
.
(3) VCORE is for internal device use only. Do not apply external DC loading or voltage at VCORE.
(4) Do not apply external DC loading or voltage at ROSC. Connect the recommended resistor at ROSC using the DCO in external resistor
mode. Connect ROSC to AVSS when operating the DCO in internal resistor mode.
(5) See 节8.7.7.1 for SD24 specifications.
(6) A protection diode is connected to VCC for the SD24 input pins. No protection diode is connected to VSS
.
(7) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
8.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
VCC
VSS
TA
Supply voltage during program execution and flash programming or erase (VCC = VCC
)
2.2
3.6
V
V
Supply voltage (AVSS = DVSS = VSS
Operating free-air temperature
)
0
T temperature range
T temperature range
105
105
°C
°C
nF
–40
–40
TJ
Operating junction temperature
Recommended capacitor at VCORE
CVCORE
470
CVCC
CVCORE
/
Capacitor ratio of VCC to VCORE
10
0
fSYSTEM
Processor frequency (maximum MCLK frequency) (1) (2)
16.384 MHz
(1) The MSP430i CPU is clocked directly with MCLK.
(2) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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16.384
0
2.2
3.6
Supply Voltage (V)
图8-1. Maximum System Frequency
8.4 Active Mode Supply Current (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fDCO = 16.384 MHz, fMCLK = fSMCLK = 1.024 MHz,
fACLK = 32 kHz,
Program executes from flash,
Active mode
IAM, 1.024MHz current at
1.024 MHz
3 V
1.6
mA
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
fDCO = 16.384 MHz, fMCLK = fSMCLK = 8.192 MHz,
fACLK = 32 kHz,
Program executes from flash,
Active mode
IAM, 8.192MHz current at
8.192 MHz
3 V
3 V
3.0
4.5
mA
mA
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
fDCO = fMCLK = fSMCLK = 16.384 MHz,
fACLK = 32 kHz,
Program executes from flash,
Active mode
IAM, 16.384MHz current at
16.384 MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
(2) All peripherals are inactive.
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
TA = 25°C, VCC = 2.2 V
TA = 25°C, VCC = 3 V
TA = 105°C, VCC = 2.2 V
TA = 105°C, VCC = 3 V
fMCLK = 1.024 MHz
fMCLK = 2.048 MHz
fMCLK = 4.096 MHz
fMCLK = 8.192 MHz
fMCLK = 16.348 MHz
1.5
1
0.5
0
2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3 3.1 3.2 3.3 3.4 3.5 3.6
0
2
4
6
8
10
12
fMCLK - Frequency (MHz)
14
16
18
VCC - Supply Voltage (V)
D007
D008
图8-2. Active Mode Current vs Supply Voltage
图8-3. Active Mode Current vs MCLK Frequency
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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN TYP MAX UNIT
fDCO = 16.384 MHz, fMCLK = fSMCLK = 0 MHz,
fACLK = 32 kHz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0
Low-power mode 3
(LPM3) current (2)
ILPM3
ILPM4
ILPM4.5
25°C
3 V
210
70
µA
µA
Low-power mode 4
(LPM4) current (3)
fDCO = fMCLK = fSMCLK = fACLK = 0 MHz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1
25°C
3 V
3 V
fDCO = fMCLK = fSMCLK = fACLK = 0 MHz,
REGOFF = 1, CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C
75
nA
nA
Low-power mode 4.5
(LPM4.5) current (3)
105°C
325
(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by ACLK included. All other peripherals are inactive.
(3) All peripherals are inactive.
8.6 Thermal Resistance Characteristics
THERMAL METRIC(1)
PACKAGE
VALUE(2) (3)
UNIT
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.9
25.5
8.6
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
RθJC(TOP)
RθJB
QFN-32 (RHB)
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
8.6
ΨJB
0.3
ΨJT
1.4
RθJC(BOTTOM)
RθJA
77.5
18.2
35.5
35.0
0.5
RθJC(TOP)
RθJB
TSSOP-28 (PW)
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
ΨJT
N/A
RθJC(BOTTOM)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC package thermal metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) N/A = Not applicable
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8.7 Timing and Switching Characteristics
8.7.1 Reset Timing
8.7.1.1 Reset Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tRESET
Pulse duration required at the RST/NMI pin to accept a reset
4
µs
8.7.2 Clock Specifications
8.7.2.1 DCO in External Resistor Mode
recommended resistor at ROSC pin: 20 kΩ, 0.1%, ±50 ppm/°C)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
IDCO
DCO current consumption
DCO frequency calibrated
DCO absolute tolerance calibrated
DCO frequency temperature drift
85
16.384
MHz
fDCO
VCC = 3 V, TA = 25°C
±0.25%
dfDCO/dT
±20 ppm/°C
dfDCO/dVCC DCO frequency supply voltage drift
200
50%
40
600
ppm/V
DCDCO
Tdcoon
Duty cycle
DCO start-up time
µs
(1) The maximum parasitic capacitance at ROSC pin should not exceed 5 pF to ensure the specified DCO start-up time.
8.7.2.2 DCO in Internal Resistor Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
IDCO
DCO current consumption
DCO frequency calibrated
DCO absolute tolerance calibrated
DCO frequency temperature drift
85
16.384
MHz
fDCO
VCC = 3 V, TA = 25°C
±0.9%
dfDCO/dT
±200 ppm/°C
dfDCO/dVCC DCO frequency supply voltage drift
200
50%
40
600
ppm/V
DCDCO
Tdcoon
Duty cycle
DCO start-up time
µs
8.7.2.3 DCO Overall Tolerance Table
over operating free-air temperature range (unless otherwise noted)
OVERALL
ACCURACY
(%)
TEMPERATURE
CHANGE
TEMPERATURE
DRIFT (%)
VOLTAGE
CHANGE
VOLTAGE
DRIFT (%)
OVERALL
DRIFT (%)
RESISTOR OPTION
±2.9
0
2.2 V to 3.6 V
2.2 V to 3.6 V
0 V
±0.084
±0.084
0
±2.984
±0.084
±2.9
±3.884
±0.984
±3.8
–40°C to 105 °C
0°C
Internal resistor
±2.9
±0.29
0
–40°C to 105 °C
–40°C to 105 °C
0°C
2.2 V to 3.6 V
2.2 V to 3.6 V
0 V
±0.084
±0.084
0
±0.374
±0.084
±0.29
±0.624
±0.334
±0.54
External resistor with
50-ppm TCR
±0.29
–40°C to 105 °C
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8.7.2.4 DCO in Bypass Mode Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Frequency in DCO bypass mode(1)
MIN
MAX
UNIT
fDCOBYP
0
16.384
MHz
(1) External digital clock frequency in DCO bypass mode must be 16.384 MHz for the SD24 module to meet the specified performance.
8.7.3 Wake-up Characteristics
8.7.3.1 Wake-up Times From Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
tWAKE-UP-LPM3
tWAKE-UP-LPM4
Wake-up time from LPM3 to active mode MCLK = SMCLK = 1.024 MHz
Wake-up time from LPM4 to active mode MCLK = SMCLK = 1.024 MHz
1
45
µs
Wake-up time from LPM4.5 to active
CVCORE = 470 nF
tWAKE-UP-LPM4.5-IO
0.45
0.45
ms
ms
mode upon I/O event(1)
tWAKE-UP-LPM4.5-
Wake-up time from LPM4.5 to active
CVCORE = 470 nF
mode upon external reset ( RST)(1)
RESET
(1) This value represents the time from the wake-up event to the reset vector execution by CPU.
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8.7.4 I/O Ports
8.7.4.1 Schmitt-Trigger Inputs –General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.5 VCC
1.50
TYP
MAX UNIT
0.7 VCC
VIT+
Positive-going input threshold voltage
V
V
3 V
2.10
0.55 VCC
1.65
0.25 VCC
0.75
VIT-
Negative-going input threshold voltage
3 V
3 V
Vhys
CI
0.4
1.1
V
Input voltage hysteresis (VIT+ –VIT-
)
Input capacitance
VIN = VSS or VCC
5
pF
8.7.4.2 Inputs –Ports P1 and P2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger pulse
duration to set interrupt flag
t(int)
External interrupt timing(1)
3 V
20
ns
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
8.7.4.3 Leakage Current –General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See (1) (2)
VCC
MIN
MAX UNIT
±50 nA
Ilkg(Py.x)
High-impedance leakage current
3 V
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input.
8.7.4.4 Outputs –General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
I(OHmax) = –6 mA(1)
I(OLmax) = 6 mA(1)
VCC
3.0 V
3.0 V
MIN
VCC –0.60
VSS
MAX UNIT
VOH
VOL
VCC
VSS + 0.60
V
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
8.7.4.5 Output Frequency –General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Py.x, CL = 20 pF, RL = 3.2 kΩ (1) (2)
Py.x, CL = 20 pF(2)
VCC
3 V
3 V
TYP UNIT
16.384 MHz
16.384 MHz
fPy.x
Port output frequency (with load)
fPort_CLK Clock output frequency
(1) A resistive divider with two times 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% of VCC at the specified toggle frequency.
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8.7.4.6 Typical Characteristics –Outputs
One output loaded at a time.
14
12
10
8
22
20
18
16
14
12
10
8
6
4
6
2
4
2
0
TA = 25°C
TA = 105°C
TA = 25°C
TA = 105°C
0
-2
-2
0
0.25 0.5 0.75
1
1.25 1.5 1.75
VOL - Low-Level Output Voltage (V)
2
2.25
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
VOL - Low Output Voltage (V)
3
D004
D003
VCC = 2.2 V Measured at P1.3
VCC = 3 V Measured at P1.3
图8-4. Typical Low-Level Output Current vs Low- 图8-5. Typical Low-Level Output Current vs Low-
Level Output Voltage
Level Output Voltage
0
0
-2
TA = 25°C
TA = 105°C
TA = 25°C
TA = 105°C
-2
-4
-6
-4
-8
-10
-12
-14
-16
-18
-20
-22
-6
-8
-10
-12
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
VOH - High-Level Output Voltage (V)
2
2.2
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
VOH - High-Level Output Voltage (V)
3
D006
D005
VCC = 2.2 V Measured at P1.3
VCC = 3 V Measured at P1.3
图8-6. Typical High-Level Output Current vs High- 图8-7. Typical High-Level Output Current vs High-
Level Output Voltage
Level Output Voltage
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8.7.5 Power Management Module
8.7.5.1 PMM, High-Side Brownout Reset (BORH)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dVCC/dt | < 3 V/s
| dVCC/dt | < 3 V/s
MIN
TYP
1.08
1.18
100
MAX UNIT
BORH on voltage, VCC falling level
BORH off voltage, VCC rising level
BORH hysteresis
V
V
V(VCC_BOR_IT–)
V(VCC_BOR_IT+)
V(VCC_BOR_hys)
mV
(1)
tPOWERUP
Cold power-up time
0.75
ms
(1) This is the time duration between application of VCC and execution of reset vector by CPU.
8.7.5.2 PMM, Low-Side SVS (SVSL)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
1.70
14
MAX UNIT
V(SVSL)
SVSL trip voltage on VCORE
V
V(SVSL_hys) SVSL hysteresis
mV
µA
I(SVSL)
SVSL current consumption
3
8.7.5.3 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
VCORE
Core voltage
1.83
V
8.7.5.4 PMM, Voltage Monitor (VMON)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.17
2.32
2.62
2.82
6
MAX UNIT
VMONIN trip level
VMONLVLx = 111b
VMONLVLx = 001b
VMONLVLx = 010b
VMONLVLx = 011b
VCC trip level –1
VCC trip level –2
VCC trip level –3
VMON current consumption
VMON settling time
VMONtrip_level
V
IVMON
tVMON
µA
µs
0.5
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8.7.6 Reference Module
8.7.6.1 Voltage Reference (REF)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC
VBG
Supply voltage range
2.2
3.6
V
V
Bandgap output voltage calibrated
VCC = 3 V
1.146 1.158
50
1.17
PSRR_DC Power supply rejection ratio (DC)
VCC = 2.2 V to 3.6 V
µV/V
VCC = 2.2 V to 3.6 V, f = 1 kHz,
ΔVpp = 100 mV
PSRR_AC Power supply rejection ratio (AC)
0.35
10
mV/V
dVBG/dT
Bandgap reference temperature coefficient
VCC = 3 V
50 ppm/°C
8.7.6.2 Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 3 V, TA = 30°C
VCC = 3 V, TA = 105°C
MIN
610
765
TYP
650
805
3
MAX UNIT
690
mV
845
Vsensor
Temperature sensor output voltage
Isensor
Temperature sensor quiescent current consumption
Temperature coefficient of sensor
µA
TCsensor
1.96
2.07
2.17 mV/°C
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8.7.7 SD24
8.7.7.1 SD24 Power Supply and Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VCC
Supply voltage range
AVSS = DVSS = 0 V
2.2
3.6
V
GAIN: 1, 2, 4, 8, 16
GAIN: 1, 16
3 V
3 V
190
Analog plus digital supply current per
converter (reference current not included)
ISD24
SD24OSRx = 256
µA
250
8.7.7.2 SD24 Internal Voltage Reference
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VSD24REF
CVREF
SD24 internal reference voltage
Recommended capacitor at VREF
SD24REFS = 1
3 V
1.146 1.158
1.17
V
100
200
nF
µs
tSD24REF_settle SD24 reference buffer settling time
SD24REFS = 0 →1, CVREF = 100 nF
(1) When SD24 operates with internal reference (SD24REFS = 1), the VREF pin must not be loaded externally. Only the recommended
capacitor value, CVREF must be connected at the VREF pin to AVSS.
8.7.7.3 SD24 External Voltage Reference
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage range
Input current
TEST CONDITIONS
VCC
3 V
3 V
MIN
TYP
MAX UNIT
VREF(I)
IREF(I)
SD24REFS = 0
SD24REFS = 0
1.0
1.2
1.5
50
V
nA
8.7.7.4 SD24 Input Range
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Differential full-scale input voltage
range
+VREF
GAIN
/
–VREF
GAIN
/
VID,FSR
V
VID = VI,A+ –VI,A–
SD24GAINx = 1
±928
±464
±232
±116
±58
SD24GAINx = 2
SD24GAINx = 4
SD24GAINx = 8
SD24GAINx = 16
Differential input voltage range for
specified performance(2)
VID
SD24REFS = 1
mV
Input impedance
(pin A+ or A- to AVSS
ZI
SD24GAINx = 1, 16
SD24GAINx = 1, 16
3 V
3 V
200
400
kΩ
kΩ
(3)
)
Differential input impedance (pin A+
to pin A-)(3)
ZID
300
VI
Absolute input voltage range
VCC
VCC
V
V
AVSS –1
AVSS –1
VIC
Common-mode input voltage range
(1) All parameters pertain to each SD24 channel.
(2) The full-scale range is defined by VFSR+ = +VREF/GAIN and VFSR– = –VREF/GAIN; FSR = VFSR+ –VFSR– = 2xVREF/GAIN. If VREF is
sourced externally, the analog input range should not exceed 80% of VFSR+ or VFSR–; that is, VID = 0.8 VFSR– to 0.8 VFSR+. If VREF is
sourced internally, the given VID ranges apply.
(3) Applicable for SD24 modulator OFF as well as ON conditions.
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8.7.7.5 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
89
MAX UNIT
SD24GAINx = 1
SD24GAINx = 2
SD24GAINx = 4
SD24GAINx = 8
SD24GAINx = 16
SD24GAINx = 1
84
89
Signal-to-noise +
distortion ratio
SINAD
THD
fIN = 50 Hz(1)
3 V
87
dB
83
77
100
95
Total harmonic distortion SD24GAINx = 8
SD24GAINx = 16
fIN = 50 Hz(1)
3 V
dB
90
SD24GAINx = 1
Spurious-free dynamic
SD24GAINx = 8
range
100
95
SFDR
INL
fIN = 50 Hz(1)
3 V
3 V
dB
SD24GAINx = 16
90
Integral nonlinearity,
SD24GAINx: 1, 8, 16
end-point fit
0.003 % FSR
–0.003
SD24GAINx = 1
SD24GAINx = 2
1
2
G
Nominal gain
SD24GAINx = 4
SD24GAINx = 8
SD24GAINx = 16
3 V
4
8
16
EG
Gain error
SD24GAINx: 1, 2, 4, 8, 16
SD24GAINx: 1, 8, 16
3 V
3 V
2%
–2%
Gain error temperature
coefficient
50 ppm/°C
ΔEG/ ΔT
SD24GAINx = 1
SD24GAINx = 16
SD24GAINx = 1
SD24GAINx = 16
4
EOS
Offset error
3 V
3 V
mV
2
±5
±3
±25
Offset error temperature
coefficient
ppm
FSR/°C
ΔEOS/ΔT
±10
SD24GAINx = 1, Common-mode input signal:
VID = 928 mV, fIN = 50 Hz
–55
–60
–90
–95
–95
Common-mode rejection
ratio at 50 Hz
CMRR,50Hz
AC PSRR
3 V
dB
dB
SD24GAINx = 16, Common-mode input signal:
VID = 58 mV, fIN = 50 Hz
SD24GAINx: 1, VCC = 3 V ±50 mV × sin(2π× fVCC × t), fVCC
50 Hz, Inputs grounded (no analog signal applied)
=
=
3 V
3 V
3 V
AC power supply
rejection ratio
SD24GAINx: 8, VCC = 3 V ±50 mV × sin(2π× fVCC × t), fVCC
50 Hz, Inputs grounded (no analog signal applied)
SD24GAINx: 16, VCC = 3 V ±50 mV × sin(2π× fVCC × t), fVCC
50 Hz, Inputs grounded (no analog signal applied)
=
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 1
–120
–110
–110
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 8
Crosstalk between
converters
XT
3 V
dB
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 16
(1) The following voltages are applied to the SD24 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π× fIN × t)
VI,A–(t) = 0 V –VPP/2 × sin(2π× fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) –VIN,A–(t) = VPP × sin(2π× fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24 input range).
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8.7.7.6 SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)
external reference voltage is 1.2 V., over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
91
MAX UNIT
SD24GAINx = 1
SD24GAINx = 2
SD24GAINx = 4
SD24GAINx = 8
SD24GAINx = 16
SD24GAINx = 1
SD24GAINx = 8
SD24GAINx = 16
SD24GAINx = 1
SD24GAINx = 8
SD24GAINx = 16
90
Signal-to-noise + distortion
ratio
SINAD
THD
fIN = 50 Hz(1)
3 V
88
dB
83
77
100
95
Total harmonic distortion
fIN = 50 Hz(1)
3 V
dB
90
100
95
Spurious-free dynamic
range
SFDR
INL
fIN = 50 Hz(1)
3 V
3 V
dB
90
Integral nonlinearity, end-
point fit
SD24GAINx: 1, 8, 16
0.003 % FSR
–0.003
SD24GAINx = 1
SD24GAINx = 2
SD24GAINx = 4
SD24GAINx = 8
SD24GAINx = 16
1
2
G
Nominal gain
3 V
4
8
16
EG
Gain error
SD24GAINx: 1, 2, 4, 8, 16
SD24GAINx: 1, 8, 16
3 V
3 V
+1%
–1%
Gain error temperature
coefficient
10 ppm/°C
ΔEG/ ΔT
SD24GAINx = 1
SD24GAINx = 16
SD24GAINx = 1
SD24GAINx = 16
4
EOS
Offset error
3 V
3 V
mV
2
±5
±3
±25
Offset error temperature
coefficient
ppm
FSR/°C
ΔEOS/ΔT
±10
SD24GAINx = 1, Common-mode input signal:
VID = 928 mV, fIN = 50 Hz
–55
–60
–90
–95
–95
Common-mode rejection
ratio at 50 Hz
CMRR,50Hz
AC PSRR
3 V
dB
dB
SD24GAINx = 16, Common-mode input signal:
VID = 58 mV, fIN = 50 Hz
SD24GAINx: 1, VCC = 3 V ±50 mV × sin(2π× fVCC × t), fVCC
50 Hz, Inputs grounded (no analog signal applied)
=
=
3 V
3 V
3 V
AC power supply rejection
ratio
SD24GAINx: 8, VCC = 3 V ±50 mV × sin(2π× fVCC × t), fVCC
50 Hz, Inputs grounded (no analog signal applied)
SD24GAINx: 16, VCC = 3 V ±50 mV × sin(2π× fVCC × t), fVCC
= 50 Hz, Inputs grounded (no analog signal applied)
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 1
–120
–110
–110
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 8
Crosstalk between
converters
XT
3 V
dB
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 16
(1) The following voltages are applied to the SD24 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π× fIN × t)
VI,A–(t) = 0 V –VPP/2 × sin(2π× fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) –VIN,A–(t) = VPP × sin(2π× fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24 input range).
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8.7.7.7 Typical Characteristics
90
87
84
81
78
75
72
69
66
63
60
57
90
85
80
75
70
65
60
55
0
0.2
0.4
0.6
VPP (V)
0.8
1
1.2
25
50
75 100 125 150 175 200 225 250 275
OSR
D002
D001
A.fSD24 = 1.024 MHz
OSR = 256
SD24REFS = 1
SD24GAINx = 1
A.fSD24 = 1.024 MHz
SD24REFS = 1
SD24GAINx = 1
图8-8. SINAD vs OSR
图8-9. SINAD vs VPP
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8.7.8 eUSCI
8.7.8.1 eUSCI (UART Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
MIN
MAX UNIT
feUSCI
eUSCI input clock frequency
External: UCLK
fSYSTEM MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
4
MHz
8.7.8.2 eUSCI (UART Mode) Deglitch Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
UCGLITx = 0
8
15
20
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
30
50
70
50
60
ns
tt
UART receive deglitch time(1)
2.2 V, 3 V
70
100
100
150
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
8.7.8.3 eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MIN
MAX UNIT
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
8.7.8.4 eUSCI (SPI Master Mode) Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
2.2 V, 3 V
2.2 V, 3 V
2.2 V
MIN
150
200
MAX UNIT
tSTE,LEAD
tSTE,LAG
STE lead time, STE active to clock
STE lag time, Last clock to STE inactive
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
ns
ns
40
ns
30
STE access time, STE active to SIMO
data out
tSTE,ACC
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
3 V
2.2 V
40
ns
30
STE disable time, STE inactive to SIMO
high impedance
tSTE,DIS
3 V
2.2 V
50
30
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
ns
3 V
tHD,MI
2.2 V, 3 V
2.2 V
7
tVALID,MO
tHD,MO
UCLK edge to SIMO valid, CL = 20 pF
CL = 20 pF
ns
5
3 V
2.2 V, 3 V
0
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in 图8-10 and 图8-11.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in 图
8-10 and 图8-11.
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,ACC
tSTE,DIS
图8-10. SPI Master Mode, CKPH = 0
UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
tSTE,DIS
tSTE,ACC
图8-11. SPI Master Mode, CKPH = 1
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8.7.8.5 eUSCI (SPI Slave Mode) Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
2.2 V, 3 V
2.2 V, 3 V
2.2 V
MIN
MAX UNIT
tSTE,LEAD
tSTE,LAG
STE lead time, STE active to clock
STE lag time, Last clock to STE inactive
3
ns
ns
0
35
ns
25
tSTE,ACC
STE access time, STE active to SOMI data out
3 V
STE disable time, STE inactive to SOMI high
impedance
tSTE,DIS
2.2 V, 3 V
35
ns
tSU,SI
tHD,SI
SIMO input data setup time
SIMO input data hold time
2.2 V, 3 V
2.2 V, 3 V
2.2 V
1
5
ns
ns
35
25
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
ns
3 V
2.2 V
35
25
tHD,SO
CL = 20 pF
3 V
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), refer to the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in 图8-12 and 图8-13.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in 图
8-12 and 图8-13.
UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SI
tLOW/HIGH
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
图8-12. SPI Slave Mode, CKPH = 0
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
图8-13. SPI Slave Mode, CKPH = 1
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8.7.8.6 eUSCI (I2C Mode) Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-14)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3 V
2.2 V, 3 V
0
4.8
1.2
4.9
1.26
0.12
4.7
1.08
4.9
1.18
75
400
kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
tHD,DAT
tSU,DAT
Setup time for a repeated START
Data hold time
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
µs
µs
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
Data setup time
tSU,STO
Setup time for STOP
2.2 V, 3 V
2.2 V, 3 V
µs
ns
110
50
25
15
33
37
41
160
80
35
Pulse duration of spikes suppressed
by input filter
tSP
15
40
10
20
tTIMEOUT
Clock low timeout
2.2 V, 3 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
图8-14. I2C Mode Timing
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8.7.9 Timer_A
8.7.9.1 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK
External: TACLK
fTA
Timer_A input clock frequency
3.0 V
16.384 MHz
All capture inputs, Minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
3.0 V
20
ns
8.7.10 Flash
8.7.10.1 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX UNIT
VCC(PGM/ERASE) Program and erase supply voltage
2.2
3.6
476
8
V
kHz
mA
fFTG
Flash timing generator frequency
Supply current from VCC during program
Supply current from VCC during erase
Cumulative program time(1)
257
IPGM
IERASE
tCPT
2.2 V, 3.6 V
2.2 V, 3.6 V
2.2 V, 3.6 V
13
8
mA
ms
Program and erase endurance
Data retention duration
20000
100
cycles
years
tRetention
tWord
TJ = 25°C
(2)
Word or byte program time
25
20
(2)
tBlock, 0
Block program time for first byte or word
Block program time for each additional byte or
word
(2)
tBlock, 1-63
11
tFTG
(2)
(2)
(2)
tBlock, End
tMass Erase
tSeg Erase
Block program end-sequence wait time
Mass erase time
6
10593
9628
Segment erase time
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word-write mode, individual byte-write mode, and block-write mode.
(2) These values are hardwired into the state machine of the flash controller (tFTG = 1/fFTG).
8.7.11 Emulation and Debug
8.7.11.1 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
0
20 MHz
tSBW,Low
tSBW, En
tSBW,Rst
fTCK
Spy-Bi-Wire low clock pulse duration
0.025
15
1
μs
μs
μs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)
Spy-Bi-Wire return to normal operation time
TCK input frequency, 4-wire JTAG(2)
15
0
100
10 MHz
80
Rinternal
Internal pulldown resistance on TEST
45
60
kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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9 Detailed Description
9.1 Overview
The MSP430i204x, MSP430i203x, MSP430i202x devices consist of a powerful 16-bit RISC CPU, a DCO-based
clock system that generates system clocks, a power-management module (PMM) with built-in voltage reference
and voltage monitor, two to four 24-bit sigma-delta analog-to-digital converters (ADCs), a temperature sensor, a
16-bit hardware multiplier, two 16-bit timers, one eUSCI-A module and one eUSCI-B module, a watchdog timer
(WDT), and up to 16 I/O pins.
9.2 Functional Block Diagrams
图9-1 shows the functional block diagram for the MSP430i2041 and MSP430i2040 in the RHB package.
ROSC
VCC DVSS AVSS VCORE RST/NMI
P1.x
P2.x
8
8
ACLK
Clock
System
TA0
TA1
Port P1
Port P2
RAM
Flash
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/Os,
Interrupt
capability
8 I/Os,
Interrupt
capability
SMCLK
2KB
1KB
32KB
16KB
MCLK
MAB
MDB
16.384-MHz
CPU
with 16
registers
Emulation
2BP
Hardware
Multiplier
(16x16)
SD24
Power
Management
JTAG
Interface
eUSCI_A0
Watchdog
WDT
eUSCI_B0
SPI, I2C
4
Sigma-Delta
Analog-to-
Digital
LDO
REF
VMON
Brownout
MPY,
MPYS,
MAC,
UART,
IrDA, SPI
15 or 16 bit
Spy-Bi-
Wire
Converters
MACS
图9-1. Functional Block Diagram –RHB Package –MSP430i2041, MSP430i2040
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图9-2 shows the functional block diagram for the MSP430i2041 and MSP430i2040 in the PW package.
ROSC
VCC DVSS AVSS VCORE RST/NMI
P1.x
P2.x
4
8
ACLK
Clock
System
TA0
TA1
Port P1
Port P2
RAM
Flash
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/Os,
Interrupt
capability
4 I/Os,
Interrupt
capability
SMCLK
2KB
1KB
32KB
16KB
MCLK
16.384-MHz
CPU
MAB
MDB
with 16
registers
Emulation
2BP
Hardware
Multiplier
(16x16)
SD24
Power
Management
JTAG
Interface
eUSCI_A0
Watchdog
WDT
eUSCI_B0
SPI, I2C
4
Sigma-Delta
Analog-to-
Digital
LDO
REF
VMON
Brownout
UART,
IrDA, SPI
MPY,
MPYS,
MAC,
15 or 16 bit
Spy-Bi-
Wire
Converters
MACS
图9-2. Functional Block Diagram –PW Package –MSP430i2041, MSP430i2040
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图9-3 shows the functional block diagram for the MSP430i2031 and MSP430i2030 in the RHB package.
ROSC
VCC DVSS AVSS VCORE RST/NMI
P1.x
P2.x
8
8
ACLK
Clock
System
TA0
TA1
Port P1
Port P2
RAM
Flash
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/Os,
Interrupt
capability
8 I/Os,
Interrupt
capability
SMCLK
2KB
1KB
32KB
16KB
MCLK
16.384-MHz
CPU
MAB
MDB
with 16
registers
Emulation
2BP
Hardware
Multiplier
(16x16)
SD24
Power
Management
JTAG
Interface
eUSCI_A0
Watchdog
WDT
eUSCI_B0
SPI, I2C
3
Sigma-Delta
Analog-to-
Digital
LDO
REF
VMON
Brownout
UART,
IrDA, SPI
MPY,
MPYS,
MAC,
15 or 16 bit
Spy-Bi-
Wire
Converters
MACS
图9-3. Functional Block Diagram –RHB Package –MSP430i2031, MSP430i2030
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图9-4 shows the functional block diagram for the MSP430i2031 and MSP430i2030 in the PW package.
ROSC
VCC DVSS AVSS VCORE RST/NMI
P1.x
P2.x
4
8
ACLK
Clock
System
TA0
TA1
Port P1
Port P2
RAM
Flash
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/Os,
Interrupt
capability
4 I/Os,
Interrupt
capability
SMCLK
2KB
1KB
32KB
16KB
MCLK
16.384-MHz
CPU
MAB
MDB
with 16
registers
Emulation
2BP
Hardware
Multiplier
(16x16)
SD24
Power
Management
JTAG
Interface
eUSCI_A0
Watchdog
WDT
eUSCI_B0
SPI, I2C
3
Sigma-Delta
Analog-to-
Digital
LDO
REF
VMON
Brownout
UART,
IrDA, SPI
MPY,
MPYS,
MAC,
15 or 16 bit
Spy-Bi-
Wire
Converters
MACS
图9-4. Functional Block Diagram –PW Package –MSP430i2031, MSP430i2030
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图9-5 shows the functional block diagram for the MSP430i2021 and MSP430i2020 in the RHB package.
ROSC
VCC DVSS AVSS VCORE RST/NMI
P1.x
P2.x
8
8
ACLK
Clock
System
TA0
TA1
Port P1
Port P2
RAM
Flash
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/Os,
Interrupt
capability
8 I/Os,
Interrupt
capability
SMCLK
2KB
1KB
32KB
16KB
MCLK
16.384-MHz
CPU
MAB
MDB
with 16
registers
Emulation
2BP
Hardware
Multiplier
(16x16)
SD24
Power
Management
JTAG
Interface
eUSCI_A0
Watchdog
WDT
eUSCI_B0
SPI, I2C
2
Sigma-Delta
Analog-to-
Digital
LDO
REF
VMON
Brownout
UART,
IrDA, SPI
MPY,
MPYS,
MAC,
15 or 16 bit
Spy-Bi-
Wire
Converters
MACS
图9-5. Functional Block Diagram –RHB Package –MSP430i2021, MSP430i2020
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图9-6 shows the functional block diagram for the MSP430i2021 and MSP430i2020 in the PW package.
ROSC
VCC DVSS AVSS VCORE RST/NMI
P1.x
P2.x
4
8
ACLK
Clock
System
TA0
TA1
Port P1
Port P2
RAM
Flash
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/Os,
Interrupt
capability
4 I/Os,
Interrupt
capability
SMCLK
2KB
1KB
32KB
16KB
MCLK
16.384-MHz
CPU
MAB
MDB
with 16
registers
Emulation
2BP
Hardware
Multiplier
(16x16)
SD24
Power
Management
JTAG
Interface
eUSCI_A0
Watchdog
WDT
eUSCI_B0
SPI, I2C
2
Sigma-Delta
Analog-to-
Digital
LDO
REF
VMON
Brownout
UART,
IrDA, SPI
MPY,
MPYS,
MAC,
15 or 16 bit
Spy-Bi-
Wire
Converters
MACS
图9-6. Functional Block Diagram –PW Package –MSP430i2021, MSP430i2020
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9.3 CPU
The MSP430i CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator respectively. The remaining registers are general-purpose registers (see 图9-7).
Peripherals are connected to the CPU using data, address, and control buses and can be handled with all
instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
图9-7. CPU Registers
CAUTION
The CPU will lock up if the device enters a low-power mode (CPU off) within 64 cycles after reset.
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9.4 Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can
operate on word and byte data. 表 9-1 gives examples of the three types of instruction formats; 表 9-2 lists the
address modes.
表9-1. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
Dual operands, source and destination
Single operands, destination only
Relative jump, unconditional or conditional
R4 + R5 →R5
PC →(TOS), R8 →PC
Jump-on-equal bit = 0
表9-2. Address Mode Descriptions
ADDRESS MODE
Register
S (1) D (2)
SYNTAX
EXAMPLE
OPERATION
MOV Rs,Rd
MOV R10,R11
R10 →R11
✓
✓
✓
✓
✓
✓
✓
✓
✓
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) →M(6+R6)
M(EDE) →M(TONI)
M(MEM) →M(TCDAT)
M(R10) →M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) →R11
R10 + 2 →R10
Indirect autoincrement
Immediate
MOV @Rn+,Rm
MOV #X,TONI
✓
✓
#45 →M(TONI)
(1) S = source
(2) D = destination
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9.5 Operating Modes
MSP430i204x, MSP430i203x, MSP430i202x devices have one active mode and four software-selectable low-
power modes. An interrupt event can wake up the device from the low-power modes LPM0 to LPM4, service the
request, and restore back to the low-power mode on return from the interrupt program.
The following five operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 or low-power mode 1 (LPM0 = LPM1)
– CPU is disabled
– Internal regulator remains enabled
– DCO remains enabled
– MCLK is disabled
– ACLK and SMCLK remain active
• Low-power mode 2 or low-power mode 3 (LPM2 = LPM3)
– CPU is disabled
– Internal regulator remains enabled
– DCO remains enabled
– MCLK and SMCLK are disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– Internal regulator remains enabled
– DCO is disabled
– MCLK, SMCLK, and ACLK are disabled
• Low-power mode 4.5 (LPM4.5)
– Internal regulator is disabled
– No RAM retention
– I/O pad state retention
– Wake from RST/NMI, ports pins P2.1 or P2.2
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9.6 Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFE0h. The vector
contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the
CPU goes into LPM4 immediately after power up.
表9-3. Interrupt Vector Addresses
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT WORD ADDRESS
PRIORITY
Power up
External reset
Watchdog
BORIFG
RSTIFG
WDTIFG
Reset
0FFFEh
15, highest
Flash key violation
KEYV
PC out-of-range (1)
(2)
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
(Non)maskable,
(Non)maskable,
(Non)maskable
0FFFCh
0FFFAh
0FFF8h
14
13
12
ACCVIFG (2) (4)
Timer TA1
TA1CCR0 CCIFG (3)
Maskable
TA1CCR1 CCIFG,
TA1CCR2 CCIFG,
TA1CTL TAIFG (2) (3)
Timer TA1
Maskable
Voltage monitor
Watchdog timer
VMONIFG
WDTIFG
Maskable
Maskable
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
11
10
9
eUSCI_A0 receive or transmit
eUSCI_B0 receive or transmit
UCA0RXIFG, UCA0TXIFG
UCB0RXIFG, UCB0TXIFG
8
SD24CCTLx SD24OVIFG,
SD24CCTLx SD24IFG(2) (3)
SD24
Maskable
Maskable
0FFEEh
0FFECh
7
6
Timer TA0
TA0CCR0 CCIFG (3)
TA0CCR1 CCIFG,
TA0CCR2 CCIFG,
TA0CTL TAIFG (2) (3)
Timer TA0
I/O port P1
Maskable
Maskable
0FFEAh
5
P1IFG.0 to P1IFG.7 (2) (3)
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
4
3
2
1
I/O port P2
P2IFG.0 to P2IFG.7 (2) (3)
Maskable
0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2) Multiple source flags
(3) Interrupt flags are in the module.
(4) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
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9.7 Special Function Registers
Some interrupt enable and interrupt flag bits are collected into the lowest address space. Special function
register bits not allocated to a functional purpose are not physically present in the device. Simple software
access is provided with this arrangement.
Legend
rw
Bit can be read and written.
rw-0, rw-1
rw-(0), rw-(1)
rw-[0], rw-[1]
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
Bit can be read and written. It is Reset or Set by BOR.
SFR bit is not present in device.
表9-4. Interrupt Enable 1 (Address = 00h)
7
6
5
4
3
2
1
0
ACCVIE
rw-0
NMIIE
rw-0
OFIE
rw-0
WDTIE
rw-0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer
mode.
OFIE
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
表9-5. Interrupt Flag Register 1 (Address = 02h)
7
6
5
4
3
2
1
0
NMIIFG
rw-0
RSTIFG
rw-[0]
BORIFG
rw-[1]
OFIFG
rw-0
WDTIFG
rw-(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault. This flag can be cleared by software when the oscillator runs free of fault.
Brown out reset flag. This bit is set after VCC power up and can be cleared by software.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Set by the RST/NMI pin in NMI configuration.
BORIFG
RSTIFG
NMIIFG
9.8 Flash Memory
The flash memory can be programmed through the Spy-Bi-Wire or JTAG port, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory:
• Flash memory has n segments of main memory and one segment of information memory.
• Segment size is 1KB for both main memory and information memory.
• Segments 0 to n in main memory can be erased in one step, or each segment may be individually erased.
• Information memory segment can be erased separately or as a group with main memory segments 0 to n.
• Information memory segment contains calibration data. After reset, information memory segment is protected
against programming and erasing. It can be unlocked but care should be taken not to erase this segment if
the device-specific calibration data is required.
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9.9 JTAG Operation
9.9.1 JTAG Standard Interface
The MSP430i family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430i
development tools and device programmers. 表 9-6 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.
表9-6. JTAG Pin Requirements and Functions
DEVICE SIGNAL
P1.0/UCA0STE/MCLK/TCK
P1.1/UCA0CLK/SMCLK/TMS
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
TEST/SBWTCK
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input/TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
IN
OUT
IN
RST/NMI/SBWTDIO
IN
VCC
Power supply
DVSS
Ground supply
9.9.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430i family supports the 2-wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430i development tools and device programmers. 表9-7 lists the Spy-
Bi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide.
表9-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
IN
IN, OUT
DVSS
Ground supply
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9.9.3 JTAG Disable Register
The SYSJTAGDIS register can disable the JTAG port to provide code protection and device security. JTAG is
disabled when software writes the value 0xA5A5 to this register within 64 MCLK clock cycles after a BOR or
POR reset; otherwise, the JTAG port is enabled. Any writes to this register after the first 64 MCLK clock cycles
are ignored. Reads from this register at any time return the JTAG enable or disable status. The value 0xA5A5
indicates that JTAG is disabled, and 0x9696 indicates that JTAG is enabled. The SYSJTAGDIS register is
mapped to address 01FEh.
Note
Application programming the device to any of the low power modes within first 64 MCLK clock cycles
after a BOR or POR reset will lock the device for any JTAG/SBW access.
表9-8. SYSJTAGDIS Register
15
14
13
12
11
10
9
8
JTAGKEY
rw-[1]
7
rw-[0]
6
rw-[1]
5
rw-[0]
4
rw-[0]
3
rw-[1]
2
rw-[0]
1
rw-[1]
0
JTAGKEY
rw-[1]
rw-[0]
rw-[1]
rw-[0]
rw-[0]
rw-[1]
rw-[0]
rw-[1]
JTAGKEY
0xA5A5 indicates JTAG is disabled and 0x9696 indicates JTAG is enabled.
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9.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430i2xx Family User's Guide.
9.10.1 Clock System
The clock system consists of a fixed 16.384-MHz frequency internal DCO. The DCO can operate in internal
resistor mode or external resistor mode. The DCO clock accuracy is higher when operating in external resistor
mode especially upon variation in operating temperature. This feature can be useful in applications like utility
metering in which accurate clock is necessary under varying operating temperature. When external resistor
mode is selected by application, the resistor of recommended value must be connected to ROSC pin of the
device. Refer to 节 8.7.2.1 for the recommended value of the resistor at the ROSC pin. TI recommends
connecting the ROSC pin to AVSS when operating the DCO in internal resistor mode. When a resistor fault is
detected in the external resistor mode, the DCO automatically switches to the internal resistor mode as a fail-
safe mechanism to keep the system clocks active.
The DCO can be completely bypassed and the system clocks can be sourced by an external digital clock. The
clock system generates MCLK, SMCLK, and ACLK. MCLK is used by the CPU, while SMCLK and ACLK are
used by the peripheral modules. There are programmable clock dividers for MCLK and SMCLK. ACLK runs at a
fixed 32-kHz frequency. The clock system supports active mode and four low-power modes.
9.10.2 Power-Management Module (PMM)
The PMM consists of voltage regulator that generates 1.8-V regulated core voltage. There is a brownout reset
(BOR) circuit on the high-voltage domain, and a supply voltage supervisor (SVS) module on the low-voltage
domain. The BOR and SVS provide the proper internal reset signal to the device during power on and power off.
A built-in voltage reference is used by submodules of the PMM and by the analog modules on the device. A
temperature sensor is also available in the built-in voltage reference.
The voltage monitor (VMON) on the high-voltage domain can monitor external voltage on the VMONIN pin
against the internal reference voltage or by comparing the on-chip VCC to one of three programmable threshold
voltages. During the LPM4.5 mode, the reference, voltage regulator, temperature sensor, and voltage monitor
are turned off, and only the high-side brownout circuit is active.
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9.10.3 Digital I/O
Two 8-bit I/O ports (P1 and P2) are implemented on the MSP430i204x, MSP430i203x, MSP430i202x devices.
On 32-pin RHB devices, ports P1 and P2 are complete, and 16 I/Os are available. On 28-pin PW devices, port
P2 is reduced to 4 bits, and 12 I/Os are available. On 28-pin PW devices, the unavailable pins (P2.4 to P2.7)
must be programmed to port function, output direction, and be driven with value 0.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all 8 bits of port P1 and P2
• LPM4.5 wake-up capability for Port pins P2.1 and P2.2
• Read and write access to port-control registers is supported by all instructions.
9.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
9.10.5 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see 表 9-9). TA0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
表9-9. TA0 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT OUTPUT PORT
INPUT PORT PIN
MODULE BLOCK
SIGNAL
PIN
P1.3
TA0CLK
ACLK (internal)
SMCLK (internal)
TA0CLK
TA0.0
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
TA0
TA1
NA
P1.3
P1.4
P2.5
P1.4
P2.5
TA0.0
CCR0
CCR1
TA0.0
TA0.1
DVSS
VCC
VCC
P1.5
P1.6
TA0.1
CCI1A
CCI1B
GND
P1.5
P2.6
ACLK (internal)
DVSS
VCC
VCC
TA0.2
CCI2A
P1.6
P2.7
TA0.2
TA1 CCR2 output
(internal)
CCI2B
CCR2
TA2
DVSS
VCC
GND
VCC
TA1 CCI2B input
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9.10.6 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple capture/compares, PWM outputs, and interval timing (see 表 9-10). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
表9-10. TA1 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT OUTPUT PORT
INPUT PORT PIN
MODULE BLOCK
SIGNAL
PIN
P1.7
TA1CLK
ACLK (internal)
SMCLK (internal)
TA1CLK
TA1.0
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
TA0
TA1
NA
P1.7
P2.0
P2.4
P2.0
P2.4
TA1.0
CCR0
CCR1
TA1.0
TA1.1
DVSS
VCC
VCC
P2.1
P2.2
TA1.1
CCI1A
CCI1B
GND
P2.1
P2.2
ACLK (internal)
DVSS
VCC
VCC
TA1.2
CCI2A
TA1.2
TA0 CCR2 output
(internal)
CCI2B
CCR2
TA2
DVSS
VCC
GND
VCC
TA0 CCI2B input
9.10.7 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such
as UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3-pin or 4-pin) and I2C.
One eUSCI_A and one eUSCI_B module are implemented on MSP430i20xx devices.
9.10.8 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16-bit,
16×8-bit, 8×16-bit, and 8×8-bit operations. The module supports signed and unsigned multiplication as well as
signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
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9.10.9 SD24
There are up to four independent 24-bit sigma-delta ADCs. Each converter is designed with a fully differential
analog input pair and programmable gain amplifier input stage. Also the converters are based on second-order
oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb-type filters
with selectable oversampling ratios of up to 256.
The SD24 converters can operate with internal reference (SD24REFS = 1) or with external reference
(SD24REFS = 0). When SD24 operates with internal reference the VREF pin must not be loaded externally.
Connect only the recommended capacitor value (CVREF) at VREF pin to AVSS (see 节8.7.7.2).
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9.11 Input/Output Diagrams
9.11.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
Py.x/Mod1/Mod2/JTAG Pin Diagram shows the pin diagram. 表 9-11 summarizes the selection of the pin
function.
JTAG enable
From JTAG
From JTAG
Pad Logic
Direction
0: Input
1: Output
0 0
0 1
1 0
1 1
PyDIR.x
1
0
From module 1
0 0
0 1
1 0
1 1
PyOUT.x
From module 1
From module 2
DVSS
1
0
Py.x/Mod1/Mod2/JTAG
PySEL1.x
PySEL0.x
PyIN.x
EN
D
To modules
and JTAG
Functional representation only.
图9-8. Py.x/Mod1/Mod2/JTAG Pin Diagram
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表9-11. Port P1 (P1.0 to P1.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x JTAG Enable
P1.0/UCA0STE/MCLK/TCK
0
P1.0 (I/O)(2)
UCA0STE
N/A
I: 0; O: 1
0
0
0
1
0
0
X(3)
0
1
1
0
1
0
0
MCLK
1
N/A
0
DVSS
1
TCK(4)
X
X
0
0
X
0
1
1
0
0
P1.1/UCA0CLK/SMCLK/TMS
1
2
3
P1.1 (I/O)(2)
UCA0CLK
N/A
I: 0; O: 1
X(3)
0
1
1
0
1
0
0
SMCLK
N/A
1
0
DVSS
1
TMS(4)
P1.2 (I/O)(2)
X
X
0
0
X
0
1
1
0
0
P1.2/UCA0RXD/UCA0SOMI/
ACLK/TDI/TCLK
I: 0; O: 1
UCA0RXD/UCA0SOMI
X(3)
N/A
0
1
1
0
1
0
0
ACLK
1
N/A
0
DVSS
1
TDI/TCLK(4)
P1.3 (I/O)(2)
UCA0TXD/UCA0SIMO
TA0CLK
DVSS
X
X
0
0
X
0
1
1
0
0
P1.3/UCA0TXD/UCA0SIMO/
TA0CLK/TDO/TDI
I: 0; O: 1
X(3)
0
1
0
0
1
N/A
0
1
1
0
1
DVSS
1
TDO/TDI(4)
X
X
X
(1) X = Don't care
(2) Default condition
(3) Direction is controlled by eUSCI_A0 module.
(4) The pin direction is controlled by the JTAG module. The JTAG mode selection is made through the Spy-Bi-Wire 4-wire entry sequence.
Neither P1SEL0.x and P1SEL1.x nor P1DIR.x have an effect in these cases.
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9.11.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
Py.x/Mod1/Mod2 Pin Schematic shows the pin diagram. 表9-12 summarizes the selection of the pin function.
Pad Logic
Direction
0: Input
1: Output
0 0
0 1
1 0
1 1
PyDIR.x
From module 1
0 0
0 1
1 0
1 1
PyOUT.x
From module 1
From module 2
DVSS
Py.x/Mod1/Mod2
PySEL1.x
PySEL0.x
PyIN.x
EN
D
To module
Functional representation only.
图9-9. Py.x/Mod1/Mod2 Pin Schematic
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表9-12. Port P1 (P1.4 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.4/UCB0STE/TA0.0
4
P1.4 (I/O)
UCB0STE
TA0.CCI0A
TA0.0
I: 0; O: 1
0
0
0
1
X(2)
0
1
1
0
1
1
N/A
0
DVSS
1
P1.5/UCB0CLK/TA0.1
5
6
7
P1.5 (I/O)
UCB0CLK
TA0.CCI1A
TA0.1
I: 0; O: 1
0
0
0
1
X(2)
0
1
1
0
1
1
N/A
0
DVSS
1
P1.6/UCB0SCL/UCB0SOMI/
TA0.2
P1.6 (I/O)
I: 0; O: 1
0
0
0
1
UCB0SCL/UCB0SOMI
X(2)
TA0.CCI2A
TA0.2
0
1
1
0
1
1
N/A
0
DVSS
1
P1.7/UCB0SDA/UCB0SIMO/
TA1CLK
P1.7 (I/O)
UCB0SDA/UCB0SIMO
TA1CLK
DVSS
I: 0; O: 1
0
0
0
1
X(2)
0
1
1
0
1
1
N/A
0
DVSS
1
(1) X = Don't care
(2) Direction is controlled by eUSCI_B0 module.
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9.11.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
Py.x/Mod1/Mod2 Pin Schematic shows the pin diagram. 表9-13 summarizes the selection of the pin function.
Pad Logic
Direction
0: Input
1: Output
0 0
0 1
1 0
1 1
PyDIR.x
0 0
0 1
1 0
1 1
PyOUT.x
From module
DVSS
Py.x/Mod1/Mod2
DVSS
PySEL1.x
PySEL0.x
PyIN.x
EN
D
To module
Functional representation only.
图9-10. Py.x/Mod1/Mod2 Pin Schematic
表9-13. Port P2 (P2.0 to P2.2 and P2.4 to P2.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P2.x)
P2.0/TA1.0/CLKIN
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
0
P2.0 (I/O)
TA1.CCI0A
TA1.0
I: 0; O: 1
0
0
0
0
1
1
1
CLKIN (DCO bypass clock)
0
0
DVSS
N/A
1
0
1
0
0
1
0
1
DVSS
P2.1 (I/O)
TA1.CCI1A
TA1.1
N/A
1
P2.1/TA1.1
1
I: 0; O: 1
0
1
0
1
0
1
1
1
0
1
DVSS
N/A
DVSS
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表9-13. Port P2 (P2.0 to P2.2 and P2.4 to P2.7) Pin Functions (continued)
CONTROL BITS OR SIGNALS
PIN NAME (P2.x)
P2.2/TA1.2
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
2
P2.2 (I/O)
TA1.CCI2A
TA1.2
N/A
I: 0; O: 1
0
0
0
0
1
1
0
1
0
DVSS
N/A
1
0
1
0
0
1
0
1
DVSS
P2.4 (I/O)
TA1.CCI0B
TA1.0
N/A
1
P2.4/TA1.0(1)
P2.5/TA0.0(1)
P2.6/TA0.1(1)
P2.7/TA0.2(1)
4
5
6
7
I: 0; O: 1
0
1
0
1
0
DVSS
N/A
1
0
1
0
0
1
0
1
DVSS
P2.5 (I/O)
TA0.CCI0B
TA0.0
N/A
1
I: 0; O: 1
0
1
0
1
0
DVSS
N/A
1
0
1
0
0
1
0
1
DVSS
P2.6 (I/O)
N/A
1
I: 0; O: 1
0
TA0.1
N/A
1
0
1
0
DVSS
N/A
1
0
1
0
0
1
0
1
DVSS
P2.7 (I/O)
N/A
1
I: 0; O: 1
0
1
0
1
0
1
TA0.2
N/A
1
1
0
1
DVSS
N/A
DVSS
(1) Available only on 32-pin RHB devices.
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9.11.4 Port P2, P2.3, Input/Output With Schmitt Trigger
Py.x/VMONIN Pin Schematic shows the pin diagram. 表9-14 summarizes the selection of the pin function.
Pad Logic
To VMON
From VMON
Direction
0: Input
1: Output
0 0
0 1
1 0
1 1
PyDIR.x
0 0
0 1
1 0
1 1
PyOUT.x
DVSS
DVSS
Py.x/VMONIN
DVSS
PySEL1.x
PySEL0.x
PyIN.x
Bus
Keeper
EN
D
No connect
Functional representation only.
图9-11. Py.x/VMONIN Pin Schematic
表9-14. Port P2 (P2.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
P2.3/VMONIN
x
FUNCTION
P2DIR.x
I: 0; O: 1
P2SEL1.x
P2SEL0.x
3
P2.3 (I/O)
N/A
0
0
0
1
0
1
X
0
1
DVSS
N/A
1
1
0
1
DVSS
VMONIN(2)
(1) X = Don't care
(2) Setting P2SEL1.3 and P2SEL0.3 disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying voltage at VMONIN pin. To enable the VMONIN function, VMONLVLx bits must be set to 3'b111 in the VMONCTL register.
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9.12 Device Descriptor
表 9-15 lists the contents of the tag-length-value (TLV) device descriptor structure for the MSP430i204x,
MSP430i203x, and MSP430i202x devices.
表9-15. MSP430i204x, MSP430i203x, MSP430i202x TLV
SIZE
(BYTES)
DESCRIPTION
ADDRESS
VALUE
Checksum
Die Record
TLV checksum
013C0h
013C2h
013C3h
013C4h
013C8h
013CAh
013CCh
013CEh
013CFh
013D0h
013D1h
013D2h
013D3h
013D4h
013D5h
013D6h
013D7h
013D8h
013D9h
013DAh
013DBh
013DCh
013DDh
013DEh
2
1
1
4
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
34
Per unit
01h
Die Record Tag
Die Record Length
0Ah
Lot/Wafer ID
Per unit
Per unit
Per unit
Per unit
02h
Die X position
Die Y position
Test results
REF Calibration Tag
REF Calibration Length
Calibrate REF –for REFCAL1 register
Calibrate REF –for REFCAL0 register
DCO Calibration Tag
02h
REF Calibration
DCO Calibration
Per unit
Per unit
03h
DCO Calibration Length
Calibrate DCO –for CSIRFCAL register
Calibrate DCO –for CSIRTCAL register
Calibrate DCO –for CSERFCAL register
Calibrate DCO –for CSERTCAL register
SD24 Calibration Tag
SD24 Calibration Length
Calibrate SD24 –for SD24TRIM register
Empty
04h
Per unit
Per unit
Per unit
Per unit
04h
02h
SD24 Calibration
Empty
Per unit
FFh
Tag Empty
FEh
Empty Length
22h
Empty
FFh
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9.13 Memory
表9-16 lists the memory organization for the specified devices.
表9-16. Memory Organization
MSP430i2040
MSP430i2030
MSP430i2020
MSP430i2041
MSP430i2031
MSP430i2021
Memory
Size
Flash
16KB
32KB
Main: interrupt vector
Main: code memory
0xFFFF to 0xFFE0
0xFFFF to 0xC000
1KB
0xFFFF to 0xFFE0
0xFFFF to 0x8000
1KB
Flash
Size
Information memory
RAM
Flash
0x13FFh to 0x1000
1KB
0x13FFh to 0x1000
2KB
Size
Address
16-bit
0x05FF to 0x0200
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x09FF to 0x0200
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
Peripherals
8-bit
8-bit SFR
9.13.1 Peripheral File Map
表9-17 lists the peripherals that support word access, and 表9-18 lists the peripherals that support byte access.
Peripherals that support both access types are listed in both tables.
表9-17. Peripherals With Word Access
MODULE
REGISTER DESCRIPTION
ACRONYM
SYSJTAGDIS
TA1CCR2
TA1CCR1
TA1CCR0
TA1R
ADDRESS
0x01FE
0x0196
0x0194
0x0192
0x0190
0x0186
0x0184
0x0182
0x0180
0x011E
0x0176
0x0174
0x0172
0x0170
0x0166
0x0164
0x0162
0x0160
0x012E
SYS
JTAG disable register
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
Timer TA1
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TA1CCTL2
TA1CCTL1
TA1CCTL0
TA1CTL
Timer_A interrupt vector
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
TA1IV
TA0CCR2
TA0CCR1
TA0CCR0
TA0R
Timer TA0
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
TA0CCTL2
TA0CCTL1
TA0CCTL0
TA0CTL
Timer_A interrupt vector
TA0IV
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表9-17. Peripherals With Word Access (continued)
MODULE
REGISTER DESCRIPTION
ACRONYM
UCA0CTLW0
UCA0CTLW1
UCA0BR0
UCA0BR1
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
ADDRESS
0x0140
0x0142
0x0146
0x0147
0x0148
0x014A
0x014C
0x014E
0x0150
0x0152
0x0153
0x015A
0x015C
0x015E
0x01C0
0x01C2
0x01C6
0x01C7
0x01C8
0x01CA
0x01CC
0x01CE
0x01D4
0x01D6
0x01D8
0x01DA
0x01DC
0x01DE
0x01E0
0x01EA
0x01EC
0x01EE
0x013E
0x013C
0x013A
0x0138
0x0136
0x0134
0x0132
0x0130
0x012C
0x012A
0x0128
0x0120
USCI_A control word 0
USCI _A control word 1
USCI_A baud rate 0
USCI_A baud rate 1
USCI_A modulation control
USCI_A status
USCI_A receive buffer
USCI_A transmit buffer
USCI_A LIN control
eUSCI_A0
USCI_A IrDA transmit control
USCI_A IrDA receive control
USCI_A interrupt enable
USCI_A interrupt flags
USCI_A interrupt vector word
USCI_B control word 0
USCI_B control word 1
USCI_B bit rate 0
UCA0IFG
UCA0IV
UCB0CTLW0
UCB0CTLW1
UCB0BR0
UCB0BR1
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
USCI_B bit rate 1
USCI_B status word
USCI_B byte counter threshold
USCI_B receive buffer
USCI_B transmit buffer
USCI_B I2C own address 0
USCI_B I2C own address 1
USCI_B I2C own address 2
USCI_B I2C own address 3
USCI_B received address
USCI_B address mask
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
eUSCI_B0
UCB0IFG
USCI interrupt vector word
Sum extend
UCB0IV
SUMEXT
Result high word
RESHI
Result low word
RESLO
Second operand
OP2
Hardware Multiplier
Multiply signed + accumulate/operand 1
Multiply + accumulate/operand 1
Multiply signed/operand 1
Multiply unsigned/operand 1
Flash control 3
MACS
MAC
MPYS
MPY
FCTL3
Flash Memory
Flash control 2
FCTL2
Flash control 1
FCTL1
Watchdog Timer
Watchdog/timer control
WDTCTL
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表9-17. Peripherals With Word Access (continued)
MODULE
REGISTER DESCRIPTION
ACRONYM
ADDRESS
0x01F0
0x0116
0x0114
0x0112
0x0110
0x0108
0x0106
0x0104
0x0102
0x0100
SD24 interrupt vector word register
SD24IV
Channel 3 conversion memory(1) (2)
Channel 2 conversion memory(2)
Channel 1 conversion memory
Channel 0 conversion memory
Channel 3 control(1) (2)
SD24MEM3
SD24MEM2
SD24MEM1
SD24MEM0
SD24CCTL3
SD24CCTL2
SD24CCTL1
SD24CCTL0
SD24CTL
SD24
(also see 表9-18)
Channel 2 control(2)
Channel 1 control
Channel 0 control
General Control
(1) Not available on MSP430i2031 and MSP430i2030 devices.
(2) Not available on MSP430i2021 and MSP430i2020 devices.
表9-18. Peripherals With Byte Access
MODULE
REGISTER DESCRIPTION
REGISTER NAME
SD24TRIM
SD24PRE3
SD24PRE2
SD24PRE1
SD24PRE0
SD24INCTL3
SD24INCTL2
SD24INCTL1
SD24INCTL0
REFCAL1
REFCAL0
VMONCTL
LPM45CTL
CSERTCAL
CSERFCAL
CSIRTCAL
CSIRFCAL
CSCTL1
ADDRESS
0x00BF
0x00BB
0x00BA
0x00B9
0x00B8
0x00B3
0x00B2
0x00B1
0x00B0
0x0063
0x0062
0x0061
0x0060
0x0055
0x0054
0x0053
0x0052
0x0051
0x0050
0x002D
0x002B
0x0029
0x002E
0x001D
0x001B
0x0015
0x0013
0x0011
SD24 trim
Channel 3 preload(1) (2)
Channel 2 preload(2)
Channel 1 preload
SD24
Channel 0 preload
(also see 表9-17)
Channel 3 input control(1) (2)
Channel 2 input control(2)
Channel 1 input control
Channel 0 input control
Reference calibration 1
Reference calibration 0
PMM
Voltage monitor control
LPM4.5 control
Clock system external resistor temperature calibration
Clock system external resistor frequency calibration
Clock system internal resistor temperature calibration
Clock system internal resistor frequency calibration
Clock system control 1
Clock System
Clock system control 0
CSCTL0
Port P2 interrupt flag
P2IFG
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt vector word
Port P2 selection 1
P2IE
P2IES
P2IV
Port P2
P2SEL1
Port P2 selection 0
P2SEL0
Port P2 direction
P2DIR
Port P2 output
P2OUT
Port P2 input
P2IN
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表9-18. Peripherals With Byte Access (continued)
MODULE
REGISTER DESCRIPTION
REGISTER NAME
P1IFG
P1IE
ADDRESS
0x002C
0x002A
0x0028
0x001E
0x001C
0x001A
0x0014
0x0012
0x0010
0x0002
0x0000
Port P1 interrupt flag
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt vector word
Port P1 selection 1
Port P1 selection 0
Port P1 direction
P1IES
P1IV
Port P1
P1SEL1
P1SEL0
P1DIR
P1OUT
P1IN
Port P1 output
Port P1 input
SFR interrupt flag 1
SFR interrupt enable 1
IFG1
Special Function
IE1
(1) Not available on MSP430i2031 or MSP430i2030 devices.
(2) Not available on MSP430i2021 or MSP430i2020 devices.
9.14 Identification
9.14.1 Device Identification
The device type can be identified from the top-side marking on the device package. See the packaging
information page or the device errata sheets listed in 节11.4 for help.
9.14.2 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in
the MSP430 Programming With the JTAG Interface.
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10 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
The following resources provide application guidelines and best practices when designing with the MSP430i20xx
devices.
Implementation of a One- or Two-Phase Electronic Watt-Hour Meter Using MSP430i20xx application
report
This application report describes the implementation of a low-cost 1- or 2-phase electronic electricity meter that
uses the TI MSP430i20xx metering processor. This application report includes information on metrology software
and hardware procedures for this single-chip implementation.
Single-Phase and DC Embedded Metering Power Using MSP430i2040 application report
This application report describes an EVM that uses the MSP430i2040 microcontroller for embedded metering
(submetering). In this application, the electricity measuring device is embedded in the end application and gives
the user information about the voltage, current, and power consumption of the device. In addition, the EVM can
compensate for line resistance and EMI filter capacitance.
Single Phase and DC Embedded Metering (Server Power Monitor) reference design
This reference design implements a high-accuracy single-phase embedded meter using an MSP430 MCU. This
EVM has built-in support to measure AC voltage, current, active power, reactive power, apparent power,
frequency, power factor, voltage THD, current THD, fundamental voltage, fundamental current, fundamental
power and DC voltage, DC current, DC active power. It can detect the input voltage to work in DC or AC mode. It
can also compensate for the effects of the wire resistance and the EMI filter capacitance so that the reading of
voltage and power matches the reading of an external meter when EMI filter is connected to the input.
Three Output Smart Power Strip reference design
This reference design implements a high-accuracy single-phase embedded metering smart power strip using an
MSP430 MCU. This design supports measurement of AC voltage, current, active power, reactive power,
apparent power, frequency, and power factor with 3 sockets measured individually. Additional hardware is added
to provide futher development like relay control and wired or wireless communication.
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11 Device and Documentation Support
11.1 Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to help with
your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.
11.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS –Experimental device that is not necessarily representative of the final device's electrical specifications
MSP –Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. 图11-1 provides a legend for reading the complete device name.
T
MSP 430
i
2
041
PW
R
Processor Family
MCU Platform
Tape and Reel
Packaging
Device Type
Series
Temperature Range
Feature Set
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
MCU Platform
Device Type
430 = TI’s MSP430 Microcontroller Platform
Specialized Application
i = Flash Industrial
Series
2 = Flash 2 series up to 16.384 MHz
Feature Set
Various levels of integration within a series
Temperature Range
Packaging
T = –40°C to 105°C
http://www.ti.com/packaging
Tape and Reel
T = Small Reel
R = Large Reel
No markings = Tube or tray
图11-1. Device Nomenclature
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11.3 Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are
available from TI and various third parties. See them all at MSP430 ultra-low-power MCUs – Design &
development.
Design Kits and Evaluation Modules
32-pin target development board and MSP-FET programmer bundle for MSP430i2x MCUs
The MSP-FET430U32A is a stand-alone ZIF socket target board used to program and debug the MSP430 MCU
in-system through the JTAG interface or the Spy-Bi-Wire (2-wire JTAG) protocol.
MSP430 LaunchPad™ Value Line Development Kit
The MSP-EXP430G2 LaunchPad development kit is an easy-to-use microcontroller development board for the
low-power and low-cost MSP430G2x MCUs. It has on-board emulation for programming and debugging and
features a 14/20-pin DIP socket, on-board buttons and LEDs and BoosterPack plug-in module pinouts that
support a wide range of modules for added functionality such as wireless, displays, and more.
MSP430i2040 Submetering EVM
This embedded metering (sub-meter or e-meter) EVM is designed based on the MSP430i2040. The EVM can be
connected to the mains (or to DC) and the load directly. The EVM measures the electrical parameters of the load
and the result of measurement can be read from the UART port. This EVM provided with built-in power supply
and isolated serial connect to facilitate user quick start to the evaluation of the MSP430i2040 in embedded
metering application.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver
Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430i20xx Code Examples
C code examples are available for every MSP device that configures each of the integrated peripherals for
various application needs.
Floating Point Math Library for MSP430
Leveraging the intelligent peripherals of TI devices, this floating point math library of scalar functions brings you
up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated
in both Code Composer Studio and IAR IDEs.
Fixed Point Math Library for MSP
The TI MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
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Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller
devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded
applications. CCS includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features.
MSP Flasher - Command Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) directly to the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users
quickly begin application development on MSP low-power MCUs. Creating MCU software usually requires
downloading the resulting binary program to the MSP device for validation and debugging.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects to
a host PC using a standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
11.4 Documentation Support
The following documents describe the MSP430i20xx MCUs. Copies of these documents are available on the
Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for example, MSP430i2041). In the upper right corner, click the "Alert me" button. This
registers you to receive a weekly digest of product information that has changed (if any). For change details,
check the revision history of any revised document.
Errata
MSP430i2041 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2040 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2031 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2031 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2021 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2021 Device Erratasheet
Describes the known exceptions to the functional specifications.
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User's Guides
MSP430i2xx Family User's Guide
Detailed description of all modules and peripherals available in this device family.
MSP430™ Flash Device Bootloader (BSL) User's Guide
The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller
during the prototyping phase, final production, and in service. Both the programmable memory (flash memory)
and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap
loader programs found in some digital signal processors (DSPs) that automatically load program code (and data)
from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the
parallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
different ESD topics to help board designers and OEMs understand and design robust system-level designs.
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.6 Trademarks
™, MSP430™, LaunchPad™, MSP430Ware™, Code Composer Studio™, and TI E2E™ are trademarks of Texas
Instruments.
所有商标均为其各自所有者的财产。
11.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
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11.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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MSP430I2021, MSP430I2020
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430I2020TPW
MSP430I2020TPWR
MSP430I2020TRHBR
MSP430I2020TRHBT
MSP430I2021TPW
MSP430I2021TPWR
MSP430I2021TRHBR
MSP430I2021TRHBT
MSP430I2030TPW
MSP430I2030TPWR
MSP430I2030TRHBR
MSP430I2030TRHBT
MSP430I2031TPW
MSP430I2031TPWR
MSP430I2031TRHBR
MSP430I2031TRHBT
MSP430I2040TPW
MSP430I2040TPWR
MSP430I2040TRHBR
MSP430I2040TRHBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
VQFN
PW
PW
28
28
32
32
28
28
32
32
28
28
32
32
28
28
32
32
28
28
32
32
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
I2020T
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
I2020T
I2020T
I2020T
I2021T
I2021T
I2021T
I2021T
I2030T
I2030T
I2030T
I2030T
I2031T
I2031T
I2031T
I2031T
I2040T
I2040T
I2040T
I2040T
RHB
RHB
PW
VQFN
250
50
RoHS & Green
RoHS & Green
TSSOP
TSSOP
VQFN
PW
2000 RoHS & Green
3000 RoHS & Green
RHB
RHB
PW
VQFN
250
50
RoHS & Green
RoHS & Green
TSSOP
TSSOP
VQFN
PW
2000 RoHS & Green
3000 RoHS & Green
RHB
RHB
PW
VQFN
250
50
RoHS & Green
RoHS & Green
TSSOP
TSSOP
VQFN
PW
2000 RoHS & Green
3000 RoHS & Green
RHB
RHB
PW
VQFN
250
50
RoHS & Green
RoHS & Green
TSSOP
TSSOP
VQFN
PW
2000 RoHS & Green
3000 RoHS & Green
RHB
RHB
VQFN
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430I2041TPW
MSP430I2041TPWR
MSP430I2041TRHBR
MSP430I2041TRHBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
VQFN
PW
PW
28
28
32
32
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
I2041T
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
I2041T
I2041T
I2041T
RHB
RHB
VQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430I2020TPWR
MSP430I2020TRHBR
MSP430I2020TRHBT
MSP430I2021TPWR
MSP430I2021TRHBR
MSP430I2021TRHBT
MSP430I2030TPWR
MSP430I2030TRHBR
MSP430I2030TRHBT
MSP430I2031TPWR
MSP430I2031TRHBR
MSP430I2031TRHBT
MSP430I2040TPWR
MSP430I2040TRHBR
MSP430I2040TRHBT
MSP430I2041TPWR
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
PW
RHB
RHB
PW
28
32
32
28
32
32
28
32
32
28
32
32
28
32
32
28
2000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
6.9
5.3
5.3
6.9
5.3
5.3
6.9
5.3
5.3
6.9
5.3
5.3
6.9
5.3
5.3
6.9
10.2
5.3
1.8
1.1
1.1
1.8
1.1
1.1
1.8
1.1
1.1
1.8
1.1
1.1
1.8
1.1
1.1
1.8
12.0
8.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
5.3
8.0
2000
3000
250
10.2
5.3
12.0
8.0
RHB
RHB
PW
5.3
8.0
2000
3000
250
10.2
5.3
12.0
8.0
RHB
RHB
PW
5.3
8.0
2000
3000
250
10.2
5.3
12.0
8.0
RHB
RHB
PW
5.3
8.0
2000
3000
250
10.2
5.3
12.0
8.0
RHB
RHB
PW
5.3
8.0
2000
10.2
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430I2041TRHBR
MSP430I2041TRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430I2020TPWR
MSP430I2020TRHBR
MSP430I2020TRHBT
MSP430I2021TPWR
MSP430I2021TRHBR
MSP430I2021TRHBT
MSP430I2030TPWR
MSP430I2030TRHBR
MSP430I2030TRHBT
MSP430I2031TPWR
MSP430I2031TRHBR
MSP430I2031TRHBT
MSP430I2040TPWR
MSP430I2040TRHBR
MSP430I2040TRHBT
MSP430I2041TPWR
MSP430I2041TRHBR
MSP430I2041TRHBT
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
PW
RHB
RHB
PW
28
32
32
28
32
32
28
32
32
28
32
32
28
32
32
28
32
32
2000
3000
250
350.0
367.0
210.0
367.0
367.0
210.0
350.0
367.0
210.0
350.0
367.0
210.0
350.0
367.0
210.0
350.0
367.0
210.0
350.0
367.0
185.0
367.0
367.0
185.0
350.0
367.0
185.0
350.0
367.0
185.0
350.0
367.0
185.0
350.0
367.0
185.0
43.0
35.0
35.0
38.0
35.0
35.0
43.0
35.0
35.0
43.0
35.0
35.0
43.0
35.0
35.0
43.0
35.0
35.0
2000
3000
250
RHB
RHB
PW
2000
3000
250
RHB
RHB
PW
2000
3000
250
RHB
RHB
PW
2000
3000
250
RHB
RHB
PW
2000
3000
250
RHB
RHB
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MSP430I2020TPW
MSP430I2021TPW
MSP430I2030TPW
MSP430I2031TPW
MSP430I2040TPW
MSP430I2041TPW
PW
PW
PW
PW
PW
PW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
28
28
28
28
28
28
50
50
50
50
50
50
530
530
530
530
530
530
10.2
10.2
10.2
10.2
10.2
10.2
3600
3600
3600
3600
3600
3600
3.5
3.5
3.5
3.5
3.5
3.5
Pack Materials-Page 4
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RHB0032M
PLASTIC QUAD FLATPACK-NO LEAD
A
5.1
4.9
B
5.1
4.9
PIN 1 INDEX AREA
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
ꢀꢀꢀꢁꢂꢃꢄꢂꢃ
9
16
28X 0.5
8
17
SYMM
33
2X
3.5
1
24
0.3
0.2
32X
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.1
0.05
C A B
C
0.5
0.3
32X
4223725/A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RHB0032M
PLASTIC QUAD FLATPACK-NO LEAD
(4.8)
2.1)
(
32
25
32X (0.6)
32X (0.25)
1
24
28X (0.5)
33
SYMM
(4.8)
2X
(0.8)
ꢅꢄꢂꢁꢆ
VIA TYP
8
17
(R0.05) TYP
9
16
2X (0.8)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
EXPOSED
METAL
OPENING
EXPOSED
METAL UNDER
SOLDER MASK
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223725/A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RHB0032M
PLASTIC QUAD FLATPACK-NO LEAD
(4.8)
4X ( 0.94)
32
25
32X (0.6)
32X (0.25)
1
24
28X (0.5)
33
SYMM
(4.8)
2X
(0.57)
METAL
TYP
8
17
(R0.05) TYP
9
16
2X (0.57)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 15X
4223725/A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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