MSP430P337IPJM_技术文档

MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

PJM or HFD PACKAGE

(TOP VIEW)

Low Supply Voltage Range 2.5 V – 5.5 V

Low Operation Current, 400 A at 1 MHz,

3 V

Ultra-Low Power Consumption (Standby

Mode Down to 0.1 µA)

Five Power-Saving Modes

V

1

2

3

4

5

6

7

8

NC

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

CC1

CIN

Wake Up from Standby Mode in 6 µS

S22/O22

S21/O21

S20/O20

S19/O19

S18/O18

S17/O17

S16/O16

S15/O15

S14/O14

S13/O13

S12/O12

S11/O11

S10/O10

S9/O9

TP0.0

TP0.1

TP0.2

TP0.3

TP0.4

TP0.5

P0.0

16-Bit RISC Architecture, 300 ns Instruction

Cycle Time

Single Common 32 kHz Crystal, Internal

System Clock up to 3.8 MHz

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P0.1/RXD

P0.2/TXD

P0.3

Integrated LCD Driver for up to 120

Segments

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

Integrated Hardware Multiplier Performs

Signed, Unsigned, and MAC Operations for

Operands Up to 16 X 16 Bits

S8/O8

S7/07

S6/O6

Serial Communication Interface (USART),

Select Asynchronous UART or

Synchronous SPI by Software

S5/O5

S4/O4

S3/O3

S2/O2

S1

S0

COM0

COM1

Slope A/D Converter Using External

Components

16-Bit Timer With Five Capture/Compare

Registers

COM2

COM3

V

SS2

V

CC2

SS3

P4.7/URXD

NC

Programmable Code Protection by Security

Fuse

Family Members Include:

MSP430C336 – 24 KB ROM, 1 KB RAM

MSP430C337 – 32 KB ROM, 1 KB RAM

MSP430P337 – 32 KB OTP, 1 KB RAM

NC – No internal connection

EPROM Version Available for Prototyping:

PMS430E337

Serial On-Board Programming

Available in 100 Pin Quad Flat-Pack (QFP)

Package, 100 Pin Ceramic Quad Flat-Pack

(CFP) package (EPROM Version)

description

The Texas Instruments MSP430 series is a ultra low-power microcontroller family consisting of several devices

whichfeaturesdifferentsetsofmodulestargetedtovariousapplications. Thecontrollerisdesignedtobebattery

operated for an extended application lifetime. With the 16-bit RISC architecture, 16 integrated registers on the

CPU, and the constant generator, the MSP430 achieves maximum code efficiency. The digital-controlled

oscillator, together with the frequency lock loop (FLL), provides a fast wake up from a low-power mode to an

active mode in less than 6 s. The MSP430x33x series micro-controllers have built in hardware multiplication

and communication capability using asynchronous (UART) and synchronous protocols.

Typical applications of the MSP430 family include electronic gas, water, and electric meters and other sensor

systems that capture analog signals, converts them to digital values, processes, displays, or transmits them to

a host system.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

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MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

2

CIN

I

Input port. CIN is used as an enable for counter TPCNT1 – timer/port

Common outputs. COMM0-3 are used for LCD backplanes – LCD

General purpose digital I/O

COM0–3

P0.0

56–53

9

O

I/O

P0.1/RXD

P0.2/TXD

P0.3–P0.7

P1.0–P1.7

P2.0–P2.7

10

General purpose digital I/O, receive digital Input port – 8-bit timer/counter

General purpose digital I/O, transmit data output port – 8-bit timer/counter

Five general purpose digital I/Os, bit 3-7

11

12–16

17–24

Eight general purpose digital I/Os, bit 0-7

25–27,

31–35

Eight general purpose digital I/Os, bit 0-7

P3.0, P3.1

P3.2/TACLK

P3.3/TA0

P3.4/TA1

P3.5/TA2

P3.6/TA3

P3.7/TA4

P4.0

36,37

38

I/O

Two general purpose digital I/Os, bit 0 and bit 1

General purpose digital I/O, clock input – timer A

39

General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR0

General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR1

General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR2

General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR3

General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR4

General purpose digital I/O, bit 0

40

41

42

43

44

P4.1

45

General purpose digital I/O, bit 1

P4.2/STE

46

47

48

49

I/O

General purpose digital I/O, slave transmit enable – USART/SPI mode

General purpose digital I/O, slave in/master out – USART/SPI mode

General purpose digital I/O, master in/slave out – USART/SPI mode

General purpose digital I/O, external clock input – USART

P4.3/SIMO

P4.4/SOMI

P4.5/UCLK

P4.6/UTXD

P4.7/URXD

R03

50

51

I/O

I

General purpose digital I/O, transmit data out – USART/UART mode

General purpose digital I/O, receive data in – USART/UART mode

Input port of fourth positive (lowest) analog LCD level (V5) – LCD

Input port of third most positive analog LCD level (V3 of V4) – LCD

Input port of second most positive analog LCD level (V2) – LCD

Output of most positive analog LCD level (V1) – LCD

88

R13

89

I

R23

90

I

R33

91

O

I

RST/NMI

S0

96

Reset input or non-maskable interrupt input port

57

O

Segment line S0 – LCD

S1

58

Segment line S1 – LCD

S2/O2–S5/O5

S6/O6–S9/O9

59–62

63–66

67–70

71–74

75–78

79, 81–83

84–87

Segment lines S2 to S5 or digital output ports, O2-O5, group 1 – LCD

Segment lines S6 to S9 or digital output ports O6-O9, group 2 – LCD

Segment lines S10 to S13 or digital output ports O10-O13, group 3 – LCD

Segment lines S14 to S17 or digital output ports O14-O17, group 4 – LCD

Segment lines S18 to S21 or digital output ports O18-O21, group 5 – LCD

Segment line S22 to S25 or digital output ports O22-O25, group 6 – LCD

S10/O10–S13/O13

S14/O14–S17/O17

S18/O18–S21/O21

S22/O22–S25/O25

S26/O26–S29/O29/CMPI

Segment line S26 to S29 or digital output ports O26-O29, group 7 – LCD. Segment line S29

can be used as comparator input port CMPI – timer/port

TCK

95

93

I

Test clock. TCK is the clock input port for device programming and test

TDI/VPP

Test data input. TDI/VPP is used as a data input port or input for programming voltage

3

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MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

94

TMS

I

Test mode select. TMS is used as an input port for device programming and test

Test data output port. TDO/TDI data output or programming data input terminal

General purpose 3–state digital output port, bit 0 – timer/port

General purpose 3–state digital output port, bit 1 – timer/port

General purpose 3–state digital output port, bit 2 – timer/port

General purpose 3–state digital output port, bit 3 – timer/port

General purpose 3–state digital output port, bit 4 – timer/port

General purpose 3–state digital input/output port, bit 5 – timer/port

Positive supply voltage

TDO/TDI

TP0.0

TP0.1

TP0.2

TP0.3

TP0.4

TP0.5

VCC1

VCC2

VSS1

VSS2

VSS3

XBUF

Xin

92

I/O

O

3

4

O

5

O

6

O

7

O

8

I/O

1

29

100

28

52

97

99

98

Positive supply voltage

Ground reference

O

I

System clock (MCLK) or crystal clock (ACLK) output

Input port for crystal oscillator

Xout/TCLK

I/O

Output terminal of crystal oscillator or test clock input

short-form description

processing unit

The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design

structure results in a RISC-like architecture, highly transparent to the application development and is

distinguished due to ease of programming. All operations, other than program-flow instructions consequently

are performed as register operations in conjunction with seven addressing modes for source and four modes

for destination operand.

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

Program Counter

cpu registers

Sixteen registers are located inside the CPU,

Stack Pointer

providing reduced instruction execution time. This

reduces a register-register operation execution

time to one cycle of the processor frequency.

Status Register

Four of the registers are reserved for special use

as a program counter, a stack pointer, a status

register and a constant generator. The remaining

registers are available as general purpose

registers.

Constant Generator

General Purpose Register

R5

Peripherals are connected to the CPU using a

data address and control bus and can be handled

easily with all instructions for memory manipula-

tion.

General Purpose Register

R14

R15

4

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MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

instruction set

The instruction set for this register-register architecture provides a powerful and easy-to-use assembly

language. The instruction set consists of 52 instructions, with three formats and seven addressing modes.

Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are

listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source–destination e.g. ADD R4,R5

R4 + R5 → R5

Single operands, destination only

Relative jump, un–/conditional

e.g. CALL R8

e.g. JNE

PC → (TOS), SR → (TOS), R8→ PC

Jump-on equal bit = 0

Instructions that can operate on both word and byte data are differentiated by the suffix ’.B’ when a byte

operation is required.

Examples:

Instructions for word operation:

Instructions for byte operation:

MOV

ede,toni

#235h,&MEM

R5

MOV.B

ADD.B

PUSH.B

–––

ede,toni

#35h,&MEM

R5

ADD

PUSH

SWPB

R5

Table 2. Address Mode Descriptions

ADDRESS MODE

S

√

D

√

SYNTAX

MOV Rs,Rd

EXAMPLE

OPERATION

R10 → R11

register

MOV R10,R11

indexed

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV 2(R5),6(R6)

M(2+R5) → M(6+R6)

M(EDE) → M(TONI)

M(MEM) → M(TCDAT)

M(R10) → M(Tab+R6)

symbolic (PC relative)

absolute

MOV &MEM,&TCDAT

MOV @Rn,Y(Rm)

MOV @Rn+,Rm

indirect

MOV @R10,Tab(R6)

MOV @R10+,R11

indirect autoincrement

M(R10) → R11

R10 + 2→ R10

immediate

√

MOV #X,TONI

MOV #45,TONI

#45 → M(TONI)

NOTE 1: S = source, D = destination.

Computedbranches(BR)andsubroutinecalls(CALL)instructionsusethesameaddressingmodesastheother

instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and

calls. The full use of this programming capability permits a program structure different from conventional 8- and

16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks

instead of using Flag type programs for flow control.

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MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

operation modes and interrupts

TheMSP430operatingmodessupportvariousadvancedrequirementsforultra-lowpowerandultra-lowenergy

consumption. This is achieved by the intelligent management of the operations during the different module

operation modes and CPU states. The requirements are fully supported during interrupt event handling. An

interrupt event awakens the system from each of the various operating modes and returns with the RETI

instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.

ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.

The following five operating modes are supported:

Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.

Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals

are active, and loop control for MCLK is active.

Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals

are active, and loop control for MCLK is inactive.

Low power mode 2 (LMP2). The CPU is disabled, peripheral operation continues, ACLK signal is active,

and MCLK and loop control for MCLK are inactive.

Low power mode 3 (LMP3). The CPU is disabled, peripheral operation continues, ACLK signal is active,

MCLKand loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator(DCO)

(

MCLK generator) is switched off.

Low power mode 4 (LMP4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive

(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO

is switched off.

The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific

peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or

enabled. However, some peripheral current-saving functions are accessed through the state of local register

bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral which is turned

on or off using one register bit.

The most general bits that influence current consumption and support fast turn-on from low power operating

modesarelocatedinthestatusregister(SR). FourofthesebitscontroltheCPUandthesystemclockgenerator:

SCG1, SCG0, OscOff, and CPUOff.

15

Reserved For Future

Enhancements

9

8

7

0

V

SCG1

SCG0

OscOff

rw-0

CPUOff

GIE

N

Z

C

interrupts

Software determines the activation of interrupts through the monitoring of hardware set interrupt flag status bits,

the control of specific interrupt enable bits in SRs, the establishment of interrupt vectors, and the programming

of interrupt handlers. The interrupt vectors and the power-up starting address are located in ROM address

locations 0FFFFh through 0FFE0h. Each vector contains the 16-bit address of the appropriate interrupt handler

instruction sequence. Table 3 provides a summation of interrupt functions and addresses.

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MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

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Table 3. Interrupt Functions and Addresses

INTERRUPT SOURCE

INTERRUPT FLAG

WDTIFG

SYSTEM INTERRUPT

WORD ADDRESS

0FFFEh

PRIORITY

15, highest

14

Power-up, external reset, Watchdog

Reset

NMI,

NMIIFG (see Note 2)

OFIFG (see Note 2)

non-maskable

(non)-maskable

0FFFCh

Oscillator fault

Dedicated I/O

P0IFG.0

P0IFG.1

maskable

0FFFAh

0FFF8h

0FFF6h

0FFF4h

0FFF2h

0FFF0h

0FFEEh

0FFECh

0FFEAh

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

13

12

11

Watchdog timer

Timer_A

WDTIFG

10

CCIFG0 (see Note 3)

TAIFG (see Note 3)

URXIFG

9

Timer_A

8

UART Receive

UART Transmit

7

UTXIFG

6

5

Timer/Port

See Note 3

maskable

4

I/O Port P2

P2IFG.07 (see Note 2)

P1IFG.07 (see Note 2)

BTIFG

3

I/O Port P1

2

1

Basic Timer

I/O Port P0

P0IFG.27 (see Note 2)

0, lowest

NOTES: 2. Multiple source flags

3. Interrupt flags are located in the module

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

that are not allocated to a functional purpose are not physically present in the device. Simple SW access is

provided with this arrangement.

interrupt enable 1 and 2

7

6

5

4

3

2

1

0

Address

0h

P0IE.1

P0IE.0

OFIE

WDTIE

rw-0

WDTIE:

OFIE:

P0IE.0:

P0IE.1:

Watchdog timer interrupt enable signal

Oscillator fault interrupt enable signal

Dedicated I/O P0.0 interrupt enable signal

P0.1 or 8-bit timer/counter, RXD interrupt enable signal

7

6

5

4

3

2

1

0

Address

01h

BTIE

TPIE

UTXIE

URXIE

rw-0

URXIE:

UTXIE:

TPIE:

USART receive interrupt enable signal

USART transmit interrupt enable signal

Timer/Port interrupt enable signal

Basic Timer interrupt enable signal

BTIE:

7

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MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

interrupt flag registers 1 and 2

7

6

5

4

3

2

1

0

Address

02h

NMIIFG

P0IFG.1

P0IFG.0

OFIFG

WDTIFG

rw-0

rw-1

rw-0

WDTIFG:

Set on overflow or security key violation

or

Reset on VCC1 power-on or reset condition at ’RST/NMI-pin

Flag set on oscillator fault

OFIFG:

P0.0IFG:

P0.1IFG:

NMIIFG:

Dedicated I/O P0.0

P0.1 or 8-bit timer/counter, RXD

Signal at ’RST/NMI-pin

7

6

5

4

3

2

1

0

Address

03h

BTIFG

UTXIFG

URXIFG

rw

rw-1

rw-0

URXIFG:

UTXIFG:

BTIFG:

USART receive flag

USART transmit flag

Basic Timer flag

module enable registers 1 and 2

7

6

5

4

3

2

1

0

Address

04h

7

6

1

0

Address

05h

UTXE

URXE

rw-0

UTXE:

URXE:

USART transmit enable

USART receive enable

8

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MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

module enable registers 1 and 2 (continued)

Legend rw:

rw-0:

Bit can be read and written

Bit can be read and written. It is reset by PUC

SFR bit not present in device

ROM memory organization

MSP430C336

MSP430C337

MSP430P337

PMS430E337

FFFFh

Int. Vector

24 kB ROM

Int. Vector

32 kB ROM

Int. Vector

FFE0h

FFDFh

FFE0h

FFDFh

FFE0h

FFDFh

32 kB OTP

or

EPROM

A000h

8000h

05FFh

0200h

05FFh

0200h

05FFh

0200h

1024B RAM

16b Per.

8b Per.

1024B RAM

16b Per.

8b Per.

1024B RAM

16b Per.

8b Per.

01FFh

0100h

00FFh

0010h

000Fh

0000h

01FFh

0100h

00FFh

0010h

000Fh

0000h

01FFh

0100h

00FFh

0010h

000Fh

0000h

SFR

peripherals

Peripherals are connected to the CPU through a data, address, and control bus and can be handled easily with

instructions for memory manipulation.

oscillator and system clock

Twoclocksareusedinthesystem, thesystem(master)clock(MCLK)andtheauxiliaryclock(ACLK). TheMCLK

isamultipleoftheACLK. TheACLK runswiththecrystaloscillatorfrequency. Thespecialdesignoftheoscillator

supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected

across two terminals without any other external components being required.

The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It

can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, OR MCLK

are accessible for use by external devices at output terminal XBUF .

The controller system clocks have to deal with different requirements according to the application and system

condition. Requirements include:

High frequency in order to react quickly to system hardware requests or events

Low frequency in order to minimize current consumption, EMI, etc.

Stable frequency for timer applications e.g. real time clock (RTC)

Enable start-stop operation with minimum delay to operation function.

9

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MIXED SIGNAL MICROCONTROLLERS

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These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The

compromise selected for the MSP430 uses a low-crystal frequency which is multiplied to achieve the desired

nominal operating range:

f

N

f_(crystal)

(system)

The crystal frequency multiplication is acheived with a frequency locked loop (FLL) technique. The factor N is

recommended to be 32, 64, 96, or 128 depending on the maximum clock frequency and the electrical

characteristics provided by this datasheet. The FLL technique, in combination with a digital controlled oscillator

(DCO) provides immediate start-up capability together with long term crystal stability. The frequency variation

of the DCO with the FLL inactive is typically 330 ppm which means that with a cycle time of 1 µs the maximum

possible variation is 0.33 ns. For more precise timing, the FLL can be used which forces longer cycle times if

the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to

meet the chosen system frequency over a long period of time.

The start-up operation of the system clock depends on the previous machine state. During a PUC, the DCO

is reset to its lowest possible frequency. The control logic starts operation immediately after recognition of PUC.

multiplication

The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8,

8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well

as unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after

the operands have been loaded into the peripheral registers. No additional clock cycles are required.

digital I/O

Five eight-bit I/O ports (P0 thru P4) are implemented. Port P0 has six control registers, P1 and P2 have seven

control registers, and P3 and P4 modules have four control registers to give maximum flexibility of digital

input/output to the application:

Individual I/O bits are independently programable.

Any combination of input, output, and interrupt conditions is possible.

Interrupt processing of external events is fully implemented for all eight bits of the P0, P1, and P2 ports.

Read/write access is available to all registers by all instructions.

The seven registers are:

Input register

contains information at the pins

contains output information

Output register

Direction register

Interrupt edge select

Interrupt flags

controls direction

contains input signal change necessary for interrupt

indicates if interrupt(s) are pending

contains interrupt enable pins

Interrupt enable

Function select

determines if pin(s) used by module or port

These registers contain eight bits each with the exception of the the interrupt flag register and the interrupt

enable register which are 6 bits each. The two least significant bit (LSBs) of the interrupt flag and enable

registers are located in the special function register (SFR). Five interrupt vectors are implemented, one for Port

P0.0, one for Port P0.1, one commonly used for any interrupt event on Port P0.2 to Port P0.7, one commonly

used for any interrupt event on Port P1.0 to Port P1.7, and one commonly used for any interrupt event on Port

P2.0 to Port P2.7.

10

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MIXED SIGNAL MICROCONTROLLERS

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LCD drive

Liquid crystal displays (LCDs) for static, 2-, 3-, and 4-MUX operation can be driven directly. The operation of

thecontrollerLCDlogicisdefinedbysoftwarethroughmemory-bitmanipulation. LCDmemoryispartoftheLCD

module, not part of data memory. Eight mode and control bits define the operation and current consumption of

the LCD drive. The information for the individual digits can be easily obtained using table programming

techniques combined with the proper addressing mode. The segment information is stored into LCD memory

using instructions for memory manipulation.

The drive capability is defined by the external resistor divider that supports analog levels for 2-, 3-, and 4-MUX

operation. Groups of the LCD segment lines can be selected for digital output signals. The MSP430x33x

configuration has four common lines, 30 segment lines, and four terminals for adjusting the analog levels.

basic timer1

The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low

frequency control signals. This is done within the system by one central divider, the basic timer, to support low

current applications. The BTCTL control register contains the flags which control or select the different

operational functions. When the supply voltage is applied or when a reset of the device (RST/NMI pin), a

watchdog overflow, or a watchdog security key violation occurrs, all bits in the register hold undefined or

unchanged status. The user software usually configures the operational conditions on the BT during

initialization.

The basic timer has two eight bit timers which can be cascaded to a sixteen bit timer. Both timers can be read

and written by software. Two bits in the SFR address range handle the system control interaction according to

the function implemented in the basic timer. These two bits are the Basic Timer Interrupt Flag (BTIFG) and the

Basic Timer Interrupt Enable (BTIE) bit.

watchdog timer

The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a S/W

upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog function

is not needed in an application, the module can work as an interval timer, which generates an interrupt after the

selected time interval.

The watchdog timer counter (WDTCNT) is a 15/16-bit upcounter which is not directly accessible by software.

The WDTCNT is controlled using the watchdog timer control register (WDTCTL), which is an 8-bit read/write

register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct

password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.

If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When

the password is read its value is 069h that minimizes accidental write operations to the WDTCTL register. A

read-access to WDTCTL is only possible by writing 05Ah as the password in the high-byte of the WDTCTL. This

avoids an accidental write-access on the WDTCTL. Additionally to the watchdog timer control bits, there are

two bits included in the WDTCTL that configure the NMI pin.

USART

The universal synchronous/asynchronous interface is a dedicated peripheral module which provides serial

communications. The USART supports synchronous SPI (3 or 4 pin), and asynchronous UART

communications protocols, using double buffered transmit and receive channels. Data streams of 7 or 8 bits

in length can be transferred at a rate determined by the program, or by a rate defined by an external clock. Low

power applications are optimized by UART mode options which allow for the receipt of only the first byte of a

complete frame. The applications software then decides if the succeeding data is to be processed. This option

reduces power consumption.

Two dedicated interrupt vectors are assigned to the USART module, one for the receive and one for the transmit

channel.

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timer/port

The timer/port module has two 8-bit counters, an input that triggers one counter and six digital outputs with

3-state capability. Both counters have an independent clock selector for selecting an external signal or one of

the internal clocks (ACLK or MCLK). One of the counters has an extended control capability to halt, count

continuously, or gate the counter by selecting one of two external signals. This gate signal sets the interrupt flag

if an external signal is selected and the gate stops the counter.

Both timers can be read to and written from by software. The two 8-bit counters can be cascaded to form a 16-bit

counter. A common interrupt vector is implemented. The interrupt flag can be set by three events in the 8-bit

countermode(gatesignaloroverflowfromthecounters)orbytwoeventsinthe16-bitcountermode(gatesignal

or overflow from the MSB of the cascaded counter).

slope A/D conversion

Slope A/D conversion is accomplished with the timer/port module using external resistor(s) for reference (R ),

ref

external resistor(s) to the measured (R

), and an external capacitor. The external components are driven

meas

by software in such a way that the internal counter measures the time that is needed to charge or discharge

the capacitor.The reference resistor’s (R ) charge or discharge time is represented by N counts. The

ref

unknown resistors (R

) charge or discharge time is represented by N

counts. The unknown resistor’s

meas

value R

is the value of R multiplied by the relative number of counts (N

/N ). This value determines

meas

ref

meas ref

resistive sensor values that corresponds to the physical data, for example temperature, when an NTC or PTC

resistor is used.

timer_a

The timer_a module offers one sixteen bit counter and five capture/compare registers. The timer clock source

can be selected to come from an external source TACLK (SSEL=0), the ACLK (SSEL=1), or MCLK (SSEL=2

or SSEL=3). The clock source can be divided by one, two, four or eight. The timer can be fully controlled (in word

mode) since it can be halted, read, and written. It can be stopped, run continuously, count up, or count up/down

using one compare block to determine the period. The five capture/compare blocks are configured by the

application software to run in either capture or compare mode.

The capture mode is primarily used to measure external or internal events with any combination of positive,

negative, or both edges of the clock. The clock can also be stopped in capture mode by software. One external

event (CCISx=0) per capture block can be selected. If CCISx=1, the ACLK is the capture signal; and if CCISx=2

or CCISx=3, software capture is chosen.

The compare mode is primarily used to generate timing for the software or application hardware or to generate

pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An

individual output module, which can run independently of the compare function or is triggered in several ways,

is assigned to each of the five capture/compare registers.

Two interrupt vectors are used by the timer_a module. One individual vector is assigned to capture/compare

block CCR0 and one common interrupt vector is assigned to the timer and the other four capture/compare

blocks. The five interrupt events using the common vector are identified by an individual interrupt vector word.

The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler

software at the correct location. This simplifies the interrupt handler and gives each interrupt event the same

interrupt handler overhead of 5 cycles.

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8-bit timer/counter

The 8-bit interval timer supports three major functions for applications:

Serial communication or data exchange

Plus counting or plus accumulation

Timer

8-bit timer/counter (continued)

The 8-bit timer/counter peripheral includes the following major blocks: an 8-bit Up-Counter with preload register,

an 8-bit Control Register, an Input clock selector, an Edge detection (e.g. Start bit detection for asynchronous

protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-bit counter.

The 8-bit counter counts up with an input clock which is selected by two control bits from the control register.

The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from

the logical .AND. of MCLK and terminal P0.1.

Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A

write-access to the counter results in loading the content of the preload register into the counter. The software

writes or reads the preload register with all instructions. The preload register acts as a buffer and can be written

immediately after the load of the counter is completed. The enable input enables the count operation. When

the enable signal is set to high, the counter will count-up each time a positive clock edge is applied to the clock

input of the counter.

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peripheral file map

Peripherals with byte access

UART

Transmit Buffer, UTXBUF

Receive Buffer, URXBUF

Baud Rate, UBR1

077h

076h

075h

074h

073h

072h

071h

070h

054h

053h

052h

051h

050h

04Fh

04Eh

04Dh

04Ch

04Bh

047h

046h

040h

044h

043h

042h

03Fh

Port P3

Port P0

Port P3 Selection, P3SEL

Port P3 Direction, P3DIR

Port P3 Output, P3OUT

Port P3 Input, P3IN

01Bh

01Ah

019h

018h

015h

014h

013h

012h

011h

010h

003h

002h

001h

000h

Baud Rate, UBR0

Modulation Control, UMCTL

Receive Control, URCTL

Transmit Control, UTCTL

UART Control, UCTL

Port P0 Interrupt Enable, P0IE

Port P0 Interrupt Edge Select, P0IES

Port P0 Interrupt Flag, P0IFG

Port P0 Direction, P0DIR

Port P0 Output, P0OUT

Port P0 Input, P0IN

EPROM

EPROM Control, EPCTL

Crystal Buffer Control, CBCTL

SCG Frequency Control, SCFQCTL

SCG Frequency Integrator, SCFI1

SCG Frequency Integrator, SCFI0

Timer Port Enable, TPE

Crystal Buffer

System Clock

Special

SFR Interrupt Flag2, IFG2

SFR Interrupt Flag1, IFG1

SFR Interrupt Enable2, IE2

SFR Interrupt Enable1, IE1

Function

Timer/Port

Timer Port Data, TPD

Peripherals with word access

Timer Port Counter2, TPCNT2

Timer Port Counter1, TPCNT1

Timer Port Control, TPCTL

Basic Timer Counter2, BTCNT2

Basic Timer Counter1, BTCNT1

Basic Timer Control, BTCTL

8-bit Timer/Counter Data, TCDAT

8-bit Timer/Counter Preload, TCPLD

8-bit Timer/Counter Control, TCCTL

LCD Memory 15, LCDM15

:

Multiply

Sum Extend, SumExt

013Eh

013Ch

013Ah

0138h

0136h

0134h

0132h

0130h

0120h

012Eh

0160h

0162h

0164h

0166h

0168h

016Ah

016Ch

016Eh

0170h

0172h

0174h

0176h

0178h

017Ah

017Ch

017Eh

Result High Word, ResHi

Result Low Word, ResLo

Second Operand, OP_2

Reserved

Basic Timer

8-bit T/C

LCD

Multiply+Accumulate/Op.1, MAC

Multiply Signed/Operand1, MPYS

Multiply Unsigned/Operand1, MPY

Watchdog/Timer Control, WDTCTL

Timer_A Interrupt Vector, TAIV

Timer_A Control, TACTL

Cap/Com Control, CCTL0

Cap/Com Control, CCTL1

Cap/Com Control, CCTL2

Cap/Com Control, CCTL3

Cap/Com Control, CCTL4

Reserved

Watchdog

Timer_A

LCD Memory 1, LCDM1

031h

030h

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

026h

025h

024h

023h

022h

021h

020h

01Fh

01Eh

01D

LCD Control & Mode, LCDC

Port P2 Selection, P2SEL

Port P2 Interrupt Enable, P2IE

Port P2 Interrupt Edge Select, P2IES

Port P2 Interrupt Flag, P2IFG

Port P2 Direction, P2DIR

Port P2 Output, P2OUT

Port P2

Port P1

Port P4

Reserved

Timer_A Register, TAR

Cap/Com Register, CCR0

Cap/Com Register, CCR1

Cap/Com Register, CCR2

Cap/Com Register, CCR3

Cap/Com Register, CCR4

Reserved

Port P2 Input, P2IN

Port P1 Selection, P1SEL

Port P1 Interrupt Enable, P1IE

Port P1 Interrupt Edge Select, P1IES

Port P1 Interrupt Flag, P1IFG

Port P1 Direction, P1DIR

Port P1 Output, P1OUT

Reserved

Port P1 Input, P1IN

Port P4 Selection, P4SEL

Port P4 Direction, P4DIR

Port P4 Output, P4OUT

Port P4 Input, P4IN

01Ch

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MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

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absolute maximum ratings

Supply voltage range, between V

Supply voltage range, between V terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V

terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V

CC

SS

Input voltage range, V

to any VSS terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V

CC1

CC2

Input voltage range to any terminal (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

CC

Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA

Storage temperature range, T , (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

Storage temperature range, T , (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

stg

V

CC1

CC2

Common Lines COM0 to COM3, Segment Lines S0 to S29

Output Drivers O2 to O29

V

SS1

V

SS2

V

CC1

V

SS1

Core Logic With

Core CPU, System, JTAG/Test,

All Peripheral Modules

J/X

T/B

A/U

G/F

V

CC1

Terminal of Timer/Port

Input Buffers and Output Drivers of Port P0–P4

V

SS1

V

SS3

Substrate and Ground Potential For Input Inverters/Buffers

V

SS2

(see Note A)

V

SS1

(see Note B)

NOTES: A. Ground potential for all port output drivers and input terminals, excluding first inverter/buffer

B. Ground potential for entire device core logic and peripheral modules

Figure 1. Supply Voltage Interconnection

15

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recommended operating conditions

PARAMETER

MIN

2.5

2.7

0

NOM

MAX

5.5

0

UNIT

Supply voltage, V , (MSP430C33x)

CC

V

Supply voltage, V , (MSP430E/P33x)

CC

3

0

Supply voltage, VSS

TMS430C33x, TMS430P33x

PMS430E33x

–40

85

Operating free-air temperature range T

°C

A

25

XTAL frequency f

(XTAL)

(signal ACLK)

32 768

HZ

V

= 3 V

= 5 V

DC

1.65

3.8

MHz

CC

Processor frequency (signal MCLK), f

system

CC

5

4

3

2

1

1.1

2

0

1

3

4

5

6

7

V

CC

– Supply Voltage – V

Figure 2. Frequency vs. Supply Voltage

16

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MSP430x33x

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

supply current (into V ) excluding external current (f

CC

= 1 MHz) (see Note 4)

(system)

PARAMETER

TEST CONDITIONS

MIN NOM

400

800

3

MAX

500

900

6

UNIT

T = –40°C +85°C,

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

A

C336/7

P337

µA

T = –40°C +85°C,

A

I

Active Mode

(AM)

T = –40°C +85°C,

A

mA

µA

T = –40°C +85°C,

10

12

A

T = –40°C +85°C,

50

70

A

C336/7

P337

T = –40°C +85°C,

100

70

130

110

200

12

A

I

Low power mode, (LPM0,1)

Low power mode, (LPM2)

(CPUOff)

T = –40°C +85°C,

A

T = –40°C +85°C,

150

7

A

T = –40°C +85°C,

A

(LPM2)

T = –40°C +85°C,

18

25

A

T = –40°C

2.0

1.6

5.2

4.2

4.0

0.1

0.4

3.5

10

A

T = 25°C

A

V

= 3 V

CC

T = 85°C

A

I

Low power mode, (LPM3)

Low power mode, (LPM4)

µA

(LPM3)

T = –40°C

A

T = 25°C

A

= 5 V

10

CC

T = 85°C

A

10

T = –40°C

A

0.8

1.5

I

T = 25°C

A

V

= 3 V/5 V

µA

(LPM4)

CC

T = 85°C

A

NOTE 4: All inputs are tied to 0V or VCC2. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured

with active Basic Timer1 Module (ACLK selected), LCD Module (f

selected)

=1024Hz, 4MUX) and USART module (UART, ACLK, 2400 Baud

LCD

Current Consumption of active mode versus system frequency, C versions only

= I * f [MHz]

I

AM

AM[1MHz] system

Current Consumption of active mode versus supply voltage, C versions only

= I + 200µA/V * (V –3)

I

AM

AM[3V]

CC

17

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MSP430x33x

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

schmitt-trigger inputs Port 0 to P4, P0.x to P4.x, Timer/Port, CIN, TP0.0–TP0.5

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

2.1

3.4

1.5

2.3

1.0

1.4

UNIT

V

Positive-going input threshold voltage

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

1.2

2.3

0.7

1.4

0.3

0.6

IT+

IT–

V

Negative-going input threshold voltage

V

V –V

Input-output voltage differential, (hysteresis)

I

O

standard inputs TCK, TMS, TDI, RST/NMI (see Note 5)

PARAMETER

Low-level input voltage

High-level input voltage

TEST CONDITIONS

MIN

NOM

MAX

UNIT

V

+0.8

CC

IL

SS

0.7V

SS

V

CC

= 3 V/5 V

V

IH

CC

NOTE 5: A serial resistor of 1kOhm to the RST/NMI is recommended to enhance latch–up immunity.

outputs Port0toP4, P0.xtoP4.x, Timer/Port, TP0.0toTP0.5, LCD:S2/O2toS29/O29, XBUF:XBUF, JTAG:TDO

PARAMETER

TEST CONDITIONS

= – 1.2 mA, See Note 6

= – 3.5 mA, See Note 7

= – 1.5 mA, See Note 6

= – 4.5 mA, See Note 7

= + 1.2 mA, See Note 6

= + 3.5 mA, See Note 7

= + 1.5 mA, See Note 6

= + 4.5 mA, See Note 7

MIN NOM

–0.4

MAX

UNIT

I

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

(OHmax)

(OLmax)

V

CC

V

CC

V

CC

V

CC

= 3 V

= 5 V

= 3 V

= 5 V

–1.0

V

High-level output voltage

V

OH

OL

–0.4

–1.0

V

+0.4

+1.0

+0.4

+1.0

SS

V

Low-level output voltage

V

NOTES: 6. The maximum total current for all outputs combined should not exceed ±9.6 mA to hold the maximum voltage drop specified.

7. The maximum total current for all outputs combined should not exceed ±28 mA to hold the maximum voltage drop specified.

leakage current (see Note 8)

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

± 50

UNIT

nA

I

High-impendance leakage current (LTP)

V

, see Note 9

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V/5 V

(LTP)

TP0.x, CIN

= VSS – VCC

S29

nA

(LS29)

(P0.x)

Port P0: P0.x

Port P1: P1.x

Port P2: P2.x

Port P3: P3.x

Port P4: P4.x

0 ≤ x ≤ 7, see Note 10

nA

NOTES: 8. The leakage current is measured with V

SS

or V

applied to the corresponding pins(s) – unless otherwise noted.

CC

9. All timer/port pins (TP0.0 to TP0.5) are Hi-Z. Pins CIN and TP0.0 to TP0.5 are connected together during leakage current

measurement. In the leakage measurement mode, the input CIN is included. The input voltage is V or V

.

CC

SS

10. The leakages of the digital port terminals are measured individually. The port terminal must be selected for input and there must

be no optional pull–up or pull–down resistor.

18

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

optional resistors (see Note 11)

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

4.8

UNIT

kΩ

R

V

= 3 V/5 V

1.2

1.8

2.4

3.6

(opt1)

(opt2)

CC

7.2

kΩ

CC

R

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V/5 V

3.6

5.5

11

7.3

11

14.6

22

kΩ

(opt3)

(opt4)

(opt5)

(opt6)

(opt7)

(opt8)

(opt9)

(opt10)

Resistors, individually programmable with ROM code, all port

pins, values applicable for pull-down and pull-up

22

44

22

44

88

33

66

132

220

310

400

55

110

154

200

77

100

NOTE 11: Optional resistors R

for pull–down or pull–up are not programmed in standard OTP/EPROM devices P/E 337.

(optx)

inputs and outputs

PARAMETER

CONDITIONS

Port P0, P1 to P2:

External trigger signal for the interrupt

flag (see Notes 12 and 13)

VCC

MIN

NOM

MAX

UNIT

t

External Interrupt

timing

3 V/ 5 V

1.5

cycle

(int)

t

Timer_A, Capture

timing

TA0-TA4

3 V/ 5 V

250

ns

(cap)

(IN)

External capture signal (see Note 14)

f

t

Input frequency

P0.1, CIN, TP.5, UCLK, SIMO, SOMI,

TACLK, TA0-TA4

3 V/ 5 V

3 V

5 V

DC

300

125

f

Mhz

ns

(system)

or t

(H)

(L)

or t

f

Output frequency

XBUF,

TA0-4,

UCLK,

C

= 20 pF

3 V/ 5 V

f

MHz

(XBUF)

(TAx)

(UCLK)

L

(system)

DC

f

/2

(system)

f

(system)

t

Duty cycle of

output

XBUF,

C

= 20 pF

(Xdc)

L

f

= 1.1 MHz

= f

3 V/ 5 V

40

35

60

65

%

(MCLK)

(XBUF) (ACLK)

= f

(XBUF) (ACLK/n)

t

∆t

(Xdc)

50

0

TA0..4, C = 20 pF

(TA)

L

t

C

= t

3 V/ 5 V

±100

ns

(TAH) (TAL)

∆t

UCLK,

= 15pF

(L)

(UC)

t

= t

0

(UCH) (UCL)

t

(τ)

USART: Deglitch

time

See Note 15

3 V

5 V

0.6

0.3

2.6

1.4

µs

NOTES: 12. The external signal sets the interrupt flag every time t

is met. It may be set even with trigger signals shorter than t

. The

(int)

conditions to set the flag must be met independently from this timing constraint. T

is defined in MCLK cycles.

(int)

13. The external interrupt signal cannot exceed the maximum input frequency (f

)

(in)

14. The external capture signal triggers the capture event every time t

is met. It may be triggered even with capture signals shorter

(cap)

. The conditions to set the flag must be met independently from this timing constraint.

than t

(cap)

15. ThesignalappliedtotheUSARTreceivesignal/terminal(URXD)shouldmeetthetimingrequirementsoft toensurethattheURXS

(τ)

flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t . The operating conditions

to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on

the URXD line.

19

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electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

LCD

PARAMETER

TEST CONDITIONS

Voltage at R33

MIN

NOM

MAX

UNIT

V

2.5

V

CC

+0.2

(33)

2

Voltage at R23

Voltage at R13

Voltage at R03

(V –V ) ×

33 03

/

3

+ V

(23)

03

+ V

Analog voltage

V

= 3 V/5 V

V

CC

1

–V ) × /

(33) (03) 3

(V

– 2.5

(33)

(13)

(03)

V

+0.2

(03)

CC

Output 1

Output 0

I

)<= 10 nA

V

– 0.125

V

CC

O(HLCD)

O(LLCD)

(R03)

(R13)

(R23)

(HLCD

(R33)

V

CC

= 3 V/5 V

V

<= 10 nA

V

SS

V

+ 0.125

(LLCD)

SS

No load at all

segment and

common lines,

I

R03 = V

±20

SS

R13 = V /3

CC

±20

Input leakage

nA

R23 = 2 × V /3

±20

V

CC

= 3 V/5 V

CC

V

– 0.1

+ 0.1

(Sxx0)

(Sxx1)

(Sxx2)

(Sxx3)

(03)

(13)

(23)

(33)

(03)

(13)

(23)

(33)

V

Segment line

voltage

I = – 3 µA,

(Sxx)

V

CC

= 3 V/5 V

V

POR

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

µs

V

t

Delay

150

200

2.4

0.4

(POR)

V

0.9

0

(POR)

V

= 3V/ 5V

CC

V

(min_POR)

(reset)

t

PUC/POR

Reset is accepted internally

2

µs

crystal oscillator, XIN, XOUT

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

pF

C

Integrated capacitance at input

12

(XIN)

(XOUT)

(INL)

Integrated capacitance at output

pF

V

CC

= 3V/ 5V

X

VSS

0.8 x VCC1

0.2 x VCC1

VCC1

Input levels

V

(INH)

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

N

= 1 A0h

(DCO)

FN_4=FN_3=FN_2 = 0

f

DCO

V

= 3 V/5 V

1

MHz

(NOM)

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

0.15

0.18

1.25

1.45

0.36

0.39

2.5

3

0.6

0.62

4.7

N

= 00 0110 0000

(DCO)

FN_4=FN_3=FN_2 = 0

f

MHz

(DCO3)

(DCO26)

(DCO3)

(DCO26)

(DCO3)

(DCO26)

(DCO3)

(DCO26)

f

N

= 11 0100 0000

(DCO)

FN_4=FN_3=FN_2 = 0

5.5

1.05

1.2

N

= 00 0110 0000

(DCO)

FN_4=FN_3=0, FN_2 = 1

2xf

3xf

4xf

(NOM)

8.1

N

= 11 0100 0000

(DCO)

FN_4=FN_3=0, FN_2 = 1

9.9

0.5

0.6

3.7

4.5

0.7

0.8

4.8

6

1.5

N

= 00 0110 0000

(DCO)

FN_4=0, FN_3=1, FN_2=X

1.8

11

N

= 11 0100 0000

(DCO)

FN_4=0,FN_3 =1, FN_2=X

13.8

1.85

2.4

N

= 00 0110 0000

(DCO)

FN_4=1, FN_3 = FN_2=X

(NOM)

13.3

17.7

N

= 11 0100 0000

(DCO)

FN_4=1, FN_3 = FN_2=X

f

= f

(MCLK) (NOM)

N

S

V

= 3 V/5 V

A0h 1A0h

1.07

340h

1.13

(DCO)

CC

FN_4=FN_3=FN_2 = 0

f

= S x f

(NDCO)

V

(NDCO)+1

f

(DCO26)

4xf

3xf

NOM

f

(DCO26)

f

(DCO3)

Legend

NOM

f

(DCO26)

f

(DCO3)

2xf

f

NOM

Tolerance at Tap 26

f

(DCO26)

DCO Frequency

Adjusted by Bits

2 9–2 5 in SCFI1

f

(DCO3)

NOM

Tolerance at Tap 3

f

(DCO3)

FN_2 = 0

FN_3 = 0

FN_4 = 0

FN_2 = 1

FN_3 = 0

FN_4 = 0

FN_2 = X

FN_3 = 1

FN_4 = 0

FN_2 = X

FN_3 = X

FN_4 = 1

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

RAM

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

V

CPU halted, See Note 16

1.8

V

(RAMh)

NOTE 16: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program

execution should happen during this supply voltage condition.

Timer/Port comparator

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

350

UNIT

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V

175

I

µA

(CP)

= 5 V

600

V

Comparator, (timer/port)

CPON = 1

= 3 V/5 V

= 3 V

0.230 × V

0.260 × V

CC1

V

ref(CP)

CC1

5

37

42

mV

V

hys(CP)

= 5 V

10

JTAG, program memory

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

V

= 3 V

= 5 V

DC

5

CC

f

JTAG/Test

TCK frequency

MHz

(TCK)

10

CC

Pull-up resistors on TMS, TCK, TDI,

See Note 17

R

V

CC

= 3 V/ 5 V

25

60

90

kΩ

(test)

Fuse blow voltage, C versions, See Note 19

Fuse blow voltage, E/P versions, See Note 19

Supply current on TDI/VPP to blow fuse

Time to blow the fuse

V

= 3 V/ 5 V

5.5

6.0

12.0

100

1

CC

V

(FB)

11.0

JTAG/Fuse,

See Note 18

CC

I

t

mA

ms

V

(FB)

V

Programming voltage, applied to TDI/VPP

Current from programming voltage source

Programming time, single pulse

V

CC

V

CC

V

CC

V

CC

V

CC

= 3 V/ 5 V

11.0

5

11.5

100

12.0

70

(PP)

(pps)

(ppf)

I

t

mA

ms

µs

Programming time, fast algorithm

EPROM(E) and

OTP(P) versions only

P

n

Number of pulses for successful programming

Erase time wave length 2537 Å @

4

100

t

30

min

(erase)

2

15 Ws/cm (UV lamp of 12 mW/ cm )

Write/erase cycles

1000

10

Data retention Tj <55°C

Year

NOTES: 17. The TMS and TCK pull-up resistors are implemented in all ROM(C), OTP(P) and EPROM(E) versions. The pull-up resistor on TDI

is implemented in C versions only.

18. Once the fuse is blown no further access to the MSP430 JTAG/Test feature is possible.

19. The voltage supply to blow the fuse is applied to TDI/VPP pin during the fuse blowing procedure.

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

APPLICATION INFORMATION

V

CC

V

CC

(see Note A)

(see Note B)

(see Note A)

GND

(see Note A)

GND

CMOS INPUT

CMOS SCHMITT-TRIGGER INPUT

V

CC

(see Note A)

(see Note B)

(see Note A)

(see Note B)

GND

I/O WITH SCHMITT-TRIGGER INPUT

CMOS 3-STATE OUTPUT

TDO_Internal

V

CC

TDO_Control

TDI_Control

60 k TYP

TDI_Internal

MSP430C336/337: TMS, TCK, TDI

MSP430P336/E337: TMS, TCK

MSP430C33x: TDO/TDI

MSP430P/E33x: TDO/TDI

NOTES: A. Optional selection of pull-up or pull-down resistors available on ROM (masked) versions.

B. Fuses for the optional pull-up and pull-down resistors can only be programmed at the factory.

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

APPLICATION INFORMATION

VPP_ Internal

TDI_ Internal

TDI/VPP

JTAG

Fuse

TDO/TDI_Control

TDO/TDI

TMS

TDO_ Internal

JTAG Fuse

Blow

Control

From/To JTAG_CBT_SIG_REG

Figure 3. MSP430P337/E337: TDI/VPP, TDO/TDI

NOTES: A. During programming activity and when blowing the JTAG fuse, the TDI/VPP terminal is used to apply the correct voltage source.

The TDO/TDI terminal is used to apply the test input data for JTAG circuitry.

B. The TDI/VPP terminal of the ’P337 and ’E337 does not have an internal pull-up resistor. An external pull-down resistor is

recommended to avoid a floating node which could increase the current consumption of the device.

C. The TDO/TDI terminal is in a high-impedance state after POR. The ’P337 and ’E337 needs a pull-up or a pull-down resistor to avoid

floating a node which could increase the current consumption of the device.

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

MECHANICAL DATA

PJM (R-PQFP-G100)

PLASTIC QUAD FLATPACK

0,38

0,22

M

0,65

80

0,13

51

50

81

14,20 17,45

12,35 TYP

13,80 16,95

100

31

1

30

0,16 NOM

18,85 TYP

20,20

19,80

23,45

22,95

Gage Plane

2,90

2,50

0,25

0,25 MIN

0°–7°

1,03

0,73

Seating Plane

0,10

3,40 MAX

4040022/B 03/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-022

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x33x

MIXED SIGNAL MICROCONTROLLERS

SLAS163 – FEBRUARY 1998

MECHANICAL DATA

HFD (S-GQFP-G100)

CERAMIC QUAD FLATPACK

0,65

80

0,30 TYP

51

81

50

14,20

13,80

17,45

16,95

12,35 TYP

100

31

1

30

0,15 TYP

18,85 TYP

20,20

19,20

23,45

22,95

3,70 TYP

0,10 MIN

0°–8°

1,00

0,60

Seating Plane

0,10

4,25 MAX

4081530/A 09/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	MSP430P337IPJM
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLERS 混合信号微控制器微控制器和处理器外围集成电路可编程只读存储器时钟
文件：	总27页 (文件大小：354K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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