MUX36D08IDWR [TI]

1pA 开路泄漏电流、36V、8:1 精密模拟多路复用器 | DW | 28 | -40 to 125;


型号：	MUX36D08IDWR
厂家：	TEXAS INSTRUMENTS
描述：	1pA 开路泄漏电流、36V、8:1 精密模拟多路复用器 \| DW \| 28 \| -40 to 125 复用器
文件：	总51页 (文件大小：1697K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

MUX36xxx 36V 低电容、低泄漏电流、高精度模拟多路复用器

1 特性

3 说明

•

低导通电容

MUX36S16 和 MUX36D08 (MUX36xxx) 是现代互补金

属氧化物半导体 (CMOS) 模拟多路复用器 (MUX)。

MUX36S16 提供 16:1 单端通道，而 MUX36D08 提供

8:1 差分通道或双 8:1 单端通道。MUX36S16 和

MUX36D08 在由双电源（±5V 至 ±18V）或单电源

（10V 至 36V）供电时均能正常运行。这些器件在由

对称电源（如 V_DD= 12V，V_SS= –12V）和非对称电

源（如 V_DD= 12V，V_SS= –5V）供电时也能保证优异

性能。所有数字输入具有兼容晶体管-晶体管逻辑电路

(TTL) 的阈值。当器件在有效电源电压范围内运行时，

该阈值可保证 TTL 和 CMOS 逻辑电路的兼容性。

–

MUX36S16：13.5pF

MUX36D08：8.7pF

•

低输入泄漏：1pA

低电荷注入：0.31pC

轨至轨运行

宽电源电压范围：±5V 至 ±18V 或 10V 至 36V

低导通电阻：125Ω

转换时间：97ns

先断后合开关操作

EN 引脚可连接至 V_DD

逻辑电平：2V 至 V_DD

低电源电流：45µA

MUX36S16 和 MUX36D08 的导通和关断泄漏电流较

低，允许此类多路复用器以最小误差转换高输入阻抗源

传输的信号。电源电流低至 45µA，支持其应用于功耗

敏感型应用。

ESD 保护 HBM：2000V

业界通用的 TSSOP/SOIC 封装和更小的 WQFN 封

装选项

器件信息⁽¹⁾

2 应用

器件型号

封装

封装尺寸（标称值）

9.70mm × 6.40mm

17.9mm × 7.50mm

5.00mm × 5.00mm

4.00mm x 4.00mm

TSSOP (28)

•

工厂自动化和工业过程控制

MUX36S16

MUX36D08中添加了

WQFN 封装选项

SOIC (28)

可编程逻辑控制器 (PLC)

模拟输入模块

WQFN (RTV) (32)

WQFN (RSN) (32)

ATE 测试设备

数字万用表

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

电池监控系统

简化电路原理图

泄漏电流与温度间的关系

1000

I_D(ON)+

I_S(OFF)+

500

I_D(OFF)+

Bridge Sensor

Thermocouple

V_INP

-500

ADC

PGA/INA

MUX36D08

I_S(OFF)-

V_INM

-1000

I_D(OFF)-

Current

Sensing

-1500

I_D(ON)-

Photo

LED

Detector

-2000

Optical Sensor

Analog Inputs

-75

-50

-25

100 125 150

Temperature (èC)

D006

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASED9

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

8.3 Feature Description................................................. 26

8.4 Device Functional Modes........................................ 28

Application and Implementation ........................ 29

9.1 Application Information............................................ 29

9.2 Typical Application ................................................. 29

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 7

6.1 Absolute Maximum Ratings ...................................... 7

6.2 ESD Ratings.............................................................. 7

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 8

6.5 Electrical Characteristics: Dual Supply ..................... 8

6.6 Electrical Characteristics: Single Supply................. 10

6.7 Typical Characteristics............................................ 12

Parameter Measurement Information ................ 17

7.1 Truth Tables............................................................ 17

Detailed Description ............................................ 25

8.1 Overview ................................................................. 25

8.2 Functional Block Diagram ....................................... 25

10 Power Supply Recommendations ..................... 31

11 Layout................................................................... 32

11.1 Layout Guidelines ................................................. 32

11.2 Layout Example .................................................... 32

12 器件和文档支持 ..................................................... 34

12.1 文档支持................................................................ 34

12.2 相关链接................................................................ 34

12.3 接收文档更新通知 ................................................. 34

12.4 社区资源................................................................ 34

12.5 商标....................................................................... 34

12.6 静电放电警告......................................................... 34

12.7 Glossary................................................................ 34

13 机械、封装和可订购信息....................................... 34

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (April 2018) to Revision C

Page

•

Added BW, THD+N, and C_INrows to the Electrical Characteristics: Dual Supply ................................................................. 9

Changed V_DDand V_SSsupply current MAX values for ±15V supplies in Electrical Characteristics: Dual Supply ................. 9

Changed V_DDand V_SSsupply current MAX values for 12V supplies in Electrical Characteristics: Single Supply............... 11

Changes from Revision A (November 2017) to Revision B

Page

•

向“特性”中添加了 WQFN 封装选项........................................................................................................................................ 1

已添加在器件信息.................................................................................................................................................................. 1

Added pinout information for WQFN packages ..................................................................................................................... 3

Added data for WQFN packages to Thermal Information ...................................................................................................... 8

Changes from Original (November 2016) to Revision A

Page

•

已更改将特性列表中的转换时间从 85ns 更改为 97ns（典型值） ........................................................................................ 1

已添加在特性和器件信息部分中添加了 SOIC 封装 ............................................................................................................. 1

Added the DW (SOIC) package to the Pin Configuration and Functions section .................................................................. 3

Added SOIC package to the Thermal Information table ........................................................................................................ 8

Changed Transition time Typ value From 85: ns To: 97ns for ±15 V supplies in the Electrical Characteristics: Dual

Supply table............................................................................................................................................................................ 9

•

Added additional specifications for the SOIC packages (Q_J, Off-isolation, and channel-to-channel crosstalk) for ±15

V supplies in Electrical Characteristics: Dual Supply ............................................................................................................. 9

Changed Transition time Typ value From: 91 To: 102 ns for 12 V supply in the Electrical Characteristics: Single

Supply table.......................................................................................................................................................................... 11

Added additional specifications for the SOIC packages (Q_J, Off-isolation, and channel-to-channel crosstalk) for 12 V

supply in Electrical Characteristics: Single Supply............................................................................................................... 11

MUX36S16, MUX36D08

www.ti.com.cn

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

5 Pin Configuration and Functions

MUX36S16: DW and PW Package

28-Pin SOIC and TSSOP

Top View

MUX36S16: RTV and RSN Package

32-Pin WQFN

Top View

VDD

VSS

S16

S15

S14

S13

S12

S11

S10

S16

S15

S14

S13

S12

S11

S10

Thermal

Pad

GND

Not to scale

Pin Functions, MUX36S16

FUNCTION

DESCRIPTION

TSSOP/

SOIC

NAME

WQFN

Digital input

Address line 0

Address line 1

Address line 2

Address line 3

Analog input or output Drain pin. Can be an input or output.

Active high digital input. When this pin is low, all switches are turned off. When

this pin is high, the A[3:0] logic inputs determine which switch is turned on.

Digital input

GND

Power supply

Ground (0 V) reference

12, 13,

26, 27,

28, 30,

2, 3, 13

No connect

Do not connect

S10

Analog input or output Source pin 1. Can be an input or output.

Analog input or output Source pin 2. Can be an input or output.

Analog input or output Source pin 3. Can be an input or output.

Analog input or output Source pin 4. Can be an input or output.

Analog input or output Source pin 5. Can be an input or output.

Analog input or output Source pin 6. Can be an input or output.

Analog input or output Source pin 7. Can be an input or output.

Analog input or output Source pin 8. Can be an input or output.

Analog input or output Source pin 9. Can be an input or output.

Analog input or output Source pin 10. Can be an input or output.

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Pin Functions, MUX36S16 (continued)

FUNCTION

DESCRIPTION

TSSOP/

SOIC

NAME

WQFN

S11

S12

S13

S14

S15

S16

Analog input or output Source pin 11. Can be an input or output.

Analog input or output Source pin 12. Can be an input or output.

Analog input or output Source pin 13. Can be an input or output.

Analog input or output Source pin 14. Can be an input or output.

Analog input or output Source pin 15. Can be an input or output.

Analog input or output Source pin 16. Can be an input or output.

Positive power supply. This pin is the most positive power-supply potential. For

reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF

between V_DDand GND.

VDD

Power supply

Negative power supply. This pin is the most negative power-supply potential. In

single-supply applications, this pin can be connected to ground. For reliable

operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF

between V_SSand GND.

VSS

Power supply

MUX36S16, MUX36D08

www.ti.com.cn

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

MUX36D08: DW and PW Package

28-Pin SOIC and TSSOP

Top View

MUX36D08: RTV and RSN Package

32-Pin WQFN

Top View

VDD

VSS

S8A

S7A

S6A

S5A

S4A

S3A

S2A

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

GND

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

S1A

Thermal

Pad

Not to scale

Pin Functions: MUX36D08

FUNCTION

DESCRIPTION

TSSOP/

SOIC

NAME

WQFN

Digital input

Address line 0

Address line 1

Address line 2

Analog input or output Drain pin A. Can be an input or output.

Analog input or output Drain pin B. Can be an input or output.

Active high digital input. When this pin is low, all switches are turned off. When

Digital input

this pin is high, the A[2:0] logic inputs determine which pair of switches is turned

on.

GND

Power supply

Ground (0 V) reference

11, 12,

13, 26,

28, 30,

3, 13, 14

No connect

Do not connect

S1A

S2A

S3A

S4A

S5A

S6A

S7A

S8A

S1B

S2B

S3B

Analog input or output Source pin 1A. Can be an input or output.

Analog input or output Source pin 2A. Can be an input or output.

Analog input or output Source pin 3A. Can be an input or output.

Analog input or output Source pin 4A. Can be an input or output.

Analog input or output Source pin 5A. Can be an input or output.

Analog input or output Source pin 6A. Can be an input or output.

Analog input or output Source pin 7A. Can be an input or output.

Analog input or output Source pin 8A. Can be an input or output.

Analog input or output Source pin 1B. Can be an input or output.

Analog input or output Source pin 2B. Can be an input or output.

Analog input or output Source pin 3B. Can be an input or output.

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Pin Functions: MUX36D08 (continued)

FUNCTION

DESCRIPTION

TSSOP/

SOIC

NAME

WQFN

S4B

S5B

S6B

S7B

S8B

Analog input or output Source pin 4B. Can be an input or output.

Analog input or output Source pin 5B. Can be an input or output.

Analog input or output Source pin 6B. Can be an input or output.

Analog input or output Source pin 7B. Can be an input or output.

Analog input or output Source pin 8B. Can be an input or output.

Positive power supply. This pin is the most positive power supply potential. For

reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF

between V_DDand GND.

VDD

Power supply

Negative power supply. This pin is the most negative power supply potential. In

single-supply applications, this pin can be connected to ground. For reliable

operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF

between V_SSand GND.

VSS

Power supply

MUX36S16, MUX36D08

www.ti.com.cn

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

MAX

UNIT

V_DD

Supply

V_SS

0.3

Voltage

V_DD– V_SS

Digital pins⁽²⁾: EN, A0, A1, A2, A3

Analog pins⁽²⁾: Sx, SxA, SxB, D, DA, DB

V_SS– 0.3

V_SS– 2

–30

V_DD+ 0.3

V_DD+ 2

Current⁽³⁾

°C

Operating, T_A

Junction, T_J

Storage, T_stg

–55

150

Temperature

150

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage limits are valid if current is limited to ±30 mA.

(3) Only one pin at a time.

6.2 ESD Ratings

VALUE

2000

500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

Dual supply

(1)

(2)

V_DD

V_SS

Positive power-supply voltage

Single supply

Negative power-supply voltage (dual supply)

–5

–18

V_DD– V_SS

Supply voltage

V_S

Source pins voltage⁽³⁾

Drain pins voltage

V_SS

–25

–40

V_DD

V_D

V_EN

V_A

Enable pin voltage

Address pins voltage

I_CH

T_A

Channel current (T_A= 25°C)

Operating temperature

°C

125

(1) When V_SS= 0 V, V_DDcan range from 10 V to 36 V.

(2) V_DDand V_SScan be any value as long as 10 V ≤ (V_DD– V_SS) ≤ 36 V.

(3) V_Sis the voltage on all the S pins.

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

6.4 Thermal Information

MUX36S16/ MUX36D08

(TSSOP)

(SOIC)

RTV

(WQFN)

RSN

(WQFN)

THERMAL METRIC⁽¹⁾

UNIT

28 PINS

79.8

24.0

37.6

1.2

28 PINS

53.6

30.1

28.5

9.0

32 PINS

33.0

20.8

13.9

0.3

32 PINS

33.7

26.5

13.4

0.3

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

37.1

N/A

28.4

N/A

13.8

4.1

13.4

4.1

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics: Dual Supply

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG SWITCH

Analog signal range

On-resistance

T_A= –40°C to +125°C

V_S= 0 V, I_S= –1 mA

V_SS

V_DD

170

200

230

250

125

145

R_ON

V_S= ±10 V, I_S= –1 mA

V_S= 10 V, 0 V, –10 V

T_A= –40°C to +85°C

T_A= –40°C to +125°C

On-resistance

mismatch between

channels

ΔR_ON

T_A= –40°C to +85°C

T_A= –40°C to +125°C

On-resistance

flatness

R_FLAT

T_A= –40°C to +85°C

T_A= –40°C to +125°C

On-resistance drift

V_S= 0 V

0.62

Ω/°C

–0.04

–0.15

–1.2

–0.15

–1

0.001

0.04

0.15

1.2

0.15

Switch state is off,

I_S(OFF)

I_D(OFF)

I_D(ON)

Input leakage current V_S= ±10 V, V_D= ±10

T_A= –40°C to +85°C

T_A= –40°C to +125°C

V⁽¹⁾

0.01

Switch state is off,

Output off-leakage

V_S= ±10 V, V_D= ±10

current

T_A= -40°C to +85°C

T_A= -40°C to +125°C

V⁽¹⁾

–4.5

–0.2

–1

4.5

0.2

Output on-leakage

current

Switch state is on,

V_D= ±10 V, V_S= floating

T_A= –40°C to +85°C

T_A= –40°C to +125°C

–5.3

–15

5.3

Switch state is on,

V_DA= V_DB= ±10 V, V_S

floating

Differential on-

leakage current

I_DL(ON)

T_A= –40°C to +85°C

T_A= –40°C to +125°C

–100

–500

100

500

LOGIC INPUT

V_IH

V_IL

I_D

Logic voltage high

Logic voltage low

Input current

0.8

0.1

µA

(1) When V_Sis positive, V_Dis negative, and vice versa.

MUX36S16, MUX36D08

www.ti.com.cn

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

Electrical Characteristics: Dual Supply (continued)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

PARAMETER

SWITCH DYNAMICS⁽²⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

136

145

151

V_S= ±10 V, R_L= 300 Ω,

C_L= 35 pF

t_ON

Enable turn-on time

T_A= –40°C to +85°C

T_A= –40°C to +125°C

V_S= ±10 V, R_L= 300 Ω,

C_L= 35 pF

t_OFF

Enable turn-off time

Transition time

T_A= –40°C to +85°C

T_A= –40°C to +125°C

143

151

157

V_S= 10 V, R_L= 300 Ω,

C_L= 35 pF,

t_t

T_A= –40°C to +85°C

T_A= –40°C to +125°C

Break-before-make

time delay

t_BBM

V_S= 10 V, R_L= 300 Ω, C_L= 35 pF, T_A= –40°C to +125°C

TSSOP package

SOIC package

TSSOP package

SOIC package

TSSOP package

SOIC package

TSSOP package

SOIC package

TSSOP package

SOIC package

TSSOP package

SOIC package

0.31

0.67

±0.9

±1.1

–98

–94

–88

–100

–96

–88

–83

260

430

V_S= 0 V

C_L= 1 nF, R_S= 0 Ω

Q_J

Charge injection

Off-isolation

V_S= –15 V to +15 V

Nonadjacent channel to D,

DA, DB

R_L= 50 Ω, V_S= 1 V_RMS

f = 1 MHz

Adjacent channel to D, DA,

Nonadjacent channels

Adjacent channels

Channel-to-channel

crosstalk

R_L= 50 Ω, V_S= 1 V_RMS

f = 1 MHz

MUX36S16

MUX36D08

V_S= 1 V_RMS, R_L= 50

Ω , C_L= 5 pF

–3dB Bandwidth

Total harmonic

distortion plus noise

THD + N

V_S= 0 V or V_DD, R_L= 600 Ω , C_L= 50 pF, f = 20Hz to 20kHz

0.09%

1.1

Digital input

capacitance

C_IN

V_IN= 0 V or V_DD

C_S(OFF)

Input off-capacitance f = 1 MHz, V_S= 0 V

2.1

11.1

6.4

12.2

7.5

MUX36S16

MUX36D08

MUX36S16

MUX36D08

Output off-

C_D(OFF)

f = 1 MHz, V_S= 0 V

capacitance

13.5

8.7

C_S(ON)

Output on-

f = 1 MHz, V_S= 0 V

capacitance

C_D(ON)

10.2

POWER SUPPLY

All V_A= 0 V or 3.3 V,

V_S= 0 V, V_EN= 3.3 V,

V_DDsupply current

T_A= –40°C to +85°C

T_A= –40°C to +125°C

µA

All V_A= 0 V or 3.3 V,

V_S= 0 V, V_EN= 3.3 V,

V_SSsupply current

T_A= –40°C to +85°C

T_A= –40°C to +125°C

(2) Specified by design; not subject to production testing.

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

6.6 Electrical Characteristics: Single Supply

at T_A= 25°C, V_DD= 12 V, and V_SS= 0 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

235

MAX

UNIT

ANALOG SWITCH

Analog signal range

On-resistance

T_A= –40°C to +125°C

V_S= 10 V, I_S= –1 mA

V_SS

V_DD

340

390

430

R_ON

T_A= –40°C to +85°C

T_A= –40°C to +125°C

ΔR_ON

On-resistance match V_S= 10 V, I_S= –1 mA

T_A= –40°C to +85°C

T_A= –40°C to +125°C

On-resistance drift

V_S= 10 V

1.07

Ω/°C

–0.04

–0.15

–1.2

0.001

0.04

0.15

1.2

Switch state is off,

V_S= 1 V and V_D= 10 V,

or V_S= 10 V and V_D= 1

V⁽¹⁾

I_S(OFF)

I_D(OFF)

I_D(ON)

Input leakage current

T_A= –40°C to +85°C

T_A= –40°C to +125°C

–0.15

–0.75

–2.4

0.01

0.15

0.75

2.4

Switch state is off,

V_S= 1 V and V_D= 10 V,

or V_S= 10 V and V_D= 1

V⁽¹⁾

Output off leakage

current

T_A= –40°C to +85°C

T_A= –40°C to +125°C

–0.15

–0.75

–2.5

0.15

0.75

2.5

Switch state is on,

Output on leakage

current

V_D= 1 V and 10 V, V_S

floating

T_A= –40°C to +85°C

T_A= –40°C to +125°C

–15

Switch state is on,

V_DA= V_DB= 1 V and 10

V, V_S= floating

Differential on-

leakage current

I_DL(ON)

T_A= –40°C to +85°C

T_A= –40°C to +125°C

–100

–500

100

500

LOGIC INPUT

V_IH

V_IL

I_D

Logic voltage high

2.0

Logic voltage low

Input current

0.8

0.1

µA

(1) When V_Sis 1 V, V_Dis 10 V, and vice versa.

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Electrical Characteristics: Single Supply (continued)

at T_A= 25°C, V_DD= 12 V, and V_SS= 0 V (unless otherwise noted)

PARAMETER

SWITCH DYNAMIC CHARACTERISTICS⁽²⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

145

149

V_S= 8 V, R_L= 300 Ω,

C_L= 35 pF

t_ON

Enable turn-on time

Enable turn-off time

T_A= –40°C to +85°C

T_A= –40°C to +125°C

V_S= 8 V, R_L= 300 Ω,

C_L= 35 pF

t_OFF

T_A= –40°C to +85°C

T_A= –40°C to +125°C

102

147

V_S= 8 V, C_L= 35 pF

107

V_S= 8 V, R_L= 300 Ω,

C_L= 35 pF,

T_A= –40°C to +85°C

T_A= –40°C to +125°C

153

155

t_t

Transition time

V_S= 8 V, R_L= 300 Ω,

C_L= 35 pF,

Break-before-make

time delay

t_BBM

V_S= 8 V, R_L= 300 Ω, C_L= 35 pF, T_A= –40°C to +125°C

TSSOP package

SOIC package

TSSOP

0.12

0.38

±0.17

±0.48

–97

–94

–88

–100

–99

-88

V_S= 6 V

C_L= 1 nF, R_S= 0 Ω

Q_J

Charge injection

Off-isolation

V_S= 0 V to 12 V

SOIC package

TSSOP package

SOIC package

TSSOP package

SOIC package

TSSOP package

SOIC package

TSSOP

Nonadjacent channel to D,

DA, DB

R_L= 50 Ω, V_S= 1 V_RMS

f = 1 MHz

Adjacent channel to D, DA,

Nonadjacent channels

Adjacent channels

Channel-to-channel

crosstalk

R_L= 50 Ω, V_S= 1 V_RMS

f = 1 MHz

SOIC package

-83

C_S(OFF)

C_D(OFF)

Input off-capacitance f = 1 MHz, V_S= 6 V

2.4

3.4

15.4

9.1

MUX36S16

MUX36D08

MUX36S16

MUX36D08

Output off-

f = 1 MHz, V_S= 6 V

capacitance

7.8

16.2

9.9

C_S(ON)

Output on-

f = 1 MHz, V_S= 6 V

capacitance

C_D(ON)

11.6

POWER SUPPLY

All V_A= 0 V or 3.3 V,

V_S= 0 V, V_EN= 3.3 V

V_DDsupply current

T_A= –40°C to +85°C

T_A= –40°C to +125°C

µA

All V_A= 0 V or 3.3 V,

V_S= 0 V, V_EN= 3.3 V

V_SSsupply current

T_A= –40°C to +85°C

T_A= –40°C to +125°C

(2) Specified by design, not subject to production test.

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6.7 Typical Characteristics

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

400

350

300

250

200

150

100

T_A= 90èC

V_DD= 10 V, V_SS= -10 V

350

T_A= 125èC

T_A= 25èC

V_DD= 16.5 V, V_SS= -16.5 V

300

250

200

150

100

V_DD= 13.5 V, V_SS= -13.5 V

T_A= 0èC

V_DD= 15 V, V_SS= -15 V

T_A= -40èC

V_DD= 18 V, V_SS= -18 V

-18

-14

-10

-6

Source or Drain Voltage (V)

-2

-18

-14

-10

-6

Source or Drain Voltage (V)

-2

D001

D002

V_DD= 15 V, V_SS= –15 V

图 2. On-Resistance vs Source or Drain Voltage

图 1. On-Resistance vs Source or Drain Voltage

700

600

500

400

300

200

100

700

600

500

400

300

200

100

T_A= 85èC

T_A= 125èC

V_DD= 5 V, V_SS= -5 V

V_DD= 6 V, V_SS= -6 V

T_A= 25èC

V_DD= 7 V, V_SS= -7 V

T_A= 0èC

T_A= -40èC

-8

-6

-4

-2

Source or Drain Voltage (V)

D003

D004

V_DD= 12 V, V_SS= 0 V

图 3. On-Resistance vs Source or Drain Voltage

图 4. On-Resistance vs Source or Drain Voltage

250

200

150

100

700

600

500

400

300

200

100

V_DD= 14 V, V_SS= 0 V

V_DD= 33 V, V_SS= 0 V

V_DD= 36 V, V_SS= 0 V

V_DD= 30 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

V_DD= 10 V, V_SS= 0 V

Source or Drain Voltage (V)

D024

D005

图 5. On-Resistance vs Source or Drain Voltage

图 6. On-Resistance vs Source or Drain Voltage

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Typical Characteristics (接下页)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

250

200

150

100

200

150

100

Source or Drain Voltage (V)

-12

-6

Source or Drain Voltage (V)

D025

D026

V_DD= 24 V, V_SS= 0 V

V_DD= 12 V, V_SS= –12 V

图 7. On-Resistance vs Source or Drain Voltage

图 8. On-Resistance vs Source or Drain Voltage

1000

900

600

300

I_D(ON)+

I_S(OFF)+

500

I_D(OFF)+

I_D(ON)+

I_S(OFF)-

-500

-1000

-1500

-2000

I_S(OFF)-

I_D(OFF)-

I_D(OFF)+

-300

-600

-900

I_D(OFF)-

I_D(ON)-

75 100 125 150

-75

-50

-25

100 125 150

-75

-50

-25

Temperature (èC)

D006

D007

V_DD= 15 V, V_SS= –15 V

图 9. Leakage Current vs Temperature

V_DD= 12 V, V_SS= 0 V

图 10. Leakage Current vs Temperature

V_DD= 5 V, V_SS= -5 V

V_DD= 12 V, V_SS= 0 V

V_DD= 5 V, V_SS= -5 V

V_DD= 12 V, V_SS= 0 V

V_DD= 10 V, V_SS= -10 V

-1

V_DD= 15 V, V_SS= -15 V

-2

-15

-10

-5 0

Source Voltage (V)

-15

-10

-5 0

Source Voltage (V)

D011

D027

MUX36S16, source-to-drain

图 11. Charge Injection vs Source Voltage

MUX36D08, source-to-drain

图 12. Charge Injection vs Source Voltage

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Typical Characteristics (接下页)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

150

120

V_DD= 10 V, V_SS= -10 V

t_ON(V_DD= 12 V, V_SS= 0 V)

t_ON(V_DD= 15 V, V_SS= -15 V)

V_DD= 15 V, V_SS= -15 V

-3

t_OFF(V_DD= 12 V, V_SS= 0 V)

-6

t_OFF(V_DD= 15 V, V_SS= -15 V)

V_DD= 12 V, V_SS= 0 V

-9

-15

-10

-5

Drain voltage (V)

-75

-50

-25

100 125 150

Temperature (èC)

D008

D010

Drain-to-source

图 13. Charge Injection vs Drain Voltage

图 14. Turn-On and Turn-Off Times vs Temperature

-20

-40

Adjacent Channel to D (Output)

Adjacent Channels

-40

-60

-80

-100

-120

-140

-100

-120

-140

Non-Adjacent Channel to D (Output)

Non-Adjacent Channels

100k

10M

Frequency (Hz)

100M

100k

10M

Frequency (Hz)

100M

D012

D013

图 15. Off Isolation vs Frequency

图 16. Crosstalk vs Frequency

100

-5

V_DD= 5 V, V_SS= -5 V

-10

-15

-20

-25

-30

0.1

V_DD= 15 V, V_SS= -15 V

0.01

100

Frequency (Hz)

10k

100k

10M

Frequency (Hz)

100M

D014

D021

图 17. THD+N vs Frequency

图 18. On Response vs Frequency

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Typical Characteristics (接下页)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

C_D(ON)

C_S(OFF)

C_D(OFF)

C_D(ON)

C_S(OFF)

-15

-10

-5

Source or Drain Voltage (V)

-15

-10

-5

Source or Drain Voltage (V)

D015

D016

MUX36S16, V_DD= 15 V, V_SS= –15 V

MUX36D08, V_DD= 15 V, V_SS= –15 V

图 19. Capacitance vs Source Voltage

图 20. Capacitance vs Source Voltage

C_S(OFF)

C_D(ON)

C_D(OFF)

C_D(ON)

C_D(OFF)

C_S(OFF)

12 18

Source or Drain Voltage (V)

12 18

Source or Drain Voltage (V)

D017

D018

MUX36S16, V_DD= 30 V, V_SS= 0 V

MUX36D08, V_DD= 30 V, V_SS= 0 V

图 21. Capacitance vs Source Voltage

图 22. Capacitance vs Source Voltage

C_D(ON)

C_D(OFF)

C_D(ON)

C_S(OFF)

C_D(OFF)

Source or Drain Voltage (V)

D019

D020

MUX36S16, V_DD= 12 V, V_SS= 0 V

MUX36D08, V_DD= 12 V, V_SS= 0 V

图 23. Capacitance vs Source Voltage

图 24. Capacitance vs Source Voltage

MUX36S16, MUX36D08

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Typical Characteristics (接下页)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

-5

-10

-15

-20

-25

-25 -20 -15 -10

-5

Source Current (mA)

D028

图 25. Source Current vs Drain Current

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ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

7 Parameter Measurement Information

7.1 Truth Tables

表 1. MUX36S16

X⁽¹⁾

ON-CHANNEL

All channels are off

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

Channel 9

Channel 10

Channel 11

Channel 12

Channel 13

Channel 14

Channel 15

Channel 16

(1) X denotes don't care..

表 2. MUX36D08

X⁽¹⁾

ON-CHANNEL

All channels are off

Channels 1A and 1B

Channels 2A and 2B

Channels 3A and 3B

Channels 4A and 4B

Channels 5A and 5B

Channels 6A and 6B

Channels 7A and 7B

Channels 8A and 8B

(1) X denotes don't care.

MUX36S16, MUX36D08

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7.1.1 On-Resistance

The on-resistance of the MUX36xxx is the ohmic resistance across the source (Sx, SxA, or SxB) and drain (D,

DA, or DB) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol R_ONis

used to denote on-resistance. The measurement setup used to measure R_ONis shown in 图 26. Voltage (V) and

current (I_CH) are measured using this setup, and R_ONis computed as shown in 公式 1:

R_ON= V / I_CH

(1)

I_CH

V_S

图 26. On-Resistance Measurement Setup

7.1.2 Off Leakage

There are two types of leakage currents associated with a switch during the OFF state:

1. Source off-leakage current

2. Drain off-leakage current

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol I_S(OFF)

Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.

This current is denoted by the symbol I_D(OFF)

The setup used to measure both off-leakage currents is shown in 图 27

I_{s (OFF)}

I_{D (OFF)}

V_S

V_D

图 27. Off-Leakage Measurement Setup

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7.1.3 On-Leakage Current

On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in

the ON state. The source pin is left floating during the measurement. 图 28 shows the circuit used for measuring

the on-leakage current, denoted by I_D(ON)

I_{D (ON)}

NC = No Connection

V_D

图 28. On-Leakage Measurement Setup

7.1.4 Differential On-Leakage Current

In case of a differential signal, the on-leakage current is defined as the differential leakage current that flows into,

or out of, the drain pins when the switches are in the ON state. The source pins are left floating during the

measurement. 图 29 shows the circuit used for measuring the on-leakage current on each signal path, denoted

by I_DA(ON)and I_DB(ON). The absolute difference between these two currents is defined as the differential on-

leakage current, denoted by I_DL(ON)

I_DA(ON)

SxA

I_DB(ON)

SxB

V_D

NC = No Connection

图 29. Differential On-Leakage Measurement Setup

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7.1.5 Transition Time

Transition time is defined as the time taken by the output of the MUX36xxx to rise or fall to 90% of the transition

after the digital address signal has fallen or risen to 50% of the transition. 图 30 shows the setup used to

measure transition time, denoted by the symbol t_t.

V_DD

V_SS

3 V

VDD

VSS

Address

Signal (V_IN

50%

)

V_S1

0 V

S2-S15

S16

V_IN

t_t

V_S16

V_S1

90%

Output

MUX36S16

Output

2 V

GND

300 Ω

35 pF

90%

V_S16

图 30. Transition-Time Measurement Setup

7.1.6 Break-Before-Make Delay

Break-before-make delay is a safety feature that prevents two inputs from connecting when the MUX36xxx is

switching. The MUX36xxx output first breaks from the ON-state switch before making the connection with the

next ON-state switch. The time delay between the break and the make is known as break-before-make delay. 图

31 shows the setup used to measure break-before-make delay, denoted by the symbol t_BBM

V_DD

V_SS

3 V

VSS

VDD

Address

Signal (V_IN

)

V_S

0 V

S2-S15

S16

V_IN

Output

MUX36S16

80%

Output

2 V

GND

300 Ω

35 pF

t_BBM

图 31. Break-Before-Make Delay Measurement Setup

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7.1.7 Turn-On and Turn-Off Time

Turn-on time is defined as the time taken by the output of the MUX36xxx to rise to 90% final value after the

enable signal has risen to 50% final value. 图 32 shows the setup used to measure turn-on time. Turn-on time is

denoted by the symbol t_ON

Turn off time is defined as the time taken by the output of the MUX36xxx to fall to 10% initial value after the

enable signal has fallen to 50% initial value. 图 32 shows the setup used to measure turn-off time. Turn-off time

is denoted by the symbol t_OFF

V_DD

V_SS

3 V

VDD

VSS

Enable

Drive (V_IN)

50%

V_S

S2-S16

0 V

t_OFF(EN)

MUX36S16

t_ON(EN)

V_S

0.9 V_S

Output

GND

300 Ω

35 pF

0.1 V_S

V_IN

0 V

图 32. Turn-On and Turn-Off Time Measurement Setup

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7.1.8 Charge Injection

The MUX36xxx have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and

PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate

signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is

denoted by the symbol Q_INJ. 图 33 shows the setup used to measure charge injection.

V_SS

V_DD

VDD

VSS

3 V

V_EN

MUX36S16

0 V

R_S

V_OUT

C_L

1 nF

V_OUT

V_S

GND

Q_INJ= C_L×

V_OUT

V_EN

图 33. Charge-Injection Measurement Setup

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7.1.9 Off Isolation

Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX36xxx when a 1-V_RMSsignal is

applied to the source pin (Sx, SxA, or SxB) of an off-channel. 图 34 shows the setup used to measure off

isolation. Use 公式 2 to compute off isolation.

V_DD

V_SS

0.1 µF

Network Analyzer

VSS

VDD

50 ꢀ

50 Ω

V_S

V_OUT

R_L

50 Ω

GND

图 34. Off Isolation Measurement Setup

≈

’

◊

V_OUT

V_S

Off Isolation = 20 ∂ Log

∆

(2)

7.1.10 Channel-to-Channel Crosstalk

Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx, SxA, or SxB) of an off-channel,

when a 1-V_RMSsignal is applied at the source pin of an on-channel. 图 35 shows the setup used to measure

channel-to-channel crosstalk. Use 公式 3 to compute, channel-to-channel crosstalk.

V_DD

V_SS

0.1 µF

VSS

VDD

Network Analyzer

V_OUT

R_L

50 Ω

V_S

GND

图 35. Channel-to-Channel Crosstalk Measurement Setup

≈

∆

’

◊

V_OUT

V_S

Channel-to-Channel Crosstalk = 20 ∂ Log

(3)

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7.1.11 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin of an on-channel, and the output measured at the drain pin of the MUX36xxx. 图 36 shows the

setup used to measure bandwidth of the mux. Use 公式 4 to compute the attenuation.

V_DD

V_SS

0.1 µF

Network Analyzer

VSS

VDD

V₁

50 ꢀ

V_S

V₂

V_OUT

R_L

50 Ω

GND

图 36. Bandwidth Measurement Setup

≈

∆

’

◊

V₂

Attenuation = 20 ∂ Log

(4)

7.1.12 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the

ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux

output. The on-resistance of the MUX36xxx varies with the amplitude of the input signal and results in distortion

when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as

THD+N. 图 37 shows the setup used to measure THD+N of the MUX36xxx.

V_DD

V_SS

0.1 µF

Audio Precision

V_SS

V_DD

R_S

V_S

5 V_RMS

V_IN

V_OUT

R_L

10 kΩ

GND

图 37. THD+N Measurement Setup

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8 Detailed Description

8.1 Overview

The MUX36xxx are a family of analog multiplexers. The Functional Block Diagram section provides a top-level

block diagram of both the MUX36S16 and MUX36D08. The MUX36S16 is a 16-channel, single-ended, analog

mux. The MUX36D08 is an 8-channel, differential or dual 8:1, single-ended, analog mux. Each channel is turned

on or turned off based on the state of the address lines and enable pin.

8.2 Functional Block Diagram

MUX36D08

MUX36S16

S1A

S2A

S7A

S8A

S1B

S2B

S14

S7B

S8B

S15

S16

1-of-8

1-of-16

Decoder

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8.3 Feature Description

8.3.1 Ultralow Leakage Current

The MUX36xxx provide extremely low on- and off-leakage currents. The MUX36xxx are capable of switching

signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error

because of the ultra-low leakage currents. 图 38 shows typical leakage currents of the MUX36xxx versus

temperature.

1000

I_D(ON)+

I_S(OFF)+

500

I_D(OFF)+

-500

I_S(OFF)-

-1000

I_D(OFF)-

-1500

I_D(ON)-

-2000

-75

-50

-25

100 125 150

Temperature (èC)

D006

图 38. Leakage Current vs Temperature

8.3.2 Ultralow Charge Injection

The MUX36xxx have a simple transmission gate topology, as shown in 图 39. Any mismatch in the stray

capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is

opened or closed.

OFF ON

C_GDN

C_GSN

C_GSP

C_GDP

OFF ON

图 39. Transmission Gate Topology

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Feature Description (接下页)

The MUX36xxx have special charge-injection cancellation circuitry that reduces the source-to-drain charge

injection to as low as 0.31 pC at V_S= 0 V, and ±0.9 pC in the full signal range, as shown in 图 40.

V_DD= 5 V, V_SS= -5 V

V_DD= 12 V, V_SS= 0 V

V_DD= 10 V, V_SS= -10 V

-1

V_DD= 15 V, V_SS= -15 V

-2

-15

-10

-5 0

Source Voltage (V)

D011

图 40. Source-to-Drain Charge Injection

The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux),

where D becomes the input and Sx becomes the output. 图 41 shows the drain-to-source charge injection across

the full signal range.

V_DD= 10 V, V_SS= -10 V

V_DD= 15 V, V_SS= -15 V

-3

-6

V_DD= 12 V, V_SS= 0 V

-9

-15

-10

-5

Drain voltage (V)

D008

图 41. Drain-to-Source Charge Injection

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Feature Description (接下页)

8.3.3 Bidirectional Operation

The MUX36xxx are operable as both a mux and demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins

of the MUX36xxx are used either as input or output. Each MUX36xxx channel has very similar characteristics in

both directions.

8.3.4 Rail-to-Rail Operation

The valid analog signal for the MUX36xxx ranges from V_SSto V_DD. The input signal to the MUX36xxx swings

from V_SSto V_DDwithout any significant degradation in performance. The on-resistance of the MUX36xxx varies

with input signal, as shown in 图 42

400

V_DD= 10 V, V_SS= -10 V

350

V_DD= 16.5 V, V_SS= -16.5 V

300

250

200

150

100

V_DD= 13.5 V, V_SS= -13.5 V

V_DD= 15 V, V_SS= -15 V

V_DD= 18 V, V_SS= -18 V

-18

-14

-10

-6

-2

Source or Drain Voltage (V)

D001

图 42. On-resistance vs Source or Drain Voltage

8.4 Device Functional Modes

When the EN pin of the MUX36xxx is pulled high, one of the switches is closed based on the state of the

address lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the

address lines. The EN pin can be connected to V_DD(as high as 36 V).

MUX36S16, MUX36D08

www.ti.com.cn

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The MUX36xxx family offers outstanding input/output leakage currents and ultra-low charge injection. These

devices operate up to 36 V, and offer true rail-to-rail input and output. The on-capacitance of the MUX36xxx is

very low. These features makes the MUX36xxx a family of precision, robust, high-performance analog

multiplexer for high-voltage, industrial applications.

9.2 Typical Application

图 43 shows a 16-bit, differential, 8-channel, multiplexed, data-acquisition system. This example is typical in

industrial applications that require low distortion and a high-voltage differential input. The circuit uses the

ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along

with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential mux. This TI Precision

Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the MUX36D08,

OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.

Analog Inputs

REF3140

RC Filter

OPA350

RC Filter

Bridge Sensor

Reference Driver

Gain Network

OPA192

Thermocouple

REF

OPA140

V_INP

Charge

Kickback

Filter

Gain Network

OPA192

ADS8864

Current Sensing

V_INM

Photo

Detector

LED

High-Voltage Multiplexed Input

High-Voltage Level Translation

VCM

Optical Sensor

图 43. 16-Bit Precision Multiplexed Data-Acquisition System for High-Voltage Inputs With Lowest

Distortion

9.2.1 Design Requirements

The primary objective is to design a ±20 V, differential, 8-channel, multiplexed, data-acquisition system with

lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave

input. The design requirements for this block design are:

•

System supply voltage: ±15 V

ADC supply voltage: 3.3 V

ADC sampling rate: 400 kSPS

ADC reference voltage (REFP): 4.096 V

System input signal: A high-voltage differential input signal with a peak amplitude of 20 V and frequency

(f_IN) of 10 kHz are applied to each differential input of the mux.

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Typical Application (接下页)

9.2.2 Detailed Design Procedure

The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system

for highest system linearity and fast settling. The overall system block diagram is illustrated in 图 43. The circuit

is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output buffer,

attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple channels

using a single ADC, providing a low-cost solution. This design systematically approaches each analog circuit

block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input

signal at each input channel. Detailed design considerations and component selection procedure can be found in

the TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition System for High-

Voltage Inputs with Lowest Distortion.

9.2.3 Application Curve

1.0

0.8

0.6

0.4

0.2

0.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

œ20

œ15

œ10

œ5

C030

ADC Differential Peak-to-Peak Input (V)

图 44. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block

MUX36S16, MUX36D08

www.ti.com.cn

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

10 Power Supply Recommendations

The MUX36xxx operates across a wide supply range of ±5 V to ±18 V (10 V to 36 V in single-supply mode). The

devices also perform well with unsymmetric supplies such as V_DD= 12 V and V_SS= –5 V. For reliable operation,

use a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to ground.

The on-resistance of the MUX36xxx varies with supply voltage, as illustrated in 图 45

400

V_DD= 10 V, V_SS= -10 V

350

V_DD= 16.5 V, V_SS= -16.5 V

300

250

200

150

100

V_DD= 13.5 V, V_SS= -13.5 V

V_DD= 15 V, V_SS= -15 V

V_DD= 18 V, V_SS= -18 V

-18

-14

-10

-6

-2

Source or Drain Voltage (V)

D001

图 45. On-Resistance Variation With Supply and Input Voltage

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

图 46 illustrates an example of a PCB layout with the MUX36S16IPW, and 图 47 illustrates an example of a PCB

layout with MUX36D08IPW.

Some key considerations are:

1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure

that the capacitor voltage rating is sufficient for the V_DDand V_SSsupplies.

2. Keep the input lines as short as possible. In case of the differential signal, make sure the A inputs and B

inputs are as symmetric as possible.

3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.

4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

11.2 Layout Example

V_DD

Via to

GND Plane

Via to

GND Plane

V_SS

S16

S15

S14

S13

S12

S11

S10

MUX36S16IPW

Via to

GND Plane

GND

图 46. MUX36S16IPW Layout Example

MUX36S16, MUX36D08

www.ti.com.cn

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

Layout Example (接下页)

V_DD

Via to

GND Plane

Via to

V_SS

S8A

S7A

S6A

S5A

S4A

S3A

S2A

S1A

GND Plane

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

GND

MUX36D08IPW

Via to

GND Plane

图 47. MUX36D08IPW Layout Example

MUX36S16, MUX36D08

ZHCSFV0C –NOVEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

•

《ADS8864

号：SBAS572）

位、400kSPS

串行接口、微功耗、微型、单端输入、SAR

模数转换器》（文献编

《采用 e-trim 技术的 36V、轨到轨输入/输出、低失调电压、低输入偏置电流 OPAx192 运算放大器》（文献编

号：SBOS620）

《OPAx140 高精度、低噪声、轨到轨输出、11MHz JFET 运算放大器》（文献编号：SBOS498）

12.2 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。

表 3. 相关链接

器件

产品文件夹

单击此处

立即订购

单击此处

技术文档

单击此处

工具与软件

单击此处

支持和社区

单击此处

MUX36S16

MUX36D08

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jun-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

MUX36D08IDWR

MUX36D08IPW

ACTIVE

SOIC

TSSOP

QFN

1000 RoHS & Green

50 RoHS & Green

NIPDAU

Level-3-260C-168 HR

Level-1-260C-UNLIM

-40 to 125

MUX36D08D

Samples

NIPDAU

MUX36D080A

MUX36D08IPWR

MUX36D08IRSNR

2000 RoHS & Green

3000 RoHS & Green

RSN

MUX

36D08

MUX36D08IRTVR

ACTIVE

WQFN

RTV

3000 RoHS & Green

1000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

MUX

36D08

Samples

MUX36S16IDWR

MUX36S16IPW

ACTIVE

SOIC

TSSOP

QFN

NIPDAU

Level-3-260C-168 HR

Level-1-260C-UNLIM

-40 to 125

MUX36S16DA

MUX36S160A

Samples

RoHS & Green

MUX36S16IPWR

MUX36S16IRSNR

2000 RoHS & Green

3000 RoHS & Green

RSN

MUX

36S16

MUX36S16IRTVR

ACTIVE

WQFN

RTV

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

MUX

36S16

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jun-2022

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MUX36D08IDWR

MUX36D08IPWR

MUX36D08IRSNR

MUX36D08IRTVR

MUX36S16IDWR

MUX36S16IPWR

MUX36S16IRSNR

MUX36S16IRTVR

SOIC

TSSOP

QFN

1000

2000

3000

1000

2000

3000

330.0

32.4

16.4

12.4

32.4

16.4

12.4

11.35 18.67

3.1

1.8

16.0

12.0

8.0

32.0

16.0

12.0

32.0

16.0

12.0

6.9

4.25

5.3

10.2

4.25

5.3

RSN

RTV

1.15

1.1

WQFN

SOIC

8.0

11.35 18.67

3.1

16.0

12.0

8.0

TSSOP

QFN

6.9

4.25

5.3

10.2

4.25

5.3

1.8

RSN

RTV

1.15

1.1

WQFN

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MUX36D08IDWR

MUX36D08IPWR

MUX36D08IRSNR

MUX36D08IRTVR

MUX36S16IDWR

MUX36S16IPWR

MUX36S16IRSNR

MUX36S16IRTVR

SOIC

TSSOP

QFN

1000

2000

3000

1000

2000

3000

350.0

367.0

350.0

367.0

350.0

367.0

350.0

367.0

66.0

43.0

35.0

66.0

43.0

35.0

RSN

RTV

WQFN

SOIC

TSSOP

QFN

RSN

RTV

WQFN

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

MUX36D08IPW

MUX36S16IPW

TSSOP

530

10.2

3600

3.5

Pack Materials-Page 3

PACKAGE OUTLINE

RTV0032E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.15

4.85

PIN 1 INDEX AREA

5.15

4.85

SIDE WALL LEAD

METAL THICKNESS

DIM A

0.8

0.7

OPTION 1

0.1

OPTION 2

0.2

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(DIM A) TYP

3.45 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

28X 0.5

SYMM

3.5

0.30

32X

0.18

0.1

C A B

0.05

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4225196/A 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTV0032E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32X (0.6)

32X (0.24)

(1.475)

28X (0.5)

SYMM

(4.8)

(

0.2) TYP

VIA

(R0.05)

TYP

(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225196/A 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTV0032E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32X (0.6)

32X (0.24)

28X (0.5)

(0.845)

SYMM

(4.8)

METAL

TYP

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4225196/A 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

MUX36D08IDWR [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E