MUX36S08IRRJR [TI]
1pA 开路泄漏电流、36V、8:1、1 通道精密模拟多路复用器 | RRJ | 16 | -40 to 125;
| 型号： | MUX36S08IRRJR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1pA 开路泄漏电流、36V、8:1、1 通道精密模拟多路复用器 | RRJ | 16 | -40 to 125 复用器 |
| 文件： | 总47页 (文件大小：2476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
MUX36xxx 36V 低电容、低泄漏电流、高精度模拟多路复用器
1 特性
3 说明
1
•
低导通电阻
MUX36S08 和 MUX36D04 (MUX36xxx) 是现代互补金
属氧化物半导体 (CMOS) 模拟多路复用器 (mux)。
MUX36S08 提供 8:1 单端通道，而 MUX36D04 提供
差动 4:1 或双 4:1 单端通道。MUX36S08 和
MUX36D04 在双电源（±5V 至 ±18V）或单电源（10V
至 36V）供电时均能正常运行。它们在由对称电源
（如 VDD = 12V、VSS = –12V）和非对称电源（如
VDD = 12V、
–
–
MUX36S08：9.4pF
MUX36D04：6.7pF
•
•
•
•
•
•
•
•
•
•
•
•
•
低泄漏电流：1pA
低电荷注入：0.3pC
轨至轨运行
宽电源电压范围：±5V 至 ±18V 或 10V 至 36V
低导通电阻：125Ω
VSS = –5V）供电时也能保证优异性能。所有数字输入
具有兼容晶体管-晶体管逻辑电路 (TTL) 的阈值。当器
件在有效电源电压范围内运行时，该阈值可确保 TTL
和 CMOS 逻辑电路的兼容性。
转换时间：92ns
先断后合开关操作
EN 引脚与 VDD 相连
逻辑电平：2V 至 VDD
低电源电流：45µA
MUX36S08 和 MUX36D04 的导通和关断泄漏电流较
低，允许此类多路复用器以最小误差转换来源于高输入
阻抗源的信号。仅为 45µA 的低电源电流支持其应用于
便携式 应用。
ESD 保护 HBM：2000V
行业标准 TSSOP 封装和更小型的 WQFN 封装
有关其他配置，请参阅：
–
–
–
–
–
TMUX6111/ 12/ 13（4 通道 SPST）
TMUX6121/ 22/ 23（2 通道 SPST）
TMUX6119（1 通道 SPDT）
TMUX6136（2 通道 SPDT）
TMUX6104（1 通道 4:1）
器件信息(1)
器件型号
MUX36S08
封装
TSSOP (16)
WQFN (16)
封装尺寸（标称值）
5.00mm × 4.40mm
4.00mm x 4.00mm
MUX36D04
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
2 应用
空白
•
•
•
•
•
工厂自动化和工业过程控制
可编程逻辑控制器 (PLC)
模拟输入模块
自动测试设备
电池监控系统
简化电路原理图
泄漏电流与温度间的关系
900
ID(ON)+
600
300
0
Bridge Sensor
Thermocouple
ID(OFF)+
IS(OFF)+
œ
VINP
ADC
PGA/INA
+
MUX36D04
VINM
IS(OFF)œ
œ300
Current
Sensing
ID(OFF)œ
œ600
ID(ON)œ
œ900
Photo
LED
Detector
0
25
50
75
100 125 150
œ75 œ50 œ25
Optical Sensor
C006
Temperature (°C)
Analog Inputs
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS705
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
目录
8.11 Channel-to-Channel Crosstalk.............................. 21
8.12 Bandwidth ............................................................. 22
8.13 THD + Noise ......................................................... 22
Detailed Description ............................................ 23
9.1 Overview ................................................................. 23
9.2 Functional Block Diagram ....................................... 23
9.3 Feature Description................................................. 24
9.4 Device Functional Modes........................................ 26
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics: Dual Supply ..................... 7
7.6 Electrical Characteristics: Single Supply................... 9
7.7 Typical Characteristics............................................ 11
Parameter Measurement Information ................ 15
8.1 Truth Tables............................................................ 15
8.2 On-Resistance ........................................................ 16
8.3 Off-Leakage Current ............................................... 16
8.4 On-Leakage Current ............................................... 17
8.5 Differential On-Leakage Current ............................. 17
8.6 Transition Time ....................................................... 18
8.7 Break-Before-Make Delay....................................... 18
8.8 Turn-On and Turn-Off Time .................................... 19
8.9 Charge Injection...................................................... 20
8.10 Off Isolation........................................................... 21
9
10 Application and Implementation........................ 27
10.1 Application Information.......................................... 27
10.2 Typical Application ............................................... 27
11 Power Supply Recommendations ..................... 29
12 Layout................................................................... 30
12.1 Layout Guidelines ................................................. 30
12.2 Layout Example .................................................... 30
13 器件和文档支持 ..................................................... 31
13.1 文档支持................................................................ 31
13.2 相关链接................................................................ 31
13.3 接收文档更新通知 ................................................. 31
13.4 社区资源................................................................ 31
13.5 商标....................................................................... 31
13.6 静电放电警告......................................................... 31
13.7 术语表 ................................................................... 31
14 机械、封装和可订购信息....................................... 31
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (April 2018) to Revision D
Page
•
•
•
•
•
•
•
已添加 特征：有关其他配置，请参阅 ..................................................................................................................................... 1
Added RRJ (WQFN) package option to the MUX36D08 ...................................................................................................... 4
Changed the WQFN S6 pin number From: 19 To: 9.............................................................................................................. 4
Added the RRJ package option to the MUX36D04 ............................................................................................................... 5
Added WQFN (RRJ) data to Thermal Information ................................................................................................................. 7
Changed On-resistance drift unit value From: Ω To: %/°C .................................................................................................... 7
Changed IDL(ON) unit value From: nA To: pA........................................................................................................................... 7
Changes from Revision B (July 2016) to Revision C
Page
•
•
•
•
•
•
已添加 已将 WQFN 封装选项添加到 特性 .............................................................................................................................. 1
已添加 已在器件信息中添加了 WQFN 封装选项 .................................................................................................................... 1
Changed Description column of MUX36D04 row in Device Comparison Table .................................................................... 4
Added WQFN (RUM) data to Thermal Information ................................................................................................................ 7
Changed On-resistance drift TYP value From: 0.52 To: 0.64 in Electrical Characteristics: Dual Supply .............................. 7
Changed Analog Switch, ID parameter in Electrical Characteristics: Dual Supply table: split parameter into ID(OFF) and
ID(ON) parameters, changed symbols, parameter names, and test conditions ....................................................................... 7
•
•
•
Changed Analog Switch, IDL(ON) parameter test conditions in Electrical Characteristics: Dual Supply table ......................... 7
Changed On-resistance drift TYP value From: 0.47 To: 1.13 in Electrical Characteristics: Single Supply ........................... 9
Changed Analog Switch, ID parameter in Electrical Characteristics: Single Supply table: split parameter into ID(OFF)
2
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
and ID(ON) parameters, changed symbols, parameter names, and ID(ON) test conditions ....................................................... 9
Changed and swapped data between 25°C and 85°C to fix the typo ................................................................................. 10
Changed 图 30: changed low-voltage level to 0 V ............................................................................................................... 18
Changed 图 33: added 0 V line, flipped VS supply symbol .................................................................................................. 20
Changed 图 37: changed 5 VRMS marking in Audio Precision box....................................................................................... 22
Changed description of MUX36D04 in Overview section..................................................................................................... 23
Changed 图 43: changed OPA140 amplifier and charge kickback filter box ....................................................................... 27
•
•
•
•
•
•
Changes from Revision A (January 2016) to Revision B
Page
•
•
Added differential on-leakage current parameter to Electrical Characteristics table ............................................................. 7
Added Differential On-Leakage Current section................................................................................................................... 17
Changes from Original (January 2016) to Revision A
Page
•
已由“产品预览”更改为“量产数据” ............................................................................................................................................ 1
Copyright © 2016–2019, Texas Instruments Incorporated
3
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
5 Device Comparison Table
PRODUCT
MUX36S08
MUX36D04
DESCRIPTION
8-channel, single-ended analog multiplexer (8:1 mux)
4-channel differential or dual 4:1 single-ended analog multiplexer (8:2 mux)
6 Pin Configuration and Functions
MUX36S08: PW Package
16-Pin TSSOP
MUX36S08: RUM and RRJ Package
16-Pin WQFN
Top View
Top View
A0
EN
VSS
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
A2
GND
VDD
S5
VSS
S1
1
2
3
4
12
11
10
9
GND
VDD
S5
Thermal
Pad
S2
S2
S6
S3
S3
S6
S4
S7
D
S8
Not to scale
Not to scale
RUM and RRJ have the same package
dimension, but different thermal pad
dimension and lead finger length.
Pin Functions: MUX36S08
PIN
FUNCTION
DESCRIPTION
NAME
A0
TSSOP
WQFN
15
1
16
15
8
Digital input
Digital input
Digital input
Address line 0
Address line 1
Address line 2
A1
14
A2
13
D
6
Analog input or output Drain pin. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is high,
the A[2:0] logic inputs determine which switch is turned on.
EN
2
16
Digital input
GND
S1
S2
S3
S4
S5
S6
S7
S8
14
4
12
2
Power supply
Ground (0 V) reference
Analog input or output Source pin 1. Can be an input or output.
Analog input or output Source pin 2. Can be an input or output.
Analog input or output Source pin 3. Can be an input or output.
Analog input or output Source pin 4. Can be an input or output.
Analog input or output Source pin 5. Can be an input or output.
Analog input or output Source pin 6. Can be an input or output.
Analog input or output Source pin 7. Can be an input or output.
Analog input or output Source pin 8. Can be an input or output.
5
3
6
4
7
5
12
11
10
9
10
9
8
7
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
VSS
13
3
11
1
Power supply
Power supply
Power supply
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
Thermal
Pad(1)
Exposed Pad. The exposed pad is electrically connected to VSS internally. Connect EP to VSS to
achieve rated thermal and ESD performance.
-
-
(1) RUM and RRJ have the same package dimension, but different thermal pad dimension and lead finger length.
4
Copyright © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
MUX36D04: PW Package
16-Pin TSSOP
MUX36D04: RUM and RRJ Package
16-Pin WQFN
Top View
Top View
A0
EN
1
2
3
4
5
6
7
8
16
A1
15
14
13
12
11
10
9
GND
VDD
S1B
S2B
S3B
S4B
DB
VSS
S1A
S2A
S3A
S4A
DA
VSS
S1A
S2A
S3A
1
2
3
4
12
11
10
9
VDD
S1B
S2B
S3B
Thermal
Pad
Not to scale
Not to scale
RUM and RRJ have the same package
dimension, but different thermal pad
dimension and lead finger length.
Pin Functions: MUX36D04
PIN
FUNCTION
DESCRIPTION
NAME
A0
TSSOP
WQFN
1
16
8
15
14
6
Digital input
Digital input
Address line 0
Address line 1
A1
DA
Analog input or output Drain pin A. Can be an input or output.
Analog input or output Drain pin B. Can be an input or output.
DB
9
7
Active high digital input. When this pin is low, all switches are turned off. When this pin is high,
the A[1:0] logic inputs determine which pair of switches is turned on.
EN
2
16
Digital input
GND
S1A
S2A
S3A
S4A
S1B
S2B
S3B
S4B
15
4
13
2
Power supply
Ground (0 V) reference
Analog input or output Source pin 1A. Can be an input or output.
Analog input or output Source pin 2A. Can be an input or output.
Analog input or output Source pin 3A. Can be an input or output.
Analog input or output Source pin 4A. Can be an input or output.
Analog input or output Source pin 1B. Can be an input or output.
Analog input or output Source pin 2B. Can be an input or output.
Analog input or output Source pin 3B. Can be an input or output.
Analog input or output Source pin 4B. Can be an input or output.
5
3
6
4
7
5
13
12
11
10
11
10
9
8
Positive power supply. This pin is the most positive power supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
14
3
12
1
Power supply
Power supply
Power supply
Negative power supply. This pin is the most negative power supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
Thermal
Pad(1)
Exposed Pad. The exposed pad is electrically connected to VSS internally. Connect EP to VSS
to achieve rated thermal and ESD performance.
-
-
(1) RUM and RRJ have the same package dimension, but different thermal pad dimension and lead finger length.
Copyright © 2016–2019, Texas Instruments Incorporated
5
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–40
MAX
40
UNIT
VDD
Supply
VSS
0.3
V
Voltage
VDD – VSS
40
Digital input pins: (2)EN, A0, A1, A2
Analog input pins: (2)Sx, SxA, SxB, D, DA, DB
VSS – 0.3
VSS – 2
–30
VDD + 0.3
VDD + 2
30
V
V
Current(3)
mA
Operating, TA
Junction, TJ
Storage, Tstg
–55
150
Temperature
150
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Only one pin at a time
(3) Voltage limits are valid if current is limited to ±30 mA.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
5
NOM
MAX
18
UNIT
Dual supply
(1)
(2)
VDD
VSS
Positive power-supply voltage
V
Single supply
10
36
Negative power-supply voltage (dual supply)
–5
–18
36
V
V
VDD – VSS
Supply voltage
10
VS
Source pins voltage(3)
Drain pins voltage
VSS
VSS
VSS
VSS
–25
–40
VDD
VDD
VDD
VDD
25
V
VD
VEN
VA
V
Enable pin voltage
V
Address pins voltage
V
ICH
TA
Channel current (TA = 25°C)
Operating temperature
mA
°C
125
(1) When VSS = 0 V, VDD can range from 10 V to 36 V.
(2) VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 36 V.
(3) VS is the voltage on all S pins.
6
Copyright © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
7.4 Thermal Information
MUX36S08 and MUX36D04
THERMAL METRIC(1)
PW (TSSOP) RUM (WQFN) RRJ (WQFN)
UNIT
16 PINS
103.8
36.8
16 PINS
37.3
31.6
16.2
0.5
16 PINS
46.2
37.7
21.7
0.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
49.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.7
ψJB
49.1
16.2
6.1
21.7
6.2
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics: Dual Supply
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog signal range
On-resistance
TA = –40°C to +125°C
VSS
VDD
170
200
230
V
VS = 0 V, ICH = 1 mA
125
145
Ω
RON
TA = –40°C to +85°C
VS = ±10 V, ICH = 1 mA
Ω
Ω
TA = –40°C to
+125°C
250
2.4
2.4
6
9
On-resistance mismatch
between channels
TA = –40°C to +85°C
ΔRON
VS = ±10 V, ICH = 1 mA
TA = –40°C to
+125°C
11
6
TA = –40°C to +85°C
53
RFLAT
On-resistance flatness
On-resistance drift
VS = 10 V, 0 V, –10 V
VS = 0 V
Ω
TA = –40°C to
+125°C
58
0.64
%/°C
nA
–0.04
–0.15
0.001
0.04
0.15
Switch state is off,
TA = –40°C to +85°C
IS(OFF)
ID(OFF)
ID(ON)
Input leakage current
VS = ±10 V, VD = ±10 V(1)
TA = –40°C to
+125°C
–1.9
1.9
–0.1
–0.5
0.005
0.008
3
0.1
0.5
Switch state is off,
TA = -40°C to +85°C
Output off leakage current
Output on leakage current
nA
nA
pA
VS = ±10 V, VD = ±10 V(1)
TA = –40°C to
+125°C
–2
2
–0.1
–0.5
0.1
0.5
Switch state is on,
VD = ±10 V, VS = floating
TA = –40°C to +85°C
TA = –40°C to
+125°C
–3.3
3.3
–15
15
Switch state is on,
VDA = VDB = ±10 V,
VS = floating
Differential on-leakage
current
TA = –40°C to +85°C
–100
100
IDL(ON)
TA = –40°C to
+125°C
–500
2
500
LOGIC INPUT
VIH
VIL
Logic voltage high
Logic voltage low
V
V
0.8
(1) When VS is positive, VD is negative, and vice versa.
Copyright © 2016–2019, Texas Instruments Incorporated
7
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
Electrical Characteristics: Dual Supply (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ID
Input current
0.15
µA
SWITCH DYNAMICS(2)
88
136
144
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +85°C
tON
tOFF
tt
Enable turn-on time
ns
ns
ns
TA = –40°C to
+125°C
151
63
92
75
83
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +85°C
Enable turn-off time
Transition time
TA = –40°C to
+125°C
90
143
151
VS = 10 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +85°C
TA = –40°C to
+125°C
157
Break-before-make time
delay
VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to
+125°C
tBBM
QJ
30
54
ns
VS = 0 V
CL = 1 nF, RS = 0 Ω
0.3
Charge injection
pC
VS = –15 V to +15 V
±0.6
Nonadjacent channel
to D, DA, DB
–96
–85
–96
RL = 50 Ω, VS = 1 VRMS
f = 1 MHz
,
Off-isolation
dB
Adjacent channel to
D, DA, DB
Nonadjacent
channels
RL = 50 Ω, VS = 1 VRMS
f = 1 MHz
,
Channel-to-channel crosstalk
dB
Adjacent channels
–88
2.4
7.5
4.3
9.4
6.7
CS(OFF)
CD(OFF)
Input off-capacitance
Output off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
2.9
8.4
5
pF
pF
MUX36S08
MUX36D04
MUX36S08
MUX36D04
10.6
7.7
CS(ON)
,
Output on-capacitance
f = 1 MHz, VS = 0 V
pF
CD(ON)
POWER SUPPLY
45
59
62
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
TA = –40°C to +85°C
VDD supply current
µA
µA
TA = –40°C to
+125°C
83
25
34
37
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
TA = –40°C to +85°C
VSS supply current
TA = –40°C to
+125·C
57
(2) Specified by design, not subject to production testing.
8
Copyright © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
7.6 Electrical Characteristics: Single Supply
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
235
3.1
MAX
UNIT
V
ANALOG SWITCH
Analog signal range
On-resistance
TA = –40°C to +125°C
VS = 10 V, ICH = 1 mA
VSS
VDD
340
390
430
12
RON
TA = –40°C to +85°C
Ω
TA = –40°C to +125°C
ΔRON
On-resistance match
On-resistance drift
Input leakage current
VS = 10 V, ICH = 1 mA
VS = 10 V
TA = –40°C to +85°C
TA = –40°C to +125°C
19
Ω
23
1.13
%/°C
nA
–-0.04
–0.15
–1.9
–0.1
–0.5
–2
0.001
0.04
0.15
1.9
0.1
0.5
2
Switch state is off,
IS(OFF)
ID(OFF)
ID(ON)
VS = 1 V and VD = 10 V,
TA = –40°C to +85°C
TA = –40°C to +125°C
or VS = 10 V and VD = 1 V(1)
0.005
0.008
Switch state is off,
Output off leakage current VS = 1 V and VD = 10 V,
TA = –40°C to +85°C
TA = –40°C to +125°C
nA
nA
or VS = 10 V and VD = 1 V(1)
–0.1
–0.5
–3.3
0.1
0.5
3.3
Switch state is on,
Output on leakage current VD = 1 V and 10 V,
VS = floating
TA = –40°C to +85°C
TA = –40°C to +125°C
LOGIC INPUT
VIH
VIL
ID
Logic voltage high
2.0
V
V
Logic voltage low
Input current
0.8
0.15
µA
SWITCH DYNAMIC CHARACTERISTICS(2)
85
48
87
140
145
149
83
VS = 8 V, RL = 300 Ω,
CL= 35 pF
tON
Enable turn-on time
Enable turn-off time
TA = –40°C to +85°C
TA = –40°C to +125°C
ns
ns
VS = 8 V, RL = 300 Ω,
CL= 35 pF
tOFF
TA = –40°C to +85°C
TA = –40°C to +125°C
94
102
147
VS = 8 V, CL= 35 pF
VS = 8 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +85°C
TA = –40°C to +125°C
153
155
tt
Transition time
ns
VS = 8 V, RL = 300 Ω,
CL= 35 pF
Break-before-make time
delay
tBBM
VS = 8 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C
30
54
ns
VS = 6 V
CL = 1 nF, RS = 0 Ω
0.15
±0.4
-96
-85
–96
-88
2.7
9.1
5
QJ
Charge injection
Off-isolation
pC
VS = 0 V to 12 V,
Nonadjacent channel to D, DA, DB
Adjacent channel to D, DA, DB
Nonadjacent channels
RL = 50 Ω, VS = 1 VRMS
f = 1 MHz
,
,
dB
Channel-to-channel
crosstalk
RL = 50 Ω, VS = 1 VRMS
dB
pF
pF
f = 1 MHz
Adjacent channels
CS(OFF)
CD(OFF)
Input off-capacitance
Output off-capacitance
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
3.2
10
5.7
12
8
MUX36S08
MUX36D04
MUX36S08
MUX36D04
10.8
6.9
CS(ON)
CD(ON)
,
Output on-capacitance
f = 1 MHz, VS = 6 V
pF
(1) When VS is 1 V, VD is 10 V, and vice versa.
(2) Specified by design; not subject to production testing.
Copyright © 2016–2019, Texas Instruments Incorporated
9
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
Electrical Characteristics: Single Supply (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
POWER SUPPLY
42
53
56
77
31
38
51
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
VDD supply current
VSS supply current
TA = –40°C to +85°C
TA = –40°C to +125°C
23
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
TA = –40°C to +85°C
TA = –40°C to +125°C
µA
10
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
7.7 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250
250
200
150
100
50
TA = 125°C
TA = 85°C
VDD = 15 V
VSS = œ15 V
VDD = 13.5 V
VSS = œ13.5 V
200
150
100
50
TA = 25°C
VDD = 18 V
VSS = œ18 V
VDD = 16.5 V
VSS = œ16.5 V
TA = œ40°C
TA = 0°C
0
0
0
5
10
15
20
0
6
12
18
œ20
œ15
œ10
œ5
œ18
œ12
œ6
C002
Source or Drain Voltage (V)
Source or Drain Voltage (V)
C001
VDD = 15 V, VSS = –15 V
图 1. On-Resistance vs Source or Drain Voltage
图 2. On-Resistance vs Source or Drain Voltage
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
VDD = 5 V
VSS = œ5 V
VDD = 6 V
VSS = œ6 V
TA = 85°C
TA = 125°C
TA = 25°C
VDD = 7 V
VSS = œ7 V
TA = 0°C
TA = œ40°C
0
2
4
6
8
0
2
4
6
8
10
12
œ8
œ6
œ4
œ2
C004
C003
Source or Drain Voltage (V)
Source or Drain Voltage (V)
VDD = 12 V, VSS = 0 V
图 3. On-Resistance vs Source or Drain Voltage
图 4. On-Resistance vs Source or Drain Voltage
250
200
150
100
50
700
600
500
400
300
200
100
0
VDD = 10 V
VSS = 0 V
VDD = 30 V
VSS = 0 V
VDD = 12 V
VSS = 0 V
VDD = 14 V
VSS = 0 V
VDD = 36 V
VSS = 0 V
VDD = 33 V
VSS = 0 V
0
0
6
12
18
24
30
36
0
2
4
6
8
10
12
14
C023
Source or Drain Voltage (V)
Source or Drain Voltage (V)
C005
图 5. On-Resistance vs Source or Drain Voltage
图 6. On-Resistance vs Source or Drain Voltage
版权 © 2016–2019, Texas Instruments Incorporated
11
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250
250
200
150
100
50
200
150
100
50
0
0
0
6
12
18
24
0
6
12
œ12
œ6
C024
C029
Source or Drain Voltage (V)
Source or Drain Voltage (V)
VDD = 24 V, VSS = 0 V
VDD = 12 V, VSS = –12 V
图 7. On-Resistance vs Source or Drain Voltage
图 8. On-Resistance vs Source or Drain Voltage
900
600
300
0
900
600
300
0
ID(ON)+
ID(ON)+
IS(OFF)+
ID(OFF)+
ID(OFF)+
IS(OFF)+
IS(OFF)œ
œ300
œ600
œ900
œ300
œ600
œ900
IS(OFF)œ
ID(OFF)œ
ID(OFF)œ
ID(ON)œ
ID(ON)œ
0
25
50
75
100 125 150
0
25
50
75
100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
C006
C007
Temperature (°C)
Temperature (°C)
VDD = 15 V, VSS = –15 V
VDD = 12 V, VSS = 0 V
图 9. Leakage Current vs Temperature
图 10. Leakage Current vs Temperature
2
1
2
1
VDD = 15 V
VSS = œ15 V
VDD = 15 V
VSS = œ15 V
0
0
VDD = 10 V
VSS = œ10 V
VDD = 10 V
VSS = œ10 V
VDD = 12 V
VSS = 0 V
œ1
œ2
œ1
œ2
VDD = 12 V
VSS = 0 V
0
5
10
15
0
5
10
15
œ15
œ10
œ5
œ15
œ10
œ5
C008
C025
Source Voltage (V)
Source Voltage (V)
MUX36S08, source-to-drain
图 11. Charge Injection vs Source Voltage
MUX36D04, source-to-drain
图 12. Charge Injection vs Source Voltage
12
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
9
150
120
90
60
30
0
tON (VDD = 15 V, VSS = œ15 V)
VDD = 15 V
VSS = œ15 V
6
3
tON (VDD = 12 V, VSS = 0 V)
VDD = 10 V
VSS = œ10 V
0
VDD = 12 V
VSS = 0 V
œ3
œ6
œ9
tOFF (VDD = 15 V, VSS = œ15 V)
tOFF (VDD = 12 V, VSS = 0 V)
0
5
10
15
0
25
50
75
100 125 150
œ15
œ10
œ5
œ75 œ50 œ25
C011
Drain voltage (V)
Temperature (°C)
C010
Drain-to-source
图 13. Charge Injection vs Source or Drain Voltage
图 14. Turn-On and Turn-Off Times vs Temperature
0
0
œ20
œ20
Adjacent Channel to D (Output)
Adjacent Channels
œ40
œ60
œ40
œ60
œ80
œ80
œ100
œ120
œ140
œ100
œ120
œ140
Non-Adjacent Channels
Non-Adjacent Channel to D (Output)
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
C013
C012
Frequency (Hz)
Frequency (Hz)
图 15. Off Isolation vs Frequency
图 16. Crosstalk vs Frequency
100
10
3
0
VDD = 5 V
VDD = 15 V
VSS = œ5 V
VSS = œ15 V
1
œ3
œ6
œ9
0.1
0.01
10
100
1k
10k
100k
100k
1M
10M
100M
1G
C014
C018
Frequency (Hz)
Frequency (Hz)
图 17. THD+N vs Frequency
图 18. On Response vs Frequency
版权 © 2016–2019, Texas Instruments Incorporated
13
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
18
18
15
12
9
15
12
CD(ON
)
CD(OFF
)
9
6
3
0
CD(ON
)
6
CD(OFF
)
CS(OFF)
3
CS(OFF)
10
0
0
5
10
15
0
5
15
œ15
œ10
œ5
œ15
œ10
œ5
C026
Source Voltage (V)
C015
Source or Drain Voltage (V)
MUX36S08, VDD = 15 V, VSS = –15 V
图 19. Capacitance vs Source Voltage
MUX36D04, VDD = 15 V, VSS = –15 V
图 20. Capacitance vs Source Voltage
18
15
12
9
18
15
12
9
CD(ON
)
CD(OFF
)
CD(ON
)
6
6
CD(OFF
)
CS(OFF)
3
3
CS(OFF)
25
0
0
0
5
10
15
20
25
30
0
5
10
15
20
30
C016
C028
Source Voltage (V)
Source or Drain Voltage (V)
MUX36S08, VDD = 30 V, VSS = 0 V
MUX36D04, VDD = 30 V, VSS = 0 V
图 22. Capacitance vs Source Voltage
图 21. Capacitance vs Source Voltage
18
15
12
9
18
15
12
9
CD(ON)
CD(OFF
)
CD(ON
)
6
6
CD(OFF)
CS(OFF)
3
3
CS(OFF)
0
0
0
3
6
9
12
0
3
6
Source or Drain Voltage (V)
9
12
C027
Source or Drain Voltage (V)
C022
MUX36S08, VDD = 12 V, VSS = 0 V
MUX36D04, VDD = 12 V, VSS = 0 V
图 24. Capacitance vs Source Voltage
图 23. Capacitance vs Source Voltage
14
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
20
15
10
5
0
œ5
œ10
œ15
œ20
œ25
0
5
10
15
20
25
œ25 œ20 œ15 œ10 œ5
Source Current (mA)
C021
图 25. Source Current vs Drain Current
8 Parameter Measurement Information
8.1 Truth Tables
表 1 and 表 2 show the truth tables for the MUX36S08 and MUX36D04, respectively.
表 1. MUX36S08 Truth Table
EN
0
A2
X(1)
0
A1
X(1)
0
A0
X(1)
0
STATE
All channels are off
Channel 1
1
1
0
0
1
Channel 2
1
0
1
0
Channel 3
1
0
1
1
Channel 4
1
1
0
0
Channel 5
1
1
0
1
Channel 6
1
1
1
0
Channel 7
1
1
1
1
Channel 8
(1) X denotes don't care..
表 2. MUX36D04 Truth Table
EN
0
A1
X(1)
0
A0
X(1)
0
STATE
All channels are off
Channels 1A and 1B
Channels 2A and 2B
Channels 3A and 3B
Channels 4A and 4B
1
1
0
1
1
1
0
1
1
1
(1) X denotes don't care.
版权 © 2016–2019, Texas Instruments Incorporated
15
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
8.2 On-Resistance
The on-resistance of the MUX36xxx is the ohmic resistance across the source (Sx, SxA, or SxB) and drain (D,
DA, or DB) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is
used to denote on-resistance. The measurement setup used to measure RON is shown in 图 26. Voltage (V) and
current (ICH) are measured using this setup, and RON is computed as shown in 公式 1:
V
S
D
ICH
VS
图 26. On-Resistance Measurement Setup
RON = V / ICH
(1)
8.3 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 27
Is (OFF)
ID (OFF)
A
S
D
A
VS
VD
图 27. Off-Leakage Measurement Setup
16
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
8.4 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. 图 28 shows the circuit used for measuring
the on-leakage current, denoted by ID(ON)
.
ID (ON)
A
S
D
NC
NC = No Connection
VD
图 28. On-Leakage Measurement Setup
8.5 Differential On-Leakage Current
In case of a differential signal, the on-leakage current is defined as the differential leakage current that flows into
or out of the drain pins when the switches is in the on state. The source pins are left floating during the
measurement. 图 29 shows the circuit used for measuring the on-leakage current on each signal path, denoted
by IDA(ON) and IDB(ON). The absolute difference between these two current is defined as the differential on-leakage
current IDL(ON)
.
IDA(ON)
A
SxA
DA
NC
IDB(ON)
A
DB
SxB
NC
VD
NC = No Connection
图 29. Differential On-Leakage Measurement Setup
版权 © 2016–2019, Texas Instruments Incorporated
17
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
8.6 Transition Time
Transition time is defined as the time taken by the output of the MUX36xxx to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to 50% of the transition. 图 30 shows the setup used to
measure transition time, denoted by the symbol tt.
VDD
VSS
3 V
VDD
VSS
Address
Signal (VIN
50%
50%
)
S1
VS1
A0
A1
A2
0 V
S2-S7
S8
VIN
tt
tt
VS8
VS1
90%
Output
MUX36S08
Output
EN
D
2 V
GND
300 Ω
35 pF
90%
VS8
图 30. Transition-Time Measurement Setup
8.7 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the MUX36xxx is
switching. The MUX36xxx output first breaks from the on-state switch before making the connection with the next
on-state switch. The time delay between the break and the make is known as break-before-make delay. 图 31
shows the setup used to measure break-before-make delay, denoted by the symbol tBBM
.
VDD
VSS
3 V
VSS
VDD
Address
Signal (VIN
)
S1
VS
A0
A1
A2
0 V
S2-S7
S8
VIN
Output
MUX36S08
80%
80%
Output
2 V
EN
D
GND
300 Ω
35 pF
tBBM
图 31. Break-Before-Make Delay Measurement Setup
18
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
8.8 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the MUX36xxx to rise to a 90% final value after the
enable signal has risen to a 50% final value. 图 32 shows the setup used to measure turn-on time. Turn-on time
is denoted by the symbol tON
.
Turn off time is defined as the time taken by the output of the MUX36xxx to fall to a 10% initial value after the
enable signal has fallen to a 50% initial value. 图 32 shows the setup used to measure turn-off time. Turn-off time
is denoted by the symbol tOFF
.
VDD
VSS
3 V
VDD
VSS
Enable
Drive (VIN)
50%
50%
S1
VS
A0
A1
A2
S2-S8
0 V
tOFF (EN)
MUX36S08
tON (EN)
0.9 VS
Output
Output
EN
D
GND
300 Ω
35 pF
0.1 VS
VIN
图 32. Turn-On and Turn-Off Time Measurement Setup
版权 © 2016–2019, Texas Instruments Incorporated
19
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
8.9 Charge Injection
The MUX36xxx have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QINJ. 图 33 shows the setup used to measure charge injection.
VSS
VDD
VDD
VSS
A0
A1
A2
3 V
VEN
MUX36S08
0 V
RS
S
D
VOUT
EN
VOUT
CL
1 nF
VOUT
VS
GND
QINJ = CL ×
VOUT
VEN
图 33. Charge-Injection Measurement Setup
20
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
8.10 Off Isolation
Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX36xxx when a 1-VRMS signal is
applied to the source pin (Sx, SxA, or SxB) of an off-channel. 图 34 shows the setup used to measure off
isolation. Use 公式 2 to compute off isolation.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VSS
VDD
50 ꢀ
S
50 Ω
VS
D
VOUT
RL
50 Ω
GND
图 34. Off Isolation Measurement Setup
≈
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
∆
«
(2)
8.11 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx, SxA, or SxB) of an off-channel,
when a 1-VRMS signal is applied at the source pin of an on-channel. 图 35 shows the setup used to measure, and
公式 3 is the equation used to compute, channel-to-channel crosstalk.
VDD
VSS
0.1 µF
0.1 µF
VSS
VDD
Network Analyzer
VOUT
S1
RL
50 Ω
R
S2
50 Ω
VS
GND
图 35. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(3)
21
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
8.12 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin of an on-channel, and the output is measured at the drain pin of the MUX36xxx. 图 36 shows the
setup used to measure bandwidth of the mux. Use 公式 4 to compute the attenuation.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VSS
VDD
V1
50 ꢀ
S
VS
V2
D
VOUT
RL
50 Ω
GND
图 36. Bandwidth Measurement Setup
≈
∆
«
’
÷
◊
V2
Attenuation = 20 ∂ Log
V
1
(4)
8.13 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the MUX36xxx varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N. 图 37 shows the setup used to measure THD+N of the MUX36xxx.
VDD
VSS
0.1 µF
0.1 µF
Audio Precision
VSS
VDD
RS
S
IN
VS
D
5 VRMS
VIN
VOUT
RL
10 kΩ
GND
图 37. THD+N Measurement Setup
22
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
9 Detailed Description
9.1 Overview
The MUX36xxx are a family of analog multiplexers. The Functional Block Diagram section provides a top-level
block diagram of both the MUX36S08 and MUX36D04. The MUX36S08 is an 8-channel, single-ended, analog
mux. The MUX36D04 is a 4-channel, differential or dual 4:1, single-ended, analog mux. Each channel is turned
on or turned off based on the state of the address lines and enable pin.
9.2 Functional Block Diagram
MUX36D04
MUX36S08
S1
S2
S3
S4
S5
S6
S7
S8
S1A
S2A
S3A
S4A
S1B
S2B
S3B
S4B
DA
DB
D
1-of-4
1-of-8
Decoder
Decoder
A0
A1
EN
A0
A1
A2
EN
版权 © 2016–2019, Texas Instruments Incorporated
23
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
9.3 Feature Description
9.3.1 Ultralow Leakage Current
The MUX36xxx provide extremely low on- and off-leakage currents. The MUX36xxx are capable of switching
signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error
because of the ultralow leakage currents. 图 38 shows typical leakage currents of the MUX36xxx versus
temperature.
900
ID(ON)+
600
300
0
ID(OFF)+
IS(OFF)+
IS(OFF)œ
œ300
ID(OFF)œ
œ600
ID(ON)œ
œ900
0
25
50
75
100 125 150
œ75 œ50 œ25
C006
Temperature (°C)
图 38. Leakage Current vs Temperature
9.3.2 Ultralow Charge Injection
The MUX36xxx have a simple transmission gate topology, as shown in 图 39. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
图 39. Transmission Gate Topology
24
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
Feature Description (接下页)
The MUX36xxx have special charge-injection cancellation circuitry that reduces the source-to-drain charge
injection to as low as 0.3 pC at VS = 0 V, and ±0.6 pC in the full signal range, as shown in 图 40.
2
1
0
VDD = 15 V
VSS = œ15 V
VDD = 10 V
VSS = œ10 V
œ1
œ2
VDD = 12 V
VSS = 0 V
0
5
10
15
œ15
œ10
œ5
C025
Source Voltage (V)
图 40. Source-to-Drain Charge Injection vs Source or Drain Voltage
The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux),
where D becomes the input and Sx becomes the output. 图 41 shows the drain-to-source charge injection across
the full signal range.
9
VDD = 15 V
VSS = œ15 V
6
3
VDD = 10 V
VSS = œ10 V
0
VDD = 12 V
VSS = 0 V
œ3
œ6
œ9
0
5
10
15
œ15
œ10
œ5
C011
Drain voltage (V)
图 41. Drain-to-Source Charge Injection vs Source or Drain Voltage
9.3.3 Bidirectional Operation
The MUX36xxx are operable as both a mux and demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins
of the MUX36xxx are used either as input or output. Each MUX36xxx channel has very similar characteristics in
both directions.
版权 © 2016–2019, Texas Instruments Incorporated
25
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
Feature Description (接下页)
9.3.4 Rail-to-Rail Operation
The valid analog signal for the MUX36xxx ranges from VSS to VDD. The input signal to the MUX36xxx swings
from VSS to VDD without any significant degradation in performance. The on-resistance of the MUX36xxx varies
with input signal, as shown in 图 42
250
VDD = 15 V
VSS = œ15 V
VDD = 13.5 V
VSS = œ13.5 V
200
150
100
50
VDD = 18 V
VSS = œ18 V
VDD = 16.5 V
VSS = œ16.5 V
0
0
5
10
15
20
œ20
œ15
œ10
œ5
Source or Drain Voltage (V)
C001
图 42. On-Resistance vs Source or Drain Voltage
9.4 Device Functional Modes
When the EN pin of the MUX36xxx is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the
address lines. The EN pin can be connected to VDD (as high as 36 V).
26
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The MUX36xxx family offers outstanding input/output leakage currents and ultralow charge injection. These
devices operate up to 36 V, and offer true rail-to-rail input and output. The on-capacitance of the MUX36xxx is
very low. These features makes the MUX36xxx a family of precision, robust, high-performance analog
multiplexer for high-voltage, industrial applications.
10.2 Typical Application
图 43 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential mux. This TI Precision
Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the MUX36D04,
OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
Analog Inputs
REF3140
RC Filter
OPA350
RC Filter
Bridge Sensor
Thermocouple
Reference Driver
Gain Network
Gain Network
OPA192
+
REF
+
OPA140
VINP
Charge
Kickback
Filter
Gain Network
OPA192
+
ADS8864
Current Sensing
Photo
VINM
Detector
LED
High-Voltage Multiplexed Input
High-Voltage Level Translation
VCM
Optical Sensor
图 43. 16-Bit Precision Multiplexed Data-Acquisition System for High-Voltage Inputs With Lowest
Distortion
版权 © 2016–2019, Texas Instruments Incorporated
27
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
Typical Application (接下页)
10.2.1 Design Requirements
The primary objective is to design a ±20 V, differential, 4-channel, multiplexed, data-acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave
input. The design requirements for this block design are:
•
•
•
•
•
System supply voltage: ±15 V
ADC supply voltage: 3.3 V
ADC sampling rate: 400 kSPS
ADC reference voltage (REFP): 4.096 V
System input signal: A high-voltage differential input signal with a peak amplitude of 20 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
10.2.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system
for highest system linearity and fast settling. The overall system block diagram is illustrated in 图 43. The circuit
is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output buffer,
attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple channels
using a single ADC, providing a low-cost solution. This design systematically approaches each analog circuit
block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input
signal at each input channel.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition
System for High-Voltage Inputs with Lowest Distortion.
10.2.3 Application Curve
1.0
0.8
0.6
0.4
0.2
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
0
5
10
15
20
œ20
œ15
œ10
œ5
C030
ADC Differential Peak-to-Peak Input (V)
图 44. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block
28
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
11 Power Supply Recommendations
The MUX36xxx operates across a wide supply range of ±5 V to ±18 V (10 V to 36 V in single-supply mode).
They also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable operation, use
a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to ground.
The on-resistance of the MUX36xxx varies with supply voltage, as illustrated in 图 45
250
VDD = 15 V
VSS = œ15 V
VDD = 13.5 V
VSS = œ13.5 V
200
150
100
50
VDD = 18 V
VSS = œ18 V
VDD = 16.5 V
VSS = œ16.5 V
0
0
5
10
15
20
œ20
œ15
œ10
œ5
Source or Drain Voltage (V)
C001
图 45. On-Resistance Variation With Supply and Input Voltage
版权 © 2016–2019, Texas Instruments Incorporated
29
MUX36S08, MUX36D04
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
图 46 illustrates an example of a PCB layout with the MUX36S08IPW, and 图 47 illustrates an example of a PCB
layout with MUX36D04IPW.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible. In case of the differential signal, make sure the A inputs and B
inputs are as symmetric as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
12.2 Layout Example
Via to
ground plane
Via to
ground plane
AO
EN
A1
A2
C
C
GND
VDD
VSS
S1
S2
MUX36S08IPW
S5
S3
S4
S6
S7
D
S8
图 46. MUX36S08IPW Layout Example
Via to
ground plane
Via to
ground plane
Via to
ground plane
AO
EN
A1
C
C
GND
VDD
VSS
S1B
S1A
S2A
S3A
S4A
MUX36D04IPW
S2B
S3B
S4B
DB
DA
图 47. MUX36D04IPW Layout Example
30
版权 © 2016–2019, Texas Instruments Incorporated
MUX36S08, MUX36D04
www.ti.com.cn
ZHCSEI0D –JANUARY 2016–REVISED FEBURARY 2019
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
•
•
•
《支持双极输入范围的 ADS8664 12 位、500kSPS、4 通道和 8 通道单电源 SAR ADC》(SBAS492)
《OPA140 高精度、低噪声、轨至轨输出、11MHz JFET 运算放大器》(SBOS498)
《采用 e-Trim™ 技术的 OPA192 36V、轨至轨输入/输出、低失调电压、低输入偏置电流运算放大器》
(SBOS620)
13.2 相关链接
表 3 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品的快速链
接。
表 3. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
MUX36S08
MUX36D04
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2019, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MUX36D04IPW
MUX36D04IPWR
MUX36D04IRRJR
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
WQFN
PW
PW
16
16
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
MUXD04C
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
MUXD04C
RRJ
MUX
36D04
MUX36D04IRUMR
ACTIVE
WQFN
RUM
16
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX
36D04
MUX36S08IPW
MUX36S08IPWR
MUX36S08IRRJR
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
WQFN
PW
PW
16
16
16
90
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
MUXS08B
2000 RoHS & Green
3000 RoHS & Green
MUXS08B
RRJ
MUX
36S08
MUX36S08IRUMR
ACTIVE
WQFN
RUM
16
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX
36S08
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MUX36D04IPWR
MUX36D04IRRJR
MUX36D04IRUMR
MUX36S08IPWR
MUX36S08IRRJR
MUX36S08IRUMR
TSSOP
WQFN
WQFN
TSSOP
WQFN
WQFN
PW
RRJ
RUM
PW
16
16
16
16
16
16
2000
3000
3000
2000
3000
3000
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
6.9
4.25
4.25
6.9
5.6
4.25
4.25
5.6
1.6
1.15
1.15
1.6
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q2
Q2
Q1
Q2
Q2
RRJ
RUM
4.25
4.25
4.25
4.25
1.15
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MUX36D04IPWR
MUX36D04IRRJR
MUX36D04IRUMR
MUX36S08IPWR
MUX36S08IRRJR
MUX36S08IRUMR
TSSOP
WQFN
WQFN
TSSOP
WQFN
WQFN
PW
RRJ
RUM
PW
16
16
16
16
16
16
2000
3000
3000
2000
3000
3000
356.0
367.0
367.0
356.0
367.0
367.0
356.0
367.0
367.0
356.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
RRJ
RUM
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MUX36D04IPW
MUX36S08IPW
PW
PW
TSSOP
TSSOP
16
16
90
90
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
RRJ0016A
WQFN - 0.8 mm max height
C
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.95
SYMM
(0.1) TYP
5
8
EXPOSED
THERMAL PAD
Min 0.25
4
9
2X 1.95
SYMM
17
2.1 0.1
12X 0.65
1
12
0.35
0.25
PIN 1 ID
16X
13
16
0.1
C A B
0.7
0.5
16X
0.05
4224485/A 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RRJ0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(o2.1)
SYMM
16
13
SEE SOLDER MASK
DETAIL
16X (0.8)
12
1
16X (0.3)
17
SYMM
(3.6)
12X (0.65)
(0.8)
4
9
(R0.05) TYP
5
8
(0.8)
(Ø0.2) TYP
(3.6)
VIA
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224485/A 08/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RRJ0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.57) TYP
13
16
16X (0.8)
1
12
16X (0.3)
(0.57) TYP
(3.6)
12X (0.65)
SYMM
4X (o0.94)
4
9
(R0.05) TYP
EXPOSED METAL
17
8
5
SYMM
(3.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224485/A 08/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RUM 16
4 x 4, 0.65 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224843/A
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明