O9039A387IZWSRQ1_技术文档

Support &

Community

Reference

Design

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

TPS65903x-Q1 汽车处理器电源管理单元 (PMU)

1 器件概要

1.1 特性

1

时钟同步

• 11 个通用低压降稳压器 (LDO)（阶跃为 50mV）：

• 符合汽车类应用的要求

– 具有符合 AEC-Q100 标准的下列特性：

– 温度等级 3：-40°C 至 85°C

– 静电放电 (ESD) 分类：

– 其中四个 LDO 输出为 0.9V-3.3V@300mA，由经

过预稳压的电源供电

– 其中四个 LDO 输出为 0.9V-3.3V@200mA，由经

过预稳压的电源供电

–

人体放电模型 (HBM) 等级 2

CDM 等级 C3

– 其中一个 LDO 输出为 0.9V-3.3V@50mA，由经

过预稳压的电源供电

– 闩锁分类：

–

I²C 和 SPI 引脚：等级 IIB

其他所有引脚：等级 IIA

– 一个 100mA 通用串行总线 (USB) LDO

– 其中一个 LDO 为低噪声 LDO，输出电压为 0.9V

至 3.3V，输出电流高达 100mA（低噪声性能高

达 50mA）

– 两个供 PMU 内部使用的附加 LDO

– 短路保护

• 七个降压开关模式电源 (SMPS) 稳压器：

– 其中一个输出为 0.7V-1.65V/6A（阶跃为

10mV）

– 支持数字电压调节 (DVS) 控制的双相配置

– 其中一个输出为 0.7V-1.65V/4A（阶跃为

10mV）

– 支持 DVS 控制的双相配置

– 其中一个输出为 0.7V-3.3V/3A（阶跃为 10mV 或

20mV）

• 时钟管理 16MHz 晶体振荡器和 32kHz RC 振荡器

– 一个缓冲式 32kHz 输出

• 具有警报唤醒机制的实时时钟 (RTC)

• 具有三个外部输入通道和六个自监控内部通道的 12

位 Σ-Δ 通用模数转换器 (GPADC)

• 过热监控

– 高温警告

– 热关断

• 控制

– 单相配置

– 该稳压器可搭配 1 个 6A 稳压器构成 1 个 9A

三相稳压器（通过 DVS 控制）

– 其中两个输出为 0.7V-3.3V/2A（阶跃为 10mV 或

20mV）

– 可配置上电和断电序列（一次性可编程 [OTP]）

– 睡眠和激活状态之间的可配置序列（OTP 可编

程）

– 单相配置

– 一个支持 DVS 控制的稳压器，也可配置为 3A

稳压器

– 一个可包含在启动序列中的专用数字输出信号

– 其中两个输出为 0.7V-3.3V/1A（阶跃为 10mV 或

20mV）

– 单相配置

– 一个支持 DVS 控制的稳压器

– 除 1A SMPS 稳压器外的所有稳压器均支持输出

电流测量

(REGEN)

– 三个与 GPIO 复用且可包含在启动序列中的数字

输出信号

– 可选控制接口

– 一个用于资源配置和 DVS 控制的串行外设接

口 (SPI)

– 两个 I²C 接口。其中一个专用于 DVS 控制，

另一个是用于资源配置和 DVS 控制的通用 I²C

接口

– 双相和三相稳压器均支持差分遥感（输出和接

地）

– 通过硬件和软件控制的 ECO 模式™高达 5mA，

静态电流为 15µA

– 短路保护

– 电源正常指示（电压和过流指示）

– 内部软启动可限制浪涌电流

– 可通过相位同步将 SMPS 与外部时钟或内部备用

• 欠压锁定

• 系统电压范围为 3.135V 至 5.25V

• 封装选项

– 12mm × 12mm、169 引脚 nFBGA 封装，焊球间

距为 0.8mm

1.2 应用

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWCS095

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

•

汽车信息娱乐系统

汽车数字集群

•

汽车传感器融合

可编程逻辑控制器

1.3 描述

TPS659038-Q1 和 TPS659039-Q1 器件是适用于汽车应用的电源管理集成电路 (PMIC)。该器件提供七个

可配置的降压转换器，输出电流高达 6A，可用于存储器、处理器内核、输入/输出 (I/O) 或 LDO 预稳压。其

中一个可配置的降压转换器与另一个 3A 稳压器组合后可提供高达 9A 的输出电流。所有降压转换器均可与

频率介于 1.7MHz 至 2.7MHz 之间的外部时钟或频率为 2.2MHz 的内部回退时钟同步。TPS659038-Q1 器件

包含 11 个 LDO 稳压器，而 TPS659039-Q1 器件包含 6 个 LDO 稳压器供外部使用。这些 LDO 稳压器可由

系统电源或经过预稳压的电源供电。上电和断电控制器可进行配置，能够支持所有上电和断电序列（基于

OTP）。TPS659038-Q1 和 TPS659039-Q1 器件包括 32kHz RC 振荡器，可在上电和断电过程中对所有资

源进行排序。在需要快速启动的情况下，也可使用 16MHz 晶体振荡器来快速为系统产生一个稳定的 32kHz

频率。所有 LDO 和 SMPS 转换器均可由 SPI 或 I²C 接口或通过电源请求信号进行控制。此外，电压调节寄

存器允许将 SMPS 转换为 SPI、I²C 或顶部/底部控制所需的不同电压。每种封装中都有一个专用引脚可配置

为上电序列的一部分，用于控制外部资源。该器件具备通用输入输出 (GPIO) 功能，两个 GPIO 均可配置为

上电序列的一部分，用于控制外部资源。电源请求信号通过启用电源模式控制功能来实现电源优化。该器件

具有一个带有三条外部输入通道的通用 (GP) ∑-Δ 模数转换器 (ADC)。TPS659038-Q1 和 TPS659039-Q1

器件采用间距为 0.8mm 的 13 焊球 × 13 焊球 nFBGA 封装。

器件信息⁽¹⁾

封装

器件型号

封装尺寸（标称值）

12.00mm × 12.00mm

TPS659038-Q1

TPS659039-Q1

ZWS (169)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

2

器件概要

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

1.4 简化方框图

TPS659038-Q1

TPS659039-Q1

LDO1

300 mA

SMPS12

0.7 to 1.6 V,

10-mV step, 6 A

Programmable Power

Sequencer Controller

LDO2

300 mA

Dual Phase or

Triple Phase

ECO

PWM

DVS

LDO3

300 mA

SMPS3

0.7 to 1.6 V,

10-mV step

1 to 3.3 V,

Switch On or OFF

TPS659038-Q1 Only

20-mV step, 3 A

LDO4

300 mA

OTP Controller

LDO5

200 mA

SMPS45

0.7 to 1.6 V,

10-mV step, 4 A

OTP Registers

Registers

LDO6

200 mA

Dual Phase or

Triple Phase

LDO7

SMPS7

0.7 to 1.6 V,

10-mV step

1 to 3.3 V,

200 mA

LDO8

170 mA

Watchdog

20-mV step, 2 A

SMPS6

0.7 to 1.6 V,

10-mV step

Thermal Monitoring

and Shutdown

LDO9

50 mA

1 to 3.3 V,

20-mV step, 2 or 3 A

LDOLN

50 mA

Power Good Monitor

VSYS Monitor

SMPS8

0.7 to 1.6 V,

10-mV step

1 to 3.3-V,

LDOUSB

100 mA

20-mV step, 1 A

SMPS9

0.7 to 1.6 V,

10-mV step

1 to 3.3 V,

LDOVRTC

25 mA

20-mV step, 1 A

2

12-Bit GPADC

with 3 External

Channels

Reference and Bias

RTC

2x I C or 1x SPI

PLL for external

SyncClk

16-MHz XTAL

8x GPIO

器件概要

3

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

内容

1

器件概要.................................................... 1

1.1 特性 ................................................... 1

1.2 应用 ................................................... 1

1.3 描述 ................................................... 2

1.4 简化方框图............................................ 3

修订历史记录............................................... 4

Device Comparison ..................................... 8

Pin Configuration and Functions..................... 9

4.1 Pin Functions ......................................... 9

5.15 Electrical Characteristics: Current Consumption.... 28

5.16 Electrical Characteristics: Digital Input Signal

Parameters .......................................... 29

5.17 Electrical Characteristics: Digital Output Signal

Parameters .......................................... 29

5.18 Electrical Characteristics: I/O Pullup and Pulldown

Resistance .......................................... 31

2

3

4

5.19 I²C Interface Timing Requirements ................. 32

5.20 SPI Timing Requirements........................... 33

5.21 Typical Characteristics .............................. 35

Detailed Description ................................... 37

6.1 Overview ............................................ 37

6.2 Functional Block Diagrams.......................... 38

6.3 Feature Description ................................. 39

6.4 Device Functional Modes ........................... 66

Application and Implementation .................... 83

7.1 Application Information.............................. 83

7.2 Typical Application .................................. 83

Power Supply Recommendations .................. 94

Layout .................................................... 94

9.1 Layout Guidelines ................................... 94

9.2 Layout Example ..................................... 98

4.2

Device Ball Mapping – 13 × 13 nFBGA, 169 Balls,

6

7

0,8-mm Pitch ........................................ 14

4.3 Signal Descriptions.................................. 16

Specifications ........................................... 18

5.1 Absolute Maximum Ratings......................... 18

5.2 ESD Ratings ........................................ 18

5.3 Recommended Operating Conditions............... 19

5.4 Thermal Information................................. 19

5

5.5

5.6

5.7

Electrical Characteristics: Latch Up Rating ......... 19

Electrical Characteristics: LDO Regulator .......... 20

8

9

Electrical Characteristics: Dual-Phase (SMPS12

and SMPS45) and Triple-Phase (SMPS123 and

SMPS457) Regulators .............................. 22

5.8

5.9

Electrical Characteristics: Stand-Alone Regulators

(SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9).. 23

Electrical Characteristics: Reference Generator

10 器件和文档支持......................................... 101

10.1 器件支持 ........................................... 101

10.2 文档支持 ........................................... 101

10.3 相关链接 ........................................... 101

10.4 接收文档更新通知.................................. 101

10.5 社区资源 ........................................... 102

10.6 商标 ................................................ 102

10.7 静电放电警告....................................... 102

10.8 Glossary............................................ 102

11 机械、封装和可订购信息.............................. 102

11.1 封装材料信息....................................... 102

(Bandgap) ........................................... 25

5.10 Electrical Characteristics: 16-MHz Crystal Oscillator,

32-kHz RC Oscillator, and Output Buffers .......... 25

5.11 Electrical Characteristics: DC-DC Clock Sync ...... 26

5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC. 26

5.13 Electrical Characteristics: Thermal Monitoring and

Shutdown............................................ 28

5.14 Electrical Characteristics: System Control

Thresholds .......................................... 28

2 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision K (January 2018) to Revision L

Page

•

将 ESD 分类从 C4B 改为 C3 ....................................................................................................... 1

Updated the LDOVRTC_OUT pulldown resistor recommendation to only include applicable silicon revisions. ....... 11

Changed ESD Ratings for charge device model on 6 pins ................................................................... 18

Clarified that LDO1 and LDO2 input pins are not included in this minimum recommended operating voltage. See

Electrical Characteristics: LDO Regulators for more information. ............................................................ 19

Changed minimum recommended operating condition of OSC16MIN from 0V to -0.7V ................................. 19

Added LDO and SMPS output capacitance footnote .......................................................................... 20

Changed VSYS_LO hysteresis from 95mV to 75mV........................................................................... 28

Updated Caution statement to only include applicable silicon revisions. ................................................... 37

Changed discharge resistance to match electrical characteristics table .................................................... 40

Added information about shutdown timing during short circuit detection ................................................... 43

Updated POWERGOOD description to clarify multi-phase operation. ...................................................... 43

Updated LDOVRTC note to only include applicable silicon revisions. ....................................................... 48

Added details on identifying device version...................................................................................... 66

Added typical debounce time from POWERHOLD to the enable of the first rail in the power sequence. .............. 69

•

4

修订历史记录

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

•

Added VSYS_LO note for applicable silicon revisions. ........................................................................ 79

Updated POR requirements to only include applicable silicon revisions. ................................................... 81

SMPS and LDO output capacitance specification further explained ......................................................... 88

Added design considerations for VCC1 capacitance to support loss of power ............................................. 88

Corrected 9-Vpp with 7V absolute maximum specification in the Layout Guidelines section............................. 94

Updated requirements relating to measurement of high-side and low-side FETs in the Layout Guidelines section... 96

Updated images and description on differential measurements across high-side and low-side FETs .................. 97

Changes from Revision J (March 2017) to Revision K

Page

•

Removed pullup and pulldown from BOOT0 pin description .................................................................. 16

Deleted the nominal T_stgvalue (27°C) from the Absolute Maximum Ratings table......................................... 18

Deleted the voltage mode to the I/O digital supply voltage, VIO_IN parameter from the Recommended

Operating Conditions table......................................................................................................... 19

Deleted the voltage on the VCC1 GPADC pins (TBC) parameter from the Recommended Operating Conditions

table................................................................................................................................... 19

Added 2-A mode for SMPS6 in the test conditions for high-side and low-side MOSFET forward current limit and

low-side MOSFET negative current limit in the Electrical Characteristics: Stand-Alone Regulators (SMPS3,

SMPS6, SMPS7, SMPS8, and SMPS9) table................................................................................... 24

已添加 the number of active SMPS phases (K) to the equation for the temperature compensated result in the

Current Monitoring and Short Circuit Detection section........................................................................ 43

已添加 additional description of SMPS short detection and recovery behavior............................................. 43

已添加 equation to convert GPADC code to internal die temperature ....................................................... 52

已添加 description of VIO power-up timing, and updated start up timing diagram ......................................... 73

已添加 additional description of VSYS_LO functionality ....................................................................... 79

Added link to application note about POR generation.......................................................................... 81

•

Changes from Revision I (June 2016) to Revision J

Page

•

首次公开发布数据表 .................................................................................................................. 2

Added recommendation for external pulldown resistor on the LDOVRTC_OUT pin in the Pin Functions table........ 11

已更改 the description of the LDOVRTC when in the BACKUP and OFF states and added a note in the

LDOVRTC section .................................................................................................................. 47

已添加 the note and pulldown equations to the System Voltage Monitoring section....................................... 81

•

Changes from Revision H (October 2015) to Revision I

Page

•

Changed the typical value for the Channel 11 SMPS output current measurement gain factor parameter in the

12-Bit Sigma-Delta ADC table..................................................................................................... 27

Changed the typical value for the channel 11 SMPS output current measurement current offset parameter in the

12-Bit Sigma-Delta ADC table..................................................................................................... 27

Updated part numbers and settings for released devices in the Design Parameters table ............................... 86

Changes from Revision G (October 2015) to Revision H

Page

•

Added DC accuracy spec for LDO3 and LDO4 when I_O= 300 mA, which is the new I_Omax from the previous

revision ............................................................................................................................... 20

Added V_DROPOUTspec for LDO3 and LDO4 when I_O= 300 mA, which is the new I_Omax from the previous revision.. 20

Added DC Load Regulation spec for LDO3 and LDO4 when I_O= 300 mA, which is the new I_Omax from the

previous revision .................................................................................................................... 21

Updated PSRR spec for LDO3 and LDO4 when I_O= 300 mA, which is the new I_Omax from the previous revision .. 21

Added DC Load Transient spec for LDO3 and LDO4 when I_O= 300 mA, which is the new I_Omax from the

previous revision .................................................................................................................... 21

Updated the current capability of LDO3 and LDO4 from 200 mA to 300 mA throughout the specification ............ 39

•

修订历史记录

5

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Changes from Revision F (February 2015) to Revision G

Page

•

Updated the functional block diagram by removing the external connections and combining both 38/39 devices

in one diagram. ...................................................................................................................... 38

Added caution statement for operating the GPADC in SW mode. ........................................................... 53

Updated the component numbering in the Typical Applications Diagrams to align with EVM schematics and 表

7-2 ................................................................................................................................... 85

Added description of OSC16M_CFG OTP bit, and the required setting of this bit in relation to the presence of a

16-MHz crystal for proper device function........................................................................................ 91

•

Changes from Revision E (December 2014) to Revision F

Page

•

已更改 the DVS-Capable Regulators section; the slew rate of the output voltage is fixed at 2.5 mV/µs................ 45

Updated the Design Requirements section ..................................................................................... 86

已更改 the REFERENCE COMPONENT numbers in the Recommended External Components for Automotive

Usage table ......................................................................................................................... 87

已删除 the Recommended External Components for Commercial Usage table from the Typical Application

section ............................................................................................................................... 87

已更改 the body size for CX8045GB16384H0HEQZ1 in the Recommended External Components for

•

Automotive Usage table ............................................................................................................ 87

已删除 the GPADC EXTERNAL COMPONENTS from the Recommended External Components for Automotive

Usage table .......................................................................................................................... 87

Changes from Revision D (October 2014) to Revision E

Page

•

Added caution statement to the Specifications section ........................................................................ 18

已添加 caution statement to the Specifications section ....................................................................... 37

Changes from Revision C (June 2014) to Revision D

Page

•

已删除出口管制提示（通篇） ...................................................................................................... 2

Removed all notions of (3.6V tolerance) from VRTC digital pins without fail-safe feature ................................ 17

Changed Replaced LDOVRTC_max+ 0.3 notion with actual value of 2.15 under the ABS Max Rating table for

VRTC digital input pins ............................................................................................................. 18

Changed Replaced LDOVRTC_maxnotion with actual value of 1.85 under the ROC table for OSC16MIN and

VRTC digital input pins ............................................................................................................. 19

Updated typical IQ(on) value of LDOUSB-IN1 from 30µA to 45µA in accordance with characterization data ......... 21

Added Caution clause to describe the scenario which may cause unexpected shutdown of the PLL, and the

actions to recover from such fault condition. .................................................................................... 72

Added comments for the ideal SMPS voltage-spike measurement condition under Layout Guidance section. ....... 96

•

Changes from Revision B (June 2014) to Revision C

Page

•

Updated Latch Up Current Class specification format and separated LDOVANA_OUT pin specification from all

other pins............................................................................................................................. 19

Updated typical value of high-side FET r_DS(on)from 50mΩ to 115mΩ for all multi-phase SMPSs ....................... 22

Updated typical value of low-side FET r_DS(on)from 39mΩ to 30mΩ for all multi-phase SMPSs .......................... 22

Updated typical value of High-side FET r_DS(on)from 50mΩ to 115mΩ for all single-phase SMPSs except SMPS 8

& 9 .................................................................................................................................... 24

Updated typical value of high-side FET r_DS(on)from 110mΩ to 180mΩ for SMPS8 & 9 ................................... 24

Updated typical value of low-side FET r_DS(on)from 39mΩ to 30mΩ for all single-phase SMPSs except SMPS 8 &

9 ...................................................................................................................................... 24

Updated the typical value of CLK32KGO output buffer rise and fall time based on characterization data. ............ 25

Updated the min and max value of CLK32KGO1V8 output buffer rise and fall time based on simulation data. ...... 25

Added comments on limitation of Vout/Vin ratio and Vin monitor and shut down mechanism when a SMPS

converter is in ECO mode.......................................................................................................... 40

•

6

修订历史记录

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Changes from Revision A (May 2014) to Revision B

Page

•

Corrected the default state of the NSLEEP pin to PPU under Pin Function table.......................................... 12

Corrected the voltage range for the GPADC_IN0 and GPADC_IN1 pins under the Recommended Operating

Conditions table ..................................................................................................................... 19

Reduced minimum output inductance to -30% of the recommended value of 1µH for SMPSs in multi-phase

configuration ......................................................................................................................... 22

Reduced minimum output inductance to -30% of the recommended value of 1µH for SMPSs in single-phase

configuration ......................................................................................................................... 23

Added device Current Consumption specification for Sleep Mode when VSYS = 5.25V ................................. 28

Added paragraph with regards to the importance of VSYS being the first supply available to the device. ............ 39

Added approximate power rail shut down time from a short detection....................................................... 43

Added approximate wait time for the device to reach OFF state from No Supply state. .................................. 67

Added a paragraph under the Application Information section to emphasize the importance of operating the

device under ROC, and encourage customers to consider thermal management, power sequencing and layout

strategy to maximize device performance........................................................................................ 83

•

Changes from Original (April 2014) to Revision A

Page

•

Added option to float the VPROG pin when it is configured as an input pin ............................................... 12

Updated Output Type of I2C2_SDA_SDO pin to specify Push-pull type when the pin is configured in SPI mode .... 17

Corrected the minimum voltage level for all SMPS-related input pins to match VSYS minimum input level in

Recommended Operating Conditions ........................................................................................... 19

Moved Latch Up Current Classification table out of the Handling Ratings table............................................ 19

Corrected editing error which added an invalid Ripple spec for LDO1 & LDO2 ............................................ 22

Updated the maximum specification of device Current Consumption in OFF Mode from 30 µA to 45 µA ............. 28

Updated the definition and test condition of the device Current Consumption in SLEEP mode from having only

SMPS6 and SMPS8 enabled to having only LDO2 and LDO9 enabled. Also updated the typical and maximum

specifications to associate with the new definition. ............................................................................. 28

Added the specific description that SDO line defaults to high impedance when the pin is configured as SPI

mode. ................................................................................................................................ 64

Corrected the recommended part number for the Crystal decoupling caps in automotive use case .................... 87

•

修订历史记录

7

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

3 Device Comparison

POWER BREAKDOWN

Total DC-DC converters

Total DC-DC converter rails

LDOs

TPS659038-Q1

TPS659039-Q1

9

7

9

7

6

11

0,8-mm pitch 169ZWS

(12 × 12 mm) nFBGA

0,8-mm 169ZWS

(12 × 12 mm) nFBGA

Package

8

Device Comparison

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

4 Pin Configuration and Functions

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2

3

4

5

6

7

8

9 10 11 12 13

Figure 4-1. 169-Pin ZWS Plastic Ball Grid Array (PBGA)

Bottom View

4.1 Pin Functions

Pin Functions

FUNCTION

AVAILABILITY

CONNECTION

IF NOT USED OR

NOT AVAILABLE

I/O

DESCRIPTION

PU/PD⁽¹⁾

NAME

REFERENCE

NO.

'38⁽²⁾

'39⁽²⁾

REFGND1

VBG

A4

B7

—

O

√

System reference ground

Bandgap reference voltage

Ground

N/A

—

STEP-DOWN CONVERTERS (SMPSs)

D10

SMPS1_GND

SMPS1_IN

E9

—

I

√

Power ground connection for SMPS1

Power input for SMPS1

Ground

System supply

Floating

—

E10

D11

D12

D13

E11

E12

E13

F9

SMPS1_SW

SMPS2_GND

SMPS2_IN

O

—

I

Switch node of SMPS1; connect output inductor

Power ground connection for SMPS2

Power input for SMPS2

F10

G10

G11

G12

G13

F11

F12

F13

B13

Ground

System supply

SMPS2_SW

O

I

√

Switch node of SMPS2; connect output inductor

Floating

Ground

—

SMPS1_2_FDBK

Output voltage-sense (feedback) input for SMPS1 and SMPS2

(1) The PU/PD column shows the pullup and pulldown resistors on the digital input lines. Pullup and pulldown resistors:

PU

pullup

PD

pulldown

PPU

PPD

software-programmable pullup

software-programmable pulldown

(2) '38 designates the TPS659038-Q1 and '39 designates TPS659039-Q1

Pin Configuration and Functions

9

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Pin Functions (continued)

NAME

FUNCTION

AVAILABILITY

CONNECTION

IF NOT USED OR

NOT AVAILABLE

I/O

DESCRIPTION

PU/PD⁽¹⁾

NO.

'38⁽²⁾

'39⁽²⁾

SMPS1_2_FDBK_GND

SMPS3_GND

C12

H10

J9

I

√

Ground-sense (feedback) input for SMPS1 and SMPS2

Ground

—

I

√

Power ground connection for SMPS3

Power input for SMPS3

Ground

—

J10

H11

H12

H13

J11

J12

J13

K13

F4

SMPS3_IN

System supply

SMPS3_SW

O

I

√

Switch node of SMPS3; connect output inductor

Output voltage-sense (feedback) input for SMPS3

Power ground connection for SMPS4

Floating

Ground

—

SMPS3_FDBK

SMPS4_GND

G4

G5

F1

—

SMPS4_IN

F2

I

√

Power input for SMPS4

System supply

Floating

—

F3

G1

G2

G3

K2

SMPS4_SW

O

Switch node of SMPS4; connect output inductor

SMPS4_5_FDBK

I

√

Output voltage-sense (feedback) input for SMPS4 and SMPS5

Ground-sense (feedback) input for SMPS4 and SMPS5

Ground

—

SMPS4_5_FDBK_GND

K3

H4

H5

J4

SMPS5_GND

SMPS5_IN

—

I

√

Power ground connection for SMPS5

Power input for SMPS5

Ground

System supply

Floating

—

J1

J2

J3

H1

H2

H3

L5

SMPS5_SW

O

Switch node of SMPS5; connect output inductor

SMPS6_GND

SMPS6_IN

—

I

√

Power ground connection for SMPS6

Power input for SMPS6

Ground

—

L6

M6

N6

M5

N5

K6

System supply

SMPS6_SW

O

I

√

Switch node of SMPS6 connect output inductor

Output voltage sense (feedback) input for SMPS6

Floating

Ground

—

SMPS6_FDBK

D4

D5

E4

SMPS7_GND

SMPS7_IN

—

I

√

Power ground connection for SMPS7

Power input for SMPS7

Ground

System supply

Floating

—

E1

E2

E3

D1

D2

D3

B1

SMPS7_SW

O

Switch node of SMPS7; connect output inductor

SMPS7_FDBK

SMPS8_GND

I

√

Output voltage-sense (feedback) input for SMPS7

Power ground connection for SMPS8

Floating

Ground

—

L9

—

L10

M9

N9

M10

N10

SMPS8_IN

I

√

Power input for SMPS8

System supply

Floating

—

SMPS8_SW

O

Switch node of SMPS8 connect output inductor

10

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Pin Functions (continued)

NAME

FUNCTION

AVAILABILITY

CONNECTION

IF NOT USED OR

NOT AVAILABLE

I/O

DESCRIPTION

PU/PD⁽¹⁾

NO.

'38⁽²⁾

'39⁽²⁾

SMPS8_FDBK

L11

L7

I

√

Output voltage-sense (feedback) input for SMPS8

Power ground connection for SMPS9

Ground

—

SMPS9_GND

SMPS9_IN

—

√

L8

M8

N8

M7

N7

J8

I

Power input for SMPS9

System supply

—

SMPS9_SW

O

I

√

Switch node of SMPS9 connect output inductor

Output voltage-sense (feedback) input for SMPS9

Floating

Ground

—

SMPS9_FDBK

LOW DROPOUT REGULATORS

LDO1_OUT

LDO12_IN

LDO2_OUT

LDO3_OUT

C6

A6

O

I

√

LDO1 output voltage

Floating

System supply

Floating

—

Power input voltage for LDO1 and LDO2 regulators

LDO2 output voltage

B6

O

K11

L12

L13

K12

K4

LDO3 output voltage

Floating

LDO34_IN

I

√

Power input voltage for LDO3 and LDO4 regulators

System supply

—

LDO4_OUT

LDO5_OUT

O

√

LDO4 output voltage

LDO5 output voltage

Floating

—

M4

N4

N3

L4

LDO58_IN

I

√

Power input voltage for LDO5 and LDO8 regulators

System supply

—

LDO6_IN

I

√

Power input voltage for LDO6 regulator

LDO6 output voltage

System supply

Floating

—

LDO6_OUT

LDO7_LDOUSB_IN

LDO7_OUT

LDO8_OUT

LDO9_IN

O

I

A10

C9

K5

√

Power input voltage for LDO7 and LDOUSB (LDOUSB_IN1) regulators

LDO7 output voltage

System supply

Floating

O

I

LDO8 output voltage

Floating

C4

A5

√

Power input voltage for LDO9 regulator

LDO9 output voltage

System supply

Floating

LDO9_OUT

LDOUSB_IN2

LDOUSB_OUT

O

I

A9

Power input voltage 2 for LDOUSB regulator

LDOUSB output voltage

System supply

Floating

B9

O

LOW NOISE DROPOUT REGULATORS

LDOLN_IN

C5

B5

I

√

Power input voltage for LDOLN regulator

LDOLN output voltage

System supply

Floating

—

LDOLN_OUT

O

LOW-DROPOUT REGULATORS (INTERNAL)

LDOVANA_OUT

C8

O

√

LDOVANA output voltage

N/A

—

LDOVRTC output voltage. For silicon revisions 1.3 or earlier, rapid power off and on

requires a pulldown resistor on the LDOVRTC_OUT pin. See 节 6.4.11 for more

details.

LDOVRTC_OUT

A8

O

√

SIGMA-DELTA GPADC

GPADC_IN0

B2

C2

C3

B4

I

√

GPADC input 0

Ground

Floating

—

GPADC_IN1

GPADC input 1

GPADC_IN2

I

GPADC input 2

GPADC_VREF

CLOCKING

O

GPADC output reference voltage

CLK32KGO

M11

C1

O

√

32-kHz digital-gated output clock available when VIO_IN input supply is present

Filtering capacitor for the 16-MHz crystal oscillator

Floating

—

OSC16MCAP

Floating or Ground in

Bypass Mode

OSC16MIN

A3

I

√

16-MHz crystal oscillator input or digital clock input

—

OSC16MOUT

SYNCDCDC

SYSTEM CONTROL

BOOT0

A2

B8

O

I

√

16-MHz crystal oscillator output or floating in case of digital clock

Sync pin to sync DC-DCs with external clock

Floating

Ground

—

-

L3

K7

I

√

Boot ball 0 for power-up sequence selection

Boot ball 1 for power-up sequence selection

Ground or VRTC

—

BOOT1

PPU

PPD⁽³⁾

ENABLE1

GPIO_0

J5

I

√

Peripheral power request input 1

General-purpose input⁽³⁾or output

Floating

Ground or VSYS

(VCC1)

B12

I/O

PPD

(3) Default option

Pin Configuration and Functions

11

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Pin Functions (continued)

NAME

FUNCTION

AVAILABILITY

CONNECTION

IF NOT USED OR

NOT AVAILABLE

I/O

DESCRIPTION

PU/PD⁽¹⁾

NO.

'38⁽²⁾

'39⁽²⁾

PPU

PPD

—

I/O

O

√

Primary function: General-purpose input⁽³⁾or output

Secondary function: VBUSDET - VBUS detection

General-purpose input⁽³⁾or output

Floating

GPIO_1

C13

PPU

PPD

—

I/O

GPIO_2

GPIO_3

GPIO_4

A12

H9

O

I

√

Secondary function: REGEN2 — External regulator enable output 2

Floating

Ground

General-purpose input⁽³⁾or output

PPD

PPU

PPD⁽³⁾

—

I/O

O

√

Primary function: General-purpose input⁽³⁾or output

Secondary function: SYSEN1 — External system enable

Primary function: General-purpose input⁽³⁾or output

Floating

Ground

K10

PPU

PPD⁽³⁾

I/O

GPIO_5

C10

Secondary function: CLK32KGO1V8 — 32-kHz digital-gated output clock available

when VRTC is present

O

√

Floating

—

PPU

PPD⁽³⁾

—

I/O

Primary function: General-purpose input⁽³⁾or output

GPIO_6

GPIO_7

N11

G9

O

I/O

I

√

Secondary function: SYSEN2 — External system enable

Primary function: General-purpose input⁽³⁾or output

Secondary function: POWERHOLD input

Floating

Ground or VRTC

PPD

PPD⁽³⁾

Control I²C serial clock (external pullup) and SPI clock signal

I2C1_SCL_SCK

I2C1_SDA_SDI

L1

L2

I/O

√

Floating

—

Control I²C serial bidirectional data (external pullup) and SPI data signal

DVS I²C serial bidirectional data (external pullup) and SPI data read signal or I²C

serial bidirectional data (external pullup)

I2C2_SDA_SDO

I2C2_SCL_SCE

H8

M3

I/O

√

Floating

—

DVS I²C serial clock (external pullup) and SPI enable signal or I²C serial clock

(external pullup)

INT

K1

E6

O

I

√

Maskable interrupt output request to the host processor

Warm reset input

N/A

—

PPU⁽³⁾

PPD

PU

NRESWARM

Floating

NSLEEP

E5

I

√

NSLEEP request signal

Floating

RPWRON

C11

K8

I

√

External remote switch-on event

Floating

PWRDOWN

PWRON

Power-down signal

PPD

PU

G8

F8

I

External power-on event (on-button switch-on event)

External regulator enable output 1

Reset input

REGEN1

O

I

—

RESET_IN

K9

PPD

—

RESET_OUT

POWER DETECTION

POWERGOOD

VBUS

G6

O

System reset/power on output (Low—Reset, High—Active or Sleep)

J7

D8

O

I

√

Indication signal for valid regulator output voltages

VBUS Detection Voltage

Floating

Ground

—

VCC_SENSE

VCC_SENSE2

B3

I

System supply sense line

System supply

A11

I

System supply sense line

PROGRAMMING, TESTING

I

√

Primary function: OTP programming voltage

Secondary function: TESTV

Ground or Floating

Floating

—

VPROG

N12

O

POWER SUPPLIES

A7

E7

GND_ANA

GND_DIG

—

√

Analog power ground

Digital power ground

Ground

—

F5

M13

M12

12

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Pin Functions (continued)

FUNCTION

AVAILABILITY

CONNECTION

IF NOT USED OR

NOT AVAILABLE

I/O

DESCRIPTION

PU/PD⁽¹⁾

NAME

NO.

'38⁽²⁾

'39⁽²⁾

A1

A13

B10

B11

D6

D7

E8

F6

PBKG

F7

—

√

Substrate ground

Ground

—

G7

H6

H7

J6

M1

M2

N1

N13

C7

N2

D9

VCC1

I

—

I

√

Analog input voltage supply

System supply

Ground

—

VIO_GND

VIO_IN

Digital ground connection

Digital supply input for GPIOs and I/O supply voltage

System supply

Pin Configuration and Functions

13

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

4.2 Device Ball Mapping – 13 × 13 nFBGA, 169 Balls, 0,8-mm Pitch

Figure 4-2 shows the nFBGA package ball mapping of the TPS659038-Q1 device and Figure 4-3 shows

the nFBGA package ball mapping of the TPS659039-Q1 device.

A

B

C

D

E

F

G

H

J

K

L

M

N

PBKG

SMPS1_2_FDBK

GPIO_1

SMPS1_IN

SMPS1_SW

SMPS2_SW

SMPS2_IN

SMPS3_IN

SMPS3_SW

SMPS3_FDBK

LDO34_IN

GND_ANA

PBKG

13

12

11

10

9

13

12

11

10

9

SMPS1_2_FDBK_

GND

GPIO_2

VCC_SENSE2

LDO7_LDOUSB_IN

LDOUSB_IN2

LDOVRTC_OUT

GND_ANA

GPIO_0

PBKG

SMPS1_IN

SMPS1_GND

VIO_IN

SMPS1_SW

SMPS1_GND

PBKG

SMPS2_SW

SMPS2_GND

REGEN1

SMPS2_IN

SMPS2_GND

GPIO_7

SMPS3_IN

SMPS3_GND

GPIO_3

SMPS3_SW

SMPS3_GND

LDO4_OUT

LDO3_OUT

GPIO_4

LDO34_IN

SMPS8_FDBK

SMPS8_GND

SMPS9_GND

SMPS6_GND

LDO6_OUT

BOOT0

GND_DIG

CLK32KGO

SMPS8_SW

SMPS8_IN

SMPS9_IN

SMPS9_SW

SMPS6_IN

SMPS6_SW

LDO58_IN

I2C2_SCL_SCE

PBKG

VPROG

GPIO_6

RPWRON

GPIO_5

PBKG

SMPS8_SW

SMPS8_IN

SMPS9_IN

SMPS9_SW

SMPS6_IN

SMPS6_SW

LDO58_IN

LDO6_IN

LDOUSB_OUT

SYNCDCDC

VBG

LDO7_OUT

LDOVANA_OUT

VCC1

RSET_IN

VBUS

PWRON

I2C2_SDA_SDO SMPS9_FDBK

POWERGOOD

PWRDOWN

BOOT1

8

PBKG

GND_ANA

NRESWARM

NSLEEP

PBKG

PWRGOOD

7

LDO12_IN

LDO2_OUT

LDOLN_OUT

GPADC_VREF

VCC_SENSE

GPADC_IN0

LDO1_OUT

LDOLN_IN

LDO9_IN

PBKG

RESET_OUT

SMPS4_GND

SMPS4_SW

PBKG

SMPS6_FDBK

LDO8_OUT

LDO5_OUT

6

LDO9_OUT

SMPS7_GND

SMPS7_SW

GND_ANA

SMPS4_GND

SMPS4_IN

SMPS5_GND

SMPS5_SW

ENABLE1

SMPS5_GND

SMPS5_IN

5

REFGND1

SMPS7_GND

SMPS7_IN

4

SMPS4_5_FDBK_

GND

OSC16MIN

GPADC_IN2

GPADC_IN1

3

OSC16MOUT

SMPS4_5_FDBK

I2C1_SDA_SDI

VIO_GND

2

PBKG

SMPS7_FDBK

OSC16MCAP

SMPS7_SW

SMPS7_IN

SMPS4_IN

SMPS4_SW

SMPS5_SW

SMPS5_IN

INT

I2C1_SCL_SCK

PBKG

1

A

B

C

D

E

F

G

H

J

K

L

M

N

Figure 4-2. Top-View Ball Mapping for TPS659038-Q1 – nFBGA 13 × 13, 169 Balls, 0,8-mm Pitch

14

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

A

B

C

D

E

F

G

H

J

K

L

M

N

PBKG

SMPS1_2_FDBK

GPIO_1

SMPS1_IN

SMPS1_SW

SMPS2_SW

SMPS2_IN

SMPS3_IN

SMPS3_SW

SMPS3_FDBK

LDO34_IN

GND_ANA

PBKG

13

12

11

10

9

SMPS1_2_FDBK_

GND

GPIO_2

GPIO_0

PBKG

SMPS1_IN

SMPS1_GND

VIO_IN

SMPS1_SW

SMPS1_GND

PBKG

SMPS2_SW

SMPS2_GND

REGEN1

SMPS2_IN

SMPS2_GND

GPIO_7

SMPS3_IN

SMPS3_GND

GPIO_3

SMPS3_SW

SMPS3_GND

NC

LDO3_OUT

GPIO_4

RSET_IN

PWRDOWN

BOOT1

LDO34_IN

SMPS8_FDBK

SMPS8_GND

SMPS9_GND

SMPS6_GND

NC

GND_DIG

CLK32KGO

SMPS8_SW

SMPS8_IN

SMPS9_IN

SMPS9_SW

SMPS6_IN

SMPS6_SW

LDO58_IN

I2C2_SCL_SCE

PBKG

VPROG

GPIO_6

12

VCC_SENSE2

RPWRON

GPIO_5

11

LDOUSB_IN1

PBKG

SMPS8_SW

SMPS8_IN

SMPS9_IN

SMPS9_SW

SMPS6_IN

SMPS6_SW

LDO58_IN

LDO6_IN

10

LDOUSB_IN2

LDOUSB_OUT

SYNCDCDC

VBG

NC

9

LDOVRTC_OUT

LDOVANA_OUT

VCC1

VBUS

PWRON

I2C2_SDA_SDO SMPS9_FDBK

8

GND_ANA

PBKG

GND_ANA

NRESWARM

NSLEEP

PBKG

PWRGOOD

PBKG

7

LDO12_IN

LDO2_OUT

LDOLN_OUT

GPADC_VREF

VCC_SENSE

GPADC_IN0

LDO1_OUT

LDOLN_IN

LDO9_IN

GPADC_IN2

GPADC_IN1

PBKG

RESET_OUT

SMPS4_GND

SMPS4_SW

PBKG

SMPS6_FDBK

NC

6

LDO9_OUT

SMPS7_GND

SMPS7_SW

GND_ANA

SMPS4_GND

SMPS4_IN

SMPS5_GND

SMPS5_SW

ENABLE1

SMPS5_GND

SMPS5_IN

5

REFGND1

SMPS7_GND

SMPS7_IN

NC

4

SMPS4_5_FDBK_

GND

OSC16MIN

BOOT0

3

OSC16MOUT

SMPS4_5_FDBK

I2C1_SDA_SDI

VIO_GND

2

PBKG

SMPS7_FDBK

OSC16MCAP

SMPS7_SW

SMPS7_IN

SMPS4_IN

SMPS4_SW

SMPS5_SW

SMPS5_IN

INT

I2C1_SCL_SCK

PBKG

1

A

B

C

D

E

F

G

H

J

K

L

M

N

Figure 4-3. Top-View Ball Mapping for TPS659039-Q1 – nFBGA 13 × 13, 169 Balls, 0,8-mm Pitch

Pin Configuration and Functions

15

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

5 Specifications

5.1 Absolute Maximum Ratings

(2)

See⁽¹⁾

.

MIN

–0.3

–2

MAX

UNIT

V

Voltage on VCC1 pins

6

7

Voltage on VCC_SENSE, VCC_SENSE2 pins

All LDOs and SMPS supply voltage input pins (except LDOUSB_IN2)

Voltage on SMPSx_SW pins, 10 ns transient

All SMPS-related input pins _FDBK

V

6

V

7

V

–0.3

3.6

20

V

LDOUSB regulator LDOUSB_IN2 input voltage

V

–0.3

VIO_max

0.3

VIO_max

0.3

+

I/O digital supply voltage (VIO_IN with respect to VIO_GND)

+

V

Voltage

VBUS

–2

20

5.25

2.5

V

Voltage on the GPADC pins: GPADC_IN0, GPADC_IN1

Voltage on the GPADC pins: GPADC_IN2

OTP supply voltage VPROG

–0.3

20

Without fail-safe

Voltage on VRTC digital input pins

2.15

5.25

V

With fail-safe

VIO_max

0.3

+

Voltage on VIO digital input pins (VIO_IN pin reference)

–0.3

Voltage on VSYS digital input pins (VCC1 pin reference)

Peak output current on all pins other than power resources

Power pins, nFBGA

–0.3

–5

6

5

V

mA

A

1

Current

Buck SMPS, SMPSx_IN, SMPSx_SW, and SMPSx_OUT total per phase

LDOs

4

A

1

A

Junction temperature range, T_J

Storage temperature, T_stg

–45

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2) When operating the TPS659038-Q1 andTPS659039-Q1 devices without an external crystal, each SMPS regulating an output voltage

greater than 1.8 V must be disabled before VCC is removed. Lowering VCC below the programmed VSYS_LO level while any SMPS is

regulating an output voltage above 1.8 V may cause damage to the device.

5.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charge device model (CDM), per AEC Q100-011

V

Corner pins (A1, A13, N1, and N13)

Pins B4, B7, H8, L1, L2, M3

All other pins

Electrostatic

discharge

V_(ESD)

±450

V

±500

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

18

Specifications

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

5.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

All system voltage input pins, VCC1 (named VSYS in the specification)

3.135

3.8

5.25

V

VCC_SENSE and VCC_SENSE2, HIGH_VCC_SENSE = 0 (if measured with GPADC,

see also 表 6-1)

VCC1 – 1

All LDO-related input pins, _IN (except LDOUSB)⁽¹⁾

1.75

3.6

3.8

5.25

V

LDOUSB_IN1

LDOUSB_IN2

4.3

5.25

All SMPS-related input pins, _IN

3.135

0

5.25

All SMPS-related input pins, _FDBK

All SMPS-related input pins, _FDBK_GND

I/O digital supply voltage, VIO_IN, for 1.8-V Mode

I/O digital supply voltage, VIO_IN, for 3.3-V Mode

Voltage on the GPADC pins, GPADC_IN0, GPADC_IN1

Voltage on the GPADC pins GPADC_IN2 pin

V_Omax + 0.3

0.3

–0.3

1.71

3.135

0

1.8

3.3

1.89

3.465

1.25

0

2.5

LDOVRT

C

Voltage on the crystal oscillator pin, OSC16MIN

OTP supply voltage, VPROG

-0.7

0

1.85

10

V

8

LDOVRT

C

Voltage on VRTC digital input pins

0

1.85

Voltage on VIO digital input pins (VIO_IN pin reference)

Voltage on VSYS digital input pins (VCC1 pin reference)

Lead temperature (soldering, 10 seconds)

Operating free-air temperature⁽²⁾

0

VIO

3.8

260

27

VIO_max

5.25

V

°C

–40

85

Operating junction temperature, T_J

27

125

(1) Does not include LDO1 and LDO2 minimum input voltages.

(2) Additional cooling strategies may be necessary to maintain junction temperature at recommended limits.

5.4 Thermal Information

TPS659038-Q1

TPS659039-Q1

THERMAL METRIC⁽¹⁾

UNIT

ZWS (NFBGA)

169 PINS

36.4

6.6

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

18.6

0.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

18.2

—

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5.5 Electrical Characteristics: Latch Up Rating

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I²C / SPI pins

90

mA

100

I_LU

Latch up current Class 2

LDOVANA_OUT pin

All other pins

–60

Specifications

19

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

5.6 Electrical Characteristics: LDO Regulator

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input filtering capacitance (C29, C30, Connected from LDOx_IN to GND. Shared input tank capacitance

0.6

2.2

µF

C31, C32, C33, C34)

(depending on platform requirements)

Output filtering capacitance (C35,

C36, C37, C38, C39, C40, C41, C42, Connected from LDOx_OUT to GND (Except LDO9)

0.6

2.2

2.7

µF

C43, C45, C46, C47)⁽¹⁾

Connected from LDO9_OUT to GND

LDO9 Output filtering capacitance

0.6

2.2

1

2.7

1.2

(C44)⁽¹⁾

Connected from LDO9_OUT to GND. LDO9 configured in BYPASS MODE

(LDO9_CTRL.LDO_PYPASS_EN = 1)

LDO6 inductive load (LDO6)

LDO6 load resistance (LDO6)

Connected between LDO6 output (LDO6_OUT) and GND

70

15

350

40

700

50

µH

Ω

< 100 kHz

20

100

10

600 mΩ

20 mΩ

C_ESR

Filtering capacitor ESR

1 ≤ MHz f ≤ 10 MHz

1

0.9V ≤ V_O≤ 2.15V

1.2

VCC1

LDO1, LDO2

2.2V ≤ V_O≤ 3.3V

0.9V ≤ V_O≤ 2.15V

2.2V ≤ V_O≤ 3.3V

0.9V ≤ V_O≤ 1.75V

1.8V ≤ V_O≤ 3.3V

Bypass Mode

1.2

5.25

VCC1

5.25

1.75

3.6

LDOLN, LDO3, LDO4, LDO5, LDO6, LDO7,

LDO8

V_I(LDOx)

Input voltage

VCC1

5.25

LDO9

V

3.6

0.9V ≤ V_O≤ 2.15V

2.2V ≤ V_O≤ 3.3V

0.9V ≤ V_O≤ 2.15V

2.2V ≤ V_O≤ 3.3V

VCC1

5.25

V_I(LDOUSB1)

Input voltage

LDOUSB from LDOUSB_IN1

LDOUSB from LDOUSB_IN2

3.6

4.3

VCC1

5.25

V_I(LDOUSB2)

V_CC(1)

Input voltage

4.3

VCC1 used for internal power supply

V_O(LDOx)< V_I(LDOx)- D_V(LDOx)

Step size

3.135

0.9

3.8

50

5.25

LDO output voltage programmable⁽²⁾

(except LDOVRTC and LDOVANA)

3.3

V

V_O(LDOx)

mV

0.99 ×

V_O(LDOx)

–0.014

1.006 ×

V_O(LDOx)

+0.014

All LDOs except LDO3, LDO4, LDOVANA, and LDOVRTC

LDO3, LDO4: I_O≤ 200 mA

0.99 ×

V_O(LDOx)

–0.014

1.006 ×

V_O(LDOx)

+0.014

Total DC output voltage accuracy,

including voltage references, DC load

and line regulations, process and

temperature

T_DCOV(LDOx)

V

0.99 ×

V_O(LDOx)

–0.018

1.006 ×

V_O(LDOx)

+0.018

LDO3, LDO4: 200 mA < I_O≤ 300 mA

LDOVRTC_OUT

1.726

2.002

1.8

1.850

2.119

150

290

550

290

230

150

290

200

900

150

300

200

170

50

LDOVANA_OUT

2.093

LDO1, LDO2: I_O= I_Omax

LDO3, LDO4: I_O= 200 mA

LDO3, LDO4: I_O= I_Omax

LDO5, LDO6, LDO7, LDO8: I_O= I_Omax

LDO9: I_O= I_Omax

V_{DROPOUT(LDOx)}

Dropout voltage⁽³⁾

mV

LDOLN: I_O= I_Omax

LDOLN: I_O= 100 mA (Functional, not low-noise performance)

LDOUSB – From LDOUSB_IN1: I_O= I_Omax

LDOUSB – From LDOUSB_IN2: I_O= I_Omax

LDOVRTC, LDOVANA: I_O= I_Omax

LDO1, LDO2, LDO3, LDO4

LDO5, LDO6, LDO7

V_{DROPOUT(LDOx)}

Dropout voltage (internal LDOs)

Output current

I_O(LDOx)

LDO8

LDO9, LDOLN

mA

LDOUSB

100

10

LDOVANA

I_O(LDOx)

Output current, internal LDOs

LDOVRTC

25

(1) Additional information about how this parameter is specified is located in the 节 7.2.2 section.

(2) LDO output voltages are programmed separately.

(3) D_V(LDOx)= V_I–V_O, where V_O= V_Onom – 2%

20

Specifications

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Electrical Characteristics: LDO Regulator (continued)

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

380

400

120

150

100

55

TYP

600

650

200

250

325

250

MAX UNIT

1800

LDO1, LDO2

LDO3, LDO4, LDO5, LDO6, LDO7, LDO8

LDO9

1300

400

I_SHORT(LDOx)

LDO current limitation

LDOUSB

600

740

400

500

16

mA

LDOLN

LDOVANA

LDOVRTC

LDO inrush current

LDO1, LDO2

mA

mV

I_O= 0 to I_Omax at pin, LDO1, LDO2

I_O= 0 to 200 mA at pin, LDO3, LDO4

I_O= 0 to I_Omax at pin, LDO3, LDO4

I_O= 0 to I_Omax at pin, all other LDOs

V_I= V_Imin to V_Imax, I_O= I_Omax

4

14

ΔV_O(ΔVI)(DC)

DC load regulation ΔV_O

18

4

14

0.1%

0.2%

DC line regulation, except VRTC,

ΔV_O/ V_O

ΔV_O(ΔVI)(DC)

V_SYS= V_SYSmin to V_SYSmax, _IO= IOUTmax. VIN constant (LDO

0.3%

0.75%

1%

preregulated), V_O≤ 2.2 V

DC line regulation on LDOVRTC,

ΔV_O/V_O

DC_LNR(LDOVRTC)

V_SYS= V_SYSmin to V_SYSmax, I_O= I_Omax

Bypass resistance of LDO9

Turnon time

V_I≥ 2.7 V, programmed to BYPASS

4.2

Ω

t_on

t_off

I_O= 0, V_O= 0.1 V up to V_Omin

100

250

500

µs

Turnoff time

(except VRTC )

I_O= 0, V_Odown to 10% × V_O

500

125

µs

Pulldown discharge resistance at LDO OFF mode, pulldown enabled and LDO disabled. Also applies to bypass

output, except LDOVRTC

R_DIS

30

Ω

mode

_ƒ= 217 Hz, I_O= I_Omax

ƒ = 50 kHz, I_O= I_Omax

ƒ = 1 MHz, I_O= I_Omax

ƒ = 217 Hz, I_O= 200 mA

ƒ = 217 Hz, I_O= I_Omax

ƒ = 50 kHz, I_O= I_Omax

ƒ = 1 MHz, I_O= I_Omax

ƒ = 217 Hz, I_O= I_Omax

ƒ = 50 kHz, I_O= I_Omax

ƒ = 1 MHz, I_O= I_Omax

ƒ = 217 Hz, I_O= I_Omax

55

28

25

55

50

20

55

20

55

25

90

45

35

90

60

45

35

90

45

35

90

45

35

0.1

0.2

39

Power supply ripple rejection, LDO1,

LDO2

dB

Power supply ripple rejection, LDO3,

LDO4

PSRR

Power supply ripple rejection, LDO5,

LDO6, LDO7, LDO8, LDO9, LDOUSB

Power supply ripple rejection, LDOLN ƒ = 50 kHz, I_O= I_Omax

ƒ = 1 MHz, I_O= I_Omax

dB

µA

For all LDOs, T = 27°C

Quiescent current OFF mode

I_Q(off)

For all LDOs, T ≥ 85°C

I_L= 0 mA (LDO1, LDO2), 0.9 V ≤ V_O≤ 3.3 V, V_O(LDOx)< V_I(LDOx)– D_V(LDOx)

70

47

I_L= 0 mA (LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9), V_O(LDOx)

V_I(LDOx)– D_V(LDOx)

<

36

I_L= 0 mA (LDOLN) , V_O≤ 1.8 V, V_O(LDOx)< V_I(LDOx)– D_V(LDOx)

I_L= 0 mA (LDOLN) , V_O> 1.8 V, V_O(LDOx)< V_I(LDOx)– D_V(LDOx)

I_L= 0 mA (LDOUSB) – IN1, V_O(LDOx)< V_I(LDOx)– D_V(LDOx)

I_L= 0 mA (LDOUSB) – IN2, V_O(LDOx)< V_I(LDOx)– D_V(LDOx)

I_O< 100 µA

140

180

45

190

210

65

I_Q(on)

Quiescent current LDO ON mode

µA

18

25

4%

2%

1%

Quiescent current coefficient LDO ON

mode, I_QO= I_Q(on)+ αQ × I_O

αQ

100 µA ≤ I_O< 1 mA

I_O≥ 1 mA

ON mode, I_O= 10 mA to I_Omax / 2, t_r= t_f= 1 µs. All LDOs except LDO3,

LDO4, LDO9, LDOLN

–25

25

ON mode, I_O= 10 mA to 100 mA, t_r= t_f= 1 µs. LDO3, LDO4

ON mode, I_O= 10 mA to I_Omax / 2, t_r= t_f= 1 µs. LDO3, LDO4

ON mode, I_O= 1 mA to I_Omax /2, t_r= t_f= 1 µs. LDO9, LDOLN

ON mode, I_O= 100 µA to I_Omax / 2, t_r= t_f= 1 µs.

V_Istep = 600 mVpp, t_r= t_f= 10 µs

–25

–40

–25

–50

25

T_LDR

Transient load regulation ΔV_O

mV

25

33

0.25%

0.8%

0.5%

T_LNR

Transient line regulation, ΔV_O/ V_O

V_SYSstep = 600 mVpp, t_r= t_f= 10 µs. V_Iconstant (LDO preregulated), V_O

2.2 V

≤

1.6%

Specifications

21

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Electrical Characteristics: LDO Regulator (continued)

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

5000

1250

150

250

400

62

MAX UNIT

100 Hz < ƒ ≤ 10 kHz

10 kHz < ƒ ≤ 100 kHz

100 kHz < ƒ≤ 1 MHz

ƒ > 1 MHz

8000

2500

nV/√Hz

300

Noise (except LDOLN)

500

100 Hz < ƒ ≤ 5 kHz, I_O= 50 mA, V_O≤ 1.8 V

5 kHz < ƒ ≤ 400 kHz, I_O= 50 mA, V_O≤ 1.8 V

400 kHz < ƒ ≤ 10 MHz, I_O= 50 mA, V_O≤ 1.8 V

LDO1, LDO2, ripple (from internal charge pump)

500

Noise (LDOLN)

Ripple

125 nV/√Hz

25

50

5

mVpp

5.7 Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase

(SMPS123 and SMPS457) Regulators

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input capacitance (C9, C10, C11, C12,

C13)

4.7

µF

Output capacitance (C18, C19, C21,

C22)⁽¹⁾

SMPS12 or SMPS45 dual phase operation, per phase

33

47

57

µF

Output capacitance (C20, C24)⁽¹⁾

SMPS3 and SMPS7 (triple phase operation)

47

2

57

C_ESR

Filtering capacitor ESR

1 ≤ MHz f ≤ 10 MHz

10

mΩ

Output filter inductance (L1, L2, L3, L4,

L5)

SMPSx_SW

0.7

1

1.3

µH

DCR_L

Filter inductor DC resistance

50

100

mΩ

V_I(SMPSx)

Input voltage range, SMPSx_IN

V_SYS(VCC1)

3.135

0.7

5.25

V

RANGE = 0 (value for RANGE must not be changed when SMPS is

active). In Eco-mode the output voltage values are fixed (defined

before Eco-mode is enabled). RANGE = 1 is not supported for Multi-

phase regulators.

1.65

V

V_OSMPSx

Output voltage, programmable, SMPSx

Step size, 0.7 V ≤ V_O≤ 1.65 V (RANGE = 0)

10

mV

DC output voltage accuracy, includes

voltage references, DC load/line

regulation, process and temperature

Eco-mode

–3%

–1%

4%

2%

Forced PWM mode

Max load, V_I= 3.8 V, V_O= 1.2 V, ESR_CO= 2 mΩ, measure with 20-

MHz LPF

Ripple, dual phase

Ripple, triple phase

4

1

mVPP

Max load, V_I= 3.8 V, V_O= 1.2 V, ESR_CO= 2 mΩ, measure with 20-

MHz LPF

DC_LNR

DC_LDR

DC line regulation

DC load regulation

0.1

%/V

%/A

Transient load step response, dual

phase

I_O= 0.8 to 2 A, t_r= t_f= 400 ns, C_O= 47 µF , L= 1 µH

I_O= 0.5 to 500 mA, t_r= t_f= 100 ns, C_O= 47 µF , L= 1 µH

3%

Transient load step response, triple

phase

T_LDSR

Transient load step response, dual or

triple phase

Rated output current, SMPS12

Rated output current, SMPS123

Rated output current, SMPS45

Maximum output current, Eco-mode

Advance thermal design is required to avoid thermal shutdown

6

9

4

5

I_Omax

A

mA

A

SMPS123, each phase

SMPS45, each phase

SMPS123, each phase

SMPS45, each phase

SMPS123, phase 1

3.7

2.7

4

3

I_LIM

High-side MOSFET forward current limit

Low-side MOSFET forward current limit

Low-side MOSFET negative current limit

HS FET

3.7

2.7

0.6

115

30

I_LIM

A

LS FET

SMPS45, phase 4

SMPS123, each phase

SMPS45, each phase

SMPS123, each phase

SMPS45, each phase

N-channel MOSFET on-resistance,

high-side FET

r_DS(on)

mΩ

HS FET

N-channel MOSFET on-resistance, low-

side FET

r_DS(on)

mΩ

LS FET

30

t_start

Time from enable to start of the ramp

150

µs

(1) Additional information about how this parameter is specified is located in the 节 7.2.2 section.

22 Specifications

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and

SMPS457) Regulators (continued)

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

t_ramp

Time from enable to 80% of V_O

Overshoot during turn-on

Output voltage slew rate

C_O< 57 µF per phase, no load

400

1000

5%

µs

Fixed TSTEP

2.5

mV/µs

SMSP turned off

300

Pulldown discharge resistance at

SMPS2, SMPS4 output

R_DIS

Ω

SMPSx_SW, SMPS turned off. Pulldown is at the master phase

output.

9

22

Between SMPS1_2_FDBK, SMPS1_2_FDBK_GND

Between SMPS4_5_FDBK, SMPS4_5_FDBK_GND

SMPS3_FDBK input resistance

380

1300

1

Input resistance for remote sense/sense

line

R_SENSE

kΩ

I_Q(off)

Quiescent current – OFF mode

I_L= 0 mA

0.1

13.5

15

µA

Eco-mode, device not switching, V_O< 1.8 V

Eco-mode, device not switching, V_O≥ 1.8 V

19

Quiescent current - ON mode, dual or

triple phase

21

I_Q(on)

FORCED_PWM mode, I_L= 0 mA, V_I= 3.8 V, device switching, 1-

phase operation

11

mA

SMPS output voltage rising, referenced to programmed output voltage

SMPS output voltage falling, referenced to programmed output voltage

IL_AVG_COMP_rising

–7.5%

V_SMPSPG

Powergood threshold

–12.5%

I_Omax– 20%

I_Omax I_Omax + 20%

IL_AVG_COMP

Powergood: GPADC monitoring SMPS IL_AVG_COMP_falling, 3A-phase

IL_AVG_COMP_falling, 2A-phase

IL_AVG_COMP_rising – 5%

IL_AVG_COMP_rising – 8%

5.8 Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8,

and SMPS9)

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input capacitance (C11, C14, C15, C16,

C17)

4.7

µF

Output capacitance (C20, C23, C24,

C25, C26)⁽¹⁾

SMPSx operation

1 ≤ MHz f ≤ 10 MHz

SMPSx_SW

33

47

2

57

10

µF

mΩ

µH

C_ESR

Filtering capacitor DC ESR

Output filter inductance (L3, L6, L7, L8,

L9)

0.7

1

1.3

DCR_L

Filter inductor DC resistance

50

100

mΩ

V_I(SMPSx)

Input voltage range, SMPSx_IN

VSYS (VCC1)

3.135

0.7

5.25

V

RANGE = 0 (value for RANGE must not be changed when SMPS is

active). In Eco-mode the output voltage value is fixed (defined before

Eco-mode is enabled).

1.65

3.3

V

RANGE = 1 (value for RANGE must not be changed when SMPS is

active). In Eco-mode the output voltage value is fixed (defined before

Eco-mode is enabled).

V_OSMPSx

Output voltage, programmable, SMPSx

1

Step size, 0.7 V ≤ V_O≤ 1.65 V

Step size, 1 V ≤ V_O≤ 3.3 V

Eco-mode

10

20

mV

DC output voltage accuracy, includes

voltage references, DC load/line

regulation, process and temperature

–3%

–1%

4%

2%

PWM mode

Max load, V_I= 3.8 V, V_O= 1.2 V,

ESR_CO= 2 mΩ, measure with 20-MHz LPF

Ripple

8

mVPP

DC_LNR

DC_LDR

DC line regulation

DC load regulation

T_A= –40°C to 85°C

0.1

%/V

%/A

SMPS3, SMPS6, SMPS7 , I_OUT= 0.5 to 500 mA,

t_r= t_f= 100 ns, C_O= 47 µF , L = 1 µH

3%

T_LDSR

Transient load step response

SMPS8, SMPS9, I_O= 0.5 to 500 mA,

t_r= t_f= 1 µs, C_O= 47 µF , L = 1 µH

(1) Additional information about how this parameter is specified is located in the 节 7.2.2 section.

Submit Documentation Feedback

Specifications

23

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and

SMPS9) (continued)

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_I≥ 3 V

3

Advance thermal design is required to avoid thermal shutdown

Rated output current, SMPS3

V_I< 3 V

2

Advance thermal design is required to avoid thermal shutdown

When OTP programmed with BOOST_CURRENT = 0

Advance thermal design is required to avoid thermal shutdown

2

I_Omax

A

Rated output current, SMPS6

Rated output current, SMPS7

When OTP programmed with BOOST_CURRENT = 1

Advance thermal design is required to avoid thermal shutdown

3

Advance thermal design is required to avoid thermal shutdown

2

1

Rated output current, SMPS8, SMPS9 Advance thermal design is required to avoid thermal shutdown

Maximum output current, Eco-mode

SMPS3 and SMPS6 in 3-A mode

5

mA

A

3.7

2.7

1.7

4

3

I_LIM

High-side MOSFET forward current limit SMPS6 in 2-A mode, SMPS7

SMPS8, SMPS9

HS FET

2

SMPS3 and SMPS6 in 3-A mode

3.7

2.7

1.7

0.6

115

180

30

I_LIM

Low-side MOSFET forward current limit SMPS6 in 2-A mode, SMPS7

SMPS8, SMPS9

A

LS FET

SMPS3 and SMPS6 in 3-A mode

Low-side MOSFET negative current limit SMPS6 in 2-A mode, SMPS7

SMPS8, SMPS9

SMPS3

N-channel MOSFET on-resistance

(high-side FET)

r_DS(on)

SMPS6, SMPS7

mΩ

HS FET

LS FET

SMPS8, SMPS9

SMPS3

N-channel MOSFET on-resistance (low-

side FET)

r_DS(on)

SMPS6, SMPS7

30

SMPS8, SMPS9

79

t_start

Time from enable to start of the ramp

150

400

µs

t_ramp

Time from enable to 80% of V_O

Overshoot during turn-on

Output voltage slew rate

C_O< 57 µF, no load

1000

5%

Fixed TSTEP, only available on SMPS6, SMPS8

SMPSx_FDBK, SMPS turned off

SMPSx_SW, SMPS turned off

I_L= 0 mA

2.5

300

9

mV/µs

Ω

Pulldown discharge resistance at

SMPSx output

R_DIS

I_Q(off)

22

1

Quiescent current – OFF mode

0.1

12

µA

Eco-mode, device not switching, V_O< 1.8 V

15

23

µA

Quiescent current – ON mode - SMPS3, Eco-mode, device not switching, V_O≥ 1.8 V

SMPS6, SMPS7

13.5

I_Q(on)

FORCED_PWM mode, I_L= 0 mA,

V_I= 3.8 V, device switching

11

mA

µA

Eco-mode, device not switching, V_O< 1.8 V

10.5

12

15

23

Quiescent current – ON mode - SMPS8, Eco-mode, device not switching, V_O≥ 1.8 V

SMPS9

I_Q(on)

FORCED_PWM mode, I_L= 0 mA,

V_I= 3.8 V, device switching

7

mA

SMPS output voltage rising, referenced to programmed output voltage

–7.5%

V_SMPSPG

Powergood threshold

SMPS output voltage falling, referenced to programmed output voltage

IL_AVG_COMP_rising

–12.5%

I_Omax – 20%

I_Omax I_Omax + 20%

IL_AVG_COMP

Powergood: GPADC monitoring SMPS IL_AVG_COMP_falling, 3-A phase

IL_AVG_COMP_falling, 2-A phase

IL_AVG_COMP_rising – 5%

IL_AVG_COMP_rising – 8%

24

Specifications

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

5.9 Electrical Characteristics: Reference Generator (Bandgap)

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

Filtering capacitor

TEST CONDITIONS

MIN

30

TYP

100

3.8

0.85

20

MAX UNIT

Connected from VBG to REFGND

150 nF

Input voltage (V_I)

Output voltage

Ground current

Start-up time

2.1

5.25

V

40 µA

ms

1

3

5.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and

Output Buffers

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

CRYSTAL CHARACTERISTICS

Crystal frequency

TEST CONDITIONS

MIN

TYP

16.384

33

MAX UNIT

Typical with specified load capacitors

Parameter of crystal; T_A= 27°C

Parameter of crystal

MHz

20 ppm

43 mH

Crystal frequency tolerance

Crystal motional inductance

Crystal series resistance

–20

23

At fundamental frequency

90

Ω

The power dissipated in the crystal during oscillator

operation

Oscillator drive power

15

10

120 µW

11 pF

Corresponding to crystal frequency, including

parasitic capacitances

Load capacitance

9

Crystal shunt capacitance

Parameter of crystal

0.5

4

pF

T_Jfrom –40°C to 125°C, VCC1 from 3.15 V to 5.25

Oscillator frequency drift

V

–50

50 ppm

10 ms

Excluding crystal tolerance

Time from VCC1 > 3.15 V until 32-kHz clock output

is available from crystal oscillator

Oscillator startup time

32-kHz RC OSCILLATOR

Output frequency low-level output voltage

Output frequency accuracy

Cycle jitter (RMS)

32768

0

Hz

After trimming, T_A= 27°C

–10%

40%

10%

Output duty cycle

50%

4

60%

Settling time

150 µs

Active current consumption

Power-down current

8

µA

30 nA

CLK32KGO OUTPUT BUFFER

Logic output external load

Rise and fall time

5

35

50

50 pF

100 ns

60%

C_L= 35 pF, 10% to 90%

Logic output signal

Duty cycle

40%

50%

CLK32KGO1V8 OUTPUT BUFFER

Settling time

25

7

50 µs

10 µA

30 nA

2%

Active current consumption

Power-down current

5

Duty cycle degradation contribution

External output load

–2%

5

10

15

50 pF

30 ns

20 ns

Output delay time

Output load = 10 pF

Output rise/fall time

7.5

SYNCCLKOUT OUTPUT BUFFER

Logic output external load

Rise and fall time

5

35

50

50 pF

C_L= 35 pF, 10% to 90%

100 ns

Specifications

25

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output

Buffers (continued)

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Logic output signal

MIN

TYP

MAX UNIT

Duty cycle

40%

50%

60%

5.11 Electrical Characteristics: DC-DC Clock Sync

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SYNC CLOCK SPECIFICATION AND DITHER PARAMETERS

The allowed range of the

ƒ_SYNC

1.7

2.2

2.7 MHz

128 kHz

external sync clock input

A_DITHER

M_DITHER

Dither amplitude

kHz/

1.35

Dither slope

µs

SYNC DC-DC DIGITAL CLOCK INPUT

Low-level input on

SYNCDCDC pin

0.3 ×

V

V_IL

–0.3

0

VRTC

High-level input on

SYNCDCDC pin

0.7 ×

VRTC

V_IH

VRTC

5.25

80%

V

Duty cycle of SYNCDCDC

input signal

20%

0.1 ×

VRTC

Hysteresis of input buffer

V

SYNC CLOCK AND FREQUENCY FALLBACK

ƒ_FALLBACK

Fall-back frequency

1.98

2.8

2.2

2.42 MHz

1.65 MHz

The low saturation frequency

output of the PLL

ƒ_SAT,LO

The high saturation

frequency output of the PLL

ƒ_SAT,HI

MHz

Time from initial application

or removal of sync clock until

PLL output has settled to 1%

of its final value

ƒ_SETTLE

100 µs

The steady-state percent

difference between f_SYNCand

the switching frequency

ƒ_ERROR

–1%

15

1%

Time delay between

corresponding staggered

phases

t_d

30

45 ns

5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

During conversion

MIN

TYP

MAX UNIT

I_Q(on)

I_Q(off)

ƒ

Current consumption

OFF mode current

Running frequency

Resolution

1500

1600 µA

GPADC is not enabled (no conversion)

1

µA

MHz

Bit

2.5

12

Number of available external

inputs

3

5

Number of available internal

inputs

26

Specifications

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Electrical Characteristics: 12-Bit Sigma-Delta ADC (continued)

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Active or sleep with VANA ON and

RC15MHZ_ON_IN_SLEEP = 1 or sleep with

GPADC_FORCE = 1

0

µs

Turnon time

Sleep or OFF

794

282

µs

Sleep with VANA enabled

Gain error (without scaler)

Gain error of the scaler

Offset before trimming

Offset drift after trimming

Gain error drift (after

–3.5%

–1%

–50

3.5%

1%

50 LSB

Temperature and supply

–2

2

LSB

trimming, including reference Temperature and supply

voltage)

–0.6%

0.2%

INL

Integral nonlinearity

Differential nonlinearity

Input capacitance

Best fitting

–3.5

–1

3.5 LSB

pF

DNL

GPADC_IN0–GPADC_IN2

0.5

Source resistance without capacitance

Source capacitance with > 20-kΩ source resistance

20 kΩ

nF

Source input impedance

100

GPADC_VREF voltage

reference

1.237

1.25

1.263

V

Load current for

GPADC_VREF

200 µA

Typical range

0

1.250

Input range (sigma-delta

ADC)

V

Assured range without saturation

1 channel, EXTEND_DELAY = 0

1 channel, EXTEND_DELAY = 1

2 channels

0.01

1.215

113

563

223

0

Conversion time

µs

CURRENT_SRC_CH0[1:0] = 00 (default)

CURRENT_SRC_CH0[1:0] = 01

CURRENT_SRC_CH0[1:0] = 10

CURRENT_SRC_CH0[1:0] = 11

4.5

14.45

19.2

5.13

15.55

20.7

5.75

16.65

22.1

GPADC_IN0 current source

µA

SMPS current monitoring

(GPADC Channel 11)

See 公式 1 and 公式 2

Channel 11 SMPS output

current measurement gain

factor

I_FS0

3.958

A

Channel 11 SMPS output

current measurement current

offset

I_OS0

0.652

Channel 11 SMPS output

current measurement

temperature coefficient

ppm/

C

TC_R0

–1090

SMPS3, SMPS6, SMPS7 I_{L_error}(%) = I_{L_meas}/ I_L

100 at 1 A, 25°C

×

–13%

–9%

13%

9%

SMPS6, SMPS7 I_{L_error}(%) = I_{LOAD_meas}/ I_L× 100

at 2 A, 25°C

SMPS output current

measurement Accuracy, I_ERR

(%), GPADC trimmed

SMPS3 I_{L_error}(%) = I_{L_meas}/ I_L× 100 at 3 A, 25°C

SMPS45 I_{L_error}(%) = I_{L_meas}/ I_L× 100 at 4 A, 25°C

–8%

–7%

8%

7%

SMPS12 I_{L_error}(%) = I_{L_meas}/ I_L× 100 at 6 A,

25°C,

–7%

7%

SMPS123 I_{L_error}(%) = I_{L_meas}/ I_L× 100 at 9 A,

25°C

Specifications

27

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

5.13 Electrical Characteristics: Thermal Monitoring and Shutdown

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Rising threshold, THERM_HD_SEL[1:0] = 00

Falling threshold, THERM_HD_SEL[1:0] = 00

Rising threshold, THERM_HD_SEL[1:0] = 01

Falling threshold, THERM_HD_SEL[1:0] = 01

Rising threshold, THERM_HD_SEL[1:0] = 10

Falling threshold, THERM_HD_SEL[1:0] = 10

Rising threshold, THERM_HD_SEL[1:0] = 11

Falling threshold, THERM_HD_SEL[1:0] = 11

Rising threshold

MIN

104

95

TYP

117

108

121

112

125

116

130

120

148

123

MAX UNIT

129

119

109

99

133

124

°C

Hot-die temperature

threshold

113

104

117

108

133

111

136

128

143

132

163

°C

Thermal shutdown threshold

Falling threshold

135

Off ground current (two

sensors on the die,

specification for one sensor)

Device in OFF state, V_CC1= 3.8 V, T = 25°C

0.1

I_Q(off)

µA

Device in OFF state

0.5

On ground current (two

sensors on the die,

specification for one sensor)

Device in ACTIVE state, V_CC1= 3.8 V, T = 25°C

Device in ACTIVE state, GPADC measurement

7

15

I_Q(on)

µA

25

40

5.14 Electrical Characteristics: System Control Thresholds

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2

TYP

2.15

2

MAX UNIT

POR (power-on reset) rising-edge threshold Measured on VCC1 pin

2.5

2.1

V

POR falling-edge threshold

POR hysteresis

Measured on VCC1 pin

Rising edge to falling edge

Voltage range, 50-mV steps

Voltage accuracy

1.9

40

300 mV

3.10

2.75

–50

75

V

VSYS_LO, measured on VCC1 pin

VSYS_LO hysteresis

95 mV

Falling edge to rising edge

Voltage range, 50-mV steps

Voltage accuracy

460 mV

2.9

–55

2.75

–70

2.9

2.8

3.85

105 mV

4.6

140 mV

V

VSYS_HI, measured on VCC_SENSE pin

Voltage range, 50-mV steps

Voltage accuracy

V

VSYS_MON, measured on VCC_SENSE

Rising Threshold

3.6

3.3

V

VBUS Detection (VBUS wake-up

comparator threshold)

Falling Threshold

5.15 Electrical Characteristics: Current Consumption

Over operating free-air temperature range, typical values are at T_A= 27°C (unless otherwise noted)

PARAMETER

OFF MODE

TEST CONDITIONS

MIN

TYP

MAX UNIT

Current consumption in

OFF mode

VSYS (VCC1) = 3.8 V

20

45

µA

SLEEP MODE

LDO2 and LDO9 enabled without load, VSYS (VCC1) = 3.8 V

16-MHz oscillator completely disabled

120

150

180

225

µA

with system clock coming solely on

internal 32KHz RC oscillator

VSYS (VCC1) = 5.25 V

Current consumption in

SLEEP mode

VSYS (VCC1) = 3.8 V

VSYS (VCC1) = 5.25 V

2.64

3.3

2.81

3.5

LDO2 and LDO9 enabled without load,

16-MHz oscillator enabled

mA

28

Specifications

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

5.16 Electrical Characteristics: Digital Input Signal Parameters

Over operating free-air temperature range, typical values are at T_A= 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1

pin (unless otherwise noted)

PARAMETER

PWRON, RPWRON

TEST CONDITIONS

MIN

TYP

MAX UNIT

Low-level input voltage

related to VSYS (VCC1 pin

reference)

0.35 ×

V

V_IL

V_IH

–0.3

0

VSYS

High-level input voltage

related to VSYS (VCC1 pin

reference)

VSYS +

0.65 ×

VSYS

0.3 ≤

5.25

V

0.05 ×

VSYS

Hysteresis

ENABLE1, GPIO_4, GPIO_6, I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SCL_SCE, I2C2_SDA_SDO

Low-level input voltage

related to VIO (VIO_IN pin

reference)

0.3 ×

VIO

V_IL

V_IH

–0.3

0

V

High-level input voltage

related to VIO (VIO_IN pin

reference)

0.7 ×

VIO

VIO +

0.3

VIO

V

0.05 ×

VIO

Hysteresis

Capacitive load for SDA and

SCL in I2C mode

C_B

400 pF

BOOT0, PWRDOWN, RESET_IN, NSLEEP, NRESWARM, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_5, GPIO_7 OR POWERHOLD

Low-level input voltage

related to VRTC

0.3 ×

VRTC

V_IL

V_IH

–0.3

0

V

High-level input voltage

related to VRTC

0.7 ×

VRTC

VRTC +

0.3

VRTC

0.05 ×

VRTC

Hysteresis

Input voltage maximum for

RESET_IN and GPIO_7

5.25

BOOT1

Low-level input voltage

related to VRTC

0.3 ×

VRTC

V_IL

–0.3

0

V

High-level input voltage

related to VRTC

0.95 ×

VRTC

VRTC +

0.3

V_IH

VRTC

5.17 Electrical Characteristics: Digital Output Signal Parameters

Over operating free-air temperature range, typical values are at T_A= 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1

pin (unless otherwise noted)

PARAMETER

REGEN1, REGEN2

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_OL= 2 mA

0

0.45

0.2

V

Low-level output voltage,

push-pull and open-drain

V_OL

I_OL= 100 µA

VSYS –

0.45

I_OH= 2 mA

VSYS

V

High-level output voltage ,

push-pull

V_OH

VSYS –

0.2

I_OH= 100 µA

Supply for external pullup

resistor, open-drain

GPIO_1 or VBUSDET, GPIO_2

Low-level output voltage,

push-pull and open-drain

V_OL

I_OL= 10 mA

0

0.4

V

Specifications

29

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Electrical Characteristics: Digital Output Signal Parameters (continued)

Over operating free-air temperature range, typical values are at T_A= 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1

pin (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VSYS –

0.45

I_OH= 2 mA

VSYS

V

High-level output voltage,

push-pull

V_OH

VSYS –

0.2

I_OH= 100 µA

Supply for external pullup

resistor, open-drain

INT

I_OL= 2 mA

0

0.45

0.2

V

Low-level output voltage,

push-pull and open-drain

V_OL

I_OL= 100 µA

VIO –

0.45

High-level output voltage,

push-pull (VIO_IN pin

reference)

I_OH= 2 mA

VIO

V

V_OH

I_OH= 100 µA

VIO – 0.2

Supply for external pullup

resistor, open-drain

GPIO_4 or SYSEN1, GPIO_6 or SYSEN2, RESET_OUT

I_OL= 2 mA

0

0.45

0.2

V

Low-level output voltage,

push-pull

V_OL

I_OL= 100 µA

VIO –

0.45

High-level output voltage,

push-pull (VIO_IN pin

reference)

I_OH= 2 mA

VIO

V

V_OH

I_OH= 100 µA

VIO – 0.2

POWERGOOD

I_OL= 2 mA

0

0.45

0.2

V

Low-level output voltage,

open-drain

V_OL

I_OL= 100 µA

Supply for external pullup

resistor, open-drain

VRTC

V

GPIO5

I_OL= 2 mA

I_OL= 100 µA

I_OL= 2 mA

I_OL= 100 µA

0

0.45

0.2

V

Low-level output voltage,

open-drain

V_OL

0.45

0.2

Low-level output voltage,

push-pull

V_OL

VRTC –

0.45

I_OH= 2 mA

VRTC

V

High-level output voltage,

push-pull

V_OH

VRTC –

0.2

I_OH= 100 µA

Supply for external pullup

resistor, open-drain

CLK32KGO1V8, SYNCCLKOUT

I_OL= 1 mA

0

0.45

0.2

V

Low-level output voltage,

push-pull

V_OL

I_OL= 100 µA

VRTC –

0.45

I_OH= 1 mA

VRTC

V

High-level output voltage,

push-pull

V_OH

VRTC –

0.2

I_OH= 100 µA

CLK32KGO

I_OL= 1 mA

0

0.45

0.2

V

Low-level output voltage,

push-pull

V_OL

I_OL= 100 µA

VIO –

0.45

High-level output voltage,

push-pull

(VIO_IN pin reference)

I_OH= 1 mA

VIO

V

V_OH

I_OH= 100 µA

VIO – 0.2

30

Specifications

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Electrical Characteristics: Digital Output Signal Parameters (continued)

Over operating free-air temperature range, typical values are at T_A= 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1

pin (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

GPIO_0, GPIO_3, GPIO_7

External pullup to VRTC, I_OL= 2 mA

External pullup to VRTCI_OL= 100 µA

0

0.45

0.2

V

Low-level output voltage,

open-drain

V_OL

Maximum supply for external

pullup resistor, open-drain

5.25

V

I2C1_SDA_SDI, I2C2_SDA_SDO

Low-level output voltage V_OL

related to VIO (VIO_IN pin

reference)

0.1 ×

VIO

0.2 ×

VIO

3-mA sink current

0

V

Capacitive load for

I2C2_SDA_SDO

in SPI mode

C_B

20 pF

5.18 Electrical Characteristics: I/O Pullup and Pulldown Resistance

Over operating free-air temperature range, VIO refers to the VIO_IN pin, VSYS to refers to the VCC1 pin (unless otherwise

noted)

PULLUP

SUPPLY

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PWRON, RPWRON pullup resistance, fixed

pullup

VSYS

55

120

400

370

kΩ

PWRDOWN pulldown resistance

BOOT1 pullup resistance

—

VRTC

—

180

900

13.5

900

950

900

950

kΩ

GPIO_0 pulldown resistance

180

170

180

170

400

GPIO_1, GPIO_2 pullup resistance

GPIO_1, GPIO_2 pulldown resistance

GPIO_3, RESET_IN pulldown resistance

GPIO_4, GPIO_6 pullup resistance

GPIO_4, GPIO_6 pulldown resistance

GPIO_5 pullup resistance

VSYS

—

VIO

—

VRTC

—

GPIO_5 pulldown resistance

GPIO_7 or POWERHOLD pulldown

resistance

—

180

400

900

kΩ

NSLEEP, ENABLE1 pullup resistance

NSLEEP, ENABLE1 pulldown resistance

NRESWARM pullup resistance

VRTC

—

170

78

400

120

950

225

kΩ

VRTC

Specifications

31

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

5.19 I²C Interface Timing Requirements

Over operating free-air temperature range^(1)(2)(3)(4). For the timing diagram for fast and standard (F/S) modes, see 图 5-1. For

the timing diagram for high-speed (HS) mode, see 图 5-2.

MIN

MAX UNIT

Standard mode

100 kHz

Fast mode

400 kHz

High-speed mode (write operation), C_B– 100 pF max

High-speed mode (read operation), C_B– 100 pF max

High-speed mode (write operation), C_B– 400 pF max

High-speed mode (read operation), C_B– 400 pF max

Standard mode

3.4 MHz

ƒ_(SCL)

SCL clock frequency

3.4 MHz

1.7 MHz

µs

4.7

1.3

4

Bus free time between a STOP

and START condition

t_BUF

Fast mode

µs

Standard mode

µs

Hold time (REPEATED) START

condition

t_HD, t_STA

Fast mode

600

160

4.7

1.3

160

320

4

ns

High-speed mode

ns

Standard mode

µs

Fast mode

µs

t_LOW

Low period of the SCL clock

High period of the SCL clock

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

ns

µs

Fast mode

600

60

ns

t_HIGH

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

ns

120

4.7

600

160

250

100

10

ns

µs

Setup time for a REPEATED

START condition

t_SU, t_STA

Fast mode

ns

High-speed mode

ns

Standard mode

ns

t_SU, t_DAT

Data setup time

Data hold time

Fast mode

ns

High-speed mode

ns

Standard mode

0

3.45

0.9

µs

ns

Fast mode

0

t_HD, t_DAT

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

0

70

0

150

20 + 0.1

C_B

Standard mode

Fast mode

1000

300

ns

20 + 0.1

C_B

t_RCL

Rise time of the SCL signal

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

10

20

40

80

ns

20 + 0.1

C_B

Standard mode

Fast mode

1000

300

ns

Rise time of the SCL signal

after a REPEATED START

condition and after an

acknowledge bit

20 + 0.1

C_B

t_RCL1

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

10

20

80

ns

160

(1) Specified by design. Not tested in production.

(2) All values referred to V_IH(min)and V_IH(max)levels.

(3) For bus line loads C_Bbetween 100 and 400pF, the timing parameters must be linearly interpolated.

(4) A device must internally provide a data hold time to bridge the undefined part between V_IHand V_ILof the falling edge of the SCLH

signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.

32

Specifications

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

I²C Interface Timing Requirements (continued)

Over operating free-air temperature range^(1)(2)(3)(4). For the timing diagram for fast and standard (F/S) modes, see 图 5-1. For

the timing diagram for high-speed (HS) mode, see 图 5-2.

MIN

MAX UNIT

20 + 0.1

C_B

Standard mode

Fast mode

300

ns

20 + 0.1

C_B

t_FCL

Fall time of the SCL signal

Rise time of the SDA signal

Fall time of the SDA signal

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

10

20

40

80

ns

20 + 0.1

C_B

Standard mode

Fast mode

1000

300

ns

20 + 0.1

C_B

t_RDA

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

10

20

80

ns

160

20 + 0.1

C_B

Standard mode

Fast mode

300

ns

20 + 0.1

C_B

t_FDA

High-speed mode, C_B– 100 pF max

High-speed mode, C_B– 400 pF max

Standard mode

10

20

80

ns

µs

ns

160

4

Setup time for a STOP

condition

t_SU, t_STO

Fast mode

600

160

High-speed mode

5.20 SPI Timing Requirements

For the SPI timing diagram, see 图 5-3.

MIN

30

67

20

5

MAX UNIT

t_cesu

t_cehld

t_ckper

t_ckhigh

t_cklow

t_sisu

Chip-select setup time

ns

Chip-select hold time

Clock cycle time

100

ns

Clock high typical pulse duration

Clock low typical pulse duration

Input data setup time, before clock active edge

Input data hold time, after clock active edge

Data retention time

t_sihld

t_dr

5

15

t_CE

Time from CE going low to CE going high

67

SDA

SCL

t

BUF

t

f

t

f

LOW

t

su;DAT

t

r

t

r

hd;STA

t

hd;STA

su;STA

su;STO

t

hd;DAT

HIGH

Sr

S

P

S

图 5-1. Serial Interface Timing Diagram for F/S Mode

Specifications

33

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Sr

P

t

fDA

t

rDA

SDA (HS)

t

hd;DAT

t

su;STO

t

su;DAT

t

su;STA

hd;STA

SCL (HS)

t

fCL1

t

rCL1

t

rCL

t

HIGH

LOW

HIGH

LOW

See Note A

= MCS Current Source Pullup

= R Resistor Pullup

See Note A

(P)

Note A: First rising edge of the SCL (HS) signal after Sr and after each acknowledge bit.

图 5-2. Serial Interface Timing Diagram For HS Mode

SPI chip select

t

ckper

t

ckhigh

t

cklow

t

cehld

t

cesu

SPI clock enable

t

sisu

t

sihld

Address

SPI data input

SPI data output

R/W

Data

Unused

t

dr

Don’t care

SPI_Timing

图 5-3. SPI Interface Timing Diagram

34

Specifications

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

5.21 Typical Characteristics

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_O= 0.7 V

V_O= 1.2 V

V_O= 1.05 V

V_O= 1.2 V

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

4.4 4.8

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

Load Current (mA)

Load Current (A)

D010

D009

V_I= 3.8 V

ƒ_S= 2.2 MHz

V_I= 3.8 V

ƒ_S= 2.2 MHz

图 5-4. SMPS Efficiency for Multi-Phase

ECO-mode

图 5-5. SMPS Efficiency for 4-A Multi-Phase

PWM Mode

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_O= 1.05 V

V_O= 1.2 V

V_O= 1.05 V

V_O= 1.2 V

0

0.6 1.2 1.8 2.4

3

3.6 4.2 4.8 5.4

6

0

0.8 1.6 2.4 3.2

4

4.8 5.6 6.4 7.2

8

8.8

Load Current (A)

D008

D007

V_I= 3.8 V

ƒ_S= 2.2 MHz

V_I= 3.8 V

ƒ_S= 2.2 MHz

图 5-6. SMPS Efficiency for 6-A Multi-Phase

PWM Mode

图 5-7. SMPS Efficiency for 9-A Multi-Phase

PWM Mode

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

V_O= 0.7 V

V_O= 1.05 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

V_O= 3.3 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

V_O= 3.3 V

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

4.4 4.8

0

0.2

0.4

0.6

0.8

1

Load Current (mA)

Load Current (A)

D006

D005

V_I= 3.8 V

ƒ_S= 2.2 MHz

V_I= 3.8 V

ƒ_S= 2.2 MHz

图 5-8. SMPS Efficiency for 1-A Single-Phase

ECO-mode

图 5-9. SMPS Efficiency for 1-A Single-Phase

PWM Mode

Specifications

35

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Typical Characteristics (continued)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_O= 0.7 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

V_O= 3.3 V

V_O= 1.05 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

V_O= 3.3 V

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

4.4 4.8

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

Load Current (mA)

Load Current (A)

D004

D003

V_I= 3.8 V

ƒ_S= 2.2 MHz

V_I= 3.8 V

ƒ_S= 2.2 MHz

图 5-10. SMPS Efficiency for 2-A Single-Phase

ECO-ode

图 5-11. SMPS Efficiency for 2-A Single-Phase

PWM Mode

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_O= 0.7 V

V_O= 1.05 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

V_O= 3.3 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

V_O= 3.3 V

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

4.4 4.8

0

0.4

0.8

1.2

1.6

2

2.4

2.8

Load Current (mA)

Load Set (A)

D002

D001

V_I= 3.8 V

ƒ_S= 2.2 MHz

V_I= 3.8 V

ƒ_S= 2.2 MHz

图 5-12. SMPS Efficiency for 3-A Single-Phase

ECO-mode

图 5-13. SMPS Efficiency for 3-A Single-Phase

PWM Mode

36

Specifications

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

6 Detailed Description

6.1 Overview

The TPS659038-Q1 and TPS659039-Q1 device are integrated power management integrated circuits

(PMIC), both available in a 169-pin, 0.8-mm pitch, 12-mm x 12-mm nFBGA package. They are designed

specifically for automotive applications. Both devices provide seven configurable step-down converter

rails, with the ability to combine power rails and supply up to 9 A of output current in multi-phase mode.

The TPS659038-Q1 device also provides eleven external LDOs, while the TPS659039-Q1 device provides

six external LDOs. Both devices also come with a 12-bit GPADC with three external channels, eight

configurable GPIOs, two I²C interface channels or one SPI interface channel, real-time clock module with

calendar function, PLL for external clock sync and phase delay capability, and programmable power

sequencer and control for supporting different processors and applications.

The seven step-down converter rails are consisting of nine high frequency switch mode converters with

integrated FETs. They are capable of synchronizing to an external clock input and supports switching

frequency between 1.7 MHz and 2.7 MHz. The SMPS12 and SMPS45 devices are dual-phase step-down

converters, which can combine with the SMPS3 or SMPS7 device respectively and become triple-phase

converters. In addition, the SMPS12, SMPS45, SMPS6, and SMPS8 device support dynamic voltage

scaling by a dedicated I²C interface for optimum power savings.

The TPS659038-Q1 device contains 11 LDO regulators while the TPS659039-Q1 device contains six LDO

regulators for external use. All of the LDOs support 0.9 V to 3.3 V output with 50-mV step. The devices

are fully controllable by the I²C interface and can be supplied from either a system supply or a

preregulated supply.

All LDOs and step-down converters can be controlled by the SPI or I²C interface, or by power request

signals. In addition, voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I²C,

or roof and floor control.

The power-up and power-down controller is configurable and programmable through OTP. The

TPS65903x-Q1 devices include a 32-kHz RC oscillator to sequence all resources during power up and

power down. In cases where a fast start up is required, a 16-MHz crystal oscillator is also included to

quickly generate a stable 32-kHz for the system. The device also includes an RTC module which provides

date, time, calendar, and alarm capability, which is best utilized when a 16-MHz crystal or an external and

high accuracy 32-kHz clock is present.

Eight Configurable GPIOs with multiplexed feature are available on the TPS659038-Q1 and TPS659039-

Q1 devices. Three of the GPIOs, together with the REGEN1 pin can be configured and used as enable

signals for external resources, which can be included into the power-up and power-down sequence. Both

devices also include a general-purpose (GP) sigma-delta analog-to-digital converter (ADC) with three

external input channels, which can be used as thermal or voltage and current monitors.

CAUTION

When operating the TPS659038-Q1 and TPS659039-Q1 devices using silicon

revision 1.3 or earlier, without an external crystal, each SMPS regulating an

output voltage greater than 1.8 V must be disabled before VCC is removed.

Lowering VCC below the programmed VSYS_LO level while any SMPS is

regulating an output voltage above 1.8 V may cause damage to the device.

See 节 6.3.10 to identify the silicon version in the device.

Detailed Description

37

Submit Documentation Feedback

Product Folder Links: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

6.2 Functional Block Diagrams

BOOT0

BOOT1

SMPS1_IN

SMPS1

3 A

(DVS)

SMPS1_SW

PWRON

LDOVANA LDOVRTC

PwrMgmt

RESET_IN

[Slave]

Control

inputs

SMPS1_GND

SMPS2_IN

Test and program

PWRDOWN

RPWRON

VCC internal supply

Dual-

phases

EN

VSEL

RAMP

SMPS2

3 A

(DVS)

ENABLE1

NSLEEP

SMPS2_SW

SMPS1_2_FDBK

SMPS1_2_FDBK_GND

SMPS2_GND

NRESWARM

TPS659038-Q1

TPS659039-Q1

[Master]

I2C1_SCL_CLK

I2C1_SDA_SDI

I2C2_SCL_SCE

I2C2_SDA_SDO

I²C CNTL,

I²C DVS

or SPI

Triple-

phases

SMPS3

3 A

[Multi or

Stand-

alone]

SMPS3_IN

JTAG

EN

SMPS3_SW

DFT

VSEL

SMPS3_FDBK

RESET_OUT

INT

OTP controller

OTP memory

Control

outputs

SMPS3_GND

REGEN1

Internal

interrupt

events

Registers

SMPS4_IN

SMPS4

2 A

(DVS)

POWERGOOD

GPIO_0

SMPS4_SW

VCC1

POR

[Master]

SMPS4_GND

SMPS5_IN

EN

VSEL

RAMP

VBUSDET

Dual-

phases

Programmable power

sequencer controller

VCC1

VSYS_LO

GPIO_1

GPIO_2

SMPS5

2 A

(DVS)

REGEN2

SMPS5_SW

ECO

PWM

DVS

VCC_SENSE

VSYS_MON

SMPS4_5_FDBK

SMPS4_5_FDBK_GND

SMPS5_GND

[Slave]

GPIO_3

GPIO_4

Switch ON or OFF

SYSEN1

Triple-

phases

SMPS7

2 A

[Multi or

Stand-

alone]

SMPS7_IN

VBUS_SENSE

VBUS_WKUP

EN

SMPS7_SW

GPIO_6

GPIO_7

SYSEN2

SMPS7_FDBK

VSEL

WDT

SMPS7_GND

SMPS6_IN

POWERHOLD

CLK32KGO1V8

GPIO_5

EN

SMPS6_SW

SMPS6

2 A

(DVS)

OSC16MIN

VSEL

SMPS6_FDBK

RAMP

16-MHz

SMPS6_GND

SMPS8_IN

oscillator

OSC16MOUT

RTC

Internal

RC

32 kHz

RC

OSC16MCAP

CLK32KGO

EN

VSEL

RAMP

oscillator

SMPS8_SW

SMPS8

1 A

(DVS)

SMPS8_FDBK

Output

buffers

SMPS8_GND

SMPS9_IN

SYNCDCDC

EN

SMPS9_SW

SMPS9

1 A

GPADC_IN0

GPADC_IN1

GPADC_IN2

VSEL

SMPS9_FDBK

SMPS9_GND

12-bit

SD-ADC

Thermal

monitoring

GPADC_VREF

Thermal shutdown

Hot die detection

GND_DIG

GND_ANA

PBKG

Grounds

VBG

Reference

and

REFGND1

bias

Bypass

LDO9

50 mA

SDIO

(1)

LDOLN

50 mA

LDO1

300 mA

LDO2

300 mA

LDO3

300 mA

LDO4

300 mA

LDO5

200 mA

LDO8

170 mA

LDO6

200 mA

LDOUSB

100 mA

LDO7

200 mA

(1) Only available on the TPS659038-Q1 device.

Figure 6-1. Functional Block Diagram of TPS659038-Q1 and TPS659039-Q1

38

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

6.3 Feature Description

6.3.1 Power Management

The TPS65903x-Q1 device series integrates an embedded power controller (EPC) that fully manages the

state of the device during power transitions. According to four defined types of requests (ON, OFF, WAKE,

and SLEEP), the EPC executes one of the five predefined power sequences (OFF2ACT, ACT2OFF,

SLP2OFF, ACT2SLP, and SLP2ACT) to control the state of the device resources. Any resource can be

included in any power sequence. When a resource is not controlled or configured through a power

sequence, the resource remains in the default state of the resource (from OTP).

Each resource is configured only through register bits. Therefore, a resource can be controlled statically

by the user through the control interfaces (I²C or SPI) or controlled automatically by the EPC during power

transitions (predefined sequences of registers accesses).

The EPC is powered by an internal LDO which is automatically enabled when VSYS is available to the

device. It is important to ensure that VSYS (which is connected to VCC1, VCC_SENSE, and may also be

connected to SMPSx_In and LODx_IN as suggested in the device block diagram) is the first supply

available to the device to guarantee proper operation of all the power resources provided by the device. It

is also important that VSYS is stable prior to VIO supply is available to ensure proper operation of the

control interface and device IOs.

6.3.2 Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)

The power resources provided by the TPS659038-Q1 and TPS659039-Q1 devices include inductor-based

SMPSs and linear low-dropout voltage regulators (LDOs). These supply resources provide the required

power to the external processor cores, external components, and to modules embedded in the devices. 表

6-1 lists the power sources provided by the TPS65903x-Q1 devices.

表 6-1. Power Sources

RESOURCE

TYPE

VOLTAGE

CURRENT

COMMENTS

Can be used as one triple-phase regulator (9 A)

or one dual-phase (6 A) and single-phase (3 A)

regulators

SMPS1, SMPS2,

and SMPS3

0.5 to 1.65 V, 10-mV steps

1 to 3.3 V, 20-mV steps

SMPS

9 A

Can be used as one triple-phase regulator (6 A)

or one dual-phase (4 A) and single-phase (2 A)

regulators

SMPS4, SMPS5,

and SMPS7

0.5 to 1.65 V, 10-mV steps

1 to 3.3 V, 20-mV steps

SMPS

6 A

0.5 to 1.65 V, 10-mV steps

1 to 3.3 V, 20-mV steps

Can be configured as 2-A or 3-A SMPS through

OTP programming

SMPS6

SMPS8

SMPS9

SMPS

2 A or 3 A

1 A

0.5 to 1.65 V, 10-mV steps

1 to 3.3 V, 20-mV steps

0.5 to 1.65 V, 10-mV steps

1 to 3.3 V, 20-mV steps

1 A

LDO1

LDO2

LDO

0.9 to 3.3 V, 50-mV steps

300 mA

200 mA

50 mA

LDO3

LDO4

LDO5

LDO6

LDO7

LDO8

LDO9

LDOLN

LDOUSB

50 mA

100 mA

Detailed Description

39

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

6.3.2.1 Step-Down Regulators

The synchronous step-down converter used in the power-management core has high efficiency while

enabling operation with small and cost-competitive external components. The SMPSx_IN supply terminals

of all the converters can be individually connected to the VSYS supply (VCC1 terminal). Four of these

configurable step-down converters are multi-phased to create up to 4-A and 6-A rails, while another

converter can be combined to these 2 rails to create 2 rails up to 9 A and 6A of output current. All of the

step-down converters can synchronize to an external clock source between 1.7 Mhz and 2.7 MHz, or an

internal fall back clock at 2.2 MHz.

The step-down converter supports two operating modes, which can be selected independently:

Forced PWM mode: In forced PWM mode, the device avoids pulse skipping and allows easy filtering of

the switch noise by external filter components. The drawback is the higher IDDQ at low

output current levels.

ECO-mode (lowest quiescent current mode): Each step-down converter can be individually controlled

to enter a low quiescent current mode. In ECO-mode, the quiescent current is reduced and

the output voltage is supervised by a comparator while most parts of the control are disabled

to save power. The regulators should not be enabled under ECO-mode in order to ensure

the stability of the output. ECO-mode should be enabled only when a converter has less

than 5 mA of load current and V_Ocan remain constant. In addition, ECO-mode should be

disabled before a load transient step to let the converter respond in a timely manner to the

excess current draw. To ensure proper operation of the converter while it is in ECO-mode,

the output voltage level must be less then 70% of the input supply voltage level. If the V_Oof

the converter is greater than 2.8V, a safety feature of the device will monitor the supply

voltage of the converter, and automatically shut down the converter if the input voltage falls

below 4V. The purpose of this safety mechanism is to prevent damage to the converter due

to design limitation while the converter is in ECO mode.

In addition to the operating modes, the following parameters can be selected for the regulators:

Powergood: The POWERGOOD signal high indicates that all SMPS outputs are within 10% (typical

case) of the programmed value. The individual power good signal of a switching regulator is

blanked when the regulator is disabled or when the regulator voltage transitions from one set

point to another.

Output discharge: Each switching regulator is equipped with an output discharge enable bit. When this

bit is set to 1, the output of the regulator is discharged to ground with the equivalent of a 9-Ω

resistor when the regulator is disabled. If the regulator enable bit is set, the discharge bit of

the regulator is ignored.

Output current monitoring: GPADC can monitor the SMPS output current. One SMPS at a time can be

selected for measurement from the following: SMPS12, SMPS3, SMPS123, SMPS45,

SMPS457, SMPS6 and SMPS7. Selection is controlled through the GPADC_SMPS

_ILMONITOR_EN register.

Step-down converter ENABLE: The step-down converter enable and disable is part of the flexible

power-up and power-down state-machine. Each converter can be programmed so that it is

powered up automatically to a preselected voltage in one of the time slots after a power-on

condition occurs. Alternatively, each SMPS can be controlled by a dedicated terminal.

Terminals NSLEEP and ENABLE1 can be mapped to any resource (LDOs, SMPS converter,

32-kHz clock output or GPIO) to enable or disable it. Each SMPS can also be enabled and

disabled through I²C register access.

40

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

6.3.2.1.1 Sync Clock Functionality

The TPS65903x-Q1 device contains a SYNCDCDC input to sync DC-DCs with the external clock.

In forced PWM mode, SMPSs are synchronized on an external input clock (SYNCDCDC) whereas in

ECO-mode, or if the SYNCDCDC pin is grounded, the switching frequency is based on an internal RC

oscillator. The clock generated from the internal RC oscillator can be output through GPIO5 to provide

synchronization clock to external SMPSs. For PWM mode, a PLL is present to buffer the external input

clock to create nine clock signals for the nine SMPSs with different phases.

The sync clock dither specification parameters are based on a triangular dither pattern, but other patterns

that comply with the minimum and maximum sync frequency range and the maximum dither slope can

also be used.

f_SYNC

M_DITHER

T_DITHER

f_{SYNC, MAX}

A_DITHER

f_{SYNC, MIN}

t

图 6-2. Sync Clock Range and Dither

The ollowing figure shows ƒ_SYNC, the frequency of SYNCDCDC input clock and ƒ_S, the frequency of PLL

output signal.

When there is no clock present on SYNCDCDC ball, the PLL generates a clock with a frequency equal to

ƒ_FALLBACK

If a clock is present on SYNCDCDC ball with a frequency between ƒ_SAT,LOand ƒ_SAT,HI, then the PLL is

synchronised on SYNCDCDC clock and generates a clock with frequency equal to f_SYNC

If ƒ_SYNCis higher than ƒ_SAT,HI, then the PLL generates a clock with a frequency equal to ƒ_SAT,HI

If f_SYNCis smaller than ƒ_SAT,LO, then the PLL generates a clock with a frequency equal to ƒ_SAT,LO

.

Detailed Description

41

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

t_SETTLE

f_{SAT, HI}

f_A

f_FALLBACK

f_SW

f_{SAT, LO}

t_SETTLE

f_{SAT, HI}

f_A

f_SYNC

f_{SAT, LO}

No Clock

图 6-3. Sync Clock Saturation and Frequency Fallback

6.3.2.1.2 Output Voltage and Mode Selection

The default output voltage and enabling of the regulator during startup sequence is defined by OTP bits.

After start-up the software can change the output voltage with the RANGE and VSEL bits in the

SMPSx_VOLTAGE register. The value 0x0 disables the SMPS (OFF).

The operating mode of an SMPSx when the TPS65903x-Q1 device is in ACTIVE mode can be selected in

SMPSx_CTRL register with MODE_ACTIVE[1:0].

The operating mode of an SMPSx when the TPS65903x-Q1 device is in SLEEP mode is controlled by

MODE_SLEEP[1:0] bit depending on SMPS assignment to NSLEEP and ENABLE1, see 表 6-13.

Soft-start slew rate is fixed (T_ramp).

The pulldown discharge resistance for OFF mode is enabled and disabled in the SMPS_PD_CTRL

register. By default, discharge is enabled.

SMPS behavior for warm reset (reload default values or keep current values) is defined by the

SMPSx_CTRL.WR_S bit.

6.3.2.1.3 Current Monitoring and Short Circuit Detection

The step-down converters include several other features.

The SMPS sink current limitation is controlled with the SMPS_NEGATIVE_CURRENT_LIMIT_EN register.

The limitation is enabled by default.

Channel 11 of the GPADC can be used to monitor the output current of SMPS12, SMPS3, SMPS123,

SMPS45, SMPS457, SMPS6, or SMPS7. Load current monitoring is enabled for a given SMPS in the

SMPS_ILMONITOR_EN register. SMPS output power monitoring is intended to be used during the steady

state of the output voltage, and is supported in PWM mode only.

Use 公式 1 as the basic equation for the SMPS output current result.

I_FSì GPADC code

I_L=

-I_OS

2¹²-1

(

)

where

•

I_FS= I_FS0× K (K is the number of active SMPS phases)

I_OS= I_OS0× K (K is the number of active SMPS phases)

(1)

42

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Use 公式 2 to calculate the temperature compensated result.

I_FSì GPADC code

I_L=

-I_OS

12

»

ÿ

» ÿ

-1 ì 1+ TC_R0 ì Temperature - 25

2

(

)

⁄

(

)

⁄

(2)

For values of I_FS0and I_OS0, see Section 5.12.

The SMPS thermal monitoring is enabled (default) and disabled with the SMPS_THERMAL_EN register.

When enabled, the SMPS thermal status is available in the SMPS_THERMAL_STATUS register. SMPS12

and SMPS3 have shared thermal protection, in effect, if SMSP12 triggers the thermal protection, then

SMPS3 operating in stand-alone mode is disabled. There is no dedicated thermal protection in SMPS8 or

SMPS9.

Each SMPS has a detection for load current above I_LIM, indicating overcurrent or shorted SMPS output. A

register SMPS_SHORT_STATUS indicates any SMPS short condition. Depending on the interrupt short

line mask bit register (INT2_MASK.SHORT), an interrupt is generated upon any shorted SMPS. If a short

situation occurs on any enabled SMPSs, the corresponding short status bit is set in the

SMPS_SHORT_STATUS register. A switch-off signal is then sent to the corresponding SMPS, and the

SMPS remains off until the corresponding bit in the SMPS_SHORT_STATUS register is cleared. The

SMPS_SHORT_STATUS register is cleared when read, or by issuing a POR. The same behavior applies

to LDO shorts using the LDO_SHORT_STATUS registers.

A short must occur on any enabled SMPS or LDO for at least 155 us to 185 us for the short detection to

shut off the rail. During startup of the device, there is a 2 ms counter that masks any short-circuit

shutdown. This counter starts when the device is enabled and the counter is reset when any SMPSx or

LDOx rail becomes ACTIVE. When no rail has been enabled for 2 ms, the counter reaches its threshold

and the short-circuit shutdown is no longer masked for the enabled SMPSs and LDOs.

6.3.2.1.4 POWERGOOD

The external POWERGOOD terminal indicates if the outputs of the SMPS are correct or not (图 6-4).

Either voltage and current monitoring or a current monitoring only can be selected for POWERGOOD

indication. This selection is common for all SMPSs in the SMPS_POWERGOOD_MASK2

.POWERGOOD_TYPE_SELECT bit register. When both voltage and current are monitored,

POWERGOOD signal active (polarity is programmable) indicates that all SMPS outputs are within certain

percentage, V_SMPSPG, of the programmed value and that load current is below I_LIM

.

All POWERGOOD sources can be masked in the SMPS_POWERGOOD_MASK1 and

SMPS_POWERGOOD_MASK2 registers. By default, only the SMPS12 rail (or SMPS123 rail if in triple

phase) is monitored. When an SMPS is disabled, it should be masked to prevent it forcing POWERGOOD

inactive. When SMPS voltage is transitioning from one target voltage to another due to DVS command,

voltage monitoring is internally masked and POWERGOOD is not impacted.

It is also possible to include in POWERGOOD the GPADC result for SMPS output current monitoring by

setting SMPS_COMPMODE = 1. Only one SMPS can be monitored by the GPADC channel at the time.

The POWERGOOD function can also be used for monitoring an external SMPS is at the correct output

level and the load is lower than the current limit; indication is through the GPIO_7 terminal.

All

POWERGOOD

sources

can

be

masked

in

SMPS_POWERGOOD_MASK1

and

SMPS_POWERGOOD_MASK2 registers.

Detailed Description

43

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

CAUTION

The current monitor on multi-phase rails (such as SMPS12, SMPS123, or

SMPS45) may cause POWERGOOD to change to a low level (with default

polarity) when transitioning from multi-phase operation to single phase

operation. TI recommends masking the multi-phase rails as a POWERGOOD

source,

using

SMPS_POWERGOOD_MASK1,

or

debouncing

the

POWERGOOD signal if this POWERGOOD toggle is not desired in the

application design.

OVER_TEMP

INT

SMPS_SHORT_STATUS

SMPS_THERMAL_STATUS

INT2_MASK[6]

ILIM

SMPS12

SMPS3

POWERGOOD

SMPS_POWERGOOD_MASK1[0]

SMPS_POWERGOOD_MASK1[1]

POWERGOOD

SMPS_POWERGOOD_MASK1[7]

External SMPS (trrough GPIO7)

SMPS_POWERGOOD_MASK2[2]

图 6-4. POWERGOOD Block Diagram

6.3.2.1.5 DVS-Capable Regulators

The step-down converters SMPS12 or SMPS123, SMPS45 or SMPS457, SMPS6, and SMPS8 are DVS-

capable and have some additional parameters for control. The slew rate of the output voltage during

voltage level change is fixed at 2.5 mV/µs. The control for two different voltage levels (ROOF and FLOOR)

with the NSLEEP and ENABLE1 signals is available. When the ROOF_FLOOR control is not used, two

different voltage levels can be selected with the CMD bit in the SMPSx_FORCE register.

•

The output voltage slew rate for achieving new output voltage value is fixed at 2.5 mV/μs.

The NSLEEP and ENABLE1 terminals can be used for roof-floor control of SMPS. For roof-floor

operation sets the SMPSx_CTRL.ROOF_FLOOR_EN register, and assign SMPS to NSLEEP and

ENABLE1 in the NSLEEP_SMPS_ASSIGN and ENABLE1_SMPS_ASSIGN registers. When the

controlling terminal is active, the SMPS output value is defined by the SMPSx_VOLTAGE register.

When the controlling terminal is not active, the SMPS output value is defined by the SMPSx_FORCE

register.

44

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

•

Set the second value for the output voltage with the SMPSx_FORCE.VSEL register. A value of 0x0

disables the SMPS (OFF).

Select which register, SMPSx_VOLTAGE or SMPSx_FORCE, to use with the SMPSx_FORCE.CMD

bit. The default is the voltage setting of SMPSx_VOLTAGE. For the CMD bit to work, ensure that

SMPSx_CTRL.ROOF_FLOOR_EN = 0.

图 6-5 shows the SMPS controls for DVS.

Voltage control through I²C (SMPS*_CTRL.ROOF_FLOOR_EN=0)

SMPS*_VOLTAGE.VSEL, when SMPS*_FORCE.CMD=1

SMPS*_FORCE.VSEL, when SMPS*_FORCE.CMD=0

SMPS*_VOLTAGE.VSEL

SMPS*_OUT

Discharge control (pull-down)

SMPS_PD_CTRL.SMPS*

(disabled or enabled)

Tstart

I2C

VSEL[6:0] (voltage selection): OFF, 0.5 V - 1.65 V in 10-mV steps if SMPS*_VOLTAGE.RANGE = 0; 1 - 3.3 V in 20-mV steps

if SMPS*_VOLTAGE.RANGE = 1

I²C: Control through access to SMPS*_VOLTAGE, SMPS*_FORCE registers

Voltage control through external pin (SMPS*_CTRL.ROOF_FLOOR_EN=1)

SMPS*_VOLTAGE.VSEL (ACTIVE mode)

SMPS*_VOLTAGE.VSEL

SMPS*_FORCE.VSEL (SLEEP mode)

SMPS*_OUT

Discharge control (pull-down)

SMPS_PD_CTRL.SMPS*

(disabled or enabled)

Tstart

EN

EN: Control through NSLEEP or ENABLE1 (see Resources SLEEP or ACTIVE assignments table)

图 6-5. DVS – SMPS Controls

6.3.2.1.6 Non DVS-Capable Regulators

SMPS3 and SMPS7, when they are not part of the multi-phase configuration, will work as single phase

step down converters. Together with SMPS9, these are non-DVS-Capable regulators. The output voltage

slew rate is not controlled internally, and the converter will achieve the new output voltage in JUMP mode.

It is recommended that when changes to output voltage is necessary while SMPS3, SMPS7, or SMPS9

are configured as single phase converters, that the changes to their output voltages are programmed at a

rate which is slower than 2.5 mV/μs to avoid voltage overshoot or undershoot.

6.3.2.1.7 Step-Down Converters SMPS12 and SMPS123

The step-down converters SMPS1, SMPS2, and SMPS3 can be used in two different configurations:

•

SMPS12 in dual-phase configuration supporting 6-A load current and SMPS3 in single-phase

configuration supporting 3-A load current

•

SMPS123 in triple-phase configuration supporting 9-A load current

Detailed Description

45

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

SMPS1 and SMPS2 cannot be used as separate converters. In dual-phase configuration the two

interleaved synchronous buck regulator phases with built-in current sharing operate in opposite phase. In

triple-phase configuration the three interleaved synchronous buck regulator phases with built-in current

sharing operate 120° out of phase. For light loads, the converter automatically changes to 1-phase

operation.

图 6-6 shows the connections for dual-phase and triple-phase configurations.

a. Dual-Phase SMPS and Stand-Alone SMPS

b. Triple Phase SMPS

C10 (C23)

VSYS

SMPS1_IN (SMPS5_IN)

SMPS1_SW

L2 (L7)

(SMPS5_SW)

L2 (L7)

(SMPS5_SW)

SMPS1

(SMPS5)

SMPS1_GND

(SMPS5_GND)

C11, C13

[Slave]

(SMPS5_GND)

[Slave]

Vapps1

(C20, C24)

C12 (C19)

VSYS

SMPS2_IN (SMPS4_IN)

SMPS2_SW

C11, C13, C16

(C20, C24, C28)

Vapps1

SMPS2_SW

L3 (L6)

(SMPS4_SW)

L3 (L6)

(SMPS4_SW)

SMPS2

(SMPS4)

SMPS2_GND (SMPS4_GND)

[Master]

SMPS1_2_FDBK (SMPS4_5_FDBK)

SMPS1_2_FDBK_GND (SMPS4_5_FDBK_GND)

C14 (C27)

VSYS

C14 (C27)

VSYS

SMPS3_IN (SMPS7_IN)

Vapps2

C16 (C28)

SMPS3_SW

L4 (L9)

(SMPS7_SW)

SMPS3

(SMPS7)

SMPS3

(SMPS7)

SMPS3_GND (SMPS7_GND)

SMPS3_FDBK (SMPS7_FDBK)

[Stand-

alone]

[Multi]

SMPS3_FDBK (SMPS7_FDBK)

(floating)

图 6-6. Multi-Phase SMPS Connectivity

To use the SMPS123 or SMPS12 and SMPS3 in the system:

•

OTP defines dual-phase (SMPS12) operation, single-phase (SMPS3) operation, or triple-phase

(SMPS123) operation. If SMPS123 mode is selected, the SMPS12 registers control SMPS123.

•

By default SMPS123 and SMPS12 operate in multiphase mode for higher load currents and switch

automatically to single-phase mode for low load currents. Forcing multiphase operation or single-phase

operation by setting the SMPS_CTRL.SMPS123_PHASE_CTRL[1:0] bits when the SMPS123 or

SMPS12 are loaded is also possible. Under no-load condition, do not force the multiphase operation,

as this causes the SMPS to exhibit instability.

6.3.2.1.8 Step-Down Converter SMPS45 and SMPS457

The step-down converters SMPS4, SMPS5 and SMPS7 can be used in two different configurations:

•

SMPS45 in dual-phase configuration supporting 4-A load current and SMPS7 in single-phase

configuration supporting 2-A load current

•

SMPS457 in triple-phase configuration supporting 6-A load current

SMPS4 and SMPS5 cannot be used as separate converters. In dual-phase configuration the two

interleaved synchronous buck regulator phases with built-in current sharing operate in opposite phase. In

triple-phase configuration the three interleaved synchronous buck regulator phases with built-in current

sharing operate 120° out of phase. For light loads, the converter automatically changes to 1-phase

operation.

To use SMPS457 or SMPS45 and SMPS7 in the system:

46

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

•

OTP defines dual-phase (SMPS45) operation, single-phase (SMPS7) operation, or triple-phase

(SMPS457) operation. If SMPS457 mode is selected, the SMPS45 registers control SMPS457.

By default SMPS457 and SMPS45 operate in multiphase mode for higher load currents and switch

automatically to single-phase mode for low load currents. Forcing multiphase operation or single-phase

operation by setting the SMPS_CTRL.SMPS457_PHASE_CTRL[1:0] bits when the SMPS457 or

SMPS45 are loaded is also possible. Under no-load condition, do not force the multiphase operation,

as this causes the SMPS to exhibit instability.

6.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9

The SMPS3 is a buck converter supporting up to a 3-A load current, SMPS6 and SMPS7 are buck

converters supporting up to a 2-A load current. The SMPS6 can support up to 3 A if programmed in OTP

for boosted current mode. Using extended current mode increases SMPS6 current limits so to protect

external coil from damage, coil should be selected according to the higher current rating.

SMPS8 and SMPS9 are buck converters supporting up to a 1-A load current. SMPS6 and SMPS8 are

DVS-capable.

6.3.2.2 LDOs – Low Dropout Regulators

All LDOs are integrated so that they can be connected to a system supply, to an external buck boost

SMPS, or to another preregulated voltage source. The output voltages of all LDOs can be selected,

regardless of the LDO input voltage level V_I. There is no hardware protection to prevent software from

selecting an improper output voltage if the V_Iminimum level is lower than T_DCOV(total DC output voltage)

+ DV (dropout voltage). In such conditions, the output voltage would be lower and nearly equal to the input

supply. The regulator output voltage cannot be modified on the fly from one (0.9–2.1 V) voltage range to

the other (2.2–3.3 V) voltage range and vice versa. The regulator must be restarted in these cases. If an

LDO is not needed, the external components can be unplaced. The TPS65903x-Q1 devices are not

damaged by such configuration, and the other functions do not depend on the unused LDOs and work

properly.

6.3.2.2.1 LDOVANA

The VANA voltage regulator is dedicated to supply the analog functions of the TPS65903x-Q1 devices,

such as the GPADC and other analog circuits. VANA is automatically enabled and disabled when it is

needed. The automatic control optimizes the overall SLEEP state current consumption.

6.3.2.2.2 LDOVRTC

The VRTC regulator supplies always-on functions, such as real-time clock (RTC) and wake-up functions.

This power resource is active as soon as a valid energy source is present.

This resource has two modes:

•

Normal mode is able to supply all digital parts of the TPS65903x-Q1 devices

Backup mode is able to supply only always-on parts

VRTC supplies the digital part of TPS65903x-Q1 devices. In the BACKUP state, the VRTC regulator is in

low-power mode and the digital activity is reduced to the RTC parts only and maintained in retention

registers of the backup domain. The rest of the digital is under reset and the clocks are gated. In the OFF

state, the turn-on events and detection mechanism are also added to the previous RTC current load. In

the BACKUP and OFF states, the external load on VRTC should not exceed 0.5 mA. In the ACTIVE state,

VRTC switches automatically into ACTIVE mode. The reset is released and the clocks are available. In

SLEEP state, VRTC is kept active. The reset is released and only the 32-kHz clock is available. To reduce

power consumption, low-power mode can be selected by software.

Detailed Description

47

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

注

For silicon revision 1.3 or earlier, if VCC is discharged rapidly and then resupplied, a POR

may not be reliably generated. In this case a pulldown resistor can be added on the

LDOVRTC output. See 节 6.4.11 for details. See 节 6.3.10 to identify the silicon version in

the device.

6.3.2.2.3 LDO Bypass (LDO9)

LDO9 has a bypass capability to connect the input voltage to the output. It allows switching between 1.8 V

and the preregulated supply.

6.3.2.2.4 LDOUSB

This LDOUSB has two inputs, LDOUSB_IN1 and LDOUSB_IN2. LDOUSB_IN1 is shared with LDO7_IN.

The input selection occurs by the LDOUSB_ON_VBUS_VSYS bit in the LDO_CTRL register.

6.3.2.2.5 Other LDOs

All the other LDOs have the same output voltage capability, from 0.9 to 3.3 V in 50-mV steps. All the LDO

inputs can be independently connected into system voltage or into preregulated supply. The preregulated

supply can be higher or lower than the system supply.

6.3.3 Long-Press Key Detection

The TPS65903x-Q1 device can detect a long press on the PWRON terminal. Upon detection, the device

generates a LONG_PRESS_KEY interrupt and then switches the system off. The key-press duration is

configured through the LONG_PRESS_KEY.LPK_TIME bits.

The interrupt clear has two behaviors based on the configuration of the LONG_PRESS_KEY

.LPK_INT_CLR bit:

•

LONG_PRESS_KEY.LPK_INT_CLR = 0: If PWRON remains low and the interrupt is cleared, the

switch-off sequence is cancelled. If PWRON remains low and the interrupt is not cleared, the switch-off

sequence is executed.

•

LONG_PRESS_KEY.LPK_INT_CLR = 1: Switch off cannot be cancelled as long as PWRON remains

low (default).

6.3.4 RTC

6.3.4.1 General Description

The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions.

The main functions of the RTC block are:

•

Time information (seconds, minutes, hours) in binary-coded decimal (BCD) code

Calendar information (day, month, year, day of the week) in BCD code up to year 2099

Programmable interrupts generation; the RTC can generate two interrupts:

–

Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods), which can be masked

during the SLEEP state to prevent the host processor from waking up

–

Alarm interrupt at a precise time of the day (alarm function)

•

Oscillator frequency calibration and time correction with 1/32768 resolution

图 6-7 shows the RTC block diagram.

48

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

32-kHz

clock input

32-kHz

counter

Frequency

compensation

Week days

Control

Years

Seconds

Minutes

Hours

Days

Months

Interrupt

Alarm

INT_ALARM

INT_TIMER

图 6-7. RTC Block Diagram

6.3.4.2 Time Calendar Registers

All the time and calendar information is available in the time calendar (TC) dedicated registers:

SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and

YEARS_REG. The TC register values are written in BCD code.

•

Year data ranges from 00 to 99.

–

Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on)

Common Year = Other years

•

Month data ranges from 01 to 12.

Day value ranges:

–

1 to 31 when months are 1, 3, 5, 7, 8, 10, 12

1 to 30 when months are 4, 6, 9, 11

1 to 29 when month is 2 and year is a leap year

1 to 28 when month is 2 and year is a common year

•

Week value ranges from 0 to 6.

Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode.

Minutes value ranges from 0 to 59.

Seconds value ranges from 0 to 59.

Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are

listed in 表 6-2:

表 6-2. RTC Time Calendar Registers Example

REGISTER

CONTENT

0x36

SECONDS_REG

MINTURES_REG

HOURS_REG

DAYS_REG

0x54

0x10

0x05

MONTHS_REG

YEARS_REG

0x09

0x08

Detailed Description

49

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG

register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is

automatically cleared when the rounding time is performed.

Example:

•

If current time is 10H59M45S, round operation changes time to 11H00M00S

If current time is 10H59M29S, round operation changes time to 10H59M00S

6.3.4.2.1 TC Registers Read Access

TC registers read accesses can be done in two ways:

•

A direct read to the TC registers. In this case, there can be a discrepancy between the final time read

and the real time because the RTC keeps running because some of the registers can toggle in

between register accesses. Software must manage the register change during the reading.

•

Read access to shadowed TC registers. These registers are at the same addresses as the normal TC

registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this

bit is set, the content of all TC registers is transferred into shadow registers so they represent a

coherent timestamp, avoiding any possible discrepancy between them. When processing the read

accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely

transparent in terms of register access.

6.3.4.2.2 TC Registers Write Access

TC registers write accesses can be done in two ways:

•

Direct write into the TC registers. In this case, because the RTC keeps running, there can be a

discrepancy between the final time written and the target time to be written because some of the

registers can toggle in between register accesses. Software must manage the register change during

the writing.

•

Write access while RTC is stopped. Software can stop the RTC by the clearing STOP_RTC bit of the

control register and checking the RUN bit of the status to be sure that RTC is frozen. It then updates

the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written

values are aligned with the targeted values.

6.3.4.3 RTC Alarm

RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG,

ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm

time or date to the corresponding generated IT_ALARM interrupts. This interrupt is enabled through the

IT_ALARM bit in the RTC_INTERRUPTS_REG register. These register values are written in BCD code,

with the same data range as described for the TC registers (see 节 6.3.4.2).

6.3.4.4 RTC Interrupts

The RTC supports two types of interrupts:

•

IT_ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding

ALARM registers is reached. This interrupt is enable by the IT_ALARM bit in the

RTC_INTERRUPT_REG register.

•

IT_TIMER interrupt. This interrupt is generated when the periodic time set in the EVERY bits of the

RTC_INTERRUPT_REG register is reached. This interrupt is enabled by the IT_TIMER bit in the

RTC_INTERRUPT_REG register. During the SLEEP state, the IT_TIMER interrupt can either be

masked (stored and generated once out of SLEEP state) or unmasked using the

IT_SLEEP_MASK_EN bit of the RTC_INTERRUPT_REG register.

50

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

6.3.4.5 RTC 32-kHz Oscillator Drift Compensation

The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any

inaccuracy of the 32-kHz clock output from the 16.384MHz crystal oscillator. To compensate for any

inaccuracy, software must perform an external calibration of the oscillator frequency, calculate the drift

compensation needed versus one time hour period, and load the compensation registers with the drift

compensation value.

The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register.

The process happens after the first second of each hour. The time between second 1 to second 2

(T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and

RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2s complement value COMP_REG

(from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust

32768 - COMP_REG

æ

ö

ç

÷

32768

è

ø

the length of T_ADJ:

. It is therefore possible to adjust the compensation with a

1/32768-second time unit accuracy per hour and up to 1 second per hour.

Software must ensure that these registers are updated before each compensation process (there is no

hardware protection). For example, software can load the compensation value into these registers after

each hour event, during second 0 to second 1, just before the compensation period, happening from

second 1 to second 2.

It is also possible to preload the internal 32-kHz counter with the content of the RTC_COMP_MSB_REG

and RTC_COMP_LSB_REG registers when setting the SET_32_COUNTER bit in the RTC_CTRL_REG

register. This must be done when the RTC is stopped.

图 6-8 shows the RTC compensation scheduling.

HOURS_REG

3

4

5

6

0

1

...

58

59

0

1

...

58

59

0

1

...

58

59

0

1

...

58

59

SECONDS_REG

HOURS_REG

SECONDS_REG

3

4

59

0

58

2

3

Compensation Value Frozen

New Compensation Value

RTC_COMP_xxx_REG

Register

Update

Compensation

Event

图 6-8. RTC Compensation Scheduling

6.3.5 GPADC – 12-Bit Sigma-Delta ADC

The GPADC consists of a 12-bit sigma-delta ADC combined with an analog input multiplexer. The GPADC

allows the host processor to monitor a variety of analog signals using analog-to-digital conversion on the

input source. After the conversion completes, an interrupt is generated for the host processor and it can

read the result of the conversion through the I²C interface.

The GPADC on this PMIC supports 16 analog inputs. However only a total of 9 inputs are available for the

application use. Three of these inputs are available on external balls, and the remaining six are dedicated

to internal resource monitoring. One of the three external inputs is associated with a current source

allowing measurements of resistive elements (thermal sensor). To improve the measurement accuracy,

the reference voltages GPADC_VREF can be used with an external resistor for the NTC resistor

measurement. The reference voltage GPADC_VREF is always present when the GPADC is enabled.

Detailed Description

51

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

GPADC_IN0 is associated with three selectable current sources. The selectable current levels are 5, 15,

and 20 μA.

GPADC_IN1 is intended to measure temperature with an NTC sensor connected to ground. Two resistors,

one in parallel with the NTC resistor and the other one between GPADC_IN1 and GPADC_VREF, can be

used to modify the exponential function of the NTC resistor.

图 6-9 shows the block diagram of the GPADC.

ADC voltage reference

GPADC_VREF

GPADC_IN0

GPADC_IN1

Software

conversion result

GPADC_IN2

Input

Scalar

12-bit sigma

delta ADC

AUTO conversion result

Internal Channels

(Supply Voltage, DCDC

Current, and Die Temperature

Monitoring)

AUTO conversion request

Software conversion request

Interrupt

ADC control

图 6-9. Block Diagram of the GPADC

For all the measurements performed by the monitoring GPADC, voltage dividers, current to voltage

converters, and current source are integrated in the TPS65903x-Q1 devices to scale the signal to be

measured to the GPADC input range.

The conversion requests are initiated by the host processor either by software through the I²C. This mode

is useful when real-time conversion is required.

There are two kinds of conversion requests with the following priority:

•

Asynchronous conversion request (SW)

Periodic conversion (AUTO)

The EXTEND_DELAY bit in the GPADC_RT_CTRL register can extend by 400 μs the delay from the

channel selection or triggering to the sampling.

Use 公式 3 to convert from the GPADC code to the internal die temperature using GPADC channels 12

and 13.

52

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

≈

’

GPADC Code

2¹²

»

…

ÿ

ì 1.25 - 0.753 V

∆

÷

Ÿ

⁄

«

◊

Die Temperature (èC) =

2.64 mV

(3)

表 6-3. GPADC Channel Assignments

INPUT VOLTAGE

CHANNEL

TYPE

SCALER

OPERATION

FULL RANGE⁽¹⁾

PERFORMANCE RANGE⁽²⁾

Resistor value or general purpose. Select

source current 0, 5, 15, or 20 μA

0 (GPADC_IN0) External⁽³⁾

0 to 1.25 V

0.01 to 1.215 V

No

Platform temperature, NTC resistor value

and general purpose

1 (GPADC_IN1) External⁽³⁾

2 (GPADC_IN2) External⁽³⁾

0 to 1.25 V

0 to 2.5 V

0.01 to 1.215 V

0.02 to 2.43 V

No

2

Audio accessory or general purpose

2.5 to 5 V when

HIGH_VCC_SENSE

= 0

2.3 V to (VCC1–1 V)

when

2.5 to 4.86 V when

HIGH_VCC_SENSE = 0

2.3 V to (VCC1–1 V) when

HIGH_VCC_SENSE = 1

7

Internal

4

System supply voltage (VCC_SENSE)

(VCC_SENSE)

HIGH_VCC_SENSE

= 1

10 (VBUS)

Internal

0 to 6.875V

0 to 1.25 V

0 to VCC1 V

0.055 to 5.25V

5,5

No

5

VBUS Voltage

11

12

13

15

DC-DC current probe

PMIC internal die temperature

Test network

0 to 1.215 V

0.055 to VCC1 V

(1) The minimum and maximum voltage full range corresponds to typical minimum and maximum output codes (0 and 4095).

(2) The performance voltage is a range where gain error drift, offset drift, INL and DNL parameters are specified.

(3) If VANA LDO is OFF, maximum current to draw from GPADC_INx is 1 mA for reliability. For current higher than 1-mA VANA must be

set to SLEEP or ACTIVE mode.

6.3.5.1 Asynchronous Conversion Request (SW)

Software can also request conversion asynchronously. This conversion is not critical in terms of start-of-

conversion positioning. Software must select the channel to be converted, and then requests the

conversion with the GPADC_SW_SELECT register. An INT interrupt is generated when the conversion

result is ready, and the result is stored in the GPADC_SW_CONV0_LSB and GPADC_SW_CONV0_MSB

registers.

CAUTION

A defect in the digital controller of TPS65903x-Q1 devices may cause an

unreliable result from the first asynchronous conversion request after the device

exit from a warm reset. Texas Instruments recommends that user rely on

subsequent requests to obtain accurate result from the asynchronous

conversion after a device warm reset.

In addition, a cold reset event which happens during a GPADC conversion will

cause the GPADC controller to lock up. A software workaround for these issues

are described in detail in the Guide to Using the GPADC in TPS65903x and

TPS6591x Devices.

6.3.5.2 Periodic Conversion Request (AUTO)

Software can enable periodic conversions to compare one or two channels with a predefined threshold

level. Software must select one or two channels with the GPADC_AUTO_SELECT register and thresholds

and

polarity

with

the

GPADC_THRES_CONV0_LSB,

GPADC_THRES_CONV0_MSB,

GPADC_THRES_CONV1_LSB, and GPADC_THRES_CONV1_MSB registers. In addition, software must

select the conversion interval with the GPADC_AUTO_CTRL register and enable the periodic conversion

Detailed Description

53

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

with the AUTO_CONV0_EN and AUTO_CONV1_EN bits. There is no need to enable the GPADC

separately. The control logic enables and disables the GPADC automatically to save power. When AUTO

mode is the only conversion enabled, do not use the AUTO_CONV0_EN and AUTO_CONV1_EN bits to

disabled the conversion. Instead, force the state machine of the GPADC on by setting the

GPADC_CTRL1. GPADC_FORCE bit = 1, then shutdown the GPADC AUTO conversion using

GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0. Wait 100µS before disabling the GPADC state

machine by setting GPADC_CTRL1. GPADC_FORCE bit = 0. The latest conversion result is always

stored

in

the

GPADC_AUTO_CONV0_LSB,

GPADC_AUTO_CONV0_MSB,

GPADC_AUTO_CONV1_LSB, and GPADC_AUTO_CONV1_MSB registers. All selected channels are

queued and converted from channel 0 to 7. The first (lower) converted channel results is placed in the

GPADC_AUTO_CONV0 register and the second one is placed in the GPADC_AUTO_CONV1 register.

Therefore, TI recommends putting the lower channel to convert in AUTO_CONV0_SEL and the higher

channel to convert in AUTO_CONV1_SEL.

If the conversion result triggers the threshold level, an INT interrupt is generated and the conversion result

is stored. If the interrupt is not cleared or the results are not read before another auto-conversion is

completed, then the registers store only the latest results, discarding the previous ones. The

autoconversion is never stopped by an uncleared interrupt or unread registers.

Programming the triggering of the threshold level can also generate shutdown. This is available for

CONV0 and CONV1 channels independently and is enabled with the SHUTDOWN bits in the

GPADC_AUTO_CTRL register. During SLEEP and OFF modes, only channels from 0 to 10 can be

converted. For channels 12 and 13, conversion is possible in sleep if thermal sensor is not disabled.

6.3.5.3 Calibration

The GPADC channels are calibrated in the production line using a two-point calibration method. The

channels are measured with two known values (X1 and X2) and the difference (D1 and D2) to the ideal

values (Y1 and Y2) are stored in OTP memory. The principle of the calibration is shown in 图 6-10.

Measured

code

D2 = Y2 – X2

Y2

Ideal

curve

Measured

curve

Y1

D1 = Y1 – X1

Offset

Ideal code

X1

X2

Calibration points

Measured points

图 6-10. ADC Calibration Scheme

Some of the GPADC channels can use the same calibration data and the corrected result can be

calculated using the equations:

54

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Gain:

æ (D2 - D1) ö

k = 1+

ç

÷

(X2 - X1)

è

ø

(4)

(5)

Offset:

b = D1- k -1 ´ X1

(

)

If the measured code is a, the corrected code a' is:

a - b

(

)

a' =

k

(6)

表 6-4 summarizes the parameters X1 and X2, and the register of D1 and D2 needed in the calculation for

all the channels.

表 6-4. GPADC Calibration Parameters

CHANNEL

0,1

X1

X2

D1

D2

COMMENTS

2064 (0.63 V)

2064 (1.26 V)

2064 (2.52 V)

3112 (0.95 V)

3112 (1.9 V)

3112 (3.8 V)

GPADC_TRIM1

GPADC_TRIM3

GPADC_TRIM7

GPADC_TRIM2

GPADC_TRIM4

GPADC_TRIM8

Channel 1 trimming is used

2

7

6.3.6 General-Purpose I/Os (GPIO Terminals)

The TPS65903x-Q1 device integrates eight configurable general-purpose I/Os that are multiplexed with

alternative features as described in 表 6-5.

表 6-5. General Purpose I/Os Multiplexed Functions

TERMINAL

GPIO_1

PRIMARY FUNCTION

General-purpose I/O

SECONDARY FUNCTION

Output: VBUSDET (VBUS detection)

Output: REGEN2

GPIO_2

GPIO_4

Output: SYSEN1 (external system enable)

Output: CLK32KGO1V8 (32-kHz digital-fated output clock in VRTC domain) or

SYNCCLKOUT (Fallback synchronization clock for SMPS, 2.2MHz)

GPIO_5

General-purpose I/O

GPIO_6

GPIO_7

General-purpose I/O

Output: SYSEN2 (external system enable)

Input: POWERHOLD

For GPIO characteristics, refer to:

•

Ball description (see Section 4)

Electrical characteristics (see Section 5.16, and Section 5.17 )

Pullup and pulldown characteristics (see Section 5.18)

Each GPIO event can generate an interrupt on either rising and/or falling edge and each line is individually

maskable (as described in 节 6.3.8)

All GPIOs can be used as wake-up events.

注

GPIO_4 and GPIO_6 are in the VIO domain and need the I/O supply to be available.

When configured in OTP as SYSEN1 and SYSEN2, GPIO_4 and GPIO_6 can be programmed to be part

of power-up sequence.

Selection between primary and secondary functions is controlled through the registers

PRIMARY_SECONDARY_PAD1 and PRIMARY_SECONDARY_PAD2.

Detailed Description

55

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

When configured as primary functions, all GPIOs are controlled through the following set of registers:

•

GPIO_DAT_DIR: Configure each GPIO direction individually (Read or Write)

GPIO_DATA_IN: Data line-in when configured as an input (Read Only)

GPIO_DATA_OUT: Data line-out when configured as an output (Read or Write)

GPIO_DEBOUNCE_EN: Enable each GPIO debouncing individually (Read or Write)

GPIO_CTRL: Global GPIO control to enable or disable all GPIOs (Read or Write)

GPIO_CLEAR_DATA_OUT: Clear each GPIO data out individually (Write Only)

GPIO_SET_DATA_OUT: Set each GPIO data out individually (Write Only)

PU_PD_GPIO_CTRL1, PU_PD_GPIO_CTRL2: Configure each line pull up and pull down (Read or

Write)

•

OD_OUTPUT_GPIO_CTRL: Enable individual open-drain output (Read or Write)

When configured as secondary functions, none of the GPIO control registers (see 表 6-5) affect GPIO

lines. Line configuration (pullup, pulldown, open-drain) for secondary functions is held in a separate

register set, as well as specific function settings.

6.3.6.1 REGEN Output

Dedicated REGEN signal REGEN1 can be programmed to be part of power sequences to enable external

devices like external SMPS. The REGEN2 signal is MUXed in GPIO_2, and when REGEN2 mode is

selected it can also be programmed to be part of power sequences. All REGEN signals are at VSYS level.

6.3.7 Thermal Monitoring

The TPS65903x-Q1 devices include several thermal monitoring functions:

•

Thermal protection module internal to the TPS65903x-Q1 devices, placed close to the SMPS and LDO

modules

•

Platform temperature monitoring with an external NTC resistor

Platform temperature monitoring with an external diode

The TPS65903x-Q1 devices integrate two thermal detection modules to monitor the temperature of the

die. These modules are placed on opposite sides of the chip and close to the LDO and SMPS modules.

Overtemperature at either module generates a warning to the system; if the temperature continues to rise,

the TPS65903x-Q1 devices shut down before damage to the die can occur.

Thus, there are two protection levels:

•

A hot-die (HD) function sends an interrupt to software. Software is expected to close any noncritical

running tasks to reduce power.

•

A thermal shutdown (TS) function immediately starts the TPS65903x-Q1 device switch-off.

By default, thermal protection is always enabled except in the BACKUP or OFF state. Disabling thermal

protection in SLEEP mode for minimum power consumption is possible.

To use thermal monitoring in the system:

•

Set the value for the HD temperature threshold with the OSC_THERM_CTRL.THERM_HD_SEL[1:0]

register.

TS can be disabled in SLEEP mode by setting the THERM_OFF_IN_SLEEP bit to 1 in the

OSC_THERM_CTRL register.

During operation, if the die temperature increases above HD_THR_SEL, an interrupt (INT1.HOTDIE) is

sent to the host processor. Immediate action to reduce TPS65903x-Q1 power dissipation must be

taken by shutting down some function.

•

If the die temperature of the TPS65903x-Q1 devices rise further (above 148°C) an immediate

shutdown occurs. A TS event indication is written to the status register, INT1_STATUS_HOTDIE. The

system cannot restart until the temperature falls below HD_THR_SEL.

56

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

6.3.7.1 Hot-Die Function (HD)

The HD detector monitors the temperature of the die and provides a warning to the host processor

through the interrupt system when temperature reaches a critical value. The threshold value must be set

below the thermal shutdown threshold. Hysteresis is added to the HD detection to avoid the generation of

multiple interrupts.

The integrated HD function provides the host PM software with an early warning overtemperature

condition. This monitoring system is connected to the interrupt controller and can send an interrupt when

the temperature is higher than the programmed threshold. The TPS65903x-Q1 devices allow the

programming of four junction-temperature thresholds to increase the flexibility of the system: in nominal

conditions, the threshold triggering of the interrupt can be set from 117°C to 130°C. The HD hysteresis is

10°C in typical conditions.

When an interrupt is triggered by the power-management software, immediate action must be taken to

reduce the amount of power drawn from the TPS65903x-Q1 devices (for example, noncritical applications

must be closed).

6.3.7.2 Thermal Shutdown (TS)

The TS detector monitors the temperature on the die. If the junction reaches a temperature at which

damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status

register.

The system cannot be restarted until the die temperature falls below the HD threshold.

6.3.7.3 Temperature Monitoring With External NTC Resistor or Diode

The GPADC_IN1 channel can be used to measure a temperature with an external NTC resistor. External

pullup and pulldown resistors can be connected to the input to linearize the characteristics of the NTC

resistor. The temperature limits are set by external resistors.

6.3.8 Interrupts

表 6-6 lists the TPS65903x-Q1 interrupts.

These interrupts are split into four register groups (INT1, INT2, INT3, INT4) and each group has three

associated control registers:

•

INTx_STATUS: Reflects which interrupt source has triggered an interrupt event

INTx_MASK: Used to mask any source of interrupt, to avoid generating an interrupt on a specified

source

•

INTx_LINE_STATE: Reflects the real-time state of each line associated to each source of interrupt

The INT4 register group has two additional registers, INT4_EDGE_DETECT1 and

INT4_EDGE_DETECT2, to independently configure rising and falling edge detection.

All interrupts are logically combined on a single output line INT (default active low). This line is used as an

external interrupt line to warn the host processor of any interrupt event that has occurred within the device.

The host processor has to read the interrupt status registers (INTx_STATUS) through the control interface

(I²C or SPI) to identify the interrupt source(s). Any interrupt source can be masked by programming the

corresponding mask register (INTx_MASK). When an interrupt is masked, its associated event detection

mechanism is disabled. Therefore the corresponding STATUS bit is not updated and the INT line is not

triggered if the masked event occurs. Any event happening while its corresponding interrupt is masked is

lost. If an interrupt is masked after it has been triggered (event has occurred and has not yet been

cleared), then the STATUS bit reflects the event until it is cleared and it does not trigger again if a new

event occurs (because it is now masked).

Detailed Description

57

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

Because some interrupts are sources of ON requests (see 表 6-6), source masking can be used to mask

a specific device switch-on event. Because an active interrupt line INT is treated as an ON request, any

interrupt not masked must be cleared to allow the execution of a SLEEP sequence of the device when

requested.

The INT line polarity and interrupts clearing method can be configured using the INT_CTRL register.

An INT line event can be provided to the host in either SLEEP or ACTIVE mode, depending on the setting

of the OSC_THERM_CTRL.INT_MASK_IN_SLEEP bit.

When a new interrupt occurs while the interrupt line INT is still active (not all interrupts have been

cleared), then:

•

If the new interrupt source is the same as the one that has already triggered the INT line, it can be

discarded or stored as a pending interrupt depending on the setting of the INT_CTRL.INT_PENDING

bit.

–

When the INT_CTRL.INT_PENDING bit is active (default), then any new interrupt event occurring

on the same source (while the INT line is still active) is stored as a pending interrupt. Because only

one level of pending interrupt can be stored for a given source, when several events (more than

two) occur on the same source, only the last one is stored. While an interrupt is pending, two

accesses are needed (either read or write) to clear the STATUS bit: one access for the actual

interrupt and another for the pending interrupt. Note: two consecutive read or write operations to

the same register clear only one interrupt. Another register must be accessed between the two read

or write clear operations. Example for clear-on-read: when INT signal is active, read all four

INTx_STATUS registers in sequence to collect status of all potential interrupt sources. Read access

clears the full register for an active or actual interrupt. If the INT line is still active, repeat read

sequence to check and clear pending interrupts.

–

When the INT_CTRL.INT_PENDING bit is inactive, then any new interrupt event occurring on the

same source (while the INT line is still active) is discarded. Note: two consecutive read or write

operations to the same register clear only one interrupt. Another register must be accessed

between the two read or write clear operations.

•

If the new interrupt source is different from the one that already triggered the INT line, then it is stored

immediately into its corresponding STATUS bit.

To clear the interrupt line, all status registers must be cleared. The clearing of all status registers is

achieved by using a clear-on-read or a clear-on-write method. The clearing method is selectable though

the INT_CTRL.INT_CLEAR bit. Once set, the clearing method applies to all bits for all interrupts.

•

Clear-on-read

–

Read access to a single status register clears all the bits for only this specific register (8 bits).

Therefore, clearing all interrupts requests to read the four status registers. If the INT line is still

active when the four read accesses complete, then another interrupt event has occurred during the

read process; therefore the read sequence must be repeated.

•

Clear-on-write

–

This method is bit-based; setting a specific bit to 1 clears only the written bit. Therefore, to clear a

complete status register, 0xFF must be written. Clearing all interrupts requests to write 0xFF into

the four status registers. If the INT line is still active when the four write accesses are complete,

then another interrupt event has occurred during the write process; therefore the write sequence

must be repeated.

58

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

表 6-6. Interrupt Sources

ASSOCIATED

EVENT

EDGES

DETECTION

REG.

ON REQUEST

INTERRUPT

REG. BIT

DESCRIPTION

GROUP

System voltage monitoring interrupt: Triggered when

system voltage has crossed the configured threshold

in VSYS_MON register.

VSYS_MON

Internal event Rising and falling

Never

6

5

Hot-die temperature interrupt: The embedded thermal

monitoring module has detected a die temperature

above the hot-die detection threshold. Interrupt is

generated in ACTIVE and SLEEP state, not in OFF

state.

HOTDIE

Never

PWRDOWN

Rising and falling

(terminal)

Power-down interrupt: Triggered when the event is

detected on the PWRDOWN terminal.

PWRDOWN

RPWRON

4

3

INT1

Always

(INT mask don't

care)

Remote power-on interrupt: Triggered when a signal

change is detected. Interrupt is generated in ACTIVE

and SLEEP state, not in OFF state.

RPWRON

Falling

(terminal)

Power-on long key-press interrupt. Triggered when

PWRON is low during more than the long-press delay

LONG_PRESS_KEY.LPK_TIME.

LONG_PRESS_KE

Y

PWRON

Falling

Never

2

1

6

(terminal)

Power-on interrupt: Triggered when PWRON button is

pressed (low) while the device is on. Interrupt is

generated in ACTIVE and SLEEP state, not in OFF

state.

Always

(INT mask don't

care)

PWRON

Falling

PWRON

SHORT

(terminal)

Yes

(if INT not

masked)

Short interrupt: Triggered when at least one of the

power resources (SMPS or LDO) has its output

shorted.

Internal event

Rising

RESET_IN

(terminal)

RESET_IN interrupt: Triggered when event is detected

on RESET_IN terminal.

RESET_IN

WDT

Rising

Never

4

2

Watchdog time-out interrupt: Triggered when

watchdog time-out has expired.

Internal event

INT2

Real-time clock timer interrupt: Triggered at

programmed regular period of time (every second or

minute). Running in ACTIVE, OFF, and SLEEP state,

default inactive.

Yes

(if INT not

masked)

RTC_TIMER

Internal event

Rising

1

Yes

(if INT not

masked)

Real-time clock alarm interrupt: Triggered at

programmed determinate date and time.

RTC_ALARM

VBUS

Internal event

Rising

Rising and falling

N/A

0

7

2

Yes

(if INT not

masked)

VBUS

(terminal)

VBUS wake-up comparator interrupt. Active in OFF

state. Triggered when VBUS present.

Yes

(if INT not

masked)

GPADC software end of conversion interrupt:

Triggered when conversion result is available.

GPADC_EOC_SW

Internal event

GPADC automatic periodic conversion 1: Triggered

when result of conversion is either above or below

(depending on configuration) reference threshold

GPADC_AUTO_CONV1_LSB and

Yes

(if INT not

masked)

INT3

GPADC_AUTO_1

GPADC_AUTO_0

N/A

1

0

GPADC_AUTO_CONV1_MSB.

GPADC automatic periodic conversion 0: Triggered

when result of conversion is either above or below

(depending on configuration) reference threshold

GPADC_AUTO_CONV0_LSB and

Yes

(if INT not

masked)

Internal event

GPADC_AUTO_CONV0_MSB.

Detailed Description

59

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

表 6-6. Interrupt Sources (continued)

ASSOCIATED

EVENT

EDGES

DETECTION

REG.

GROUP

INTERRUPT

ON REQUEST

REG. BIT

DESCRIPTION

Yes

(if INT not

masked)

GPIO_7

(terminal)

Rising and/or

falling

GPIO_7

7

GPIO_7 rising- or falling-edge detection interrupt

GPIO_6 rising- or falling-edge detection interrupt

GPIO_5 rising- or falling-edge detection interrupt

GPIO_4 rising- or falling-edge detection interrupt

GPIO_3 rising- or falling-edge detection interrupt

GPIO_2 rising- or falling-edge detection interrupt

GPIO_1 rising- or falling-edge detection interrupt

GPIO_0 rising- or falling-edge detection interrupt

Yes

(if INT not

masked)

GPIO_6

(terminal)

Rising and/or

falling

GPIO_6

GPIO_5

GPIO_4

GPIO_3

GPIO_2

GPIO_1

GPIO_0

6

5

4

3

2

1

0

Yes

(if INT not

masked)

GPIO_5

(terminal)

Rising and/or

falling

Yes

(if INT not

masked)

GPIO_4

(terminal)

Rising and/or

falling

INT4

Yes

(if INT not

masked)

GPIO_3

(terminal)

Rising and/or

falling

Yes

(if INT not

masked)

GPIO_2

(terminal)

Rising and/or

falling

Yes

(if INT not

masked)

GPIO_1

(terminal)

Rising and/or

falling

Yes

(if INT not

masked)

GPIO_0

(terminal)

Rising and/or

falling

6.3.9 Control Interfaces

The TPS65903x-Q1 devices have two exclusive selectable (from factory settings) interfaces; two high-

speed I²C interfaces (I2C1_SCL_SCK or I2C1_SDA_SDI and I2C2_SCL_SCE or I2C2_SDA_SDO) or one

SPI interface (I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SDA_SDO, or I2C2_SCL_SCE). Both are used to

fully control and configure the device and have access to all the registers. When the I²C configuration is

selected the I2C1_SCL_SCK or I2C1_SDA_SDI, a general purpose control (GPC) interface is dedicated

to configure the device and the I2C2_SCL_SCE or I2C2_SDA_SDO interface dynamic voltage scaling

(DVS) is dedicated to dynamically change the output voltage of the SMPS converters. The DVS I²C

interface has access only to the voltage scaling registers of the SMPS converters (read and write mode).

6.3.9.1 I²C Interfaces

The GPC I²C interface (I2C1_SCL_SCK and I2C1_SDA_SDI) is dedicated to access the configuration

registers of all the resources of the system.

The DVS I²C interface (I2C2_SCL_SCE and I2C2_SDA_SDO) is dedicated to access the DVS registers

independently from the GPC I²C.

The control interfaces comply with the HS-I²C specification and support the following features:

•

Mode: Slave only (receiver and transmitter)

Speed:

–

Standard mode (100 kbps)

Fast mode (400 kbps)

High-speed mode (3.4 Mbps)

•

Addressing: 7-bit mode addressing device

The following features are not supported:

•

10-bit addressing

General call

Master mode (bus arbitration and clock generation)

60

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

I²C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I²C-Bus

Specification and user manual, Rev 03, June 2007). The bus consists of a data line (SDA) and a clock line

(SCL) with pullup structures. When the bus is idle, the SDA and SCL lines are pulled high. All the I²C-

compatible devices connect to the I²C bus through open-drain I/O terminals, SDA and SCL. A master

device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible

for generating the SCL signal and device addresses. The master also generates specific conditions that

indicate the start and stop of data transfers. A slave device receives and/or transmits data on the bus

under control of the master device. The data transfer protocol for standard and fast modes is exactly the

same, and they are referred to as F/S mode in this document. The protocol for high-speed mode is

different from F/S mode, and it is referred to as HS mode.

6.3.9.1.1 I²C Implementation

The TPS65903x-Q1 standard I²C 7-bit slave device address is set to 010010xx (binary) where the two

least-significant bits are used for page selection.

The device is organized in five internal pages of 256 bytes (registers) as follows:

•

Slave device address 0x48: Power registers

Slave device address 0x49: Interfaces and auxiliaries

Slave device address 0x4A: Trimming and test

Slave device address 0x4B: OTP

Slave device address 0x12: DVS

The device address for the DVS I²C interface is set to 0x12.

If one of the addresses conflicts with another device I²C address, it is possible to remap each address to a

fixed alternative one as described in 表 6-7. I²C for DVS is fixed because it is dedicated interface.

表 6-7. I²C Address Configuration

REGISTER

BIT

PAGE

Power registers

ADDRESSES

ID_I2C1[0] = 0: 0x48

ID_I2C1[0] = 1: 0x58

ID_I2C1[1] = 0: 0x49

ID_I2C1[1] = 1: 0x59

ID_I2C1[2] = 0: 0x4A

ID_I2C1[2] = 1: 0x5A

ID_I2C1[3] = 0: 0x4B

ID_I2C1[3] = 1: 0x5B

ID_I2C2 = 0: 0x12

ID_I2C1[0]

ID_I2C1[1]

ID_I2C1[2]

Interfaces and auxiliaries

Trimming and test

I2C_SPI

ID_I2C1[3]

ID_I2C2

OTP

DVS

6.3.9.1.2 F/S Mode Protocol

The master initiates data transfer by generating a START condition. The START condition is when a high-

to-low transition occurs on the SDA line while SCL is high (see 图 6-11). All I²C-compatible devices should

recognize a START condition.

The master then generates the SCL pulses and transmits the 7-bit address and the read or write direction

bit (R/W) on the SDA line. During all transmissions, the master ensures that data is valid. A valid data

condition requires the SDA line to be stable during the entire high period of the clock pulse (see 图 6-12).

All devices recognize the address sent by the master and compare it to their internal fixed addresses.

Only the slave device with a matching address generates an acknowledge (see 图 6-13) by pulling the

SDA line low during the entire high period of the ninth SCL cycle. When this acknowledge is detected, the

master knows that the communication link with a slave has been established.

Detailed Description

61

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data

from the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter.

An acknowledge signal can be generated by the master or the slave, depending on which one is the

receiver. Nine-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as

long as necessary.

To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line

from low to high while the SCL line is high (see 图 6-11). This releases the bus and stops the

communication link with the addressed slave. All I²C-compatible devices must recognize the STOP

condition. Upon the receipt of a STOP condition, all devices know that the bus is released, and they wait

for a START condition followed by a matching address.

Attempting to read data from register addresses not listed in this section results in 0xFF being read out.

6.3.9.1.3 HS Mode Protocol

When the bus is idle, the SDA and SCL lines are pulled high by the pullup devices.

The master generates a START condition followed by a valid serial byte containing HS master code

00001XXX. This transmission is made in F/S mode at no more than 400 kbps. No device is allowed to

acknowledge the HS master code, but all devices must recognize it and switch their internal setting to

support 3.4-Mbps operation.

The master then generates a REPEATED START condition (a REPEATED START condition has the

same timing as the START condition). After the REPEATED START condition, the protocol is the same as

F/S mode, except transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS mode

and switches all the internal settings of the slave devices to support F/S mode. Instead of using a STOP

condition, REPEATED START conditions are used to secure the bus in HS mode.

Attempting to read data from register addresses not listed in this section results in 0xFF being read out.

DATA

CLK

S

P

START

condition

STOP

condition

I2C_start_stop

图 6-11. START and STOP Conditions

DATA

CLK

Data line

stable;

data valid

Change of data allowed

I2C_bittransfer

图 6-12. Bit Transfer on the Serial Interface

62

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Data output

by transmitter

Not acknowledge

Acknowledge

Data output

by receiver

SCL from

master

1

2

8

9

S

Clock pulse for

acknowledgement

START

condition

I2C_acknowledge

图 6-13. Acknowledge on the I²C Bus

Recognize START or

REPEATED START

condition

Recognize STOP or

REPEATED START

condition

Generate ACKNOWLEDGE

signal

P

SDA

MSB

Acknowledgement

signal from slave

Sr

Address

R/W

1

2

7

8

9

SCL

1

3-8

9

2

Sr

or

P

S

or

Sr

ACK

Clock line held low while

nterrupts are serviced

i

START or

REPEATED START

condition

STOP or

REPEATED START

condition

I2C_busprotocol

图 6-14. Bus Protocol

6.3.9.2 SPI Interface

The SPI is a 4-wire slave interface used to access and configure the device. The SPI allows read-and-

write access to the configuration registers of all resources of the system.

The SPI uses the following signals:

•

SCE (I2C2_SCL_SCE): Chip enable – Input driven by host master, used to initiate and terminate a

transaction

•

SCK (I2C1_SCL_SCK): Clock – Input driven by host master, used as master clock for data transaction

SDI (I2C1_SDA_SDI): Data input – Input driven by host master, used as data line from master to slave

SDO (I2C2_SDA_SDO): Data output – Output driven by TPS65903x-Q1 PMIC device, used as data

line from slave to master and defaults to high impedance

Detailed Description

63

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

6.3.9.2.1 SPI Modes

The SPI interface does not have access to the OTP and DVS registers (slave device address 0x4B &

0x12) of the TPS65903x-Q1 device. The SPI_PAGE_CTRL.SPI_PAGE_ACCESS regsiter can be

configured to access all other registers (slave device address 0x48, 0x49, & 0x4A) by:

•

SPI_PAGE_CTRL.SPI_PAGE_ACCESS = 0: Page1 = 0x48, Page2 = 0x49

SPI_PAGE_CTRL.SPI_PAGE_ACCESS = 1: Page1 = 0x48, Page3 = 0x4A

This SPI interface supports two access modes (Note: all shifts are done MSB first (Data, Address, Page):

• Single access (read or write)

–

This consists of fetching and storing one single data location. The protocol is depicted in 图 6-15.

The R/W bit is always provided first, followed by page address and register address fields. When

R/W = 0, a read access is performed. When R/W = 1, a write access is performed.

–

1 burst bit indicates if following transfer is a single access (BURST = 0) or a burst access (BURST

= 1).

–

4 unused bits follow the burst bit and finally the 8-bit data is either shifted in (write) or out (read).

For a write access, the data output line SDO is invalid (useless) during the whole transaction.

For a read access, the data output line SDO is invalid during the unused bits (time slot used for

data fetch) and then becomes active or valid after the unused bits.

•

Burst access (read or write)

–

This consists of fetching and storing several data at contiguous locations. The protocol is depicted

in 图 6-16.

The R/W bit is always provided first, followed by page address and register address fields. When

R/W = 0, a read access is performed. When R/W = 1, a write access is performed.

1 burst bit indicates if following transfer is a single access (BURST = 0) or a burst access (BURST

= 1).

4 unused bits follow the burst bit and finally packets of 8-bit data are either shifted in (write) or out

(read).

–

The transaction remains active as long as the SCE signal is maintained high by the host.

The address is automatically incremented internally for each new 8-bit packet received.

The host must pull the SCE signal low after a complete 8-bit data is transferred, otherwise the last

transaction is discarded.

–

For a write access, the data output line SDO is invalid (useless) during the whole transaction.

For a read access, the data output line SDO is invalid during the unused bits (time slot used for

data fetch) and then becomes active or valid after the unused bits.

64

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

6.3.9.2.2 SPI Protocol

ES2.0

SPI write

SCE

SCK

SDI

Data (8)

Register address (8)

Unused bits (5)

Burst

RW Page

(SDI)

Palmas samples SDI on SCK rising edge

=> Master to assert data on falling edge

SPI read

SCE

SCK

SDI

RW Page

Burst

(SDI)

Register address (8)

Unused bits

Unused bits (5)

'RQ¶WFDUH

Data (8)

SDO

(SDO)

Palmas samples SDI on SCK rising edge

=> Master need to assert data on falling edge

Palmas asserts SDO to get it available on SCK rising edge

=> Master need to sample data on rising edge

图 6-15. SPI Single Read and Write Access

Detailed Description

65

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

ES2.0

SPI write

SCE

SCK

SDI

Burst

Data (8)

RW Page

Register address (8)

Unused bits (5)

(SDI)

Palmas samples SDI on SCK rising edge

=> Master to assert data on falling edge

SPI read

SCE

SCK

SDI

Register address

(8)

RW Page

Burst

Unused bits (5)

'RQ¶WFDUH

(SDI)

SDO

Unused

bits

Data (8)

(SDO)

Palmas samples SDI on SCK rising edge

=> Master need to assert data on falling

edge

Palmas asserts SDO to get it available on SCK rising edge

=> Master need to sample data on rising edge

图 6-16. SPI Burst Read and Write Access

6.3.10 Device Identification

The following registers can differentiate the TPS65903x-Q1 device being used.

表 6-8. TPS65903x-Q1 Device ID

REGISTER NAME

REGISTER DESCRIPTION

VALUE

For all TPS65903x-Q1 devices, this register will have the

same value.

PRODUCT_ID_MSB

PRODUCT_ID_LSB

0x90

For all TPS65903x-Q1 devices, this register will have the

same value.

0x39

Revision 1.0

Revision 1.1

0x0

0x1

0x2

0x3

0x4

This register distinguishes which silicon

DESIGNREV

Revision 1.2

version is used.

Revision 1.3

Revision 1.4

This register will be representative of the OTP version

programmed on the device.

SW_REVISION

OTP dependent

6.4 Device Functional Modes

6.4.1 Embedded Power Controller

The EPC is composed of three main modules:

•

An event arbitration module used to prioritize ON, OFF, WAKE, and SLEEP requests.

A power state-machine used to determine which power sequence to execute, based on the system

state (supplies, temperature, and so forth) and requested transition (from the event arbitration module).

66

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

•

A power sequencer that fetches the selected power sequence from OTP and executes it. The power

sequencer sets up and controls all resources accordingly, based on the definition of each sequence.

图 6-17 shows the EPC block diagram.

Power

Sequence

Pointer

ON Requests

OFF Requests

Resources

Power

Sequencer

Event

Events

Arbitration

Power State

Machine

SLEEP Requests

WAKE Requests

Power

System State

(Supplies, Temperature, ...)

Sequences

OFF2ACT

ACT2OFF

SLP2OFF

ACT2SLP

SLP2ACT

图 6-17. EPC Block Diagram

The power state-machine is defined through the following states:

•

NO SUPPLY: The device is not powered by any energy source on the system power rail (VCC1 <

POR).

BACKUP: The device is not powered by a valid supply on the system power rail (VCC1 < VSYS_LO)

(VCC > POR).

OFF: The device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and it is

waiting for a start-up event or condition. All device resources are in the OFF state. The approximate

time for device to arrive the OFF state from the NO SUPPLY state, without considering the rise time of

VSYS and the settling time of the VSYS_LO comparator, is approximately 5.5 ms.

•

ACTIVE: The device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and

has received a start-up event. It has switched to the ACTIVE state, having full capacity to supply the

processor and other platform modules.

SLEEP: The device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and is

in low-power mode. All configured resources are set to their low-power mode, which can be ON,

SLEEP, or OFF depending on the specific resource setting. If a given resource is maintained active

(ON) during low-power mode, then all its linked subsystems are automatically maintained active.

图 6-18 shows the state diagram for the power control state-machine.

提交文档反馈意见

Detailed Description

67

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

No Supply

VCC > POR_threshold

VCC < POR

BACKUP

VCC > POR

and

VCC < VSYS_LO

VCC > VSYS_LO

VCC < VSYS_LO

VCC < POR

VCC < VSYS_LO

OFF

VCC < POR

ON Request and

VCC_SENSE > VSYS_HI

OFF Request

VCC < VSYS_LO

ACTIVE

OFF Request

SLEEP Request

WAKE Request

SLEEP

图 6-18. State Diagram for the Power Control State-Machine

Power sequences define how a resource state switches between the OFF, ACTIVE, and SLEEP states,

but they have no effect during the NO SUPPLY or BACKUP states. The EPC supervises the system

according to these power sequences, once the device is brought into the OFF state from a NO SUPPLY

or BACKUP state. This is achieved automatically by internal hardware controlling the device before

handing it over to the EPC.

68

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

The allowed power transitions are:

•

OFF to ACTIVE (OFF2ACT)

ACTIVE to OFF (ACT2OFF)

ACTIVE to SLEEP (ACT2SLP)

SLEEP to ACTIVE (SLP2ACT)

SLEEP to OFF (SLP2OFF)

Each power transition consists of a sequence of one or several register accesses that controls the

resources according to the EPC supervision. Because these sequences are stored in nonvolatile memory

(OTP), they cannot be altered.

6.4.2 State Transition Requests

6.4.2.1 ON Requests

ON requests are used to switch on the device, which transitions the device from the OFF to the ACTIVE

state. 表 6-9 lists the ON requests.

表 6-9. ON Requests

EVENT

MASKABLE

POLARITY

Low

COMMENT

Level sensitive

DEBOUNCE

16 ms ± 1 ms

N/A

RPWRON (terminal)

PWRON (terminal)

No

Low

Part of interrupts

(event)

Yes (INTx_MASK register.

Default: Masked)

Event

High

Edge sensitive

Level sensitive

N/A

POWERHOLD

(terminal)

No

3 - 5 ms typical

If one of the events listed in 表 6-9 occurs, it powers on the device, unless one of the gating conditions

listed in 表 6-10 is present. For interrupt sources that can be configured as ON requests, see 表 6-6.

表 6-10. ON Requests Gating Conditions

EVENT

MASKABLE

POLARITY

Low

COMMENT

VCC_SENSE < VSYS_HI

Device temperature exceeds HOTDIE level

VSYS_HI (event)

HOTDIE (event)

No

High

PWRDOWN (terminal)

RESET_IN (terminal)

OTP configurable

6.4.2.2 OFF Requests

OFF requests are used to switch off the device, transitioning the device from the SLEEP or the ACTIVE to

the OFF state. 表 6-11 lists the OFF requests. OFF requests have the highest priority, and there are no

gating conditions. Any OFF request is executed even though a valid SLEEP or ON request is present. The

device goes to the OFF state, and once the OFF request is cleared it reacts to an ON request, if there are

any.

表 6-11. OFF Requests

SWITCH OFF

DELAY

RESET

SEQUENCE

EVENT

MASKABLE

POLARITY

DEBOUNCE

RESET LEVEL

PWRON

(terminal)

No

Low

N/A

SWOFF_DLY

HWRST

SD

(long press key)

PWRDOWN

(terminal)

No

OTP

configurable

SWOFF_DLY

OTP

Configurable

OTP Configurable

Detailed Description

69

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

表 6-11. OFF Requests (continued)

SWITCH OFF

RESET

SEQUENCE

EVENT

MASKABLE

POLARITY

DEBOUNCE

RESET LEVEL

DELAY

N/A. WDT is

disabled by default

but software can

enable it.

WATCHDOG

TIMEOUT

(internal event)

OTP

Configurable

NA

N/A

SWOFF_DLY

OTP Configurable

THERMAL

SHUTDOWN

(internal event)

OTP

Configurable

No

NA

N/A

0

OTP Configurable

RESET_IN

(terminal)

OTP

configurable

SWOFF_DLY

OTP

Configurable

SW_RST

(register bit)

OTP

Configurable

No

NA

Low

NA

N/A

0

OTP Configurable

SD

DEV_ON

(register bit)

0

SWORST

VSYS_LO

(internal event)

OTP

Configurable

No

0

OTP Configurable

SD

POWERHOLD

(terminal)

No

0

SWORST

GPADC_SHUTD

OWN

OTP

Configurable

Yes

N/A

SWOFF_DLY

OTP Configurable

Notes:

•

SWOFF_DLY is the same for all requests. Once configured to a specific value (0, 1, 2, or 4 s) it is

applied to all OFF requests.

RESET_LEVEL is selectable as HWRST (wide set of registers is reset to default values) or SWORTS

(more limited set of registers is reset).

OFF requests are configured to force the EPC to either execute a shutdown (SD) or a cold restart

(CR).

–

When configured to generate an SD, the EPC executes a transition to the OFF state (SLP2OFF or

ACT2OFF power sequence) and remains in the OFF state.

–

When configured to generate a CR, the EPC executes a transition to the OFF state (SLP2OFF or

ACT2OFF power sequence) and restarts, transitioning to the ACTIVE state (OFF2ACT power

sequence) if none of the ON request gating conditions are present.

•

Watchdog is disabled by default. SW can enable watchdog and lock (write protect) watchdog register

(WATCHDOG).

The DEV_ON event has a lower priority over other ON events; it forces the device to go to the OFF

state only if no other ON conditions are keeping the device active (POWERHOLD).

The POWERHOLD event has a lower priority over other ON events; it forces the device to go to the

OFF state only if no other ON conditions are keeping the device active (DEV_ON).

6.4.2.3 SLEEP and WAKE Requests

SLEEP requests are used to put the device in the SLEEP state, meaning a transition from the ACTIVE to

SLEEP state. This sets internal resources into low-power mode, as well as user-defined resources into

their user predefined low-power mode. The states of the resources during active and sleep modes are

defined in the LDO*_CTRL registers and SMPS*_CTRL registers.

表 6-12 lists the SLEEP requests. Any of these events trigger the ACT2SLP sequence, unless there are

pending interrupts (unmasked). Only an interrupt or NSLEEP inactive (high) generates a WAKE request to

wake up the device (exit from the SLEEP state). A WAKE request (only during the SLEEP state) wakes up

the device and triggers a SLEEP2ACT or a SLEEP2OFF power sequence.

70

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

表 6-12. SLEEP Requests

EVENT

NSLEEP (terminal)

MASKABLE

Yes (Default: Masked)

POLARITY

Low

COMMENT

Level sensitive

For each resource, a transition from the ACTIVE to SLEEP state or SLEEP to ACTIVE state can be

controlled in two different ways:

•

Through EPC sequencing (ACT2SLP or SLP2ACT power sequence), when the resource is associated

to the NSLEEP signal.

•

Through direct control of the resource power mode (active or sleep).

–

The user can bypass SLEEP and WAKE sequencing by having resources assigned to one external

control signal (ENABLE1). This signal has direct control on the power modes (active or sleep) of

any resources associated to it and it triggers an immediate switch from one mode to the other,

regardless of the EPC sequencing.

All resources can therefore be associated to two external terminals (NSLEEP and ENABLE1) and they

switch between the SLEEP and ACTIVE states based on 表 6-13.

表 6-13. Resources SLEEP and ACTIVE Assignments

ENABLE1

ASSIGNMENT

NSLEEP

ASSIGNMENT

ENABLE1

TERMINAL STATE

NSLEEP TERMINAL

STATE

TRANSITION

0

1

0

1

0

Don't care

0 ↔ 1

0

Don't care

0 ↔ 1

Don't care

0 ↔ 1

0

ACTIVE

None

Sequenced

Immediate

Sequenced

None

SLEEP ↔ ACTIVE

ACTIVE

1

0 ↔ 1

SLEEP ↔ ACTIVE

ACTIVE

Immediate

None

1

注

•

The polarity of the NSLEEP and ENABLE1 signals is configurable through the

POLARITY_CTRL register. By default:

–

ENABLE1 is active high; a transition from 0 to 1 requests a transition from SLEEP to

ACTIVE.

–

NSLEEP is active low; a transition from 1 to 0 requests a transition from ACTIVE to

SLEEP.

Resource assignments to the NSLEEP and ENABLE1 signals are configured in the

ENABLEx_YYY_ASSIGN and NSLEEP_YYY_ASSIGN registers (where x = 1 or 2 and

YYY = RES or SMPS or LDO)

•

Several resources can be assigned to the same ENABLE1 signal and therefore, when

triggered, they all switch their power mode at the same time.

When resources are assigned only to the NSLEEP signal, their respective switching

order is controlled and defined in the power sequence.

When a resource is not assigned to any signal (NSLEEP and ENABLE1), it never

switches from the ACTIVE to SLEEP state. The resource always remains in active mode.

Detailed Description

71

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

CAUTION

A defect in the digital controller of TPS65903x-Q1 was discovered, which may

cause the PLL to shut down unexpectedly under the following sequence of

events:

•

PLL is programmed to be OFF under SLEEP mode through the PLLEN_CTRL

register

NSLEEP is assigned to control the entering of SLEEP mode for the PLL through the

NSLEEP_RES_ASSIGN register

TPS65903x-Q1 goes through a SLP2OFF state transition followed by an OFF2ACT

state transition

PLL is again assigned to be OFF in SLEEP mode through the programming of the

PLLEN_CTRL and the NSLEEP_RES_ASSIGN registers while the device remains in

ACTIVE mode

Two possible actions are recommended to help prevent the PLL from shutting

down unexpectedly:

•

[Hardware Implementation] Toggle the NSLEEP pin twice to force the ACT2SLP and

SLP2ACT state transitions as soon as TPS65903x-Q1 wakes up from back to back

SLP2OFF and OFF2ACT state transitions

•

[Software Implementation] Toggle the NSLEEP_POLARITY bit (0 → 1 → 0) of the

POLARITY_CTRL register to force the ACT2SLP and SLP2ACT device state

transitions as soon as TPS65903x-Q1 wakes up from back to back SLP2OFF and

OFF2ACT state transitions

6.4.3 Power Sequences

A power sequence is an automatic pre-programmed sequence handled by the TPS65903x-Q1 device

series to configure the device resources: SMPSs, LDOs, 32-kHz clock, part of GPIOs, , REGEN signals)

into on, off, or sleep modes. See 节 6.3.6 for GPIO details.

图 6-19 shows an example of an OFF2ACT transition followed by an ACT2OFF transition. The sequence

is triggered through PWRON terminal and the resources controlled (for this example) are: VIO, LDO1,

SMPS2, LDO6, REGEN1, LDOLN, LDOUSB, and CLK32KOUT. The time between each resource enable

and disable (TinstX) is also part of the preprogrammed sequence definition.

When a resource is not assigned to any power sequence, it remains in off mode. The user (through

software) can enable and configure this resource independently after the power sequence completes.

72

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

OFF2ACT Power Sequence

ACT2OFF Power Sequence

X

PWRON

VIO

Tinst16

Tinst15

Tinst1

LDO1

Tinst2

SMPS2

Tinst14

Tinst3

LDO6

Tinst13

Tinst4

REGEN1

Tinst12

Tinst11

Tinst5

LDOLN

Tinst6

LDOSUB

Tinst10

Tinst9

Tinst7

OSC16MOUT

Tinst8

RESET_OUT

INT

PWRON_IT=1

Interrupt Acknowledge

图 6-19. Power Sequence Example

The power sequences of the TPS65903x-Q1 device series are defined according to the processor

requirements, see the relevant Application Note for more information.

6.4.4 Start Up Timing and RESET_OUT Generation

The total start-up time of TPS65903x-Q1 from the first supply insertion until the release of reset to the

processor is defined by the boot time of internal resources as well as the OTP defined boot sequence.

Following figure shows the power up sequence timing and the generation of the RESET_OUT signal.

VCC1

VRTC

RC 32kHz

t₁

VIO

t₂

16.384-MHz oscillator

clock output

CLK32KGO

1^strail in

power

sequence

t₃

RESET_OUT

图 6-20. Start Up Timing Diagram

Detailed Description

73

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

The t₁time is the delay between VCC1 crossing the POR threshold and VIO (First rail in the power

sequence) rising up. The t₁time must be at least 6 ms. If the time from VCC to VIO is less than 6 ms, the

VIO buffers are supplied while the OTP is still being initialized, which could cause glitches on any VIO

output buffer. Supplying VIO at least 6 ms after supplying VCC makes sure that the OTP is initialized and

the output buffers are held low when VIO is supplied. The VIO_IN pin may be supplied before or after the

first rail in the power sequence is enabled, as long as it is at least 6 ms after VCC.

The t₂time is the internal 16.384-MHz crystal oscillator start-up time, or the external 32kHz clock input

availability delay time.

The t₃time is the delay between the power up sequence start and RESET_OUT release. RESET_OUT

will be released once power up sequence is complete and:

•

the 16.384MHz clock is stabilized if the 16.384MHz Xtal is present and the oscillator is enabled, or

the external 32kHz clock is stabilized and the 16.384MHz oscillator is bypassed, or

the GATE_RESET_OUT OTP bit is used to allow the TPS65903x-Q1 to power up without the

presence of the 16.384MHz crystal nor the external 32kHz clock input.

The duration of the power up sequence depends on OTP programming; average value is about 10ms.

6.4.5 Power On Acknowledge

The TPS65903x-Q1 device series is designed to support the following power on acknowledge modes:

POWERHOLD mode and AUTODEVON mode.

6.4.5.1 POWERHOLD Mode

In POWERHOLD mode, the acknowledge of the power on is achieved through a dedicated pin,

POWERHOLD. Upon receipt of an ON request, the device initiates the power-up sequence and asserts

the RESET_OUT pin high once it is in the ACTIVE state (reset released). While in the ACTIVE state, the

device remains active for 8 seconds and then automatically shuts down. During this time-frame, to keep

the device active, the host processor must assert and keep the POWERHOLD pin high. If the

POWERHOLD pin is then set back to low, it is interpreted as an OFF request by the device.

图 6-21 shows the POWERHOLD mode timing diagrams.

Switch-ON event

Device switch off starts

with no delay

Device maintained

ACTIVE for 8 seconds

Power-up sequence

RESET_OUT

POWERHOLD

图 6-21. POWERHOLD Mode Timing Diagrams

6.4.5.2 AUTODEVON Mode

In this mode, at the end of the power-up sequence, the register bit DEV_CTRL.DEV_ON is automatically

set to 1 and the device remains in its ACTIVE state until this bit is cleared by the host processor.

图 6-22 and 图 6-23 show the AUTODEVON mode timing diagrams.

74

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Switch-on event

Device maintained

ACTIVE for 8 seconds

Device switch off starts

with no delay

Power-up sequence

RESET_OUT

DEV_ON

I²C-SPI access

图 6-22. AUTODEVON Mode Timing Diagrams

The DEV_ON bit can also be configured so that it is not auto-updated (set to 1) at the end of the power-up

sequence. In this case, the device behaves similarly to the POWERWHOLD mode, except the host has

control over it using the DEV_CTRL.DEV_ON register bit instead of the POWERHOLD terminal.

Therefore, to keep the device active, the host must set and keep this bit at 1.

Switch-on event

Device maintained

ACTIVE for 8 seconds

Device switch off starts

with no delay

Power-up sequence

RESET_OUT

DEV_ON

I²C-SPI access

图 6-23. DEV_ON Mode Timing Diagrams

6.4.6 BOOT Configuration

All TPS65903x-Q1 device series resource settings are stored under the form of registers. Therefore, any

platform-related settings are linked to an action altering these registers. This action can be a static update

(register initialization value) or a dynamic update of the register (either from the user or from a power

sequence).

Resources and platform settings are stored in nonvolatile memory (OTP):

•

Static platform settings:

–

These settings define, for example, SMPS or LDO default voltages, GPIO functionality, and

TPS65903x-Q1 switch-on events. Part of the static platform settings can have two different values,

and these values are selected with the BOOT0 terminal. Static platform settings can be overwritten

by a power sequence or by the user.

•

Sequence platform settings:

–

These settings define TPS65903x-Q1 power sequences between state transitions, for example, the

OFF2ACT sequence when transitioning from OFF mode to ACTIVE mode. Each power sequence is

composed of several register accesses that define which resources (and their corresponding

registers) must be updated during the respective state transition. Three different sequences can be

defined with the BOOT0 and BOOT1 terminals. These settings can be overwritten by the user once

the power sequence completes its execution.

Detailed Description

75

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

STATIC

PLATFORM

SETTINGS

Platform settings

are modifiable by

µC during OFF,

ACTIVE, or SLEEP

transition

Reload du

r

i

ng

TE

on

(Default config for

all Boot; IO Mux,

Default

OFF ST

A

transiti

(According to respective

reset domain SWORST and

HWRST)

Voltage, etc.)

Power IC

SELECTABLE

PLATFORM

SETTINGS

Switch ON event

Initialization

done at reset

Resources

Configuration and

Control Registers

RD

BOOT0

SEQUENCE

PLATFORM

SETTINGS

Register updates

during

OFF, ACTIVE, and

SLEEP transitions

(State Transition

Micro Program)

Voltage modification,

resource

enable or disable

RD

µC controller

RD

BOOT0

BOOT1

图 6-24. Boot Terminal Control

6.4.6.1 Boot Terminal Selection

表 6-14 lists the boot terminals associated configurations.

注

Generally two of the three power sequence definitions are small modifications from the main

sequence to the respective OTP memory size.

表 6-14. Boot Terminal Associated Configurations

BOOT0

BOOT1

OTP CONFIGURATION

POWER SEQUENCE SELECTOR

0

1

0

1

0

1

Set_0

Set_1

Sel_0

Sel_1

Sel_2

The BOOT0 and BOOT1 terminals must be grounded or pulled up, but the terminals must not be

unconnected (high impedance).

The BOOT0 terminal is used to select between two different OTP sets (Set_0 and Set_1) of device

configuration (referred to as selectable platform settings in 图 6-24). For list of OTP programmable

parameters with programmed values refer to the Application Note of the relevant part number.

76

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

注

The respective VSEL[6:0] bit field in the SMPSn_VOLTAGE and SMPSn_FORCE registers

is mapped on a same OTP memory location, meaning that they are loaded at reset with the

same value and that the BOOT0 terminal changes the setting for both of them.

The BOOT0 terminal can also be used with the BOOT1 terminal as static selectors during execution of the

power sequence. This is intended to provide a possibility from within a static power sequence, to branch to

different instructions. This allows choosing power sequences (or subpart of power sequences) based on

BOOT terminals without altering power sequences themselves in OTP.

6.4.7 Reset Levels

The device series resource control registers are defined by three categories:

•

POR registers: POR registers

HW registers: HARDWARE registers

SWO registers: SWITCHOFF registers

These registers are associated to three levels of reset as described below:

•

Power-on reset (POR)

–

Power-on reset happens when the device gets its supplies and transition from the NOSUPPLY

state to the BACKUP state. This is the global device reset.

–

Additionally,

SMPS_THERMAL_STATUS,

SMPS_SHORT_STATUS,

SMSP_POWERGOOD_MASK, LDO_SHORT_STATUS and SWOFF_STATUS registers are in

POR domain. This list is indicative only.

•

HWRST – Hardware reset

–

Hardware reset happens when any OFF request is configured to generate a hardware reset. This

reset triggers a transition to the OFF state from either the ACTIVE or SLEEP state (execute either

the ACT2OFF or SLP2OFF sequence).

SWORST – Switch-off reset

–

Switch-off reset happens when any OFF request is configured to not generate a hardware reset.

This reset acts as the HWRST, except only the SWO registers are reset. The device goes in the

OFF state, from either ACTIVE or SLEEP, and therefore executes the ACT2OFF or SLP2OFF

sequence.

–

Power resource control registers for SMPS and LDO voltage levels and operating mode control are

in SWORST domain. Additionally some registers control the 32-kHz, REGENx and SYSENx,

watchdog, external charger control, and VSYS_MON comparator. This list is indicative only.

表 6-15 lists the reset levels, and 图 6-25 shows the reset levels versus registers.

表 6-15. Reset Levels

LEVEL

RESET TAG

POR

REGISTERS AFFECTED

COMMENT

0

POR, HW, SWO

This reset level is the lowest level, for which all registers are reset.

During hardware reset (HWRST), all registers are reset except the

POR registers.

1

2

HWRST

HW, SWO

SWO

SWORST

Only the SWO registers are reset.

Detailed Description

77

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

POR reset

HWRST reset

SWORST reset

v

SWO Registers

POR Registers

HW Registers

图 6-25. Reset Levels versus Registers

6.4.8 Warm Reset

The device series can execute a warm reset. The main purpose of this reset is to recover the device from

a locked or unknown state by reloading the default configuration. The warm reset is triggered by the

NRESWARM terminal. During a warm reset, the OFF2ACT sequence is executed regardless of the actual

state (ACTIVE, SLEEP) and the device returns to or remains in the ACTIVE state. Resources that are not

part of the OFF2ACT sequence are not impacted by warm reset and maintain the previous state.

Resources that are part of power-up sequence go to ACTIVE mode and the output voltage level is

reloaded from OTP or kept in the previous value depending on the WR_S bit in the SMPSx_CTRL register

or the LDOx_CTRL register.

6.4.9 RESET_IN

RESET_IN is a gating signal for on request and causes a switch-off event (Cold Reset or Shutdown). 表

6-11 shows that the RESET_IN behavior is programmable.

6.4.10 Watchdog Timer (WDT)

The watchdog timer has two modes of operation, periodic mode and interrupt mode.

In periodic mode, an interrupt is generated with a regular period N that is defined by the

WATCHDOG.TIMER setting. This interrupt is generated at the beginning of the period (when the

watchdog internal counter equals 1). The IC initiates a shutdown at the end of the period (when the

internal counter has reached N) only if the interrupt has not been cleared within the defined time frame (0

to N). In this mode, when the interrupt is cleared, the internal counter is not reset. The counter continues

to count until it reaches the maximum value (defined by the TIMER setting) and automatically rolls over to

0 in order to start a new counting period. Regardless of when the interrupt is cleared within a given period

(N), the next interrupt is generated only when the ongoing period completes (reaches N). The internal

watchdog counter is initialized and kept at 0 as long as the RESET_OUT terminal is low. The counter

begins counting as soon as the RESET_OUT terminal is released.

In interrupt mode, any interrupt source resets the watchdog counter and begins the counting. If the

sources of the interrupts are not cleared (INT line released) before the end of the predefined period N (set

by WATCHDOG.TIMER setting) then the IC initiates a shutdown. If the sources of the interrupts are

cleared within the predefined period, then the watchdog counter is discarded (DC) and no shutdown

sequence is initiated.

By default, the watchdog is disabled.

图 6-26 shows the watchdog timings.

78

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

PERIODIC MODE

Watchdog Internal

Counter

1

...

i

...

N

0

1

...

N

0

IT Not cleared in

allowed timeframe

New Watchdog IT

Watchdog IT cleared

New Watchdog IT

INT pin (active high)

Device Switch off

RESET_OUT pin

INTERRUPT MODE

Watchdog Internal

Counter

...

i

dc

0

1

...

N

0

X

0

1

IT Not cleared in

allowed timeframe

New IT (reset WDT counter)

INT pin (active high)

RESET_OUT pin

Device Switch off

IT cleared

图 6-26. Watchdog Timing Diagrams

6.4.11 System Voltage Monitoring

The power state-machine of the devices are controlled by comparators monitoring the voltage on the

VCC_SENSE and VCC1 terminals. For electrical parameters see Section 5.14.

POR:

When the supply at the VCC1 terminal is below the POR threshold, the devices are in the

NO SUPPLY state. All functionality, including RTC, is off. When the voltage in VCC1 rises

above the POR threshold, the device enters from the NO SUPPLY to the BACKUP state.

VSYS_LO: When the voltage on VCC1 terminal rises above VSYS_LO, the device enters from the

BACKUP state to the OFF state. When the device is in the ACTIVE, SLEEP, or OFF state

and the voltage on VCC1 decreases below VSYS_LO, the device enters BACKUP state.

When the device transitions from the ACTIVE state to the BACKUP state, all active SMPS

and LDO regulators, except LDOVRTC, are disabled simultaneously. When operating with a

16.384-MHz crystal, the regulators are immediately disabled after VCC1 becomes less than

VSYS_LO. When operating without a crystal, a 180-µs deglitch time occurs after VCC1

becomes less than VSYS_LO and before the regulators are disabled. The VSYS_LO level is

OTP programmable.

注

For silicon revision 1.3 or earlier, when operating without a crystal, transitioning from the

ACTIVE state to the BACKUP state using VSYS_LO while the outputs are active must

always be followed by a POR event to make sure the device is reset properly. See 节 6.3.10

to identify the silicon version in the device.

VSYS_MON: During power up, the VSYS_HI OTP value is used as a threshold for the VSYS_MON

comparator which is gating the PMIC start-up (as a threshold for transition from OFF to

ACTIVE state). The VSYS_MON comparator monitors the VCC_SENSE terminal. After

power up, software can configure the comparator threshold in the VSYS_MON register.

图 6-27 shows a block diagram of the system comparators.

Detailed Description

79

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

OTP bits

Register bits

VCC1

VSYS_LO

VCC_SENSE

VSYS_MON

Default VSYS_HI

VBUS_SENSE

VBUS_DET

VBUS_WKUP_UP

VSYS_HI

VSYS_MON

VSYS_LO

INT

STATE

OFF

ACTIVE / SLEEP

BACKUP

图 6-27. System Comparators

To use comparators in the system:

•

The VSYS_LO and VSYS_HI thresholds are defined in the OTP. Software cannot change these levels.

After start-up, the VSYS_MON comparator is automatically disabled. Software can select a new

threshold level using the VSYS_MON register and enable the comparator.

•

In order for the same coding on the rising and falling edge, the VSYS_MON comparator does not

include hysteresis and therefore can generate multiple interrupts when the voltage level is at the

threshold level. New interrupt generation has a 125-μs debounce time which allows the software to

mask the interrupt and update the threshold level or disable the comparator before receiving a new

interrupt.

图 6-28 shows additional details on the VSYS_MON comparator. When the VSYS_MON comparator is

enabled, and the internal buffer is bypassed, input impedance at the VCC_SENSE terminal is 500 kΩ

(typical). When the comparators are disabled, the VCC_SENSE terminal is at high impedance mode. If

GPADC is enabled to measure channel 6 or channel 7, 40 kΩ is added in parallel to the corresponding

comparator. See 表 6-3 for the GPADC input range.

80

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

To enable system voltage sensing above 5.25 V, an external resistive divider can be used. Internal buffers

are enabled by setting OTP bit HIGH_VCC_SENSE = 1 to provide high impedance for the external

resistive dividers. The maximum input level for the internal buffer is VCC1 – 1 V.

HIGH_VCC_SENSE

0 -> buffer bypassed (not enabled)

1 -> buffer enabled, bypass disbaled (Hi-Z at SENSE input)

VCC1

VCC_SENSE

1

0

VSYS_MON

500KΩ

HIGH_VCC_SENSE

Default VSYS_HI

30KΩ

10KΩ

Scale down,

divide by 4

GPADC

GPADC_IN7

图 6-28. VSYS_MON Comparator Details

6.4.11.1 Generating a POR

注

This section applies to silicon revisions 1.3 or earlier. Newer silicon revisions do not have this

requirement because the V_CCis continuously sampled. See 节 6.3.10 to identify the silicon

version in the device.

To generate a POR from a falling V_CC, V_CCis sampled every 1 ms and compared to the POR threshold. In

case VCC is discharged and resupplied quickly, a POR may not be reliably generated if VCC crosses the

POR threshold between samples. Another way to generate POR is to discharge the LDOVRTC regulator

to 0 V after VCC is removed. With no external load, this could take seconds for the LDOVRTC output to

discharge to 0 V. The PMIC should not be restarted after VCC is removed but before LDOVRTC is

discharged to 0 V. If necessary, TI recommends adding a pulldown resistor from the LDOVRTC output to

GND with a minimum of 3.9 kΩ to speed up the LDOVRTC discharge time. For more details, refer to POR

Generation in TPS65903x and TPS6591x Devices.

The value of the pulldown resistor should be chosen based on the desired discharge time and acceptable

current draw in the OFF state, but no greater than 0.5 mA. Use 公式 7 to calculate the pulldown resistor

based on the desired discharge time.

t_discharge(ms)

R_PD(kW) =

C_O(mF) ì 3

where

•

t_discharge= discharge time of the VRTC output

R_PD= pulldown resistance from the VRTC output to GND

Detailed Description

81

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

•

C_O= output capacitance on the VRTC line (typically 2.2 µF)

(7)

Because LDOVRTC is always on when VCC is supplied, additional current is drawn through the pulldown

resistor. The output current of LDOVRTC while the PMIC is in OFF state should not exceed 0.5 mA. Use

公式 8 to calculate the pulldown current.

1.8 V

I_PD

=

R_PD

where

•

I_PD= current through the pulldown resistor

R_PD= pulldown resistance from the VRTC regulator

(8)

82

Detailed Description

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

7 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

7.1 Application Information

The TPS659038-Q1 and TPS659039-Q1 devices are integrated power management integrated circuits

(PMIC), both available in a 169-pin, 0.8-mm pitch, 12-mm × 12-mm nFBGA package. The devices are

designed specifically for automotive applications. Both devices have seven configurable step-down

converter rails, with the ability to combine power rails and supply up to 9 A of output current in multi-phase

mode. The TPS659038-Q1 device also has eleven external LDOs, while TPS659039-Q1 device has 6

external LDOs. Both devices also come with a 12-bit GPADC with three external channels, eight

configurable GPIOs, two I²C interface channels or one SPI interface channel, a real-time clock module

with calendar function, a PLL for external clock sync and phase delay capability, and a programmable

power sequencer and control for supporting different processors and applications.

As both TPS659038-Q1 and TPS659039-Q1 devices are highly integrated PMIC devices, it is very

important that customers should take necessary actions to ensure the PMIC is operating under the

recommended operating conditions to ensure desired performance from the device. Additional cooling

strategies may be necessary to maintain the junction temperature below maximum limit allowed for the

device. To minimize the interferences when turning on a power rail while the device is in operation,

optimal PCB layout and grounding strategy are essential and are recommended in 节 9. In addition,

customer may take steps such as turning on additional rails only when the systems is operating in light

load condition.

Details on how to use this device in automotive infotainment or digital cluster applications are described

throughout this device specification. The following sections provides the typical application use case with

the recommended external components and layout guidelines. A design checklist for the TPS659038-Q1

and TPS659039-Q1 devices is also available on which provides application design guidance and cross

checks.

7.2 Typical Application

Following the typical application schematic and the list of recommended external components will allow

the TPS65903x-Q1 device to achieve accurate and stable regulation with its SMPS and LDO outputs.

These devices are internally compensated and have been designed to operate most effectively with the

component values listed in表 7-2. Deviating from these values is possible but is highly discouraged.

Application and Implementation

83

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

VCC1

VSYS

TPS659038-Q1

TPS659039-Q1

Processor

VSYS

VCC_SENSE

MPU

FDBK

SMPS12

VBAT_SENSE

PWRON

6 A

FDBK_GND

GPU & IVA

CORE

FDBK

SMPS45

4 A

RPWRON ⁽¹⁾

RESET_IN ⁽¹⁾

BOOT0

FDBK_GND

SMPS6

3 A

FDBK

BOOT1

GPIO_4

SMPS8

1A

DSPEVE

1.8-V IO

SYSEN

1

3.3-V buck

3V3

VIO_IN

1.8-V IO

SMPS7

1.8 V, 2 A

GPIO_6

SYSEN

2

DDR supply

REGEN1

SMPS9

3.3 V, 1 A

3.3-V Serial Interfaces

VDDA_RTC

GPIO_1

GPIO_2

LDOVRTC

1.8 V, 25 mA

ENABLE1 ⁽¹⁾

LDO9_IN

LDO9

1 V, 50 mA

3V3

VDD_RTC

LDOLN_IN

LDO12_IN

LDOLN

1.8 V, 50 mA

OSC, slicer, DPLL

VSYS

LDO1

1.p V, 0.3 A

Digital Core

RTC IO

LDO2

3.3 V, 0.3 A

LDO3

3 V, 0.3 A

1.8-V Serial Interfaces

LDO34_IN

LDO58_IN

LDO4 ⁽³⁾

0.3 A

External

Peripheral

VSYS

LDO5 ⁽³⁾

0.2 A

External

Peripheral

LDO8 ⁽³⁾

0.17 A

External

Peripheral

LDO6_IN

LDO6 ⁽³⁾

0.2 A

External

Peripheral

VSYS

LDO7 ⁽³⁾

0.2 A

External

Peripheral

LDO7_LDOUSB_IN

LDOUSB_IN2

VSYS

VBUS

LDOUSB

3.25 V, 0.1 A

USB PHY

GPADC_IN0 ⁽²⁾

GPADC_IN1 ⁽²⁾

GPADC_IN2 ⁽²⁾

I2C1_SCL_SCK

I2C1_SDA_SDI

I2C2_SCL_SCE

I2C2_SDA_SDO

CNTL I2C

SR I2C

GPADC_VREF ⁽¹⁾

VBUS

INT

NSLEEP

PREQ1

PORZ

RESET_OUT

NRESWARM

POWERDOWN

POWERGOOD

NRESWARM

GPIO_5

GPIO_7

CLK32KGO1V8

GPIOx

POWERHOLD

VBUSDET

GPIO_1

USB PHY

32-kHz IN

CLK32KGO

SMPS3

1.8 V,3 A

DDR3

(1) Input can be left floating if not used.

(2) Input can be left floating if not used.

(3) Only available on the TPS659038-Q1 device.

图 7-1. Application Schematic

84

Application and Implementation

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

C17

C40

C37

C8

C29

C6

BOOT0

BOOT1

SMPS1_IN

VSYS

C10

SMPS1

3 A

(DVS)

L2

SMPS1_SW

PWRON

LDOVANA LDOVRTC

PwrMgmt

RESET_IN

[Slave]

Control

inputs

VCC internal supply

SMPS1_GND

SMPS2_IN

Test and program

PWRDOWN

RPWRON

Dual-

phases

External power on

External power request

VSYS

EN

VSEL

RAMP

SMPS2

3 A

(DVS)

ENABLE1

NSLEEP

L3

SMPS2_SW

SMPS1_2_FDBK

SMPS1_2_FDBK_GND

SMPS2_GND

NRESWARM

C11, C13

C12

TPS659038-Q1

TPS659039-Q1

[Master]

I2C1_SCL_CLK

I2C1_SDA_SDI

I2C2_SCL_SCE

I2C2_SDA_SDO

I²C CNTL,

I²C DVS

or SPI

Triple-

phases

SMPS3

3 A

[Multi or

Stand-

alone]

SMPS3_IN

VSYS

JTAG

Application

processor

EN

L4

SMPS3_SW

DFT

VSEL

SMPS3_FDBK

RESET_OUT

INT

C14

OTP controller

OTP memory

C16

Control

outputs

SMPS3_GND

REGEN1

Internal

interrupt

events

Registers

SMPS4_IN

VSYS

C19

SMPS4

2 A

(DVS)

POWERGOOD

GPIO_0

L6

SMPS4_SW

VCC1

POR

[Master]

SMPS4_GND

SMPS5_IN

EN

VSEL

RAMP

VBUSDET

Dual-

phases

Programmable power

sequencer controller

VCC1

VSYS_LO

GPIO_1

GPIO_2

VSYS

SMPS5

2 A

(DVS)

REGEN2

L7

SMPS5_SW

ECO

PWM

DVS

VCC_SENSE

VSYS_MON

SMPS4_5_FDBK

SMPS4_5_FDBK_GND

SMPS5_GND

C23

C20, C24

[Slave]

GPIO_3

GPIO_4

Switch ON or OFF

GPIO signals

and controls

SYSEN1

Triple-

phases

SMPS7

2 A

[Multi or

Stand-

alone]

SMPS7_IN

VSYS

C27

VBUS_SENSE

VBUS_WKUP

EN

L9

SMPS7_SW

GPIO_6

GPIO_7

SYSEN2

SMPS7_FDBK

VSEL

C28

WDT

SMPS7_GND

SMPS6_IN

POWERHOLD

CLK32KGO1V8

GPIO_5

VSYS

C26

EN

L8

SMPS6_SW

SMPS6

2 A

(DVS)

OSC16MIN

VSEL

SMPS6_FDBK

RAMP

16-MHz

oscillator

C25

Y1

SMPS6_GND

SMPS8_IN

OSC16MOUT

RTC

Internal

RC

C21

C22

RC

32 kHz

VSYS

C43

OSC16MCAP

CLK32KGO

EN

VSEL

RAMP

oscillator

L10

C42

SMPS8_SW

SMPS8

1 A

(DVS)

SMPS8_FDBK

Output

buffers

C18

SMPS8_GND

SMPS9_IN

SYNCDCDC

(Optional)

VSYS

C45

EN

R2

L11

C44

SMPS9_SW

SMPS9

1 A

GPADC_IN0

GPADC_IN1

GPADC_IN2

VSEL

SMPS9_FDBK

SMPS9_GND

12-bit

SD-ADC

Thermal

monitoring

R3

R1

NTC

GPADC_VREF

Thermal shutdown

Hot die detection

GND_DIG

GND_ANA

PBKG

Grounds

VBG

Reference

and

REFGND1

bias

C9

Bypass

LDO9

50 mA

SDIO

(1)

LDOLN

50 mA

LDO1

300 mA

LDO2

300 mA

LDO3

300 mA

LDO4

300 mA

LDO5

200 mA

LDO8

170 mA

LDO6

200 mA

LDOUSB

100 mA

LDO7

200 mA

VSYS/VPREREGULATED(VPRE)

C1

C2

C3

C4

C5

C31

C29

C30

C32

C33

C35

C41

C39

C36

C38

C34

(1) Only available on the TPS659038-Q1 device.

图 7-2. Typical Application Schematic

Application and Implementation

85

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

7.2.1 Design Requirements

For this design example, use the parameters listed in 表 7-1.

表 7-1. Design Parameters

DESIGN PARAMETER

Supply voltage

Switching frequency

SMPS123 voltage

SMPS123 current

SMPS45 voltage

SMPS45 current

SMPS6 voltage

SMPS6 current

SMPS7 voltage

SMPS7 current

SMPS8 voltage

SMPS8 current

SMPS9 voltage

SMPS9 current

LDO1 voltage

O9039A344IZWSRQ1

3.3 V to 5 V

2.2 MHz

1.1 V

9 A

1.06 V

4 A

1.06 V

3 A

1.06 V

2 A

1.06 V

1 A

1.8 V

1 A

3.3 V

LDO1 current

300 mA

3.3 V

LDO2 voltage

LDO2 current

300 mA

1.8 V

LDO3 voltage

LDO3 current

200 mA

1.05 V

50 mA

1.8 V

LDO9 voltage

LDO9 current

LDOLN voltage

LDOLN current

LDOUSB voltage

LDOUSB current

50 mA

3.3 V

100 mA

86

Application and Implementation

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

7.2.2.2 SMPS Input Capacitors

All SMPS inputs need an input decoupling capacitor to minimize input ripple voltage. It is recommended to

use a 10-V, 4.7-µF capacitor for each SMPS. Depending on the input voltage of the SMPS, a 6.3-V or 10-

V capacitor can be used. See 表 7-2 for the specific part number of the input capacitor that is

recommended.

For optimal performance, the input capacitors should be placed as close to the SMPS input balls as

possible. See 节 9.1 for more information about component placement.

7.2.2.3 SMPS Output Capacitors

All SMPS outputs need an output capacitor to hold up the output voltage during a load step or changes to

the input voltage. To ensure stability across the entire switching frequency range, the TPS659038-Q1 and

TPS659039-Q1 devices require an output capacitance value between 33 µF and 57 µF. To meet this

requirement across temperature and DC bias voltage, it is recommended to use a 47-µF capacitor for

each SMPS. It is important to remember that each SMPS needs an output capacitor, not just each output

rail. For example, SMPS12 is a dual phase regulator and an output capacitor is required for the SMPS1

output and the SMPS2 output. Note, this requirement excludes any capacitance seen at the load and only

refers to the capacitance seen close to the device. Additional capacitance placed near the load can be

supported, but the end application or system should be evaluated for stability. See 表 7-2 for the specific

part number of the output capacitor that is recommended.

7.2.2.4 SMPS Inductors

Again, to ensure stability across the entire switching frequency range, it is recommended to use a 1-µH

inductor on each SMPS. It is important to remember that each SMPS needs an inductor, not just each

output rail. For example, SMPS12 is a dual phase regulator and an inductor is required for the

SMPS1_SW balls and the SMPS2_SW balls. See 表 7-2 for the specific part number of the inductor that is

recommended.

7.2.2.5 LDO Input Capacitors

All LDO inputs need an input decoupling capacitor to minimize input ripple voltage. It is recommended to

use a 2.2-µF capacitor for each LDO. Depending on the input voltage of the LDO, a 6.3-V or 10-V

capacitor can be used. See表 7-2 for the specific part number of the input capacitor that is recommended.

For optimal performance, the input capacitors should be placed as close to the LDO input balls as

possible. See 节 9.1 for more information about component placement.

7.2.2.6 LDO Output Capacitors

All LDO outputs need an output capacitor to hold up the output voltage during a load step or changes to

the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note, this requirement

excludes any capacitance seen at the load and only refers to the capacitance seen close to the device.

Additional capacitance placed near the load can be supported, but the end application or system should

be evaluated for stability. See 表 7-2 for the specific part number of the output capacitor that is

recommended.

7.2.2.7 VCC1

VCC1 is the supply for the analog input voltage of the device. This pin requires a 10-µF decoupling

capacitor.

Texas Instruments recommends to always power down the TPS65903x-Q1 before removing power from

VCC1. If the input voltage to the device is removed while the device is ACTIVE, the device will shut off

when VCC1 reaches the VSYS_LO threshold. As mentioned in the 节 6.4.11 section, once VCC1 reaches

VSYS_LO, there is about 180 us delay before all the output rails are disabled simultaneously.

There are two scenarios to consider in the system-level design in the event of unexpected loss of power.

88

Application and Implementation

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

7.2.2.7.1 Meeting the Power Down Sequence

To prevent a sequencing violation, it is important to block reverse current and implement a disable signal

to the PMIC. A Schottky diode can block reverse current when the input is removed. Additionally,

capacitors can help maintain the input voltage level while the power-down sequence occurs. Depending

on the system design, there are a couple ways to implement a disable signal.

For a system where the TPS65903x-Q1 is powered by the system input voltage, a supervisor can be used

to create a logic signal, indicating if the power is at a good level. An example of this solution is shown in

图 7-3.

VIN

(5 V)

VCC

PMIC

GND

Supervisor

ENABLE

图 7-3. Supporting Uncontrolled Power Down When the PMIC is Supplied by the System Input Voltage

An alternative solution is possible when a pre-regulator is present. In the case of the pre-regulator, the

pre-regulator output capacitance can also act as the energy storage to maintain VCC1 for the necessary

time. The total supply capacitance should be calculated to support the worst-case leakage current during

power down so that the voltage is maintained until the power-down sequence completes. 图 7-4 shows an

example of this configuration.

VIN

(12 V)

5 V

Buck

VCC

PGOOD

PMIC

GND

ENABLE

图 7-4. Supporting Uncontrolled Power Down when the PMIC is Supplied by a Preregulator

To determine the capacitance needed at the output of the pre-regulator, use 公式 9. This equation is used

to ensure that the power down sequence is complete before the device is disabled.

C = I × ΔT / (VCC1 – VSYS_LO)

where

•

C is total capacitance on VCC1, including pre-regulator output capacitance and PMIC input

capacitance

•

I is the total current on the PMIC input supply

ΔT is the time it takes the power-down sequence to complete

VCC1 is the voltage at the VCC1 pin

VSYS_LO is the threshold where the device is disabled

(9)

7.2.2.7.2 Maintaining Sufficient Input Voltage

In the event of high loading during loss of input voltage, there is a risk to go below the voltage level

necessary for the internal logic of the device to work properly before the device is disabled. This means

that when the VCC1 voltage supply level becomes lower than the VSYS_LO threshold, the input voltage

may continue dropping to very low voltages during the 180 us ±10% delay before the device is disabled.

Application and Implementation

89

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

If a large input voltage drop occurs before the device is disabled, the internal logic can no longer properly

drive the FETs of the SMPS, and it is possible that the high-side FET and low-side FET of the SMPS are

on at the same time. In the event that the high-side and low-side FETs for an SMPS are on at the same

time, there is a direct path from SMPSx_IN to SMPSx_GND, allowing cross-conduction and possible

damage of the device.

In order to prevent damage or irregular switching behavior, it is important that the voltage at the

SMPSx_IN pin stays above 1.8 V, including negative transients, before the device is disabled. The

minimum voltage seen at the SMPSx_IN pin is dependent on VCC1 and the PCB inductance between the

SMPSx_IN pin and the input capacitor. Use 公式 10 to determine the minimum capacitance needed on

VCC1 to ensure that the device continues switching properly before it is disabled.

C = I × ΔT / (VSYS_LO – VCC1_MIN

)

where

•

C is total capacitance on VCC1, including pre-regulator output capacitance and PMIC input

capacitance

•

I is the total current on the PMIC input supply

ΔT is the maximum debounce time after VCC1 = VSYS_LO before the device switches off (198us)

VSYS_LO is the threshold where the device is disabled

VCC1_MINis the minimum VCC1 voltage to keep the SMPSx_IN transients above 1.8 V

(10)

When measuring the SMPSx_IN and VCC1 during power down, use active differential probes and a high

resolution oscilloscope (4GS/sec or more). VCC1 can be measured over the 10uF input capacitor.

However, SMPSx_IN must be measured at the pin in order to measure the transients on this rail

accurately. To measure SMPSx_IN, place the negative lead of the differential probe at a nearby GND,

such as the GND of the SMPSx_IN input capacitor. Place the positive lead of the differential probe as

close as possible to the SMPSx_IN pin. With this set up, verify that SMPSx_IN, including the ripple on this

signal, does not drop below 1.8V before the SMPS stops switching. See 图 7-5 for an example of how to

take this measurement. For ways to decrease the amplitude of the transient spikes, see 表 9-1 for

recommended parasitic inductance requirements.

SMPSx_IN

VCCA

1.8 V minimum

SMPSx_SW

图 7-5. Waveform of SMPSx_IN Transients

7.2.2.8 VIO_IN

VIO_IN is the supply for the digital circuits inside the device. This ball requires a 0.1-µF decoupling

capacitor.

90

Application and Implementation

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

7.2.2.9 16-MHz Crystal

The TPS659038-Q1 and TPS659039-Q1 have the ability to accept a 16-MHz crystal input. Providing the

16-MHz crystal input to the device allows the output of a stable and accurate 32-kHz clock to be used by

the applications processor. The crystal input is divided down by 500 internally to produce the 32-kHz

output clock. The crystal should be connected to the device as shown in 图 7-6.

6.3 V

C1

OSC16MCAP

GND

2.2 µF

A3

A2

OSC16MIN

V1

OSC16MOUT

16.384 MHz

10 pF

GND

图 7-6. Crystal Input Configuration

As shown in 图 7-6, the OSC16MCAP pin requires a 2.2-µF 6.3-V filtering capacitor near the ball. Also,

the crystal requires between 9 pF and 11 pF of load capacitance on both terminals. To meet this

requirement, using two 10-pF capacitors is recommended. See 表 7-2 for the specific load capacitors that

are recommended.

The 16-MHz crystal is not required for operation of the TPS659038-Q1 and TPS659039-Q1 devices. The

OSC16M_CFG OTP bit can be set to disable the 16-MHz crystal completely, and enable the following 2

alternative options for system clock generation:

1. A 32-kHz square wave can be supplied to the OSC16MIN pin. This option is typically used in

applications where the processor requires an accurate system clock and there is one already available

in the system. In that case, the available 32-kHz clock can be provided to the PMIC and added to the

boot sequence as an output. In this configuration, the OSC16MOUT and OSC16MCAP pins can be left

floating, and the internal 16-MHz oscillator is bypassed. Bypassing the 16-MHz oscillator results in a

lower quiescent current.

2. If the application does not require an accurate system clock for the processor, then providing one to

the PMIC is not required. This option produces a lower quiescent current as seen in 节 5. In this

configuration, the OSC16MIN pin should be grounded, while the OSC16MOUT and OSCMCAP pins

can be left floating. Lastly, the GATE_RESET_OUT OTP bit should be used to allow the device to

power up without the presence of the 16.384-MHz crystal nor the 32-kHz clock input.

If the OSC16M_CFG OTP bit is set to 0, a 16-MHz crystal must be present for the proper operation of the

device.

7.2.2.10 GPADC

Instructions on how to perform a software conversion with the GPADC:

1. Enable software conversion mode – GPADC_SW_SELECT.SW_CONV_EN

2. Select the channel to convert – GPADC_SW_SELECT.SW_CONV0_SEL

–

For channel 0, set up the current source in the GPADC_CTRL1 register if needed.

3. For minimum latency, the GPADC can be set to always on (instead of default enabled from conversion

request) by GPADC_CTRL1.GPADC_FORCE.

4. Unmask software conversion interrupt – INT3_MASK.GPADC_EOC_SW

5. Start conversion – GPADC_SW_SELECT.SW_START_CONV0.

6. An interrupt is generated at the end of the conversion INT3_STATUS.GPADC_EOC_SW.

7. Read conversion result – GPADC_SW_CONV0_MSB and GPADC_SW_CONV0_LSB

8. Expected result = dec(GPADC_SW_CONV0_MSB[3:0].GPADC_SW_CONV0_LSB[7:0])/ 4096 × 1.25

Application and Implementation

91

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

× scalar

Instructions on how to perform an auto conversion with the GPADC:

1. Select the channel to convert – GPADC_AUTO_SELECT.AUTO_CONV0_SEL

2. Configure auto conversion frequency – GPADC_AUTO_CTRL.COUNTER_CONV

3. Set the threshold level for comparison – GPADC_THRESH_CONV0_MSB.THRESH_CONV0_MSB,

GPADC_THRESH_CONV0_LSB.THRESH_CONV0_LSB

–

Level = expected voltage threshold / (1.25 × scalar) × 4096 (in hexadecimal)

4. Set if the interrupt is triggered when conversion is above or below threshold –

GPADC_THRESH_CONV0_MSB.THRESH_CONV0_POL

5. Triggering the threshold level can also be programmed to generate shutdown –

GPADC_AUTO_CTRL.SHUTDOWN_CONV0

6. Unmask AUTO_CONV_0 interrupt – INT3_MASK.GPADC_AUTO_0

7. Enable AUTO CONV0 – GPADC_AUTO_CTRL.AUTO_CONV0_EN

8. When selected channel crosses programmed threshold, interrupt is generated –

INT3_STATUS.GPADC_AUTO_0

9. Conversion results are available – GPADC_AUTO_CONV0_MSB, GPADC_AUTO_CONV0_LSB

10. If shutdown was enabled, chip switches off after SWOFF_DLY, unless interrupt is cleared

The example above is for CONV0; a similar procedure applies to CONV1.

7.2.3 Application Curves

0.2

0.16

0.12

0.08

0.04

0

0.2

0.16

0.12

0.08

0.04

0

-0.04

-0.08

-0.12

-0.16

-0.2

-0.04

-0.08

-0.12

-0.16

-0.2

V_O= 1.05 V

V_O= 1.2 V

V_O= 1.05 V

V_O= 1.2 V

0

1.5

3

4.5

6

7.5

9

0

1

2

3

4

5

6

Output Current (A)

D011

D0112

V_I= 3.8 V

ƒ_S= 2.2 MHz

V_I= 3.8 V

ƒ_S= 2.2 MHz

图 7-7. SMPS Load Regulation for 9-A Triple Phase

图 7-8. SMPS Load Regulation for 6-A Dual Phase

92

Application and Implementation

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

0.2

0.16

0.12

0.08

0.04

0

0.2

0.16

0.12

0.08

0.04

0

-0.04

-0.08

-0.12

-0.16

-0.04

-0.08

-0.12

-0.16

-0.2

V_O= 1.05 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

V_O= 1.05 V

V_O= 1.2 V

-0.2

0

0.8

1.6

2.4

3.2

4

0

0.5

1

1.5

2

2.5

3

Output Current (A)

D013

D014

V_I= 3.8 V

ƒ_S= 2.2 MHz

V_I= 3.8 V

ƒ_S= 2.2 MHz

图 7-9. SMPS Load Regulation for 4-A Dual Phase

图 7-10. SMPS Load Regulation for 3-A Single Phase

0.2

0.16

0.12

0.08

0.04

0

0.16

0.12

0.08

0.04

0

-0.04

-0.08

-0.12

-0.16

-0.2

-0.04

-0.08

V_O= 1.05 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

V_O= 1.05 V

V_O= 1.2 V

V_O= 1.8 V

V_O= 2.5 V

-0.12

-0.16

-0.2

0

0.4

0.8

1.2

1.6

2

0

0.2

0.4

0.6

0.8

1

Output Current (A)

D015

D016

V_I= 3.8 V

ƒ_S= 2.2 MHz

V_I= 3.8 V

ƒ_S= 2.2 MHz

图 7-11. SMPS Regulation for 2-A Single Phase

图 7-12. SMPS Load Regulation for 1-A Single Phase

V_O(10 mV/div, AC coupled)

V_O(20 mV/div, AC coupled)

I_O(500 mA/div)

0.5 mA to 500 mA

load step,

0.5 mA to 500 mA load step,

t_r= t_f= 1 µs

t_r= t_f= 100 ns

Time = 2.5 ms/div

Time = 5 ms/div

V_I= 3.5 V

V_O= 1.05 V

ƒ_S= 2.2 Hz

V_I= 3.5 V

V_O= 1.05 V

ƒ_S= 2.2 Hz

图 7-13. Typical SMPS Load Transient Response for SMPS8 and

图 7-14. Typical SMPS Load Transient Response for SMPS12,

SMPS9

SMPS3, SMPS45, SMPS6 and SMPS7

Application and Implementation

93

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

8 Power Supply Recommendations

The TPS659038-Q1 and TPS659039-Q1 devices are designed to work with an analog supply voltage

range of 3.135 V to 5.25 V. The input supply should be well regulated and connected to the VCC1 pin, as

well as SMPS and LDO input pins with appropriate bypass capacitors as recommended in the 图 7-1

diagram. If the input supply is located more than a few inches from the device, additional capacitance may

be required in addition to the recommended input capacitors at the VCC1 pin and the SMPS and LDO

input pins.

9 Layout

9.1 Layout Guidelines

As in every switch-mode-supply design, general layout rules apply:

•

Use a solid ground-plane for power-ground (PGND)

Use an independent ground for Logic, LDOs and Analog (AGND)

Connect those Grounds at a star-point ideally underneath the IC.

Place input capacitors as close as possible to the input-balls of the IC. This is paramount and more

important than the output-loop!

•

Place the inductor and output capacitor as close as possible to the phase node (or switch-node) of the

IC.

•

Keep the loop-area formed by Phase-node, Inductor, output-capacitor and PGND as small as possible.

For traces and vias on power-lines, keep inductance and resistance as small as possible by using wide

traces, avoid switching layers but if needed, use plenty of vias.

The goal of the previously listed guidelines is a layout that minimizes emissions, maximizes EMI-immunity,

and maintains a safe operating area for the IC.

To minimize the spiking at the phase-node for both, high-side (VIN – SWx) as well as low-side (SWx –

PGND), the decoupling of VIN is paramount. Appropriate decoupling and thorough layout should ensure

that the spikes never exceed 7V across the high-side and low-side FETs.

The guidelines shown in 图 9-1 regarding parasitic inductance and resistance are recommended.

94

Layout

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

Parasitic Inductance: < 1 nH

Parasitic resistance:

Parasitic resistance: < 3 mΩ

As small as possible to

get best efficiency

Parasitic inductance: < 1 nH

Parasitic resistance: < 2 mΩ

SMPSx_SW

SMPSx_IN

SMPSx_SW

SMPSx_GND

Connection to power plane

Parasitic resistance:

As small as possible to get best

efficiency

For multiple

capacitors, keep the

parasitic resistance as

small as possible

among capacitors

Parasitic inductance: < 1 nH

Parasitic resistance: < 2 mΩ

图 9-1. Parasitic Inductance and Resistance

表 9-1 lists the maximum allowable parasitic (inductance measured at 100 MHz) and the achievable

values in an optimized layout.

表 9-1. Maximum Allowable Parasitic

CONNECTION

PowerPlane – C_IN

C_IN– SMPSx_IN

MAXIMUM ALLOWABLE

INDUCTANCE

MAXIMUM ALLOWABLE

RESISTANCE

OPTIMIZED LAYOUT

(EVM) INDUCTANCE

OPTIMIZED LAYOUT (EVM)

RESISTANCE

n/a

N/A for SOA, keep small for

efficiency

N/A

N/A for SOA, keep small for

efficiency

1 nH

3 mΩ

SMPS1

SMPS2

SMPS3

SMPS4

SMPS5

SMPS6

SMPS7

SMPS8

SMPS9

SMPS1

SMPS2

SMPS3

SMPS4

SMPS5

SMPS6

SMPS7

SMPS8

SMPS9

0.533 nH

0.465 nH

0.494 nH

0.472 nH

0.517 nH

0.518 nH

0.501 nH

0.509 nH

0.491 nH

0.552 nH

0.583 nH

0.668 nH

0.57 nH

SMPS1

SMPS2

SMPS3

SMPS4

SMPS5

SMPS6

SMPS7

SMPS8

SMPS9

SMPS1

SMPS2

SMPS3

SMPS4

SMPS5

SMPS6

SMPS7

SMPS8

SMPS9

1.77 mΩ

1.22 mΩ

1.37 mΩ

1.23 mΩ

1.27 mΩ

1.69 mΩ

1.27 mΩ

1.42 mΩ

1.4 mΩ

C_IN– SMPSx_GND

1 nH

2 mΩ

1.21 mΩ

0.8 mΩ

0.93 mΩ

0.81 mΩ

0.76 mΩ

1.13 mΩ

0.83 mΩ

0.73 mΩ

0.82 mΩ

0.577 nH

0.608 nH

0.646 nH

0.67 nH

0.622 nH

Layout

95

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

表 9-1. Maximum Allowable Parasitic (continued)

CONNECTION

MAXIMUM ALLOWABLE

INDUCTANCE

MAXIMUM ALLOWABLE

RESISTANCE

OPTIMIZED LAYOUT

(EVM) INDUCTANCE

OPTIMIZED LAYOUT (EVM)

RESISTANCE

SMPSx_SW – Inductor

N/A

N/A for SOA, keep small for

efficiency

N/A

SMPS1

SMPS2

SMPS3

SMPS4

SMPS5

SMPS6

SMPS7

SMPS8

SMPS9

1.9 mΩ

0.89 mΩ

1.99 mΩ

0.93 mΩ

1.37 mΩ

1.11 mΩ

1.17 mΩ

1.35 mΩ

0.88 mΩ

Inductor – C_OUT

C_OUT– GND

n/a

N/A for SOA, keep small for

efficiency

N/A

N/A for SOA, keep small for

efficiency

Use dedicated GND plane to

keep inductance low

mΩ

SMPS1

SMPS2

SMPS3

SMPS4

SMPS5

SMPS6

SMPS7

SMPS8

SMPS9

0.552 nH

0.583 nH

0.668 nH

0.57 nH

SMPS1

SMPS2

SMPS3

SMPS4

SMPS5

SMPS6

SMPS7

SMPS8

SMPS9

1.21 mΩ

0.8 mΩ

0.93 mΩ

0.81 mΩ

0.76 mΩ

1.13 mΩ

0.83 mΩ

0.73 mΩ

0.82 mΩ

0.577 nH

0.608 nH

0.646 nH

0.67 nH

0.622 nH

GND(C_IN) – GND(C_OUT

)

Use dedicated GND plane to

keep inductance low

mΩ

Use dedicated GND plane to mΩ

keep inductance low

Texas Instruments recommends to measure the voltages across the high-side FET (voltage at SMPSx_IN

vs. SMPSx_SW) and the low-side FET (SMPSx_SW vs. SMPSx_GND) with a high-bandwidth high-

sampling rate scope with a low-capacitance probe (ideally a differential probe). Measure the voltages as

close as possible to the IC-balls and verify the amplitude of the spikes. A small-loop-GND-connection to

the closest accessible SMPSx_GND (of the particular rail) is essential. Ideally, this measurement should

be performed during start-up of the respective SMPS-rail (to take in account the inrush-current) and at

high temperature.

When measuring the voltage difference between the SMPSx_IN and SMPSx_SW pins, there should be a

maximum of 7 V when measuring at the pins. Similarly, when measuring the voltage difference between

the SMPSx_SW and SMPSx_GND pins, there should be a maximum of 7 V when measuring at the pins.

For more information on cursor-positioning, see 图 9-2 and 图 9-3.

96

Layout

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

7 V maximum

SMPSx_IN - SMPSx_SW

Measure across the high-side FET (SMPSx_IN – SMPSx_SW) as close to the IC as possible. The preferred

measurement is with a differential probe. The negative side of the probe should be at SMPSx_SW and the positive

side of the probe should measure SMPSx_IN. As shown in this image, the voltage across the high-side FET should

not exceed 7 V. Repeat the measurement for all SMPSs in use.

图 9-2. Measuring the High-side FET (Differentially)

7 V maximum

SMPSx_SW - SMPSx_GND

Measure across the low-side FET (SMPSx_SW – SMPSx_GND) as close to the IC as possible. The preferred

measurement is with a differential probe. The negative side of the probe should be at SMPSx_GND and the positive

side of the probe should measure SMPSx_SW. As shown in this image, the voltage across the low-side FET should

not exceed 7 V.Repeat the measurement for all SMPSs in use.

图 9-3. Measuring the Low-side FET (Differentially)

Layout

97

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

9.2 Layout Example

图 9-4, 图 9-5, 图 9-6, and 图 9-7 show the actual placement and routing on the EVM.

图 9-4. Top Layer Overview of Inductor Placement

98

Layout

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

C_OUT

C_IN

C_OUT

图 9-5. Bottom Layer Overview of Input and Output Capacitor Placement

图 9-6. Top Layer Zoomed View of SMPS123 SW Connections to Inductors

Layout

99

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

图 9-7. Bottom Layer Zoomed View of SMPS123 Input and Output Capacitor Layout

100

Layout

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

www.ti.com.cn

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

10 器件和文档支持

10.1 器件支持

10.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构

成此类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

10.1.2 器件命名规则

本数据表使用下列缩略词和术语。有关术语、缩写和定义的详细列表，请参阅《TI 术语表》。

ADC

APE

DVS

GPIO

LDO

PM

模数转换器

应用处理器引擎

数字电压调节

通用输入输出

低压降线性稳压器

电源管理

PMIC

PSRR

RTC

SMPS

OTP

电源管理集成电路

电源抑制比

实时时钟

开关模式电源

一次性 EPROM

10.2 文档支持

10.2.1 相关文档

如需相关文档，请参阅：

•

德州仪器 (TI)，自适应（动态）电压（频率）调节 - 动机和实施应用报告

德州仪器 (TI)，《脱离电池运行的汽车信息娱乐系统处理器电源参考设计》

德州仪器 (TI)，《TPS65903x 和 TPS6591x 器件中的 GPADC 使用指南》

德州仪器 (TI)，《TPS65903x 和 TPS6591x 器件中的 POR 生成》

德州仪器 (TI)，《TPS659038-Q1 和 TPS659039-Q1 EVM 用户指南》

德州仪器 (TI)，《TPS659038-Q1 和 TPS659039-Q1 寄存器映射》

10.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。

表 10-1. 相关链接

器件

产品文件夹

请单击此处

立即订购

技术文档

请单击此处

工具与软件

请单击此处

支持和社区

请单击此处

TPS659038-Q1

TPS659039-Q1

请单击此处

10.4 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周

接收产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.5 社区资源

器件和文档支持

101

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

TPS659038-Q1, TPS659039-Q1

ZHCSG94L –AUGUST 2013–REVISED FEBRUARY 2019

www.ti.com.cn

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信

息。

10.6 商标

ECO 模式, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

10.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

10.8 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通

知，且不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

11.1 封装材料信息

湿敏等级目标：JEDEC MSL3 (260°C)

表 11-1. 封装特性

器件名称

TPS659038-Q1

TPS659039-Q1

封装类型

nFBGA

可订购产品名称

尺寸 (mm)

请参见

12mm x 12mm

间距焊球阵列 (mm)

ViP（过孔位于焊盘中）

阵列栅格

0.8

否

13 × 13，未填充

焊球数

169

厚度 (mm)

（包括焊球的最大高度）

1.4

湿敏等级目标

其它

等级-3-260C-168 HR

绿色环保，符合 RoHS 标准

102

机械、封装和可订购信息

提交文档反馈意见

产品主页链接: TPS659038-Q1 TPS659039-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Jan-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

O9039A385IZWSRQ1

O9039A385IZWSTQ1

O9039A387IZWSRQ1

O9039A387IZWSTQ1

O9039A389IZWSRQ1

O9039A389IZWSTQ1

NFBGA

ZWS

169

1000

250

330.0

24.4

12.35 12.35

2.3

16.0

24.0

Q1

1000

250

1000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Jan-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

O9039A385IZWSRQ1

O9039A385IZWSTQ1

O9039A387IZWSRQ1

O9039A387IZWSTQ1

O9039A389IZWSRQ1

O9039A389IZWSTQ1

NFBGA

ZWS

169

1000

250

336.6

41.3

1000

250

1000

250

Pack Materials-Page 2

PACKAGE OUTLINE

ZWS0169A

NFBGA - 1.4 mm max height

SCALE 1.100

PLASTIC BALL GRID ARRAY

12.1

11.9

B

A

BALL A1 CORNER

12.1

11.9

(0.9)

0.45

1.4 MAX

C

SEATING PLANE

0.12 C

BALL TYP

TYP

0.35

9.6 TYP

SYMM

(1.2) TYP

N

M

L

K

J

H

G

F

SYMM

9.6

TYP

E

D

C

0.55

169X

0.45

0.15

0.05

C A B

C

B

A

0.8 TYP

1

2

3

4

5

6

7

8

9 10 11 12 13

0.8 TYP

BALL A1 CORNER

4221886/C 05/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ZWS0169A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

169X ( 0.4)

1

2

5

6

8

9

12 13

3

4

7

10 11

A

B

C

(0.8) TYP

D

E

F

SYMM

G

H

J

K

L

M

N

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

METAL UNDER

SOLDER MASK

0.05 MAX

0.05 MIN

(

0.4)

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221886/C 05/2021

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SSZA002 (www.ti.com/lit/ssza002).

www.ti.com

EXAMPLE STENCIL DESIGN

ZWS0169A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

(

0.4) TYP

(0.8) TYP

1

2

5

6

8

9

12 13

3

4

7

10 11

A

B

C

(0.8) TYP

D

E

F

SYMM

G

H

J

K

L

M

N

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4221886/C 05/2021

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款

的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	O9039A387IZWSRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 7 个降压转换器和 6 个 LDO、适用于 ARM Cortex-A15 处理器的汽车类 3.135V 至 5.25V PMIC \| ZWS \| 169 \| -40 to 85 集成电源管理电路转换器
文件：	总110页 (文件大小：2194K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

O9039A387IZWSRQ1 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E