ONET1131ECRSMR [TI]
具有集成时钟和数据恢复 (CDR) 功能的外部调制激光驱动器 | RSM | 32 | -40 to 100;
| 型号： | ONET1131ECRSMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成时钟和数据恢复 (CDR) 功能的外部调制激光驱动器 | RSM | 32 | -40 to 100 时钟 ATM 异步传输模式 驱动 CD 电信 电信集成电路 驱动器 |
| 文件： | 总50页 (文件大小：2396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
ONET1131EC 集成时钟和数据恢复 (CDR) 功能的
外部调制激光器驱动器
1 特性
2 应用
1
•
集成调制器驱动器，其最小输出幅值最高可达 2
Vpp（单端），偏置电流最高可达 150mA（拉电
流）。
•
10Gbps 无源光纤网络 (PON)、针对 FTTx 部署的
光线路终端 (OLT) 收发器
•
XFP 和 SFP+ 10Gbps 同步光纤网络 (SONET)
OC-192 光学收发器
•
支持外部调制激光器，包括电吸收调制器激光器
(EML) 和基于 Mach-Zahnder 调制器 (MZM) 的激
光器。
•
•
XFP 和 SFP+ 10GBASE-ER/ZR 光学收发器
8x 和 10x 光纤通道光学收发器
•
•
集成 CDR 功能，支持 9.80Gbps 至 11.7Gbps 无
参考运行
3 说明
集成数模转换器 (DAC) 和模数转换器 (ADC) 的双
线制数字接口，可实现控制和诊断管理
ONET1131EC 是一款 2.5V EML 调制器驱动器，支持
发送时钟和数据恢复 (CDR) 功能，无需基准时钟即可
在 9.8Gbps 至 11.7Gbps 范围内运行。该器件在 CDR
旁路模式下能够以较低数据速率运行，其双线制串行接
口支持针对 多项功能 （如输出极性选择和输入均衡）
进行数字控制。
•
•
•
•
输出极性选择
用于调节 CDR 带宽的可编程抖动传输带宽
CDR 旁路模式，支持以低数据速率运行
具有可选监视器光电二极管 (PD) 范围的自动功率
控制 (APC) 回路
发送路径由 1 个可调节输入均衡器（可均衡长达
300mm
•
•
•
•
•
•
•
可编程发送输入均衡器
发送器交叉点调节和去加重功能
包括激光安全 特性
（12 英寸）FR4 印刷电路板微带或带状传输线）、1
个多速率 CDR 及 1 个输出调制器驱动器组成。该器件
以交叉点调节和去加重的形式提供输出波形控制，从而
增加光学眼图波罩裕度。该器件提供激光器偏置电流并
集成自动功率控制 (APC) 回路，以补偿平均光学功率
随电压、温度和时间的变化。
电源监视器和温度传感器
2.5V 单电源
工作温度范围：-40°C 至 100°C
表面贴装 4mm x 4mm 32 引脚四方扁平无引线
(QFN) 封装（间距为 0.4mm）
ONET1131EC 内置模数转换器和数模转换器，支持管
理收发器，无需使用专用微控制器。
器件信息(1)
器件型号
封装
VQFN (32)
封装尺寸（标称值）
ONET1131EC
4.00mm x 4.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化框图
Optical Module
n-bit
parallel
data
5ata
59-
ꢀÜó
PD
DEMUX
+ Optical
CDR
t!
ÇL!
/lock
/lock
Optical Transceiver
wh{!
hptical Ciber
n-bit
parallel
data
Laser + Optical
MUX
EQ
CDR
[5
5ata
ꢀÜó
/lock
/lock
ONET1131EC
Çh{!
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEQ6
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
目录
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 21
7.5 Programming .......................................................... 21
7.6 Register Mapping.................................................... 22
Application Information and Implementations . 36
8.1 Application Information............................................ 36
8.2 Typical Application, Transmitter Differential Mode.. 36
Power Supply Recommendations...................... 40
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Function........................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 DC Electrical Characteristics .................................... 6
6.6 AC Electrical Characteristics..................................... 8
6.7 Timing Requirements................................................ 9
6.8 Timing Diagram Definitions..................................... 10
6.9 Typical Characteristics............................................ 11
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
8
9
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 41
11 器件和文档支持 ..................................................... 42
11.1 接收文档更新通知 ................................................. 42
11.2 社区资源................................................................ 42
11.3 商标....................................................................... 42
11.4 静电放电警告......................................................... 42
11.5 Glossary................................................................ 42
12 机械、封装和可订购信息....................................... 42
7
4 修订历史记录
日期
修订版本
注释
2016 年 9 月
*
首次发布。
2
Copyright © 2016, Texas Instruments Incorporated
ONET1131EC
www.ti.com.cn
ZHCSFG0 –SEPTEMBER 2016
5 Pin Configuration and Function
The ONET1131EC is packaged in a small footprint 4 mm x 4 mm 32 pin RoHS compliant QFN package with a
lead pitch of 0.4 mm.
RSM Package
32 PIN VQFN
(Top View)
32 31 30 29 28 27 26 25
NC
24
23
LOL
MONB
GND
1
2
COMP
22 GND
3
4
NC
21
DIN+
DIN-
20 NC
5
6
GND
PD
19 GND
SCK
SDA
18
17
7
8
MONP
9
10 11 12 13 14 15 16
Pin Functions
NUMBER
LOL
NAME
Type
DESCRIPTION
Loss of lock indicator. High level indicates the transmitter CDR is out of lock. Open
drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper
operation. This pin is 3.3 V tolerant.
1
Digital-out
MONB
GND
2
Analog-out
Supply
Bias current monitor.
Circuit ground.
3, 6, 19, 22
4
Non-inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN–.
Must be AC coupled.
DIN+
DIN–
Analog-in
Analog-in
Inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN+. Must
be AC coupled.
5
PD
7
Analog
Analog-out
Analog-in
Analog
Photodiode input. Pin can source or sink current dependent on register setting.
Photodiode current monitor.
MONP
LF
8
9
10
Transmitter loop filter capacitor.
BIAS
VCC
Sinks or sources the bias current for the laser in both APC and open loop modes.
2.5 V ± 5% supply.
11, 14, 27, 30
Supply
Inverted transmitter data output. Internally terminated in single-ended operation
mode.
OUT–
12
CML-out
OUT+
VDD
13
15
CML-out
Supply
Non-Inverted transmitter data output.
2.5 V ± 5% supply for the digital circuitry.
Output amplitude control. Output amplitude can be adjusted by applying a voltage of
0 to 2 V to this pin. Leave open when not used.
AMP
16
Analog-in
Copyright © 2016, Texas Instruments Incorporated
3
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
Pin Functions (continued)
NUMBER
SDA
NAME
Type
DESCRIPTION
2-wire interface serial data input. Requires an external 4.7-kΩ to10-kΩ pull-up resistor
17
18
Digital-in/out
to VCC. This pin is 3.3-V tolerant.
2-wire interface serial clock input. Requires an external 4.7-kΩ to10-kΩ pull-up
resistor to VCC. This pin is 3.3-V tolerant.
SCK
NC
Digital-in
20, 21, 24, 25,
26, 28, 29
Do not connect
Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF
capacitor to ground.
COMP
23
Analog
Transmitter fault detection flag. High level indicates that a fault has occurred. Open
drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper
operation. This pin is 3.3-V tolerant.
FLT
DIS
31
Digital-out
Disables the bias current when set to high state. Includes a 250-kΩ pull-up resistor to
VCC. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper
operation Toggle to reset a fault condition. This is an ORed function with the
TXBIASEN bit (bit 2 in register 1). This pin is 3.3-V tolerant.
32
Digital-in
4
Copyright © 2016, Texas Instruments Incorporated
ONET1131EC
www.ti.com.cn
ZHCSFG0 –SEPTEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
3
UNIT
V
Supply voltage
Voltage
at VCC, VDD
at 3.3-V tolerant pins LOL, SDA, SCK, FLT, DIS
3.6
V
at all other pins MONB, DIN+, DIN–, PD, MONP, LF, BIAS,
OUT–, OUT+, AMP, COMP
–0.5
3
V
Maximum current at transmitter input pins DIN+, DIN–
10
mA
mA
Maximum current at transmitter output
OUT+, OUT–
125
pins
Maximum junction temperature, TJ
Storage temperature, Tstg
125
150
°C
°C
–65
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
UNIT
Electrostatic
discharge
V(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.37
2
TYP
MAX
UNIT
VCC
VIH
VIL
Supply Voltage
2.5
2.63
V
V
V
Digital input high voltage
Digital input low voltage
DIS, SCK, SDA, 3.3-V tolerant IOs
0.8
Control bit TXPDRNG = 1x, step size = 3 µA
Control bit TXPDRNG = 01, step size = 1.5 µA
Control bit TXPDRNG = 00, step size = 0.75 µA
TXCDR_DIS = 0
3080
1540
770
Photodiode current range
µA
9.8
1
11.7
11.7
2
Serial Data rate
Gbps
TXCDR_DIS = 1
VAMP
tR(IN)
Amplitude control input voltage range
0
V
Input rise time
20%–80%
20%–80%
30
30
45
ps
ps
°C
tF(IN
)
Input fall time
45
TC
Temperature at thermal pad
–40
100
Copyright © 2016, Texas Instruments Incorporated
5
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
UNIT
6.4 Thermal Information
RSM (VQFN)
32 PINS
37.2
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
30.1
7.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
7.6
RθJCbot
2.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 DC Electrical Characteristics
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA, unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC
Supply voltage
2.37
2.5
2.63
V
Supply current in single-ended TX
mode with CDRs enabled
158
380
197
493
119
298
164
193
508
237
623
193
376
200
526
mA
mW
mA
mW
mA
mW
mA
TXMODE = 1, TXCDR_DIS = 0, TX VOUT = 2
VPP single-ended, I(BIAS) = 0 mA
Power dissipation in single-ended TX
mode with CDRs enabled
Supply current in differential TX mode
with CDRs enabled
TXMODE = 0, TXCDR_DIS = 0, TX VOUT = 2
VPP single-ended, I(BIAS) = 0 mA
Power dissipation in differential TX
mode with CDRs enabled
IVCC
Supply current in single-ended TX
mode with CDRs disabled
TXMODE = 1, TXCDR_DIS = 1, TX VOUT = 2
VPP single-ended, I(BIAS) = 0 mA
Power dissipation in single-ended TX
mode with CDRs disabled
Supply current in differential TX mode
with CDRs disabled
TXMODE = 0, TXCDR_DIS = 1, TX VOUT = 2
VPP single-ended, I(BIAS) = 0 mA;
Power dissipation in differential TX
mode with CDRs disabled
410
100
mW
R(IN)
Data input resistance
Data input termination mismatch
Ooutput resistance
Differential between DIN+ / DIN–
Ω
5%
20
R(OUT)
Single-ended at OUT+ or OUT–
DIS pull up to VCC
60
Ω
Digital input current
–20
2.1
µA
LOL, FLT pull-up to VCC
,
VOH
Digital output high voltage
V
ISOURCE = 37.5 μA
LOL, FLT pull-up to VCC
ISINK = 350 μA
,
VOL
Digital output low voltage
Minimum bias current
0.4
5
V
(1)
I(BIAS-MIN)
See
mA
mA
Source. BIASPOL = 0, DAC set to maximum,
open and closed loop
145
95
150
100
I(BIAS-MAX)
Maximum bias current
Sink. BIASPOL = 1, DAC set to maximum,
open and closed loop
mA
I(BIAS-DIS)
Bias current during disable
Average power stability
100
µA
dB
V
APC loop enabled
±0.5
±3
Source. TXBIASPOL = 0
Sink. TXBIASPOL = 1
VCC - 0.45
Bias pin compliance voltage
Temperature sensor accuracy
0.45
V
With 1-point external mid-scale calibration
°C
(1) The bias current can be set below the specified minimum according to the corresponding register setting; however, in closed loop
operation settings below the specified value may trigger a fault.
6
Copyright © 2016, Texas Instruments Incorporated
ONET1131EC
www.ti.com.cn
ZHCSFG0 –SEPTEMBER 2016
DC Electrical Characteristics (continued)
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA, unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Photodiode reverse bias voltage
Photodiode fault current level
APC active, I(PD) = 1500 μA
1.3
2.3
V
(2)
Percent of target I(PD)
150%
12.5%
25%
V(PD)
I(MONP) / I(PD) with control bit PDRNG = 1X
I(MONP) / I(PD) with control bit PDRNG = 01
I(MONP) / I(PD) with control bit TXPDRNG = 00
With external mid-scale calibration
10%
20%
15%
30%
60%
15%
Photodiode current monitor ratio
40%
50%
Monitor diode DMI accuracy
Bias current monitor ratio
–15%
I(MONB) / I(BIAS) (nominal 1/100 = 1%), V(MONB)
< 1.5V
0.9%
1%
1..1%
Bias current DMI accuracy
I
(BIAS) ≥ 20 mA
–15%
–2%
15%
2%
Power supply monitor accuracy
With external mid-scale calibration
VCC voltage level which triggers power-on
reset
VCC(RST)
VCC reset threshold voltage
VCC reset threshold voltage hysteresis
Fault voltage at MONB
1.8
100
1.2
2.1
V
mV
V
VCC(RSTHYS)
V(MONB-FLT)
TXFLTEN = 1, TXDMONB = 0, Fault occurs
if voltage at MONB exceeds this value
1.15
1.15
1.25
1.25
TXFLTEN = 1, TXMONPFLT = 1, TXDMONP
= 0, Fault occurs if voltage at MONP
exceeds this value
V(MONP-FLT)
Fault voltage at MONP
1.2
V
(2) Specified by design over process, supply and temperature variation
Copyright © 2016, Texas Instruments Incorporated
7
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
6.6 AC Electrical Characteristics
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gbps
dB
TX INPUT SPECIFICATIONS
CDR lock range
CPRI, Ethernet, SONET, Fibre Channel
0.05 GHz < f ≤ 0.1 GHz
0.1 GHz < f ≤ 5.5 GHz
9.80
20
12
8
11.7
SDD11
Differential input return loss
15
15
5.5 GHz < f < 12 GHz
SDD11
SDD11
Differential to common mode conversion
Common mode input return loss
Input AC common mode voltage tolerance
Total Non-DDJ
0.1 GHz < f < 12 GHz
10
3
dB
dB
0.1 GHz < f < 12 GHz
15
mV
Total jitter less ISI
0.45
0.65
UIPP
UIPP
UIPP
mVPP
dB
T(JTX)
S(JTX)
VIN
Total Jitter
Sinusoidal Jitter Tolerance
Differential input voltage swing
EQ high freq boost
With addition of input jitter, See Figure 1
Maximum setting; 7 GHz
100
6
1000
EQ(boost)
9
TX OUTPUT SPECIFICATIONS
Differential output return loss
Minimum output amplitude
0.01 GHz < f < 12 GHz
12
dB
VO(MIN)
AC Coupled Outputs, 50-Ω single-ended load
0.5
VPP
TX OUTPUT SPECIFICATIONS in SINGLE-ENDED MODE of OPERATION (TXMODE = 1)
VO(MAX)
Maximum output amplitude
Output amplitude stability
High Cross Point Control Range
Low Cross Point Control Range
Cross Point Stability
AC Coupled Outputs, 50-Ω load, single-ended
AC Coupled Outputs, 50-Ω load, single-ended
50-Ω load, single-ended
2
70%
-5
VPP
230
75%
35%
mVPP
50-Ω load, single-ended
40%
5
50-Ω load, single-ended
pp
dB
TXDEADJ[0..3] = 1111, TXPKSEL = 0
TXDEADJ[0..3] = 1111, TXPKSEL = 1
5
6
Output de-emphasis
TX OUTPUT SPECIFICATIONS in DIFFERENTIAL MODE of OPERATION (TXMODE = 0)
VO(MAX)
Maximum output amplitude
Output amplitude stability
High Cross Point Control Range
Low Cross Point Control Range
Cross Point Stability
AC Coupled Outputs, 100-Ω differential load
AC Coupled Outputs, 100-Ω differential load
100-Ω differential load
3.6
65%
–5
VPP
230
75%
35%
mVPP
100-Ω differential load
40%
5
100-Ω differential load
pp
dB
TXDEADJ[0..3] = 1111, TXPKSEL = 0
TXDEADJ[0..3] = 1111, TXPKSEL = 1
5
6
Output de-emphasis
CDR SPECIFICATIONS
BW(TX)
J(PTX)
Jitter Transfer Bandwidth
9.95 Gbps, PRBS31
8
1
MHz
dB
Jitter Peaking
> 120 kHz
JGEN(rms)
JGEN(PP)
Random RMS jitter generation
Total jitter generation
Clock pattern, 50 kHz to 80 MHz
Clock pattern, 50 kHz to 80 MHz, BER = 10-12
6
mUIrms
mUIPP
60
8
Copyright © 2016, Texas Instruments Incorporated
ONET1131EC
www.ti.com.cn
ZHCSFG0 –SEPTEMBER 2016
6.7 Timing Requirements
Over recommended operating conditions, typical operating condition is at VCC = 2.5 V and TA = 25°C
MIN
TYP
50
MAX
UNIT
CAPC 0.01 µF, IPD = 500 µA, PD coupling ratio CR = 150,
PDRNG = 01
t(APC)
APC time constant
µs
t(INIT1)
t(INIT2)
t(OFF)
Power-on to initialize
Initialize to transmit
Transmitter disable time
Disable negate time
DIS pulse width
Power-on to registers ready to be loaded
Register load STOP command to part ready to transmit valid data
Rising edge of DIS to I(BIAS) ≤ 0.1 × I(BIAS-NOMINAL)
Falling edge of DIS to I(BIAS) ≥ 0.9 × I(BIAS-NOMINAL)
Time DIS must held high to reset part
0.2
1
2
5
1
ms
ms
µs
1
t(ON)
ms
ns
t(RESET)
t(FAULT)
100
Fault assert time
Time from fault condition to FLT high
50
µs
OUTPUT SPECIFICATIONS in SINGLE-ENDED MODE of OPERATION (TXMODE = 1)
tR(OUTTX)
tF(OUTTX)
Output rise time
Output fall time
20% - 80%, AC Coupled Outputs, 50-Ω load, single-ended
20% - 80%, AC Coupled Outputs, 50-Ω load, single-ended
30
30
42
42
ps
ps
TXEQ_DIS = 1, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage
4
7
12
ISI(TX)
Intersymbol interference
ps
TXEQ_DIS = 0, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage, maximum
equalization with 18-inch transmission line at the input.
Serial data output random
jitter
R(JTX)
0.4
0.75
psRMS
ps
TXPKSEL = 0
TXPKSEL = 1
28
35
Output de-emphasis width
OUTPUT SPECIFICATIONS in DIFFERENTIAL MODE of OPERATION (TXMODE = 0)
tR(OUTTX)
tF(OUTTX)
Output rise time
Output fall time
20%–80%, AC Coupled Outputs, 100-Ω differential load
20%–80%, AC Coupled Outputs, 100-Ω differential load
30
30
42
42
ps
ps
TXEQ_DIS = 1, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage
4
7
10
ISI(TX)
Intersymbol interference
ps
TXEQ_DIS = 0, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage, maximum
equalization with 18-inch transmission line at the input.
Serial data output random
jitter
R(JTX)
0.4
0.75
psRMS
ps
TXPKSEL = 0
TXPKSEL = 1
28
35
Output Peaking Width
CDR SPECIFICATIONS
t(Lock,TX) CDR Acquisition time
LOL assert time
2
ms
500
μs
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Figure 1. Input Sinusoidal Jitter Tolerance (INF-8077i Rev. 4.5 XFP MSA)
SDA
SCK
tBUFœ
tLOW
tf
tHDSTA
tr
tHIGH
P
S
S
P
tHDDAT
tSUDAT
tHDSTA
tSUSTA
tSUSTO
Figure 2. 2-Wire Interface Diagram
6.8 Timing Diagram Definitions
MIN
TYP
MAX
UNIT
kHz
µs
fSCK
SCK clock frequency
400
tBUF
Bus free time between START and STOP conditions
1.3
0.6
tHDSTA
Hold time after repeated START condition. After this period, the first
clock pulse is generated
µs
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Low period of the SCK clock
High period of the SCK clock
Setup time for a repeated START condition
Data HOLD time
1.3
0.6
0.6
0
µs
µs
µs
µs
ns
ns
ns
µs
Data setup time
100
Rise time of both SDA and SCK signals
Fall time of both SDA and SCK signals
Setup time for STOP condition
300
300
tF
tSUSTO
0.6
10
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6.9 Typical Characteristics
Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR
enabled (unless otherwise noted).
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80 100 120 140 160 180 200
TXMOD Register 12 Setting (Decimal)
TXMOD Register 12 Setting (Decimal)
D010
D011
TXMODE = 0
TXMODE = 1
Figure 3. Deterministic Jitter vs Modulation Current
Figure 4. Deterministic Jitter vs Modulation Current
8
6
4
2
0
8
6
4
2
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Free-Air Temperature (°C)
Free-Air Temperature (°C)
D012
D013
TXMODE = 0
Figure 5. Deterministic Jitter vs Temperature
TXMODE = 1
Figure 6. Deterministic Jitter vs Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
20 40 60 80 100 120 140 160 180 200 220
Modulation Current Register Setting (Decimal)
-40
-20
0
20
40
60
80
100
Free-Air Temperature (°C)
D014
D015
TXMODE = 1
Figure 7. Random Jitter vs Modulation Current
TXMODE = 1
Figure 8. Random Jitter vs Temperature
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR
enabled (unless otherwise noted).
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
Rise Time
Fall Time
Rise Time
Fall Time
0
0
0
20 40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting - Decimal
-40
-20
0
20
40
60
80
100
Free-Air Temperature (°C)
D016
D017
TXMODE = 1
TXMODE = 1
Figure 9. Rise-Time and Fall-Time vs Modulation Current
Figure 10. Rise-Time and Fall-Time vs Temperature
180
180
160
140
120
100
80
160
140
120
100
80
60
60
40
40
20
20
0
0
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
TXBIAS Register 15 and 16 Setting (Decimal)
TXBIAS Register 15 and 16 Setting (Decimal)
D018
D019
Figure 11. Source Bias Current in Open Loop Mode vs Bias
Register Setting
Figure 12. Sink Bias Current in Open Loop Mode vs Bias
Register Setting
0.5
0.4
0.3
0.2
0.1
0
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
20
40
60
80
100 120 140 160 180
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Photodiode Current (mA)
1
Bias Current (mA)
D020
D021
TXPDRNG[0..1] = 00
Figure 13. Bias-Monitor Current I(MONB) vs Bias Current
Figure 14. Photodiode-Monitor Current I(MONP) vs PD Current
12
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR
enabled (unless otherwise noted).
4.5
2.5
4
2
3.5
3
1.5
1
2.5
2
1.5
1
0.5
0
0.5
0
0
20 40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting (Decimal)
0
20 40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting (Decimal)
D022
D023
TXMODE = 0
TXMODE = 1
Figure 15. Output Voltage vs Modulation Current
Figure 16. Output Voltage vs Modulation Current
300
290
280
270
260
250
240
230
220
260
250
240
230
220
210
200
190
180
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Free Air Temperature (°C
Free Air Temperature (°C)
D024
D025
TXMODE = 0
Bias Current = 0
TXMODE = 1
Bias Current = 0
Figure 17. Supply Current vs Temperature
Figure 18. Supply Current vs Temperature
180
160
140
120
100
80
1.2
1
0.8
0.6
0.4
0.2
0
60
40
20
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
TXBMF Register 17 Setting (Decimal)
TXPMF Register 18 Setting (Decimal)
D026
D027
Figure 19. Bias Current Monitor Fault vs TXBMF Register
Setting
Figure 20. Photodiode Current Monitor Fault vs TXPMF
Register Setting
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR
enabled (unless otherwise noted).
TXMODE = 0
15 ps/Div
TXMODE = 1
15 ps/Div
Figure 21. Eye-Diagram at 11.3 Gbps
Figure 22. Eye-Diagram at 11.3 Gbps
14
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7 Detailed Description
7.1 Overview
A simplified block diagram of the ONET1131EC is shown in Functional Block Diagram.
The ONET1131EC consists of a transmitter path, an analog reference block, an analog to digital converter, and a
2-wire serial interface and control logic block with power-on reset.
The transmit path consists of an adjustable input equalizer, a multi-rate CDR and an output modulator driver. The
output driver provides a differential output voltage but can be operated in a single-ended mode to reduce the
power consumption. Output waveform control, in the form of cross-point adjustment and de-emphasis are
available to improve the optical eye mask margin. Bias current for the laser is provided and an integrated
automatic power control (APC) loop to compensate for variations in average optical power over voltage,
temperature and time is included.
The ONET1131EC contains an analog to digital converter to support transceiver digital diagnostics and can
report the supply voltage, laser bias current, laser photodiode current and internal temperature.
The 2-wire serial interface is used to control the operation of the device and read the status of the control
registers.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Equalizer
The data signal is applied to an input equalizer by means of the input signal pins DIN+ / DIN–, which provide on-
chip differential 100-Ω line termination. The equalizer is enabled by default and can be disabled by setting the
transmitter equalizer disable bit TXEQ_DIS = 1 (bit 1 of register 10). Equalization of up to 300 mm (12 inches) of
microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of
equalization is set through register settings TXCTLE [0..3] (register 11). The device can accept input amplitude
levels from 100 mVpp up to 1000 mVpp.
7.3.2 CDR
The clock and data recovery function consists of a Phase-Locked Loop (PLL) and retimer. The CDR can be
operated without a reference clock and the Voltage Controlled Oscillator (VCO) can cover 9.8 Gbps to 11.7 Gbps
data rates. The PLL is phase locked to the incoming data stream and attenuates the high frequency jitter on the
data, producing a recovered clean clock with substantially reduced jitter. An external capacitor for the PLL loop
filter is connected to the LF pin. A value of 2.2 nF is recommended. The clean clock is used to retime the
incoming data, producing an output signal with reduced jitter, and in effect, resetting the jitter budget for the
transmitter.
The CDR is enabled by default. The CDR can be disabled and bypassed by setting the transmitter CDR disable
bit TXCDR_DIS = 1 (bit 4 of register 10). Alternatively, the CDR can be left powered on but bypassed by setting
the transmitter CDR bypass bit TX_CDRBP = 1 (bit 3 of register 10); however, this function only works if the
receiver CDR bypass bit RX_CDRBP (bit 3 of register 4) is also set to 1.
The CDR is designed to meet the XFP Datacom requirements and Telecom requirements for a maximum of 1-dB
jitter peaking at a frequency greater than 120 kHz. The CDR is not designed to meet the Telecom regenerator
requirements of jitter peaking less than 0.03 dB at a frequency less than 120 kHz. The default CDR bandwidth is
typically 4.5 MHz and can be adjusted using the SEL_RES[0..2] bits (bits 5 to 7 of register 51). Adjusting these
bits changes the bandwidth of both the transmitter and receiver CDRs.
For the majority of applications, the default settings in register 19 for the transmitter CDR can be used. However,
for some applications or for test purposes, some modes of operation may be useful. The frequency detector for
the PLL is set to an automatic mode of operation by default. When a signal is applied to the transmitter input the
frequency detector search algorithm will be initiated to determine the frequency of the data. The default algorithm
ensures a fast CDR lock time of less than 2 ms. The fast lock can be disabled by setting the transmitter CDR fast
lock disable bit TXFL_DIS = 1 (bit 3 of register 19). Once the frequency has been detected then the frequency
detector will be disabled and the supply current will decrease by approximately 10mA. In some applications, such
as when there are long periods of idle data, it may be advantageous to keep the frequency detector permanently
enabled by setting the transmitter frequency detector enable bit TXFD_EN = 1 (bit 5 of register 19). For test
purposes, the frequency detector can be permanently disabled by setting the transmitter frequency detector
disable bit TXFD_DIS = 1 (bit 4 of register 19). For fast lock times the frequency detector can be set to one of
two preselected data rates using the transmitter frequency detection mode selection bits TXFD_MOD[0..1] (bits 6
and 7 of register 19). If it is desired to use the retimer at lower data rates than the standard 9.8 to 11.7Gbps then
the transmitter divider ratio should be adjusted accordingly through TXDIV[0..2] (bits 0 to 2 of register 19). For
example, for re-timed operation at 2.5 Gbps the divider should be set to divide by 4.
7.3.3 Modulator Driver
The modulation current is sunk from the common emitter node of the limiting output driver differential pair by
means of a modulation current generator, which is digitally controlled by the 2-wire serial interface.
The collector nodes of the output stages are connected to the transmitter output pins TXOUT+ and TXOUT–.
The collectors have internal 50Ω back termination resistors to VCC_TX. The outputs are optimized to drive a 50
Ω single-ended load and to obtain the maximum single-ended output voltage of 2.0Vpp, AC coupling and
inductive pull-ups to VCC are required. For reduced power consumption the DC resistance of the inductive pull-
ups should be minimized to provide sufficient headroom on the TXOUT+ and TXOUT– pins.
The polarity of the output pins can be inverted by setting the transmitter output polarity switch bit, TXOUTPOL
(bit 5 of register 10) to 1. In addition, the output driver can be disabled by setting the transmitter output driver
disable bit TXOUT_DIS = 1 (bit 6 of register 10).
16
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Feature Description (continued)
The output driver is set to differential output by default. In order to reduce the power consumption for single-
ended applications driving an electroabsorptive modulated laser (EML) the output drive register 13 should be set
to single-ended mode. The single-ended output signal is enabled by setting the transmitter mode select bit
TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and
disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).
Output de-emphasis can be applied to the signal by adjusting the transmitter de-emphasis bits TXDEADJ[0..3]
(bits 0 to 3 of register 13). In addition, the width of the applied de-emphasis can be increased by setting the
transmitter output peaking width TXPKSEL = 1 (bit 6 of register 11). The wide peaking width would typically be
useful for a more capacitive transmitter load. How de-emphasis is applied is controlled through the TXSTEP bit
(bit 5 of register 13). Setting TXSTEP = 1 delays the time of the applied de-emphasis and has more of an impact
on the falling edge. A graphical representation of the two de-emphasis modes is shown in Figure 23. Using de-
emphasis can help to optimize the transmitted output signal; however, it will add to the power consumption.
The output edge speed can be set to slow mode of operation through the TXSLOW bit (bit 4 of register 13). For
transmitter modulation output settings (TXMOD - register 12) below 0xC0 it is recommended to set TXSLOW = 1
to reduce the output jitter.
Register 13
Register 13
Bits 0œ3
Bits 0œ3
Register 11
Bit 6
Register 11
Bit 6
Transmitter De-Emphasis
Register 13 Bit 5 = 0
Transmitter De-Emphasis
Register 13 Bit 5 = 1
Figure 23. Transmitter De-Emphasis Modes
7.3.4 Modulation Current Generator
The modulation current generator provides the current for the high speed output driver described above. The
circuit can be digitally controlled through the 2-wire interface block or controlled by applying an analog voltage in
the range of 0 to 2 V to the AMP pin. The default method of control is through the 2-wire interface. To use the
AMP pin set the transmitter amplitude control bit TXAMPCTRL = 1 (bit 0 of register 10).
An 8-bit wide control bus, TXMOD[0..7] (register 12), is used to set the desired modulation current and the output
voltage.
The entire transmitter signal path, including CDR, can be disabled and powered down by setting TX_DIS = 1 (bit
7 of register 10).
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Feature Description (continued)
7.3.5 DC Offset Cancellation and Cross Point Control
The ONET1131EC transmitter has DC offset cancellation to compensate for internal offset voltages. The offset
cancellation can be disabled by setting TXOC_DIS = 1 (bit 2 of register 10).
The crossing point can be moved toward the one level by setting TXCPSGN = 1 (bit 7 of register 14) and it can
be moved toward the zero level by setting TXCPSGN = 0. The percentage of shift depends upon the register
settings of the transmitter cross-point adjustment bits TXCPADJ[0..6] (register 14).
7.3.6 Bias Current Generation and APC Loop
The bias current for the laser is turned off by default and has to be enabled by setting the laser bias current
enable bit TXBIASEN = 1 (bit 2 of register 1). In open loop operation, selected by setting TXOLENA = 1 (bit 4 of
register 1), the bias current is set directly by the 10-bit wide control word TXBIAS[0..9] (register 15 and register
16). In Automatic Power Control (APC) mode, selected by setting TXOLENA = 0, the bias current depends on
the register settings TXBIAS[0..9] and the coupling ratio (CR) between the laser bias current and the photodiode
current. CR = IBIAS/IPD. If the photodiode cathode is connected to VCC and the anode is connected to the PD pin
(PD pin is sinking current) set TXPDPOL = 1 (bit 0 of register 1). If the photodiode anode is connected to ground
and the cathode is connected to the PD pin (PD pin is sourcing current), set TXPDPOL = 0.
Three photodiode current ranges can be selected by means of the photodiode current range bits TXPDRNG[0..1]
(bits 5 and 6 of register 1). The photodiode range should be chosen to keep the laser bias control DAC,
TXBIAS[0..9], close to the center of its range. This keeps the laser bias current set point resolution high. For
details regarding the bias current setting in open-loop mode as well as in closed-loop mode, see the Register
Mapping table.
The ONET1131EC has the ability to source or sink the bias current. The default condition is for the BIAS pin to
source the current (TXBIASPOL = 0). To act as a sink, set TXBIASPOL = 1 (bit 1 of register 1).
The bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a resistor between
MONB and GND, the bias current can be monitored as a voltage across the resistor. A low temperature
coefficient precision resistor should be used. The bias current can also be monitored as a 10 bit unsigned digital
word by setting the transmitter bias current digital monitor selection bit TXDMONB = 1 (bit 5 of register 16) and
removing the resistor from MONB to ground.
The photodiode current is monitored using a current mirror with various gains that are dependent upon the
photodiode current range being used. By connecting a resistor between MONP and GND, the photodiode current
can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be
used. The photodiode current can also be monitored as a 10 bit unsigned digital word by setting the transmitter
photodiode current digital monitor selection bit TXDMONP = 1 (bit 6 of register 16) and removing the resistor
from MONP to ground.
7.3.7 Laser Safety Features and Fault Recovery Procedure
The ONET1131EC provides built in laser safety features. The following fault conditions are detected if the
transmitter fault detection enable bit TXFLTEN = 1 (bit 3 of register 1):
1. Voltage at MONB exceeds the bandgap voltage (1.2 V) or, alternately, if TXDMONB = 1 and the bias current
exceeds the bias current monitor fault threshold set by TXBMF[0..7] (register 17). When using the digital
monitor, the resistor from the MONB pin to ground must be removed.
2. Voltage at MONP exceeds the bandgap voltage (1.2 V) and the analog photodiode current monitor fault
trigger bit, TXMONPFLT (bit 7 of register 1), is set to 1. Alternately, a fault can be triggered if TXDMONP = 1
and the photodiode current exceeds the photodiode current monitor fault threshold set by TXPMF[0..7]
(register 18). When using the digital monitor, the resistor from the MONP pin to ground must be removed.
3. Photodiode current exceeds 150% of its set value,
4. Bias control DAC drops in value by more than 50% in one step.
If the fault detection is being used then to avoid a fault from occurring at start-up it is recommended to set up the
required bias current and APC loop conditions first and enable the laser bias current (TXBIASEN = 1) as the last
step in the sequence of commands.
18
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Feature Description (continued)
If one or more fault conditions occur and the transmitter fault enable bit TXFLTEN is set to 1, the ONET1131EC
responds by:
1. Setting the bias current to zero.
2. Asserting and latching the TX_FLT pin.
3. Setting the TX_FLT bit (bit 5 of register 43) to 1.
Fault recovery is performed by the following procedure:
1. The transmitter disable pin TX_DIS and/or the transmitter bias current enable bit TXBIASEN are toggled for
at least the fault latch reset time.
2. The TX_FLT pin de-asserts while the transmitter disable pin TX_DIS is asserted or the transmitter bias
current enable bit TXBIASEN is de-asserted.
3. If the fault condition is no longer present, the part returns to normal operation with its prior output settings
after the disable negate time.
4. If the fault condition is still present, TX_FLT re-asserts once TX_DIS is set to a low level and/or TXBIASEN is
set to 0 and the part will not return to normal operation.
7.3.8 Analog Block
7.3.8.1 Analog Reference and Temperature Sensor
The ONET1131EC is supplied by a single 2.5 V ±5% supply voltage connected to the VCC and VDD pins. This
voltage is referred to ground (GND) and can be monitored as a 10 bit unsigned digital word through the 2-wire
interface.
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which
all other internally required voltages and bias currents are derived.
In order to minimize the module component count, the ONET1131ECprovides an on-chip temperature sensor.
The temperature can be monitored as a 10 bit unsigned digital word through the 2-wire interface.
7.3.8.2 Power-On Reset
The ONET1131EC has power on reset circuitry which ensures that all registers are reset to default values during
startup. After the power-on to initialize time (tINIT1), the internal registers are ready to be loaded. The part is ready
to transmit data after the initialize to transmit time (tINIT2), assuming that the enable chip bit EN_CHIP = 1 (bit 0 of
register 0). In addition, the disable pin DIS must be set to zero.
The ONET1131EC bias current can be disabled by setting the DIS pin high. The internal registers are not reset.
After the transmitter disable pin DIS is set low the part returns to its prior output settings.
7.3.8.3 Analog to Digital Converter
The ONET1131EC has an internal 10 bit analog to digital converter (ADC) that converts the analog monitors for
temperature, power supply voltage, bias current and photodiode current into a 10 bit unsigned digital word. The
first 8 most significant bits (MSBs) are available in register 40 and the 2 least significant bits (LSBs) are available
in register 41. Depending on the accuracy required, 8 bits or 10 bits can be read. However, due to the
architecture of the 2-wire interface, in order to read the 2 registers, 2 separate read commands have to be sent.
The ADC is enabled by default so to monitor a particular parameter, select the parameter with ADCSEL[0..2]
(bits 0 to 2 of register 3). Table 1 shows the ADCSEL bits and the parameter that is monitored.
Table 1. ADC Selection Bits and the Monitored Parameter
ADCSEL2
ADCSEL1
ADCSEL0
MONITORED PARAMETER
Temperature
0
0
0
0
0
0
1
1
0
1
0
1
Supply voltage
Bias current
Photodiode current
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To digitally monitor the photodiode current, ensure that TXDMONP = 1 (bit 6 of register 16) and that a resistor is
not connected to the MONP pin. To digitally monitor the bias current, ensure that TXDMONB = 1 (bit 5 of register
16) and that a resistor is not connected to the MONB pin. The ADC is disabled by default. To enable the ADC,
set the ADC oscillator enable bit OSCEN = 1 (bit 6 of register 3) and set the ADC enable bit ADCEN = 1 (bit 7 of
register 3).
The digital word read from the ADC can be converted to its analog equivalent through the following formulas.
7.3.8.3.1 Temperature
Temperature (°C) = (0.5475 × ADCx) – 273
(1)
(2)
7.3.8.3.2 Power Supply Voltage
Power supply voltage (V) = (1.36m × ADCx) + 1.76
7.3.8.3.3 Photodiode Current Monitor
IPD(μA) = 2 x [ (0.62 × ADCx) – 16] for TXPDRNG00
IPD(μA) = 4 x [ (0.62 × ADCx) – 16] for TXPDRNG01
IPD(μA) = 8 x [ (0.62 × ADCx) – 16] for TXPDRNG1x
(3)
(4)
(5)
7.3.8.3.4 Bias Current Monitor
IBIAS (mA) = (0.2 × ADCx) – 4.5
(6)
Where: ADCx = the decimal value read from the ADC
7.3.8.4 2-Wire Interface and Control Logic
The ONET1131EC uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are
driven, respectively, by the serial data and serial clock from a microprocessor, for example. The SDA and SCK
pins require external 4.7-kΩ to 10-kΩ pull-up resistor to VCC for proper operation.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access
to read out the control signals. The ONET1131EC is a slave device only which means that it cannot initiate a
transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The
master device provides the clock signal as well as the START and STOP commands. The protocol for a data
transmission is as follows:
1. START command
2. Seven (7) bit slave address (0001000) followed by an eighth bit which is the data direction bit (R/W). A zero
indicates a WRITE and a 1 indicates a READ.
3. 8 bit register address
4. 8 bit register data word
5. STOP command
Regarding timing, the ONET1131EC is I2C compatible. The typical timing is shown in Figure 2 and a complete
data transfer is shown in Figure 24. Parameters for Figure 2 are defined in the Timing Diagram Definitions.
7.3.8.5 Bus Idle
Both SDA and SCK lines remain HIGH
7.3.8.6 Start Data Transfer
A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH, defines a START
condition (S). Each data transfer is initiated with a START condition.
7.3.8.7 Stop Data Transfer
A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH defines a STOP condition
(P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate
on the bus, it can generate a repeated START condition and address another slave without first generating a
STOP condition.
20
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7.3.8.8 Data Transfer
Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the
transfer of data.
7.3.9 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the
SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and
hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data
line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the
slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more
data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on
the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition, see
Figure 2.
7.4 Device Functional Modes
The ONET1131EC has two main functional modes of operation: differential transmitter output and single-ended
transmitter output.
7.4.1 Differential Transmitter Output
Operation with differential output is the default mode of operation. This mode is intended for externally modulated
lasers requiring differential drive such as Mach Zehnder modulators.
7.4.2 Single-Ended Transmitter Output
In order to reduce the power consumption for single-ended EML applications the output driver should be set to
single-ended mode. The single-ended output signal can be enabled by setting the transmitter mode select bit
TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and
disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).
7.5 Programming
Write Sequence
1
1
1
8
1
8
1
1
7
S
Slave Address
Wr
A
Register Address
A
Data Byte
A
P
Read Sequence
1
1
1
8
1
1
1
1
8
1
1
7
7
S
Slave Address
Wr
A
Register Address
A
S
Slave Address
Rd
A
Data Byte
N
P
Legend
S
Start Condition
Wr
Rd
A
Write Bit (Bit Value = 0)
Read Bit (Bit Value = 1)
Acknowledge
N
Not Acknowledge
Stop Condition
P
Figure 24. Programming Sequence
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7.6 Register Mapping
7.6.1 R/W Control Registers
7.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
Figure 25. Core Level Register 0
7
6
5
4
3
2
1
0
GLOBAL SW_PIN RESET
RWSC
Reserved
I2C RESET
RWSC
EN_CHIP
RW
RW
RWSC
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset. RWSC = Read/Write self clearing (always reads back to zero)
Table 2. Core Level Register 0 Field Descriptions
Bit
Field
Type
Reset
Description
Global Reset SW
7
GLOBAL SW_PIN RESET
Reserved
RWSC
0
1 = reset, resets all I2C and EEPROM modules to default
0 = normal operation (self-clearing, always reads back ‘0’)
6:3
2
R/W
1
0
Reserved
Reserved
RWSC
Chip reset bit
1
0
I2C RESET
EN_CHIP
RWSC
R/W
0
1
1 = resets all I2C registers to default
0 = normal operation (self-clearing, always reads back ‘0’)
Enable chip bit
1 = Chip enabled
0 = Chip disabled
22
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7.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]
Figure 26. Core Level Register 1
7
6
5
4
3
2
1
0
TXMONPFLT
R/W
TXPDRNG1
R/W
TXPDRNG0
R/W
TXOLENA
R/W
TXFLTEN
R/W
TXBIASEN
R/W
TTXBIASPOL
R/W
TXPDPOL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3. Core Level Register 1 Field Descriptions
Bit
Field
Type
Reset
Description
Analog photodiode current monitor fault trigger bit
1 = Fault trigger on MONP pin is enabled
0 = Fault trigger on MONP pin is disabled
7
TXMONPFLT
R/W
0
Photodiode current range bits
1X: up to 3080 μA / 3 μA resolution
01: up to 1540 μA / 1.5 μA resolution
00: up to 770 μA / 0.75 μA resolution
6
5
TXPDRNG1
TXPDRNG0
R/W
0
Open loop enable bit
4
3
2
1
0
TXOLENA
TXFLTEN
TXBIASEN
TXBIASPOL
TXPDPOL
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1 = Open loop bias current control
0 = Closed loop bias current control
Fault detection enable bit
1 = Fault detection on
0 = Fault detection off
Laser Bias current enable bit
1 = Bias current enabled. Toggle to 0 to reset a fault condition.
0 = Bias current disabled
Laser Bias current polarity bit
1 = Bias pin sinks current
0 = Bias pin sources current
Photodiode polarity bit
1 = Photodiode cathode connected to VCC
0 = Photodiode anode connected to GND
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7.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
Figure 27. Core Level Register 2
7
6
5
4
3
2
1
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. Core Level Register 2 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
0
Reserved
7.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
Figure 28. Core Level Register 3
7
6
5
4
3
2
1
0
ADCEN
R/W
OSCEN
R/W
Reserved
R/W
ADCRST
R/W
Reserved
R/W
ADCSEL2
R/W
ADCSEL1
R/W
ADCSEL0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Core Level Register 3 Field Descriptions
Bit
Field
Type
Reset
Description
ADC enabled bit
1 = ADC enabled
0 = ADC disabled
7
ADCEN
R/W
0h
ADC oscillator bit
6
5
4
OSCEN
R/W
R/W
R/W
0h
0h
0h
1 = Oscillator enabled
0 = Oscillator disabled
Reserved
ADCRST
Reserved
ADC reset
1 = ADC reset
0 = ADC no reset
3
2
1
Reserved
ADCSEL2
ADCSEL1
R/W
R/W
R/W
0h
0h
0h
Reserved
ADC input selection bits <2:0>
000 selects the temperature sensor
001 selects the power supply monitor
010 selects IMONB
0
ADCSEL0
R/W
0h
011 selects IMONP
1XX are reserved
24
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7.6.2 RX Registers
7.6.2.1 RX Register 4 (offset = 0000 0000) [reset = 0h]
Figure 29. RX Register 4
7
6
5
4
3
2
1
0
DIS
R/W
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. RX Register 4 Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
Set bit to 1
Reserved
DIS
0
0
6:0
Reserved
7.6.2.2 RX Register 5 (offset = 0000 0000) [reset = 0h]
Figure 30. Reserved Register 5 - 9
7
6
5
4
3
2
1
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Reserved Register 5 - 9 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
0
Reserved
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7.6.3 TX Registers
7.6.3.1 TX Register 10 (offset = 0000 0000) [reset = 0h]
Figure 31. TX Register 10
7
6
5
4
3
2
1
0
TX_DIS
R/W
TXOUT_DIS
R/W
TXOUTPOL
R/W
TXCDR_DIS
R/W
TX_CDRBP
R/W
TXOC_DIS
R/W
TXEQ_DIS
R/W
TXAMPCTRL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. TX Register 10 Field Descriptions
Bit
Field
Type
Reset
Description
TX disable bit
7
TX_DIS
R/W
0
1 = TX disabled (power-down)
0 = TX enabled
TX Output Driver disable bit
1 = output disabled
0 = output enabled
6
5
4
TXOUT_DIS
TXOUTPOL
TXCDR_DIS
R/W
R/W
R/W
0
0
0
TX Output polarity switch bit
1 = inverted polarity
0 = normal polarity
TX CDR disable bit
1 = TX CDR is disabled and bypassed
0 = TX CDR is enabled
TX CDR bypass bit
1 = TX-CDR bypassed. RX_CDRBP must be set to 1 for this function to
operate.
3
TX_CDRBP
R/W
0
0 = TX-CDR not bypassed
TX OC disable bit
2
1
0
TXOC_DIS
TXEQ_DIS
TXAMPCTRL
R/W
R/W
R/W
0
0
0
1 = TX Offset Cancellation disabled
0 = TX Offset Cancellation enabled
TX Equalizer disable bit
1 = TX Equalizer is disabled and bypassed
0 = TX Equalizer is enabled
TX AMP Ctrl
1 = TX AMP Control is enabled (analog amplitude control)
0 = TX AMP Control is disabled (digital amplitude control)
26
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7.6.3.2 TX Register 11 (offset = 0000 0000) [reset = 0h]
Figure 32. TX Register 11
7
6
5
4
3
2
1
0
TXAMPRNG
R/W
TXPKSEL
R/W
TXTCSEL1
R/W
TXTCSEL0
R/W
TXCTLE3
R/W
TXCTLE2
R/W
TXCTLE1
R/W
TXCTLE0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. TX Register 11 Field Descriptions
Bit
Field
Type
Reset
Description
TX output AMP range
7
TXAMPRNG
R/W
0
1 = Half TX output amplitude range
0 = Full TX output amplitude range
TX output peaking width
1 = wide peaking width
0 = narrow peaking width
6
TXPKSEL
R/W
0
5
4
3
2
1
0
TXTCSEL1
TXTCSEL0
TXCTLE3
TXCTLE2
TXCTLE1
TXCTLE0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
TXOUT temperature compensation select bit 1
TXOUT temperature compensation select bit 0
TX input CTLE setting
0000 = minimum
1111 = maximum
7.6.3.3 TX Register 12 (offset = 0000 0000) [reset = 0h]
Figure 33. TX Register 12
7
6
5
4
3
2
1
0
TXMOD7
R/W
TXMOD76
R/W
TXMOD5
R/W
TXMOD4
R/W
TXMOD3
R/W
TXMOD2
R/W
TXMOD1
R/W
TXMOD0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. TX Register 12 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
TXMOD7
TXMOD6
TXMOD5
TXMOD4
TXMOD3
TXMOD2
TXMOD1
TXMOD0
0
0
0
0
0
0
0
0
6
5
4
TX Modulation current setting: sets the output voltage
Output Voltage: 2.4 Vpp / 9.5 mVpp steps
3
2
1
0
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7.6.3.4 TX Register 13 (offset = 0h) [reset = 0]
Figure 34. TX Register 13
7
6
5
4
3
2
1
0
TXOUTSEL
R/W
TXMODE
R/W
TXSTEP
R/W
TXSLOW
R/W
TXDEADJ3
R/W
TXDEADJ2
R/W
TXDEADJ1
R/W
TXDEADJ0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. TX Register 13 Field Descriptions
Bit
Field
Type
Reset
Description
TX output selection bit
7
TXOUTSEL
R/W
0
1 = The negative output TXOUT– is active
0 = The positive output TXOUT+ is active
TX output mode selection bit
1 = Single-ended mode
0 = Differential mode
6
5
4
TXMODE
TXSTEP
TXSLOW
R/W
R/W
R/W
0
0
0
TX output de-emphasis mode selection bit
1 = Delayed de-emphasis
0 = Normal de-emphasis
TX edge speed selection bit
1 = Slow edge speed
0 = Normal operation
3
2
1
0
TXDEADJ3
TXDEADJ2
TXDEADJ1
TXDEADJ0
R/W
R/W
R/W
R/W
0
0
0
0
TX de-emphasis setting
0000 = minimum
1111 = maximum
7.6.3.5 TX Register 14 (offset = 0000 0000) [reset = 0h]
Figure 35. TX Register 14
7
6
5
4
3
2
1
0
TXCPSGN
R/W
TXCPADJ6
R/W
TXCPADJ5
R/W
TXCPADJ4
R/W
TXCPADJ3
R/W
TXCPADJ2
R/W
TXCPADJ61
R/W
TXCPADJ60
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. TX Register 14 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
TXCPSGN
TXCPADJ6
TXCPADJ5
TXCPADJ4
TXCPADJ3
TXCPADJ2
TXCPADJ1
TXCPADJ0
0
0
0
0
0
0
0
0
TX Eye cross-point adjustment setting
TXCPSGN = 1 (positive shift)
6
Maximum shift for 1111111
5
Minimum shift for 0000000
TXCPSGN = 0 (negative shift)
4
3
Maximum shift for 1111111
Minimum shift for 0000000
2
1
0
28
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7.6.3.6 TX Register 15 (offset = 0000 0000) [reset = 0h]
Figure 36. TX Register 15
7
6
5
4
3
2
1
0
TXBIAS9
R/W
TXBIAS8
R/W
TXBIAS7
R/W
TXBIAS6
R/W
TXBIAS5
R/W
TXBIAS4
R/W
TXBIAS3
R/W
TXBIAS2
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. TX Register 15 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
TXBIAS9
TXBIAS8
TXBIAS7
TXBIAS6
TXBIAS5
TXBIAS4
TXBIAS3
TXBIAS2
0
0
0
0
0
0
0
0
Bias current settings (8MSB; 2LSBs are in register 16)
Closed loop (APC):
Coupling ratio CR = IBIAS / IPD, TXBIAS = 0..1023, IBIAS ≤ 150 mA:
TXPDRNG = 00; IBIAS = 0.75 μA x CR x TXBIAS
TXPDRNG = 01; IBIAS = 1.5 μA x CR x TXBIAS
TXPDRNG = 1X; IBIAS = 3 μA x CR x TXBIAS
6
5
4
3
Open Loop:
IBIAS ~ 147 μA x TXBIAS in source mode
IBIAS ~ 147 μA x TXBIAS in sink mode
2
1
0
7.6.3.7 TX Register 16 (offset = 0000 0000) [reset = 0h]
Figure 37. TX Register 16
7
6
5
4
3
2
1
0
Reserved
R/W
TXDMONP
R/W
TXDMONB
R/W
Reserved
R/W
TXBIAS1
R/W
TXBIAS1
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. TX Register 16 Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R/W
0
Reserved
Digital photodiode current monitor selection bit (MONP)
6
5
TXDMONP
TXDMONB
R/W
R/W
0
0
1 = Digital photodiode monitor is active (no external resistor is needed)
0 = Analog photodiode monitor is active (external resistor is required)
Digital bias current monitor selection bit (MONB)
1 = Digital bias current monitor is active (no external resistor is needed)
0 = Analog bias current monitor is active (external resistor is required)
4:2
1
Reserved
TXBIAS1
TXBIAS0
R/W
R/W
R/W
0
0
0
Reserved
Laser Bias current setting (2 LSBs)
0
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7.6.3.8 TX Register 17 (offset = 0000 0000) [reset = 0h]
Figure 38. TX Register 17
7
6
5
4
3
2
1
0
TXBMF7
R/W
TXBMF6
R/W
TXBMF5
R/W
TXBMF4
R/W
TXBMF3
R/W
TXBMF2
R/W
TXBMF1
R/W
TXBMF0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. TX Register 17 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
TXBMF7
TXBMF6
TXBMF5
TXBMF4
TXBMF3
TXBMF2
TXBMF1
TXBMF0
0
0
0
0
0
0
0
0
Bias current monitor fault threshold
With TXDMONB = 1
Register sets the value of the bias current that will trigger a fault.
The external resistor on the MONB pin must be removed to use this
feature.
6
5
4
3
2
1
0
7.6.3.9 TX Register 18 (offset = 0000 0000) [reset = 0h]
Figure 39. TX Register 18
7
6
5
4
3
2
1
0
TXPMF7
R/W
TXPMF6
R/W
TXPMF5
R/W
TXPMF4
R/W
TXPMF3
R/W
TXPMF2
R/W
TXPMF1
R/W
TXPMF0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. TX Register 18 Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
TXPMF7
TXPMF6
TXPMF5
TXPMF4
TXPMF3
TXPMF2
TXPMF1
TXPMF0
0
0
0
0
0
0
0
0
Power monitor fault threshold
With TXDMONP = 1
Register sets the value of the photodiode current that will trigger a fault.
The external resistor on the MONP pin must be removed to use this
feature.
6
5
4
3
2
1
0
30
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7.6.3.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
Figure 40. TX Register 19
7
6
5
4
3
2
1
0
TXFD_MOD1
R/W
TXFD_MOD0
R/W
TXFD_EN
R/W
TXFD_DIS
R/W
0TXFL_DIS
R/W
TXDIV2
R/W
TXDIV1
R/W
TXDIV0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. TX Register 19 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXFD_MOD1
R/W
0
TX frequency detection mode selection
00 = auto selection enabled
01 = Pre-selected to 10.3 Gbps
10 = Pre-select to 11.1 Gbps
11 = test mode (do not use)
6
TXFD_MOD0
R/W
0
TX frequency detector enable bit
5
4
3
TXFD_EN
TXFD_DIS
TXFL_DIS
R/W
R/W
R/W
0
0
0
1 =TX frequency detector is always enabled
0 = TX frequency detector in automatic mode
TX frequency detector disable bit
1 = TX frequency detector is always disabled
0 = TX frequency detector is in automatic mode
TX CDR fast lock disable bit
1 = TX CDR fast lock disabled
0 = TX CDR in fast lock mode
2
1
TXDIV2
TXDIV1
R/W
R/W
0
0
TX Divider Ratio
000: Full-Rate,
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
101: Divide by 32
0
TXDIV0
R/W
0
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7.6.4 Reserved Registers
7.6.4.1 Reserved Registers 20-39
Figure 41. Reserved Registers 20-39
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Reserved Registers 20-39 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
0
Reserved
32
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7.6.5 Read Only Registers
7.6.5.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
Figure 42. Core Level Register 40
7
ADC9
R
6
ADC8
R
5
ADC5
R
4
ADC4
R
3
ADC3
R
2
ADC2
R
1
ADC1
R
0
ADC0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. Core Level Register 40 Field Descriptions
Bit
7
Field
Type
R
Reset
Description
Digital representation of the ADC input source (read only)
ADC9 (MSB)
ADC8
0
0
0
0
0
0
0
0
6
R
5
ADC7
R
4
ADC6
R
3
ADC5
R
2
ADC4
R
1
ADC3
R
0
ADC2
R
7.6.5.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
Figure 43. Core Level Register 41
7
6
5
4
3
2
1
ADC1
R
0
ADC0
R
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Core Level Register 41 Field Descriptions
Bit
7:2
1
Field
Type
R
Reset
0h
Description
Resereved
ADC1
Reserved
R
0h
Digital representation of the ADC input source (read only)
0
ADC0 (LSB)
R
0h
7.6.5.3 RX Registers 42 (offset = 0000 0000) [reset = 0h]
Figure 44. RX Registers 42
7
6
5
4
3
2
1
0
Reserved
R
RCLR
R
RCLR
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear
Table 21. RX Registers 42 Field Descriptions
Bit
7
Field
Type
R
Reset
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
6
RCLR
R
5
4
RCLR
R
3:0
Copyright © 2016, Texas Instruments Incorporated
33
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
7.6.5.4 TX Register 43 (offset = 0000 0000) [reset = 0h]
Figure 45. Core Level Register 43
7
TXCDRLock
R
6
TXCDRLock
R
5
TX_FLT
R
4
TX_DRVDIS
R
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear
Table 22. TX Registers 43 Field Descriptions
Bit
Field
Type
Reset
Description
TX CDR lock status bit
1 = TX CDR is not locked
0 = TX CDR is locked
7
TXCDRLock
R
0
Latched low status of bit 7. Cleared when read.
6
5
TXCDRLock (latched Low)
TX_FLT
RCLR
R
0
0
Latched low bit set to 0 when raw status goes low and keep it low even if
raw status goes high.
TX fault status bit
1 = TX fault detected
0 = TX fault not detected
TX driver disable status bit
4
TX_DRVDIS
Reserved
R
R
0
0
1 = TX fault logic disables the driver
0 = TX fault logic does not disable the driver
3:0
Reserved
34
Copyright © 2016, Texas Instruments Incorporated
ONET1131EC
www.ti.com.cn
ZHCSFG0 –SEPTEMBER 2016
7.6.6 Adjustment Registers
7.6.6.1 Adjustment Registers 44-50
Figure 46. Adjustment Registers 44-50
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Adjustment Registers 44-50 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
0
Reserved
7.6.6.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
Figure 47. Adjustment Register 51
7
SEL_RES_2
R
6
SEL_RES_1
R
5
SEL_RES_0
R
4
3
2
Reserved
R
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Adjustment Register 51 Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
SEL_RES_2
SEL_RES_1
0
1
CDR Loop Filter Resistor
000: 75,
001: 150
6
010: 225
011: 300
100: 375
101: 450
5
SEL_RES_0
R/W
0
110: 525
111: 600
Default = 225
4:0
Reserved
R/W
0
Reserved
7.6.6.3 Adjustment Registers 52-55
Figure 48. Adjustment Registers 52-55
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. Adjustment Registers 52-55 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
0
Reserved
Copyright © 2016, Texas Instruments Incorporated
35
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
8 Application Information and Implementations
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ONET1131EC is designed to be used in conjunction with a Transmitter Optical Sub-Assembly (TOSA). The
ONET1131EC, TOSA, microcontroller and power management circuitry will typically be used in an XFP or SFP+
10 Gbps optical transceiver. Figure 49 shows the ONET1131EC in differential mode of operation modulating a
differentially driven Mach Zehnder (MZ) modulator TOSA and Figure 51 and Figure 52 show the device in single-
ended output mode with an Electroabsorptive Modulated Laser (EML) TOSA. Figure 51 has the photodiode
cathode available and Figure 52 has the photodiode anode available.
8.2 Typical Application, Transmitter Differential Mode
VCC_T
VCC
4.7kꢁ
4.7kꢁ
4.7kꢁ
to10kꢁ
to10kꢁ
to10kꢁ
TX_FLT
TX_DIS
VCC
0.1ꢀF
0.1ꢀF
[h[
b/
/hat
Db5
LOL
0.01ꢀF
ahb.
Db5
5Lb+
5Lb-
Db5
t5
0.1ꢀF
0.1ꢀF
b/
b/
DIN+
DIN-
ONET1131EC
Db5
{/Y
{5!
SCK
SDA
ahbt
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
VCC
2.2nF
VDD
0.1ꢀF
VCC
0.1ꢀF
0.1ꢀF
0.1ꢀF
MZ MOD+
MZ MOD-
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Typical Application Circuit in Differential Mode
36
Copyright © 2016, Texas Instruments Incorporated
ONET1131EC
www.ti.com.cn
ZHCSFG0 –SEPTEMBER 2016
Typical Application, Transmitter Differential Mode (continued)
8.2.1 Design Requirements
Table 26. Design Parameters
PARAMETER
VALUE
Supply voltage
2.5 V
Transmitter input voltage
Transmitter output voltage
100 mVpp to 1000 mVpp differential
1 Vpp to 3.6 Vpp differential
8.2.2 Detailed Design Procedure
In the transmitter differential mode of operation, the output driver is intended to be used with a differentially
driven Mach Zehnder (MZ) modulator TOSA. On the input side, the DIN+ and DIN- pins are required to be AC
coupled to the signal from the host system and the input voltage should be between 100 mVpp and 1000 mVpp
differential. On the output side, the OUT+ pin is AC coupled to the modulator positive input and the OUT– pin is
AC coupled to the modulator negative input. A bias-T from VCC to both the OUT+ and OUT– pins is required to
supply sufficient headroom voltage for the output driver transistors. It is recommended that the inductance in the
bias-T have low DC resistance to limit the DC voltage drop and maximize the voltage supplied to the OUT+ and
OUT– pins. If the voltage on these pins drops below approximately 2.1 V then the output rise and fall times can
be adversely affected.
8.2.3 Application Curve
Figure 50. Differential Mode Transmitter Output Eye Diagram
Copyright © 2016, Texas Instruments Incorporated
37
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
8.2.4 Typical Application, Transmitter Single-Ended Mode
VCC_T
VCC
4.7kꢁ to
10kꢁ
4.7kꢁ
to10kꢁ
4.7kꢁ to
10kꢁ
TX_FLT
TX_DIS
VCC
0.1ꢀF
0.1ꢀF
[h[
b/
/hat
Db5
LOL
0.01ꢀF
ahb.
Db5
5Lb+
5Lb-
Db5
t5
0.1ꢀF
0.1ꢀF
b/
b/
DIN+
DIN-
ONET1131EC
Db5
{/Y
{5!
PD
SCK
SDA
ahbt
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
VCC
VDD
VCC
0.1ꢀF
Modulator Anode
0.1ꢀF
PD
2.2nF
0.1ꢀF
0.1ꢀF
50ꢁ
Laser
PD
EA BIAS
EML TOSA
0.1ꢀF
-3V
Copyright © 2016, Texas Instruments Incorporated
Figure 51. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Cathode
Available
38
Copyright © 2016, Texas Instruments Incorporated
ONET1131EC
www.ti.com.cn
ZHCSFG0 –SEPTEMBER 2016
VCC_T
VCC
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
4.7kꢁ
to10kꢁ
TX_FLT
0.1ꢀF
0.1ꢀF
TX_DIS
VCC
[h[
b/
/hat
Db5
LOL
0.01ꢀF
ahb.
Db5
5Lb+
5Lb-
Db5
t5
0.1ꢀF
b/
b/
DIN+
DIN-
ONET1131EC
0.1ꢀF
Db5
{/Y
{5!
PD
SCK
ahbt
SDA
4.7kꢁ
4.7kꢁ
to10kꢁ
to10kꢁ
VCC
VDD
VCC
0.1ꢀF
Modulator Anode
0.1ꢀF
2.2nF
0.1ꢀF
0.1ꢀF
50ꢁ
Laser
PD
PD
EA BIAS
EML TOSA
0.1ꢀF
Copyright © 2016, Texas Instruments Incorporated
Figure 52. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Anode
Available
Copyright © 2016, Texas Instruments Incorporated
39
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
8.2.4.1 Design Requirements
Table 27. Design Parameters
PARAMETER
VALUE
Supply voltage
2.5 V
Transmitter input voltage
Transmitter output voltage
100 mVpp to 1000 mVpp differential
0.5 Vpp to 2 Vpp single-ended
8.2.4.2 Detailed Design Procedure
In the transmitter single-ended mode of operation, the output driver is intended to be used with a single-ended
driven Electroabsorptive Modulated Laser (EML) TOSA. On the input side, the DIN+ and DIN– pins are required
to be AC coupled to the signal from the host system and the input voltage should be between 100 mVpp and
1000 mVpp differential. On the output side, it is recommended that the OUT+ pin is AC coupled to the modulator
input and the OUT– pin can be left unterminated or terminated to VCC through a 50-Ω resistor. A bias-T from
VCC to the OUT+ pin is required to supply sufficient headroom voltage for the output driver transistors. It is
recommended that the inductance in the bias-T have low DC resistance to limit the DC voltage drop and
maximize the voltage supplied to the TXOUT+ pin. If the voltage on this pins drops below approximately 2.1V
then the output rise and fall times can be adversely affected.
8.2.4.3 Application Curves
Figure 53. Single-Ended Mode Transmitter Output Eye Diagram
9 Power Supply Recommendations
The ONET1131EC is designed to operate from an input supply voltage range between 2.37 V and 2.63 V. To
reduce digital coupling into the analog circuitry, there are separate supplies for the transmitter, and digital
circuitry. VCC is used to supply power to the transmitter, and VDD is used to supply power to the digital block.
Power supply decoupling capacitors should be placed as close as possible to the respective power supply pins.
40
Copyright © 2016, Texas Instruments Incorporated
ONET1131EC
www.ti.com.cn
ZHCSFG0 –SEPTEMBER 2016
10 Layout
10.1 Layout Guidelines
For optimum performance, use 50-Ω transmission lines (100-Ω differential) for connecting the high speed inputs
and outputs. The length of transmission lines should be kept as short as possible to reduce loss and pattern-
dependent jitter.
If the single-ended mode of operation is being used (TXMODE = 1) then it is recommended to terminate the
unused output with a 50-Ω resistor to VCC. Figure 54 shows a typical layout for the high speed inputs and
outputs.
10.2 Layout Example
!/-coupling
capacitors
ÇóLb+
Crom
Iost
ÇóLb-
ÇóhÜÇ-
.ias-Ç
Cerrites
50O to ë//
Çermination
Figure 54. Board Layout
版权 © 2016, Texas Instruments Incorporated
41
ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
42
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都遵循在订单确认时所提供的TI 销售条款与条件。
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邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ONET1131ECRSMR
ONET1131ECRSMT
ACTIVE
VQFN
VQFN
RSM
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 100
-40 to 100
ONET
1131EC
ACTIVE
RSM
NIPDAU
ONET
1131EC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
28X 0.4
9
16
SEE SIDE WALL
DETAIL
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.45
0.25
32X
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
(
0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
16
(1.15)
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
(R0.05) TYP
25
32
32X (0.55)
1
24
32X (0.2)
(0.715)
(3.85)
33
SYMM
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
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担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
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束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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