ONET2511PARGTTG4 [TI]
155-mbps to 2.5-gbps Limiting amplifier; 155 - Mbps至2.5 Gbps的限幅放大器
| 型号： | ONET2511PARGTTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 155-mbps to 2.5-gbps Limiting amplifier |
| 文件： | 总14页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢆ ꢅ ꢅ ꢉꢊꢋ ꢌ ꢍ ꢃ ꢀ ꢄ ꢎꢅ ꢉꢏ ꢋ ꢌꢍ ꢐ ꢑꢊ ꢑꢃ ꢑꢁ ꢏ ꢈ ꢊꢇ ꢐꢑ ꢒ ꢑꢂ ꢓ
SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
D
D
Single 3.3-V Supply
features
Surface Mount Small Footprint 3 mm ×
3 mm 16-Pin QFN Package
D
Multi-Rate Operation from 155 Mbps Up To
2.5 Gbps
D
D
D
D
D
D
Ultralow Power Consumption
Input Offset Cancellation
High Input Dynamic Range
Output Disable
applications
D
SONET/SDH Transmission Systems at OC3,
OC12, OC24, OC48
D
D
1.0625-Gbps and 2.125-Gbps Fibre Channel
Receivers
Output Polarity Select
CML Data Outputs
Gigabit Ethernet Receivers
description
The ONET2511PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates
up to 2.5 Gbps.
This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as
low as 3 mV
.
p−p
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 1800 mV
.
p−p
The ONET2511PA is available in a small footprint 3 mm × 3 mm 16-pin QFN package. The circuit requires a
single 3.3-V supply.
This power efficient limiting amplifier is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
block diagram
A simplified block diagram of the ONET2511PA is shown in Figure 1.
This compact, low power 2.5-Gbps limiting amplifier consists of a high-speed data path with offset cancellation
block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.
The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.
COC2 COC1
Bandgap Voltage
Reference and
Bias Current
Generation
Offset
Cancellation
VCC
GND
OUTPOL
VCCO
DIN+
DIN−
+
+
+
+
+
DOUT+
−
−
DOUT−
CML
Output
Buffer
Input Buffer
Gain Stage
Gain Stage
Gain Stage
DISABLE
Figure 1. Block Diagram
high-speed data path
The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages which provide
the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available
at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also
includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function,
controlled by the signal applied to the DISABLE input pin.
An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even
for small input data signals.
The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.
For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
bandgap voltage and bias generation
The ONET2511PA limiting amplifier is supplied by a single 3.3-V 10% supply voltage connected to the VCC
and VCCO pins. This voltage is referred to ground (GND).
An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other
internally required voltages and bias currents are derived.
2
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SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
package
For the ONET2511PA a small footprint 3 mm × 3 mm 16-pin QFN package is used, with a lead pitch of 0,5 mm.
The pinout is shown in Figure 2.
16 15 14 13
12
11
10
VCCO
1
2
VCC
DIN+
DIN−
DOUT+
DOUT−
3
4
9
OUTPOL
VCC
5
6
7
8
Figure 2. Pinout of ONET2511PA in a 3 mm y 3 mm 16-Pin QFN Package (Top View)
terminal functions
The following table shows a pin description for the ONET2511PA in a 3 mm x 3 mm 16-pin QFN package.
TERMINAL
TYPE
DESCRIPTION
NAME
VCC
NO.
1, 4
Supply
3.3-V 10% supply voltage
DIN+
2
Analog in Noninverted data input. On-chip 50-Ω terminated to VCC
Analog in Inverted data input. On-chip 50-Ω terminated to VCC
Not connected
DIN–
3
N.C.
5, 7, 13
DISABLE
GND
6
8, 16, EP
9
CMOS in Disables CML output stage when set to high level
Supply
Circuit ground. Exposed die pad (EP) must be grounded.
OUTPOL
CMOS in Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects
normal polarity. Low level selects inverted polarity.
DOUT–
DOUT+
VCCO
COC1
10
11
12
14
CML out
CML out
Supply
Inverted data output. On-chip 50-Ω back-terminated to VCCO
Noninverted data output. On-chip 50-Ω back-terminated to VCCO
3.3-V 10% supply voltage for output stage
Analog
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin
and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
COC2
15
Analog
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin
and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
3
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SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
absolute maximum ratings
over operating free-air temperature range unless otherwise noted
†
VALUE
–0.3 to 4
0.5 to 4
UNIT
V
, V
CC CCO
Supply voltage, See Note 1
V
V
V
V , V
DIN+ DIN−
Voltage at DIN+, DIN–, See Note 1
V
V
,V
,V
,V
,
Voltage at TH, DISABLE, OUTPOL, DOUT+, DOUT–, COC1, and
COC2, See Note 1
–0.3 to 4
DISABLE OUTPOL DOUT+ DOUT−
COC1 COC2
, V
V
V
Differential voltage between COC1 and COC2
Differential voltage between DIN+ and DIN–
Continuous current at inputs and outputs
ESD rating at all pins except VCCO
1
2.5
V
V
COC_DIFF
DIN_DIFF
I
, I
, I
, I
–25 to 25
3
mA
DIN+ DIN− DOUT+ DOUT–
ESD
kV (HBM)
ESD rating at VCCO
1.1
T
Maximum junction temperature
125
°C
°C
°C
°C
J(max)
T
stg
Storage temperature range
−65 to 85
−40 to 85
260
T
A
Characterized free-air operating temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
T
L
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
recommended operating conditions
MIN
3
TYP
MAX
3.6
UNIT
V
Supply voltage, V , V
CC CCO
3.3
Operating free-air temperature, T
−40
85
°C
A
dc electrical characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
TYP
3.3
22
MAX
3.6
UNIT
V
V
,V
3
CC CCO
I
Supply current
DISABLE = low (excludes CML output current)
DISABLE = high
28
mA
VCC
0.25
780
50
10 mV
p−p
V
OD
Differential data output voltage swing
DISABLE = low
600
1200 mV
p−p
R
, R
IN OUT
Data input/output resistance
Data input sensitivity
Single ended
Ω
–10
BER < 10
V
3
5
mV
mV
IN,MIN
p−p
V
Data input overload
1800
2.1
IN,MAX
p−p
CMOS input high voltage
CMOS input low voltage
V
0.6
V
4
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SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
ac electrical characteristics
over recommended operating conditions (unless otherwise noted), typical operating condition is at V
= 3.3 V and
CC
T = 25°C
A
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
C
C
= open
45
70
OC
OC
Low frequency −3-dB bandwidth
kHz
= 100 nF
0.8
Data rate
2.5
Gb/s
v
Input referred noise
300 µV
NI
RMS
K28.5 pattern at 2.5 Gbps
8.5
9.3
25
6.5
3
25
23
2
2
−1 PRBS equivalent pattern at 2.5 Gbps
−1 PRBS equivalent pattern at 155 Mbps
30
50
DJ
Deterministic jitter, See Note 2
Random jitter
ps
p−p
23
Input = 5 mVpp
Input = 10 mVpp
20% to 80%
20% to 80%
f < 2 MHz
RJ
ps
RMS
t
t
Output rise time
60
60
85
85
ps
ps
dB
ns
r
Output fall time
f
PSNR
Power supply noise rejection
Disable response time
26
t
20
DIS
NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage.
APPLICATION INFORMATION
Figure 3 shows the ONET2511PA connected with an ac-coupled interface to the data signal source as well as
to the output load.
The ac-coupling capacitors C through C in the input and output data signal lines are the only required external
1
4
components. In addition, an optional external filter capacitor (C ) may be used if a lower cutoff frequency is
OC
desired.
C
OC
Optional
VCC
VCCO
VCC
C
C
C
C
1
2
3
4
DIN+
DIN−
DIN+
DIN−
DOUT+
DOUT+
DOUT−
OUTPOL
ONET2511PA
16-Pin QFN
DOUT−
VCC
OUTPOL
DISABLE
Figure 3. Basic Application Circuit With AC-Coupled I/Os
5
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SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
Typical operating condition is at V
= V
= +3.3 V and T = 25°C (unless otherwise noted)
CC
CCO
A
DIFFERENTIAL OUTPUT VOLTAGE
vs
RANDOM JITTER
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
900
800
700
600
500
400
300
200
100
0
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
0
5
10
15
20
25
30
35
40
V
ID
− Differential Input Voltage − mV
V
ID
− Differential Input Voltage − mV
P-P
P-P
Figure 4
Figure 5
BIT ERROR RATIO
vs
DIFFERENTIAL INPUT VOLTAGE
0
10
-2
10
-4
10
-6
10
-8
10
-10
10
-12
10
-14
10
-16
10
-18
10
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
ID
− Differential Input Voltage − mV
P-P
Figure 6
6
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SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND
OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND
MINIMUM INPUT VOLTAGE (5 mV
)
MAXIMUM INPUT VOLTAGE (1800 mV
)
p−p
p−p
t − Time − 100 ps/Div
t − Time − 100 ps/Div
Figure 7
Figure 8
DIFFERENTIAL OUTPUT RETURN GAIN
DIFFERENTIAL INPUT RETURN GAIN
vs
vs
FREQUENCY
FREQUENCY
0
0
−5
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
−10
−15
−20
−25
−30
−35
−40
−45
−50
0.1
1
5
0.1
1
5
f − Frequency − GHz
f − Frequency − GHz
Figure 9
Figure 10
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
ONET2511PARGTR
ONET2511PARGTRG4
ONET2511PARGTT
ONET2511PARGTTG4
Status (1)
NRND
NRND
NRND
NRND
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGT
16
16
16
16
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
QFN
RGT
RGT
RGT
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ONET2511PARGTR
ONET2511PARGTT
QFN
QFN
RGT
RGT
16
16
3000
250
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ONET2511PARGTR
ONET2511PARGTT
QFN
QFN
RGT
RGT
16
16
3000
250
340.5
340.5
333.0
333.0
20.6
20.6
Pack Materials-Page 2
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provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
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