ONET3301PARGTR [TI]
155-MBPS TO 3.3-GBPS LIMITING AMPLIFIER; 155 - Mbps至3.3 Gbps的限幅放大器
| 型号： | ONET3301PARGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 155-MBPS TO 3.3-GBPS LIMITING AMPLIFIER |
| 文件： | 总12页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃꢄꢄ ꢅꢆ ꢇꢈ
ꢆ ꢉ ꢉ ꢊꢋꢌ ꢍ ꢎ ꢃ ꢀ ꢄ ꢏꢄ ꢊꢐ ꢌ ꢍꢎ ꢑ ꢒꢋ ꢒꢃ ꢒꢁ ꢐ ꢈꢋ ꢇ ꢑꢒ ꢓꢒ ꢂꢔ
SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
D
D
Single 3.3-V Supply
features
Surface Mount Small Footprint 3 mm ×
3 mm 16-Pin QFN Package
D
Multi-Rate Operation from 155 Mbps Up to
3.3 Gbps
D
D
D
D
D
D
D
D
106-mW Power Consumption
Input Offset Cancellation
High Input Dynamic Range
Output Disable
applications
D
SONET/SDH Transmission Systems at OC3,
OC12, OC24, OC48
D
D
1.0625-Gbps and 2.125-Gbps Fibre Channel
Receivers
Output Polarity Select
CML Data Outputs
Gigabit Ethernet Receivers
Receive Signals Strength Indicator (RSSI)
Loss of Signal Detection
description
The ONET3301PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates
up to 3.3 Gbps.
This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as
low as 3 mV
.
p−p
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 1200 mV
.
p−p
The ONET3301PA comprises a loss of signals detection, as well as a received signal strength indicator.
The ONET3301PA is available in a small footprint 3 mm × 3 mm 16-pin QFN package and requires a single 3.3-V
supply.
This power efficient limiting amplifier dissipates less than 106 mW typical. It is characterized for operation from
–40°C to 85°C.
available options
T
PACKAGED DEVICE
ONET3301PARGT
ONET3301PARGTR
FEATURES
A
−40°C to 85°C
−40°C to 85°C
16-pin 3 mm x 3 mm QFN, tube
16-pin 3 mm x 3 mm QFN, tape and reel
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
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ꢆꢉ ꢉꢊꢋ ꢌ ꢍ ꢎ ꢃꢀ ꢄ ꢏ ꢄ ꢊꢐꢌꢍ ꢎ ꢑꢒ ꢋ ꢒ ꢃꢒ ꢁꢐ ꢈꢋ ꢇꢑꢒ ꢓ ꢒꢂꢔ
SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
block diagram
A simplified block diagram of the ONET3301PA is shown in Figure 1.
This compact, low power 3.3-Gbps limiting amplifier consists of a high-speed data path with offset cancellation
block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.
The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.
COC2 COC1
VCC
Offset
Cancellation
GND
OUTPOL
VCCO
DIN+
DIN−
+
+
+
+
+
DOUT+
−
−
DOUT−
CML
Output
Buffer
Input Buffer
Gain Stage
Gain Stage
Gain Stage
DISABLE
Bandgap Voltage
Reference and
Bias Current
Generation
Loss of Signal
and
RSSI Detection
LOS
RSSI
TH
Figure 1. Block Diagram
high-speed data path
The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide
the required typical gain of about 50 dB and a CML output stage. The amplified data output signal is available
at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also
includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function,
controlled by the signal applied to the DISABLE input pin.
An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even
for small input data signals.
The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.
For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
loss of signal and RSSI detection
The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block
a signal is generated, which is linear proportional to the input amplitude over a wide input voltage range. This
signal is available at the RSSI output pin.
Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means
of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of
signal is indicated at the LOS pin.
2
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SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
bandgap voltage and bias generation
The ONET3301PA limiting amplifier is supplied by a single 3.3-V 10% supply voltage connected to the VCC
and VCCO pins. This voltage is referred to ground (GND).
An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other
internally required voltages and bias currents are derived.
package
For the ONET3301PA, a small footprint 3 mm × 3 mm 16-pin QFN package is used with a lead pitch of 0,5 mm.
The pin out is shown in Figure 2.
VCC
DIN+
VCCO
DOUT+
DOUT−
OUTPOL
DIN−
VCC
Figure 2. Pinout of ONET3301PA in a 3 mm y 3 mm 16-Pin QFN Package
terminal functions
The following table shows a pin description for the ONET3301PA in a 3 mm x 3 mm 16-pin QFN package.
TERMINAL
TYPE
DESCRIPTION
NAME
VCC
NO.
1, 4
Supply
3.3-V 10% supply voltage
DIN+
2
Analog in Noninverted data input. On-chip 50-Ω terminated to VCC
Analog in Inverted data input. On-chip 50-Ω terminated to VCC
DIN–
3
TH
5
Analog in LOS threshold adjustment with resistor to GND.
DISABLE
LOS
6
CMOS in Disables CML output stage when set to high level.
7
8, 16, EP
9
CMOS out High level indicates that the input signal amplitude is below the programmed threshold level.
GND
Supply
Circuit ground. Exposed die pad (EP) must be grounded.
OUTPOL
CMOS in Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects
normal polarity. Low level selects inverted polarity.
DOUT–
DOUT+
VCCO
RSSI
10
11
12
13
CML out
CML out
Supply
Inverted data output. On-chip 50-Ω back-terminated to VCCO
Noninverted data output. On-chip 50-Ω back-terminated to VCCO
3.3-V 10% supply voltage for output stage
Analog out Analog output voltage proportional to the input data amplitude. Indicates the strength of the received
signal (RSSI).
COC1
COC2
14
15
Analog
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin
and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
Analog
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin
and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
3
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SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
absolute maximum ratings
over operating free-air temperature range unless otherwise noted
†
VALUE
–0.3 to 4
0.5 to 4
UNIT
V
, V
CC CCO
Supply voltage, See Note 1
V
V
V
V , V
DIN+ DIN−
Voltage at DIN+, DIN–, See Note 1
V
,V
,V
, V
,V
,V
,
Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT–, RSSI,
COC1, and COC2, See Note 1
–0.3 to 4
TH DISABLE LOS OUTPOL DOUT+
V
, V
, V
DOUT− RSSI COC1 COC2
V
V
Differential voltage between COC1 and COC2
Differential voltage between DIN+ and DIN–
Current into LOS
1
2.5
V
COC_DIFF
DIN_DIFF
LOS
V
I
I
–1 to 9
–25 to 25
3
mA
mA
, I
, I
, I
Continuous current at inputs and outputs
ESD rating at all pins except VCCO
ESD rating at VCCO
DIN+ DIN− DOUT+ DOUT–
ESD
kV (HBM)
1.1
T
Maximum junction temperature
125
°C
°C
°C
°C
J(max)
T
stg
Storage temperature range
−65 to 85
−40 to 85
260
T
A
Characterized free-air operating temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
T
L
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
recommended operating conditions
MIN
3
TYP
MAX
3.6
UNIT
V
Supply voltage, V , V
CC CCO
3.3
Operating free-air temperature, T
−40
85
°C
A
4
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SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
dc electrical characteristics
over recommended operating conditions (unless otherwise noted), typical operating condition is at V
= 3.3 V and
CC
T = 25°C
A
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
TYP
3.3
MAX
UNIT
V
V
,V
3
3.6
40
CC CCO
I
Supply current
DISABLE = low (excludes CML output current)
DISABLE = high
32
0.25
780
50
mA
CC
10 mV
p−p
V
OD
Differential data output voltage swing
Data input/output resistance
DISABLE = low
600
1200 mV
p−p
r
, r
IN OUT
Single ended
Ω
Input = 2 mV
, R
≥ 10 kΩ
≥ 10 kΩ
100
2800
3%
p−p RSSI
RSSI output voltage
mV
Input = 80 mV , R
p−p RSSI
RSSI linearity
20−dB input signal, V ≤ 80 mVpp
–10
BER < 10
8%
5
IN
V
V
Data input sensitivity
Data input overload
CMOS input high voltage
CMOS input low voltage
LOS high voltage
3
mV
(IN_MIN)
p−p
1200
2.1
mV
(IN_MAX)
p−p
V
0.6
0.4
V
V
I
= –30 µA
2.4
2.5
SINK
LOS low voltage
I
= 1 mA
V
SOURCE
23
LOS hysteresis
2
2
−1 PRBS (at 2.5 Gbps and 155 Mbps)
−1 PRBS (at 2.5 Gbps and 155 Mbps)
4.5
dB
23
V
TH
LOS assert threshold range
5−40
mV
p−p
ac electrical characteristics
over recommended operating conditions (unless otherwise noted), typical operating condition is at V
= 3.3 V and
CC
T = 25°C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
45
MAX
UNIT
C
C
= open
70
OC
OC
Low frequency −3-dB bandwidth
kHz
= 2.2 nF
0.8
Data rate
3.3
Gb/s
v
Input referred noise
180
8.5
9.3
7.8
25
µV
RMS
NI
K28.5 pattern at 3.3 Gbps
23
25
30
25
50
2
−1 PRBS equivalent pattern at 2.7 Gbps
K28.5 pattern at 2.1 Gbps
23
DJ
Deterministic jitter, See Note 2
Random jitter
ps
p−p
2
−1 PRBS equivalent pattern at 155 Mbps
Input = 5 mVpp
Input = 10 mVpp
20% to 80%
20% to 80%
f < 2 MHz
6.5
3
RJ
ps
RMS
t
t
Output rise time
60
85
85
ps
ps
dB
ns
µs
r
Output fall time
60
f
PSNR
Power supply noise rejection
Disable response time
LOS assert/deassert time
26
2
t
t
20
DIS
100
LOS
NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage.
5
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SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
APPLICATION INFORMATION
Figure 3 shows the ONET3301PA connected with an ac-coupled interface to the data signal source as well as
to the output load.
Besides the ac-coupling capacitors, C through C in the input and output data signal lines, the only required
1
4
external component is the LOS threshold setting resistor R . In addition, an optional external filter capacitor
TH
(C ) may be used if a low cutoff frequency is desired.
OC
C
OC
Optional
RSSI
VCC
VCCO
VCC
C
C
C
C
1
2
3
4
DIN+
DIN−
DIN+
DIN−
VCC
DOUT+
DOUT+
DOUT−
OUTPOL
ONET3301PA
16-Pin QFN
DOUT−
OUTPOL
DISABLE
LOS
R
TH
Figure 3. Basic Application Circuit With AC-Coupled I/Os
6
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SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
DIFFERENTIAL OUTPUT VOLTAGE
vs
RANDOM JITTER
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
900
800
700
600
500
400
300
200
100
0
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
0
5
10
15
20
25
30
35
40
V
ID
− Differential Input Voltage − mV
V
ID
− Differential Input Voltage − mV
P-P
P-P
Figure 4
Figure 5
BIT ERROR RATIO
vs
SMALL SIGNAL GAIN
vs
DIFFERENTIAL INPUT VOLTAGE
FREQUENCY
0
10
60
55
50
45
40
35
30
25
20
15
10
5
-2
-4
-6
-8
10
10
10
10
-10
10
-12
10
-14
10
-16
10
-18
10
0
0.01
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.1
1
10
100
1k
10k
V
ID
− Differential Input Voltage − mV
f − Frequency − MHz
Figure 7
P-P
Figure 6
7
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SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
OUTPUT EYE-DIAGRAM AT 3.3 GBPS AND
OUTPUT EYE-DIAGRAM AT 3.3 GBPS AND
MAXIMUM INPUT VOLTAGE (1200 mV
)
MINIMUM INPUT VOLTAGE (1200 mV
)
p−p
p−p
t − Time − 100 ps/Div
t − Time − 100 ps/Div
Figure 8
Figure 9
OUTPUT EYE-DIAGRAM AT
3.3 GBPS AND 855 C MINIMUM
INPUT VOLTAGE (5 mV
)
p−p
t − Time − 100 ps/Div
Figure 10
8
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SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND
OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND
MAXIMUM INPUT VOLTAGE (1200 mV
)
MINIMUM INPUT VOLTAGE (5 mV
)
p−p
p−p
t − Time − 100 ps/Div
t − Time − 100 ps/Div
Figure 11
Figure 12
LOS ASSERT/DEASSERT VOLTAGE
vs
DIFFERENTIAL INPUT RETURN GAIN
vs
EXTERNAL RESISTANCE R
FREQUENCY
TH
70
60
50
40
30
20
10
0
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
LOS Deassert Voltage
LOS Assert Voltage
0
2
4
6
8
10
12
14
0.1
1
5
R
− Thermal Resistance − kΩ
f − Frequency − GHz
TH
Figure 13
Figure 14
9
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ꢊ
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ꢍ
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ꢑ
ꢒ
ꢋ
ꢒ
ꢃꢒ
ꢁ
ꢐ
ꢈ
ꢋ
ꢇꢑ
ꢒ
ꢓ
ꢒ
ꢂ
ꢔ
SLLS603B − MARCH 2004 − REVISED DECEMBER 2004
DIFFERENTIAL OUTPUT RETURN GAIN
RECEIVE SIGNALS STRENGTH INDICATOR
vs
vs
FREQUENCY
DIFFERENTIAL INPUT VOLTAGE
0
−5
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
−10
−15
−20
−25
−30
−35
−40
−45
−50
600
400
200
0
0
10
20
30
40
50
60
70
80
90
0.1
1
5
f − Frequency − GHz
V
ID
− Differential Input Voltage − mV
P-P
Figure 15
Figure 16
10
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ONET3301PARGT
ACTIVE
QFN
RGT
16
121
None
CU NIPDAU Level-2-220C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
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Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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