ONET3301PARGTTG4 [TI]

ATM/SONET/SDH SUPPORT CIRCUIT, PQCC16, 3 X 3 MM, 0.50 MM PITCH, PLASTIC, QFN-16;


型号：	ONET3301PARGTTG4
厂家：	TEXAS INSTRUMENTS
描述：	ATM/SONET/SDH SUPPORT CIRCUIT, PQCC16, 3 X 3 MM, 0.50 MM PITCH, PLASTIC, QFN-16 ATM 异步传输模式电信电信集成电路
文件：	总18页 (文件大小：934K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ꢆ ꢉ ꢉ ꢊꢋꢌ ꢍ ꢎ ꢃ ꢀ ꢄ ꢏꢄ ꢊꢐ ꢌ ꢍꢎ ꢑ ꢒꢋ ꢒꢃ ꢒꢁ ꢐ ꢈꢋ ꢇ ꢑꢒ ꢓꢒ ꢂꢔ

SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

Single 3.3-V Supply

features

Surface Mount Small Footprint 3 mm ×

3 mm 16-Pin QFN Package

Multi-Rate Operation from 155 Mbps Up To

3.3 Gbps

106-mW Power Consumption

Input Offset Cancellation

High Input Dynamic Range

Output Disable

applications

SONET/SDH Transmission Systems at OC3,

OC12, OC24, OC48

1.0625-Gbps and 2.125-Gbps Fibre Channel

Receivers

Output Polarity Select

CML Data Outputs

Gigabit Ethernet Receivers

Receive Signal Strength Indicator (RSSI)

Loss of Signal Detection

description

The ONET3301PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates

up to 3.3 Gbps.

This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as

low as 3 mV

p−p

The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal

swings as high as 1200 mV

p−p

The ONET3301PA includes loss of signal detection, as well as a received signal strength indicator.

The ONET3301PA is available in a small footprint 3 mm × 3 mm 16-pin QFN package and requires a single 3.3-V

supply.

This power efficient limiting amplifier typically dissipates less than 106 mW. It is characterized for operation from

–40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢟ ꢢ ꢎ ꢟꢘ ꢙꢩ ꢛꢚ ꢞ ꢣꢣ ꢍꢞ ꢜ ꢞ ꢝ ꢢ ꢟ ꢢ ꢜ ꢎ ꢏ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄ ꢄ ꢅꢆ ꢇꢈ

ꢆꢉ ꢉꢊꢋ ꢌ ꢍ ꢎ ꢃꢀ ꢄ ꢏ ꢄ ꢊꢐꢌꢍ ꢎ ꢑꢒ ꢋ ꢒ ꢃꢒ ꢁꢐ ꢈꢋ ꢇꢑꢒ ꢓ ꢒꢂꢔ

SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

block diagram

A simplified block diagram of the ONET3301PA is shown in Figure 1.

This compact, low power 3.3-Gbps limiting amplifier consists of a high-speed data path with offset cancellation

block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation

block.

The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.

COC2 COC1

VCC

Offset

Cancellation

GND

OUTPOL

VCCO

DIN+

DIN−

DOUT+

−

DOUT−

CML

Output

Buffer

Input Buffer

Gain Stage

DISABLE

Bandgap Voltage

Reference and

Bias Current

Generation

Loss of Signal

and

RSSI Detection

LOS

RSSI

Figure 1. Block Diagram

high-speed data path

The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data

path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide

the required typical gain of about 50 dB and a CML output stage. The amplified data output signal is available

at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also

includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function,

controlled by the signal applied to the DISABLE input pin.

An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even

for small input data signals.

The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.

For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be

connected to the COC1/COC2 pins.

loss of signal and RSSI detection

The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block

a signal is generated, which is linearly proportional to the input amplitude over a wide input voltage range. This

signal is available at the RSSI output pin.

Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means

of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of

signal is indicated at the LOS pin.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

The relation between the LOS assert voltage V

to the TH pin can be approximated as given below:

(in mV ) and the external resistor R (in kΩ) connected

p−p TH

AST

43 kW

[

* 600 W

ń mV

p*p

AST

43 mV

(1)

(2)

p*p

ń kW ) 0.6

[

AST

bandgap voltage and bias generation

The ONET3301PA limiting amplifier is supplied by a single 3.3-V 10% supply voltage connected to the VCC

and VCCO pins. This voltage is referred to ground (GND).

An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other

internally required voltages and bias currents are derived.

package

For the ONET3301PA, a small footprint 3 mm × 3 mm 16-pin QFN package is used with a lead pitch of 0,5 mm.

The pin out is shown in Figure 2.

16 15 14 13

VCC

DIN+

VCCO

DOUT+

DOUT−

OUTPOL

DIN−

VCC

Figure 2. Pinout of ONET3301PA in a 3 mm y 3 mm 16-Pin QFN Package (Top View)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

terminal functions

The following table shows a pin description for the ONET3301PA in a 3 mm x 3 mm 16-pin QFN package.

TERMINAL

TYPE

DESCRIPTION

NAME

VCC

NO.

1, 4

Supply

3.3-V 10% supply voltage

DIN+

Analog in Noninverted data input. On-chip 50-Ω terminated to VCC

Analog in Inverted data input. On-chip 50-Ω terminated to VCC

DIN–

Analog in LOS threshold adjustment with resistor to GND.

DISABLE

LOS

CMOS in Disables CML output stage when set to high level.

8, 16, EP

CMOS out High level indicates that the input signal amplitude is below the programmed threshold level.

GND

Supply

Circuit ground. Exposed die pad (EP) must be grounded.

OUTPOL

CMOS in Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects

normal polarity. Low level selects inverted polarity.

DOUT–

DOUT+

VCCO

RSSI

CML out

Supply

Inverted data output. On-chip 50-Ω back-terminated to VCCO

Noninverted data output. On-chip 50-Ω back-terminated to VCCO

3.3-V 10% supply voltage for output stage

Analog out Analog output voltage proportional to the input data amplitude. Indicates the strength of the received

signal (RSSI).

COC1

COC2

Analog

Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin

and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).

Analog

Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin

and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).

absolute maximum ratings

over operating free-air temperature range unless otherwise noted

†

VALUE

–0.3 to 4

0.5 to 4

UNIT

, V

CC CCO

Supply voltage, See Note 1

V , V

DIN+ DIN−

Voltage at DIN+, DIN–, See Note 1

, V

Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT–, RSSI,

COC1, and COC2, See Note 1

–0.3 to 4

TH DISABLE LOS OUTPOL DOUT+

, V

DOUT− RSSI COC1 COC2

Differential voltage between COC1 and COC2

Differential voltage between DIN+ and DIN–

Current into LOS

2.5

COC_DIFF

DIN_DIFF

LOS

–1 to 9

–25 to 25

, I

Continuous current at inputs and outputs

ESD rating at all pins

DIN+ DIN− DOUT+ DOUT–

ESD

kV (HBM)

°C

Maximum junction temperature

125

J(max)

Storage temperature range

−65 to 85

−40 to 85

260

°C

stg

Characterized free-air operating temperature range

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to network ground terminal.

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SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

recommended operating conditions

MIN

TYP

MAX

3.6

UNIT

Supply voltage, V , V

CC CCO

3.3

Operating free-air temperature, T

−40

°C

dc electrical characteristics

over recommended operating conditions (unless otherwise noted), typical operating condition is at V

= 3.3 V and

T = 25°C

PARAMETER

Supply voltage

TEST CONDITIONS

MIN

TYP

3.3

MAX

UNIT

3.6

CC CCO

Supply current

DISABLE = low (excludes CML output current)

DISABLE = high

0.25

780

10 mV

p−p

Differential data output voltage swing

Data input/output resistance

DISABLE = low

600

1200 mV

p−p

, r

IN OUT

Single ended

Ω

Input = 2 mV

, R

≥ 10 kΩ

100

2800

p−p RSSI

RSSI output voltage

Input = 80 mV , R

p−p RSSI

RSSI linearity

20−dB input signal, V ≤ 80 mVpp

–10

BER < 10

Data input sensitivity

Data input overload

CMOS input high voltage

CMOS input low voltage

LOS high voltage

(IN_MIN)

p−p

1200

2.1

(IN_MAX)

p−p

0.6

0.4

= –30 µA

2.4

2.5

SINK

LOS low voltage

= 1 mA

SOURCE

LOS hysteresis

−1 PRBS (at 2.5 Gbps and 155 Mbps)

4.5

LOS assert threshold range

5−40

p−p

ac electrical characteristics

over recommended operating conditions (unless otherwise noted), typical operating condition is at V

= 3.3 V and

T = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

= open

Low frequency −3-dB bandwidth

kHz

= 100 nF

0.8

Data rate

3.3

Gb/s

Input referred noise

180

8.5

9.3

7.8

µV

RMS

K28.5 pattern at 3.3 Gbps

−1 PRBS equivalent pattern at 2.7 Gbps

K28.5 pattern at 2.1 Gbps

Deterministic jitter, See Note 2

Random jitter

p−p

−1 PRBS equivalent pattern at 155 Mbps

Input = 5 mVpp

Input = 10 mVpp

20% to 80%

f < 2 MHz

6.5

RMS

Output rise time

µs

Output fall time

PSNR

Power supply noise rejection

Disable response time

LOS assert/deassert time

DIS

100

LOS

NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

APPLICATION INFORMATION

Figure 3 shows the ONET3301PA connected with an ac-coupled interface to the data signal source as well as

to the output load.

Besides the ac-coupling capacitors, C through C in the input and output data signal lines, the only required

external component is the LOS threshold setting resistor R . In addition, an optional external filter capacitor

(C ) may be used if a lower cutoff frequency is desired.

Optional

RSSI

VCC

VCCO

VCC

DIN+

DIN−

DIN+

DIN−

VCC

DOUT+

DOUT−

OUTPOL

ONET3301PA

16-Pin QFN

DOUT−

OUTPOL

DISABLE

LOS

Figure 3. Basic Application Circuit With AC-Coupled I/Os

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SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

DIFFERENTIAL OUTPUT VOLTAGE

RANDOM JITTER

DIFFERENTIAL INPUT VOLTAGE

900

800

700

600

500

400

300

200

100

− Differential Input Voltage − mV

P-P

Figure 4

Figure 5

BIT ERROR RATIO

SMALL SIGNAL GAIN

DIFFERENTIAL INPUT VOLTAGE

FREQUENCY

-2

-4

-6

-8

-10

-12

-14

-16

-18

0.01

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.1

100

10k

− Differential Input Voltage − mV

f − Frequency − MHz

Figure 7

P-P

Figure 6

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SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

OUTPUT EYE-DIAGRAM AT 3.3 GBPS AND

MAXIMUM INPUT VOLTAGE (1200 mV

)

MINIMUM INPUT VOLTAGE (5 mV

)

p−p

t − Time − 100 ps/Div

Figure 8

Figure 9

OUTPUT EYE-DIAGRAM AT

3.3 GBPS, 855 C, AND MINIMUM

INPUT VOLTAGE (5 mV

)

p−p

t − Time − 100 ps/Div

Figure 10

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SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND

MAXIMUM INPUT VOLTAGE (1200 mV

)

MINIMUM INPUT VOLTAGE (5 mV

)

p−p

t − Time − 100 ps/Div

Figure 11

Figure 12

LOS ASSERT/DEASSERT VOLTAGE

DIFFERENTIAL INPUT RETURN GAIN

EXTERNAL RESISTANCE R

FREQUENCY

−5

−10

−15

−20

−25

−30

−35

−40

−45

−50

LOS Deassert Voltage

LOS Assert Voltage

0.1

− Threshold Voltage Setting Resistance − kΩ

f − Frequency − GHz

Figure 13

Figure 14

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ꢑꢒ

ꢋ

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ꢈꢋ

ꢇꢑ

ꢒ

ꢓ

ꢒꢂ

ꢔ

SLLS603C − MARCH 2004 − REVISED OCTOBER 2005

DIFFERENTIAL OUTPUT RETURN GAIN

RECEIVE SIGNAL STRENGTH INDICATOR

FREQUENCY

DIFFERENTIAL INPUT VOLTAGE

−5

2800

2600

2400

2200

2000

1800

1600

1400

1200

1000

800

−10

−15

−20

−25

−30

−35

−40

−45

−50

600

400

200

0.1

f − Frequency − GHz

− Differential Input Voltage − mV

P-P

Figure 15

Figure 16

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ONET3301PARGTR

NRND

QFN

RGT

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 85

301P

PYML

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Aug-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ONET3301PARGTR

QFN

RGT

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Aug-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

QFN RGT 16

SPQ

Length (mm) Width (mm) Height (mm)

338.1 338.1 20.6

ONET3301PARGTR

3000

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

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www.dlp.com

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DLP® Products

DSP

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dsp.ti.com

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Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

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www.ti.com/medical

Medical

Logic

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Power Mgmt

Microcontrollers

RFID

power.ti.com

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www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

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www.ti.com/omap

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e2e.ti.com

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