OPA124UA/2K5E4 [TI]
OPERATIONAL AMPLIFIER;
| 型号： | OPA124UA/2K5E4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPERATIONAL AMPLIFIER 放大器 光电二极管 |
| 文件： | 总9页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
OPA124
OPA124
Low Noise Precision Difet ®
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
● LOW NOISE: 6nV/√Hz (10kHz)
● LOW BIAS CURRENT: 1pA max
● LOW OFFSET: 250µV max
● PRECISION PHOTODIODE PREAMP
● MEDICAL EQUIPMENT
● OPTOELECTRONICS
● DATA ACQUISITION
● TEST EQUIPMENT
● LOW DRIFT: 2µV/°C max
● HIGH OPEN-LOOP GAIN: 120dB min
● HIGH COMMON-MODE REJECTION:
100dB min
● AVAILABLE IN 8-PIN PLASTIC DIP
AND 8-PIN SOIC PACKAGES
Substrate
+VCC
DESCRIPTION
8
7
The OPA124 is a precision monolithic FET opera-
tional amplifier using a Difet (dielectrical isolation)
manufacturing process. Outstanding DC and AC per-
formance characteristics allow its use in the most
critical instrumentation applications.
–In
2
+In
3
Noise-Free Cascode(2)
Bias current, noise, voltage offset, drift, open-loop
gain, common-mode rejection and power supply re-
jection are superior to BIFET and CMOS amplifiers.
Difet fabrication achieves extremely low input bias
currents without compromising input voltage noise
performance. Low input bias current is maintained
over a wide input common-mode voltage range with
unique cascode circuitry. This cascode design also
allows high precision input specifications and reduced
susceptibility to flicker noise. Laser trimming of thin-
film resistors gives very low offset and drift.
Output
6
2kΩ
2kΩ
2kΩ
Trim(1)
10kΩ
10kΩ
1
Trim(1)
5
2kΩ
–VCC
4
OPA124 Simplified Circuit
Compared to the popular OPA111, the OPA124 gives
comparable performance and is available in an 8-pin
PDIP and 8-pin SOIC package.
NOTES: (1) Omitted on SOIC. (2) Patented.
BIFET® National Semiconductor Corp.,
Difet® Burr-Brown Corp.
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
•
Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1993 Burr-Brown Corporation
PDS-1203C
Printed in U.S.A. March, 1998
SBOS028
SPECIFICATIONS
ELECTRICAL
At VCC = ±15VDC and TA = +25°C, unless otherwise noted.
OPA124U, P
TYP
OPA124UA, PA
OPA124PB
TYP
PARAMETER
CONDITION
MIN
MAX
MIN
TYP
MAX
MIN
MAX
UNITS
INPUT NOISE
Voltage, fO = 10Hz(4)
40
15
8
80
40
15
8
1.2
3.3
15
0.8
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
µVp-p
f
f
f
f
O = 100Hz(4)
O = 1kHz(4)
O = 10kHz(5)
B = 10Hz to 10kHz(5)
B = 0.1Hz to 10Hz
Current, fB = 0.1Hz to 10Hz
O = 0.1Hz thru 20kHz
6
0.7
1.6
9.5
0.5
f
fAp-p
fA/√Hz
f
OFFSET VOLTAGE(1)
Input Offset Voltage
vs Temperature
Supply Rejection
vs Temperature
VCM = 0VDC
A = TMIN to TMAX
CC = ±10V to ±18V
A = TMIN to TMAX
VCM = 0VDC
VCM = 0VDC
±200
±4
110
100
±800
±7.5
±150
±2
✻
±500
±4
±100
±1
✻
±250
±2
µV
µV/°C
dB
T
V
T
88
84
90
86
100
90
✻
✻
dB
BIAS CURRENT(1)
Input Bias Current
±1
±1
±5
±5
±0.5
±0.5
±2
±1
±0.35
±0.25
±1
pA
pA
OFFSET CURRENT(1)
Input Offset Current
±0.5
IMPEDANCE
Differential
Common-Mode
1013 || 1
1014 || 3
✻
✻
✻
✻
Ω || pF
Ω || pF
VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
vs Temperature
±10
92
86
±11
110
100
✻
94
✻
✻
✻
✻
✻
100
90
✻
✻
✻
V
dB
dB
V
IN = ±10VDC
T
A = TMIN to TMAX
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain
RL ≥ 2kΩ
106
125
✻
✻
120
✻
dB
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate
1.5
32
1.6
0.0003
6
10
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
MHz
kHz
V/µs
%
µs
µs
20Vp-p, RL = 2kΩ
16
1
✻
✻
✻
✻
VO = ±10V, RL = 2kΩ
THD
Settling Time, 0.1%
0.01%
Gain = –1, RL = 2kΩ
10V Step
Overload Recovery,
50% Overdrive(2)
Gain = –1
5
✻
✻
µs
RATED OUTPUT
Voltage Output
Current Output
Output Resistance
Load Capacitance Stability
Short Circuit Current
R
L = 2kΩ
±11
±5.5
±12
±10
100
1000
40
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
mA
Ω
pF
mA
V
O = ±10VDC
DC, Open Loop
Gain = +1
10
✻
✻
✻
✻
POWER SUPPLY
Rated Voltage
Voltage Range, Derated
Current, Quiescent
±15
✻
✻
✻
✻
VDC
VDC
mA
±5
±18
3.5
✻
✻
✻
✻
I
O = 0mADC
2.5
TEMPERATURE RANGE
Specification
Storage
TMIN and TMAX
–25
–65
+85
+125
✻
✻
✻
✻
✻
✻
✻
✻
°C
°C
θ Junction-Ambient: PDIP
SOIC
90
100
✻
✻
✻
✻
°C/W
°C/W
✻ Specification same as OPA124U, P
NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up. For performance at other temperatures see Typical Performance
Curves. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive.
(3) For performance at other temperatures see Typical Performance Curves. (4) Sample tested, 98% confidence. (5) Guaranteed by design.
®
2
OPA124
CONNECTION DIAGRAMS
Top View
DIP
Top View
SOIC
NC
–In
1
2
3
4
8
7
6
5
Substrate
+VS
Offset Trim
–In
1
2
3
4
8
7
6
5
Substrate
+VS
+In
–VS
Output
NC
+In
Output
–VS
Offset Trim
NC = No Connect
PACKAGE/ORDERING INFORMATION
BIAS
OFFSET
PACKAGE
DRAWING NUMBER(1)
TEMPERATURE
RANGE
CURRENT
pA, max
DRIFT
µV/°C, max
PRODUCT
PACKAGE
OPA124U
OPA124P
OPA124UA
OPA124PA
OPA124PB
8-Lead SOIC
8-Pin Plastic DIP
8-Lead SOIC
182
006
182
006
006
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
5
5
2
2
1
7.5
7.5
4
8-Pin Plastic DIP
8-Pin Plastic DIP
4
2
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Supply ........................................................................................... ±18VDC
Internal Power Dissipation(2) ......................................................... 750mW
Differential Input Voltage(3) .......................................................... ±36VDC
Input Voltage Range(3) ................................................................. ±18VDC
Storage Temperature Range .......................................... –65°C to +150°C
Operating Temperature Range ....................................... –40°C to +125°C
Lead Temperature (soldering, 10s)................................................ +300°C
Output Short Circuit Duration(4) ............................................... Continuous
Junction Temperature .................................................................... +175°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTES: (1) Stresses above these ratings may cause permanent damage.
(2) Packages must be derated based on θJA = 90°C/W for PDIP and 100°C/W
for SOIC. (3) For supply voltages less than ±18VDC, the absolute maximum
input voltage is equal to +18V > VIN > –VCC – 6V. See Figure 2. (4) Short circuit
may be to power supply common only. Rating applies to +25°C ambient.
Observe dissipation limit and TJ.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
OPA124
TYPICAL PERFORMANCE CURVES
At TA = +25°C, and VCC = ±15VDC, unless otherwise noted.
INPUT CURRENT NOISE SPECTRAL DENSITY
100
INPUT VOLTAGE NOISE SPECTRAL DENSITY
1k
100
10
10
U, P
PB
1
PB
0.1
1
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
TOTAL(1) INPUT VOLTAGE NOISE SPECTRAL
DENSITY vs SOURCE RESISTANCE
TOTAL(1) INPUT VOLTAGE NOISE (PEAK-TO-PEAK)
vs SOURCE RESISTANCE
1k
100
10
1k
100
10
RS = 10MΩ
NOTE: (1) Includes contribution
from source resistance.
RS = 1MΩ
RS = 100kΩ
PB
PB
RS = 100Ω
fB = 0.1Hz to 10Hz
NOTE: (1) Includes contribution
from source resistance.
1
1
104
105
106
Source Resistance (Ω)
107
108
109
1010
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
VOLTAGE AND CURRENT NOISE SPECTRAL
DENSITY vs TEMPERATURE
TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY
AT 1kHz vs SOURCE RESISTANCE
1k
100
10
12
10
8
100
EO
fO = 1kHz
10
RS
1
OPA124PB +
Resistor
6
0.1
Resistor Noise Only
1
4
0.01
–50
–25
0
25
50
75
100
125
100
1k
10k
100k
1M
10M
100M
Source Resistance (Ω)
Temperature (°C)
®
4
OPA124
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VCC = ±15VDC, unless otherwise noted.
BIAS AND OFFSET CURRENT
vs TEMPERATURE
BIAS AND OFFSET CURRENT
vs INPUT COMMON-MODE VOLTAGE
1k
100
10
1k
10
1
10
100
10
1
PB
Bias Current
1
1
Offset Current
0.1
0.01
0.1
0.01
0.1
0.01
0.1
0.01
–50
–25
0
25
50
75
100
125
–15
–10
–5
0
5
10
15
Ambient Temperature (°C)
Common-Mode Voltage (V)
POWER SUPPLY REJECTION
vs FREQUENCY
COMMON-MODE REJECTION
vs FREQUENCY
140
120
100
80
140
120
100
80
60
60
40
40
20
20
0
0
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
OPEN-LOOP FREQUENCY RESPONSE
140
120
100
80
120
110
100
90
–45
–90
Phase
Margin
60
Gain
≈ 65°
40
–135
–180
80
20
70
0
–15
–10
–5
0
5
10
15
1
10
100
1k
10k
100k
1M
10M
Common-Mode Voltage (V)
Frequency (Hz)
®
5
OPA124
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VCC = ±15VDC, unless otherwise noted.
GAIN-BANDWIDTH AND SLEW RATE
vs SUPPLY VOLTAGE
GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE
3
2
1
0
3
2
1
0
4
4
3
2
1
0
0
5
10
15
20
–50
–25
0
25
50
75
100
125
Supply Voltage (±VCC
)
Ambient Temperature (°C)
MAXIMUM UNDISTORTED OUTPUT
VOLTAGE vs FREQUENCY
OPEN-LOOP GAIN vs TEMPERATURE
30
140
130
120
110
100
20
10
0
1k
10k
Frequency (Hz)
100k
1M
–50
–25
0
25
50
75
100
125
Ambient Temperature (°C)
SMALL SIGNAL TRANSIENT RESPONSE
LARGE SIGNAL TRANSIENT RESPONSE
60
15
10
5
40
20
0
0
–20
–40
–60
–5
–10
–15
0
1
2
3
4
5
0
10
20
Time (µs)
30
40
50
Time (µs)
®
6
OPA124
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VCC = ±15VDC, unless otherwise noted.
SUPPLY CURRENT vs TEMPERATURE
SETTLING TIME vs CLOSED-LOOP GAIN
4
3
2
1
0
100
80
60
40
20
0
0.01%
0.1%
–50
–25
0
25
50
75
100
125
1
10
100
1k
Closed-Loop Gain (V/V)
Ambient Temperature (°C)
INPUT OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
INPUT OFFSET VOLTAGE WARM-UP DRIFT
150
20
10
U, P
75
0
PB
+25°C
+85°C
0
TA = +25°C to TA = +85°C
Air Environment
–75
–150
–10
–20
–1
0
1
2
3
4
5
0
1
2
3
4
5
6
Time From Thermal Shock (Minutes)
Time From Power Turn-On (Minutes)
®
7
OPA124
+VCC
APPLICATIONS INFORMATION
NOTE: No trim on SOIC.
7
OFFSET VOLTAGE ADJUSTMENT
2
3
6
1
The OPA124 offset voltage is laser-trimmed and will require
no further trim for most applications. In order to reduce
layout leakage errors, the offset adjust capability has been
removed from the SOIC versions (OPA124UA and
OPA124U). The PDIP versions (OPA124PB, OPA124PA,
and OPA124P) do have pins available for offset adjustment.
As with most amplifiers, externally trimming the remaining
offset can change drift performance by about 0.3µV/°C for
each 100µV of adjusted offset. The correct circuit configu-
ration for offset adjust for the PDIP packages is shown in
Figure 1.
OPA124P
5
10kΩ to 1MΩ trim potentiometer.
(100kΩ recommended).
±10mV typical trim range.
4
–VCC
FIGURE 1. Offset Voltage Trim for PDIP packages.
2
IIN
Maximum Safe Current
1
0
V
INPUT PROTECTION
Conventional monolithic FET operational amplifiers require
external current-limiting resistors to protect their inputs
against destructive currents that can flow when input FET
gate-to-substrate isolation diodes are forward-biased. Most
–1
Maximum Safe Current
BIFET amplifiers can be destroyed by the loss of –VCC
.
Unlike BIFET amplifiers, the Difet OPA124 requires input
current limiting resistors only if its input voltage is greater
than 6V more negative than –VCC. A 10kΩ series resistor
will limit input current to a safe level with up to ±15V input
levels, even if both supply voltages are lost (Figure 2).
–2
–15
–10
–5
0
5
10
15
Input Voltage (V)
FIGURE 2. Input Current vs Input Voltage with ±VCC Pins
Grounded.
Static damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers (both bipolar and FET types),
this may cause a noticeable degradation of offset voltage and
drift. Static protection is recommended when handling any
precision IC operational amplifier.
Non-Inverting
Buffer
2
2
3
8
8
Out
Out
6
6
OPA124
OPA124
GUARDING AND SHIELDING
3
In
In
In
As in any situation where high impedances are involved,
careful shielding is required to reduce “hum” pickup in input
leads. If large feedback resistors are used, they should also
be shielded along with the external input circuitry.
Bottom View
Inverting
1
8
2
Leakage currents across printed circuit boards can easily
exceed the bias current of the OPA124. To avoid leakage
problems, the OPA124 should be soldered directly into a
printed circuit board. Utmost care must be used in planning
the board layout. A “guard” pattern should completely
surround the high impedance input leads and should be
connected to a low impedance point which is at the signal
input potential.
Out
6
OPA124
7
6
5
8
3
4
Board layout for PDIP input guarding: guard top and bottom of board.
FIGURE 3. Connection of Input Guard.
The amplifier substrate should be connected to any input
shield or guard via pin 8 minimizing both leakage and noise
pickup (see Figure 3).
If guarding is not required, pin 8 should be connected to
ground.
®
8
OPA124
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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