OPA140AIDGKR [TI]
OPAx140 High-Precision, Low-Noise, Rail-to-Rail Output, 11-MHz, JFET Op Amp;
| 型号： | OPA140AIDGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPAx140 High-Precision, Low-Noise, Rail-to-Rail Output, 11-MHz, JFET Op Amp 放大器 光电二极管 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA140, OPA2140, OPA4140
SBOS498E – JULY 2010 – REVISED JULY 2021
OPAx140 High-Precision, Low-Noise, Rail-to-Rail Output, 11-MHz, JFET Op Amp
1 Features
3 Description
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Very-low offset drift: 1 μV/°C maximum
Very-low offset: 120 μV
Low input bias current: 10 pA maximum
Very-low 1/f noise: 250 nVPP, 0.1 Hz to 10 Hz
Low noise: 5.1 nV/√Hz
The OPA140, OPA2140, and OPA4140 (OPAx140)
operational amplifier (op amp) family is a series
of low-power JFET input amplifiers that features
good drift and low input bias current. The rail-to-
rail output swing and input range that includes
V– allow designers to take advantage of the low-
noise characteristics of JFET amplifiers while also
interfacing to modern, single-supply, precision analog-
to-digital converters (ADCs) and digital-to-analog
converters (DACs).
Slew rate: 20 V/μs
Low supply current: 2 mA maximum
Input voltage range includes V– supply
Single-supply operation: 4.5 V to 36 V
Dual-supply operation: ±2.25 V to ±18 V
No phase reversal
The OPA140 achieves 11-MHz unity-gain bandwidth
and 20-V/μs slew rate while consuming only 1.8 mA
(typical) of quiescent current. This device runs on a
single 4.5-V to 36-V supply or dual ±2.25-V to ±18-V
supplies.
Packages:
– Industry-standard SOIC, SON (Preview),
SOT-23, TSSOP, and VSSOP
2 Applications
All versions are fully specified from –40°C to +125°C
for use in the most challenging environments. The
OPA140 (single) is available in the 5‑pin SOT-23 8‑pin
VSSOP and 8‑pin SOIC packages. The OPA2140
(dual) is available in 8‑pin SON, 8‑pin VSSOP,
and 8‑pin SOIC packages. The OPA4140 (quad) is
available in the 14‑pin SOIC and 14‑pin TSSOP
packages.
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Intra-dc interconnect (metro)
Semiconductor test
Chemistry and gas analyzer
DC power supply, ac source, electronic load
Data acquisition (DAQ)
Lab and field instrumentation
VSUPPLY = ±18V
Competitor’s Device
Device Information
OPAx140
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
4.90 mm × 3.90 mm
2.90 mm × 1.60 mm
3.00 mm × 3.00 mm
4.90 mm × 3.90 mm
3.00 mm x 3.00 mm
3.00 mm × 3.00 mm
8.65 mm × 3.90 mm
5.00 mm × 4.40 mm
SOIC (8)
OPA140
SOT23 (5)
VSSOP (8)
SOIC (8)
OPA2140
OPA4140
SON (8) - Preview
VSSOP (8)
SOIC (14)
Time (1s/div)
TSSOP (14)
0.1-Hz to 10-Hz Noise
(1) For all available packages, see the package option
addendum at the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA140, OPA2140, OPA4140
SBOS498E – JULY 2010 – REVISED JULY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: OPA140.................................... 6
6.5 Thermal Information: OPA2140.................................. 6
6.6 Thermal Information: OPA4140.................................. 6
6.7 Electrical Characteristics: VS = 4.5 V to 36 V;
±2.25 V to ±18 V............................................................7
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................22
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 25
11 Device and Documentation Support..........................26
11.1 Device Support........................................................26
11.2 Documentation Support.......................................... 26
11.3 Receiving Notification of Documentation Updates..26
11.4 Support Resources................................................. 27
11.5 Trademarks............................................................. 27
11.6 Electrostatic Discharge Caution..............................27
11.7 Glossary..................................................................27
12 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2019) to Revision E (July 2021)
Page
•
Added OPA2140 DRG preview package and associated content to data sheet................................................ 1
Changes from Revision C (August 2016) to Revision D (January 2019)
Page
•
Changed Figure 12 x-axis title From: Frequency (Hz) To: Output Amplitude (VRMS)......................................... 8
Changes from Revision B (November 2015) to Revision C (August 2016)
Page
•
Changed units for En Input voltage noise From: µV To: nV in Section 6.7 ........................................................ 7
Changes from Revision A (August 2010) to Revision B (November 2015)
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
Changed title of Table 6-1 From: Characteristic Performance Measurements To: Table of Graphs ..................8
Changed section 7.37 title From: Power Dissipation and Thermal Protection To: Thermal Protection ........... 18
•
•
Changes from Revision * (July 2010) to Revision A (August 2010)
Page
Changed device and data sheet status to production data status......................................................................1
Added SOIC (8) (MSOP) packages....................................................................................................................3
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•
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5 Pin Configuration and Functions
1
2
3
4
8
7
6
5
NC
V+
NC
œIN
+IN
Vœ
œ
+
OUT
NC
Figure 5-1. OPA140: D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
V+
OUT
V-
1
2
3
5
4
-IN
+IN
Figure 5-2. OPA140: DBV (5-Pin SOT-23) Package, Top View
Table 5-1. Pin Functions: OPA140
PIN
OPA140
I/O
DESCRIPTION
NAME
D (SOIC),
DGK (VSSOP)
DBV (SOT)
+IN
–IN
NC
OUT
V+
3
3
4
I
Noninverting input
Inverting input
2
I
1, 5, 8
—
1
—
O
—
—
No internal connection (can be left floating)
Output
6
7
4
5
Positive (highest) power supply
Negative (lowest) power supply
V–
2
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V+
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
A
OUT B
–IN B
+IN B
OUT B
–IN B
+IN B
A
B
B
Figure 5-4. OPA2140: DRG (8-Pin SON) Package,
Top View (Preview)
Figure 5-3. OPA2140: D (8-Pin SOIC) and DGK (8-
Pin VSSOP) Packages, Top View
OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
OUT D
14
13
œIN D
A
D
12 +IN D
11
Vœ
10
+ IN B
œIN B
OUT B
+ IN C
B
C
9
œIN C
8
OUT C
Figure 5-5. OPA4140: D (14-Pin SOIC) and PW (14-Pin TSSOP) Packages, Top View
Table 5-2. Pin Functions: OPA2140 and OPA4140
PIN
OPA2140
OPA4140
I/O
DESCRIPTION
D (SOIC),
DGK (VSSOP)
DRG (SON)
NAME
D (SOIC),
PW (TSSOP)
+IN A
3
5
3
5
I
I
Noninverting input, channel A
+IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Output, channel A
—
—
2
10
12
2
I
I
I
6
6
I
—
—
1
9
I
13
1
I
O
O
O
O
—
—
7
7
Output, channel B
—
—
8
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
V–
4
11
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage, VS = (V+) – (V–)
40
Voltage(2)
Signal input pins
(V–) – 0.5
–10
(V+) + 0.5
10
V
Current(2)
mA
Output short circuit(3)
Continuous
Operating
–55
150
150
150
Temperature
Junction
°C
Storage, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails
should be current-limited to 10 mA or less.
(3) Short-circuit to VS/2 (ground in symmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.25
–40
NOM
MAX
±18
UNIT
V
Supply voltage
Specified temperature
125
°C
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6.4 Thermal Information: OPA140
OPA140
THERMAL METRIC(1)
D (SOIC)
8 PINS
160
75
DBV (SOT) DGK (VSSOP)
UNIT
5 PINS
210
200
110
8 PINS
180
55
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
60
130
N/A
120
N/A
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9
40
ψJB
50
105
N/A
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2140
OPA2140
THERMAL METRIC(1)
D (SOIC)
8 PINS
160
75
DGK (VSSOP) DRG (SON)
UNIT
8 PINS
180
55
8 PINS
50.7
50.6
23.3
0.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
60
130
N/A
120
N/A
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9
ψJB
50
23.3
7.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4140
OPA4140
THERMAL METRIC(1)
D (SOIC)
14 PINS
97
PW (TSSOP)
UNIT
14 PINS
135
45
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56
53
66
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19
N/A
60
ψJB
46
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.7 Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V
at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
30
120
220
±4
µV
VOS
Input offset voltage
VS = ±18 V, TA = –40°C to 125°C
VS = ±2.25 V to ±18 V, TA = –40°C to 125°C
µV/V
dVOS/dT
PSRR
Input offset voltage drift VS = ±18 V, TA = –40°C to 125°C
±0.35
±0.1
1
µV/°C
Power-supply rejection
VS = ±2.25 V to ±18 V, TA = –40°C to 125°C
ratio
±0.5
µV/V
INPUT BIAS CURRENT
±0.5
±0.5
±10
±3
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to 125°C
TA = –40°C to 125°C
±10
±1
IOS
Input offset current
Input voltage noise
NOISE
En
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 10 Hz
250
42
8
nVPP
nVRMS
Input voltage noise
density
en
f = 100 Hz
5.8
5.1
nV/√ Hz
fA/√ Hz
f = 1 kHz
Input current noise
density
in
f = 1 kHz
0.8
INPUT VOLTAGE
VCM
Common-mode voltage TA = –40°C to 125°C
(V–) – 0.1
126
(V+) – 3.5
V
140
Common-mode rejection VS = ±18 V, VCM = (V–) – 0.1 V
CMRR
dB
ratio
to (V+) – 3.5 V
TA = –40°C to 125°C
120
INPUT IMPEDANCE
ZID
ZIC
Differential
1013 || 10
1013 || 7
Ω || pF
Ω || pF
Common-mode
VCM = (V–) – 0.1 V to (V+) – 3.5 V
OPEN-LOOP GAIN
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 10 kΩ
120
126
126
AOL
Open-loop voltage gain
dB
114
108
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 2 kΩ
TA = –40°C to 125°C
FREQUENCY RESPONSE
BW
SR
Gain bandwidth product
11
20
MHz
V/µs
ns
Slew rate
12-bit
16-bit
880
1.6
600
ts
Settling time
µs
tOR
Overload recovery time
ns
Total harmonic distortion
+ noise
THD+N
OUTPUT
1 kHz, G = 1, VO = 3.5 VRMS
0.00005%
RLOAD = 10 kΩ, AOL ≥ 108 dB
(V–) + 0.2
(V+) – 0.2
VO
Voltage output
V
RLOAD = 2 kΩ, AOL ≥ 108 dB
(V–) + 0.35
(V+) – 0.35
Source
Sink
36
ISC
CLOAD
ZO
Short-circuit current
Capacitive load drive
mA
–30
See Figure 6-19 and Figure 6-20
16
Open-loop output
impedance
f = 1 MHz, IO = 0 A (See Figure 6-18)
Ω
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6.7 Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V (continued)
at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
IQ
Power-supply voltage
4.5 (±2.25)
9 (±18)
2
V
IO = 0 A
1.8
Quiescent current per
amplifier
mA
TA = –40°C to 125°C
2.7
CHANNEL SEPARATION
Channel separation
At dc
0.02
10
μV/V
At 100 kHz
6.8 Typical Characteristics
at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
Table 6-1. Table of Graphs
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
Offset Voltage Production Distribution
Offset Voltage Drift Distribution
Offset Voltage Drift Distribution
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
IB vs Common-Mode Voltage
Offset Voltage vs Common-Mode Voltage
IB vs Common-Mode Voltage
Input Offset Voltage vs Temperature
Output Voltage Swing vs Output Current
CMRR and PSRR vs Frequency (RTI)
Common-Mode Rejection Ratio vs Temperature
0.1-Hz to 10-Hz Noise
Input Offset Voltage vs Temperature (144 Amplifiers)
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred to Input)
Common-Mode Rejection Ratio vs Temperature
0.1-Hz to 10-Hz Noise
Input Voltage Noise Density vs Frequency
THD+N Ratio vs Frequency (80-kHz AP Bandwidth)
THD+N Ratio vs Output Amplitude
Quiescent Current vs Temperature
Quiescent Current vs Supply Voltage
Gain and Phase vs Frequency
Input Voltage Noise Density vs Frequency
THD+N Ratio vs Frequency
THD+N Ratio vs Output Amplitude
Quiescent Current vs Temperature
Quiescent Current vs Supply Voltage
Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Closed-Loop Gain vs Frequency
Open-Loop Gain vs Temperature
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (G = 1)
Small-Signal Overshoot vs Capacitive Load (G = –1)
No Phase Reversal
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
No Phase Reversal
Positive Overload Recovery
Positive Overload Recovery
Negative Overload Recovery
Negative Overload Recovery
Large-Signal Positive Settling Time (10-V Step),
Large-Signal Negative Settling Time (10-V Step)
Large-Signal Positive and Negative Settling Time
Small-Signal Step Response (G = 1)
Small-Signal Step Response (G = –1)
Large-Signal Step Response (G = 1)
Large-Signal Step Response (G = –1)
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Channel Separation vs Frequency
Small-Signal Step Response (100 mV)
Small-Signal Step Response (100 mV)
Large-Signal Step Response
Large-Signal Step Response
Short Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Channel Separation vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
Offset Voltage (mV)
Offset Voltage Drift (mV/°C)
Figure 6-1. Offset Voltage Production Distribution
Figure 6-2. Offset Voltage Drift Distribution
160
120
80
120
18 Typical Units Shown
100
80
60
40
40
20
0
0
-20
-40
-60
-80
-100
-120
-40
-80
-120
-160
-40 -25 -10
5
20 35 50 65 80 95 110 125
-18
-12
-6
0
6
12
18
Temperature (?C)
VCM (V)
Figure 6-3. Offset Voltage vs Common-Mode Voltage
Figure 6-4. Input Offset Voltage vs Temperature (144 Amplifiers)
18.0
17.5
17.0
16.5
16.0
10
Specified Common-Mode
8
Voltage Range
+14.5V
-0.1V
+25°C
-40°C
6
4
+85°C
+125°C
-16.0
-16.5
-17.0
-17.5
-18.0
+IB
2
-IB
0
0
10
20
30
40
50
60
70
-18 -15 -12 -9 -6 -3
0
3
6
9
12 15 18
Output Current (mA)
VCM (V)
Figure 6-6. Output Voltage Swing vs Output Current (Maximum
Supply)
Figure 6-5. IB vs Common-Mode Voltage
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
180
160
140
120
100
80
0.12
0.10
0.08
0.06
0.04
0.02
0
CMRR
-PSRR
+PSRR
60
40
20
0
-75 -50 -25
0
25
50
75
100 125 150
1
10
100
1k
10k 100k
1M
10M 100M
Temperature (°C)
Frequency (Hz)
Figure 6-8. Common-Mode Rejection Ratio vs Temperature
Figure 6-7. CMRR and PSRR vs Frequency (Referred to Input)
100
10
1
Time (1s/div)
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Figure 6-9. 0.1-Hz to 10-Hz Noise
Figure 6-10. Input Voltage Noise Density vs Frequency
0.01
-80
0.001
-100
-120
-140
BW = 80kHz
1kHz Signal
RL = 2kW
G = -1
G = +1
VOUT = 3VRMS
BW = 80kHz
RL = 2kW
G = -1
0.001
-100
-120
-140
0.0001
0.0001
0.00001
G = +1
NOTE: Increase at low signal levels is a result
of increased % contribution of noise.
0.00001
10
100
1k
10k 20k
0.1
1
10
100
Frequency (Hz)
Output Amplitude (VRMS
)
Figure 6-11. THD+N Ratio vs Frequency
Figure 6-12. THD+N Ratio vs Output Amplitude
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
2.5
2.0
1.5
1.0
0.5
0
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
OPA140
Specified Supply-Voltage Range
-75 -50 -25
0
25
50
75
100 125 150
0
4
8
12
16
20
24
28
32
36
Temperature (°C)
Supply Voltage (V)
Figure 6-13. Quiescent Current vs Temperature
Figure 6-14. Quiescent Current vs Supply Voltage
140
120
100
80
180
135
90
45
0
40
CL = 30pF
30
G = +10
Gain
20
10
G = +1
60
0
40
-10
Phase
20
-20
G = -1
0
-30
-20
-40
10
100
1k
10k
100k
1M
10M
100M
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 6-15. Gain and Phase vs Frequency
Figure 6-16. Closed-Loop Gain vs Frequency
1k
100
10
0
10kW Load
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
2kW Load
1
-75 -50 -25
0
25
50
75
100 125 150
10
100
1k
10k
100k
1M
10M
100M
Temperature (°C)
Frequency (Hz)
Figure 6-17. Open-Loop Gain vs Temperature
Figure 6-18. Open-Loop Output Impedance vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
ROUT = 0W
G = +1
+15V
OPA140
-15V
ROUT
ROUT = 0W
RL
CL
ROUT = 24W
ROUT = 24W
ROUT = 51W
RF = 2kW
RI = 2kW
G = -1
+15V
ROUT
ROUT = 51W
OPA140
CL
-15V
0
0
0
200
400
600
800 1000 1200 1400 1600
0
500
1000
Capacitive Load (pF)
1500
2000
Capacitive Load (pF)
Figure 6-19. Small-Signal Overshoot vs Capacitive Load (100-
mV Output Step)
Figure 6-20. Small-Signal Overshoot vs Capacitive Load (100-
mV Output Step)
35
Maximum Output
Voltage Range
Without Slew-Rate
Induced Distortion
VS
=
15 V
30
25
20
15
10
5
Output
+18V
VS
VS
=
5 V
OPA140
Output
-18V
37VPP
=
2ꢀ25 V
Sine Wave
(±18.5V)
0
Time (0.4ms/div)
10k
100k
Frequency (Hz)
1M
10M
Figure 6-22. Maximum Output Voltage vs Frequency
Figure 6-21. No Phase Reversal
VOUT
VIN
20kW
20kW
2kW
2kW
VIN
VOUT
OPA140
VOUT
OPA140
VIN
VIN
VOUT
G = -10
G = -10
Time (0.4ms/div)
Time (0.4ms/div)
Figure 6-24. Negative Overload Recovery
Figure 6-23. Positive Overload Recovery
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
1000
800
1000
800
600
600
400
400
16-bit Settling
16-bit Settling
200
200
0
0
-200
-400
-600
-800
-1000
-200
-400
-600
-800
-1000
( 1/2LSB = 0.00075%)
( 1/2LSB = 0.00075%)
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Time (ms)
Time (ms)
Figure 6-25. Large-Signal Positive Settling Time (10-V Step)
Figure 6-26. Large-Signal Negative Settling Time (10-V Step)
CL = 100pF
CL = 100pF
G = +1
+15V
RI = 2kW RF = 2kW
+15V
OPA140
OPA140
-15V
RL
CL
CL
-15V
G = -1
Time (100ns/div)
Time (100ns/div)
Figure 6-27. Small-Signal Step Response (100 mV)
Figure 6-28. Small-Signal Step Response (100 mV)
Time (400 ns/div)
Time (400 ns/div)
Figure 6-29. Large-Signal Step Response
Figure 6-30. Large-Signal Step Response
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
60
50
40
30
20
10
0
-90
-100
-110
-120
-130
-140
-150
VOUT = 3VRMS
G = +1
ISC, Source
ISC, Sink
RL = 2kW
Short-circuiting causes thermal shutdown;
see Applications Information section.
RL = 5kW
10
100
1k
10k
100k
-75 -50 -25
0
25
50
75
100 125 150
Frequency (Hz)
Temperature (°C)
Figure 6-32. Channel Separation vs Frequency
Figure 6-31. Short Circuit Current vs Temperature
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7 Detailed Description
7.1 Overview
The OPAx140 family of operational amplifiers is a series of low-power JFET input amplifiers that feature superior
drift performance and low input bias current. The rail-to-rail output swing and input range that includes V– allow
designers to use the low-noise characteristics of JFET amplifiers while also interfacing to modern, single-supply,
precision analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The OPAx140 series
achieves 11-MHz unity-gain bandwidth and 20-V/μs slew rate, and consumes only 1.8 mA (typical) of quiescent
current. These devices operate on a single 4.5-V to 36-V supply or dual ±2.25-V to ±18-V supplies.
Section 7.2 shows the simplified diagram of the OPAx140.
7.2 Functional Block Diagram
V+
Pre-Output Driver
OUT
IN–
IN+
V–
7.3 Feature Description
7.3.1 Operating Voltage
The OPA140, OPA2140, and OPA4140 series of op amps can be used with single or dual supplies from
an operating range of VS = 4.5 V (±2.25 V) and up to VS = 36 V (±18 V). These devices do not require
symmetrical supplies; they only require a minimum supply voltage of 4.5 V (±2.25 V). For VS less than ±3.5 V,
the common-mode input range does not include midsupply. Supply voltages higher than 40 V can permanently
damage the device; see Section 6.1. Key parameters are specified over the operating temperature range, TA =
–40°C to 125°C. Key parameters that vary over the supply voltage or temperature range are shown in Section
6.8 of this data sheet.
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7.3.2 Capacitive Load and Stability
The dynamic characteristics of the OPAx140 have been optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50 Ω,
for example) in series with the output.
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) and Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step) illustrate graphs of Small-Signal Overshoot vs Capacitive Load for several values of
ROUT. Also, see the Feedback Plots Define Op Amp AC Performance Application Bulletin, available for download
from www.ti.com, for details of analysis techniques and application circuits.
7.3.3 Output Current Limit
The output current of the OPAx140 series is limited by internal circuitry to 36 mA/–30 mA (sourcing/sinking),
to protect the device if the output is accidentally shorted. This short circuit current depends on temperature, as
shown in Short Circuit Current vs Temperature.
7.3.4 Noise Performance
Figure 7-1 shows the total circuit noise for varying source impedances with the operational amplifier in a
unity-gain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPA140 and OPA211 are shown with total circuit noise calculated. The op amp itself contributes both a voltage
noise component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest
noise op amp for a given application depends on the source impedance. For low source impedance, current
noise is negligible, and voltage noise generally dominates. The OPA140, OPA2140, and OPA4140 family has
both low voltage noise and extremely low current noise because of the FET input of the op amp. As a result, the
current noise contribution of the OPAx140 series is negligible for any practical source impedance, which makes it
the better choice for applications with high source impedance.
The equation in Figure 7-1 shows the calculation of the total circuit noise, with these parameters:
•
•
•
•
•
en = voltage noise
In = current noise
RS = source impedance
k = Boltzmann's constant = 1.38 × 10–23 J/K
T = temperature in degrees Kelvin (K)
For more details on calculating noise, see Section 7.3.5.
10k
EO
OPA211
1k
RS
100
OPA140
Resistor Noise
10
EO2 = en2 + (in RS)2 + 4kTRS
1
100
1k
10k
100k
1M
Source Resistance, RS (W)
Figure 7-1. Noise Performance of the OPA140 and OPA211 in Unity-Gain Buffer Configuration
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7.3.5 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 7-1. The source impedance is usually fixed; consequently, select the
op amp and the feedback resistors to minimize the respective contributions to the total noise.
Noise Calculation in Gain Configurations illustrates both noninverting (A) and inverting (B) op amp circuit
configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute
noise. In general, the current noise of the op amp reacts with the feedback resistors to create additional noise
components. However, the extremely low current noise of the OPAx140 means that its current noise contribution
can be neglected.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
A) Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
2
R2
R1
R2
R1
R2
R1
2
EO
2
en
2
2
es
e12 + e2
+
R1
1 +
1 +
=
+
EO
4kTRS
4kTR1
4kTR2
Where eS
=
= thermal noise of RS
= thermal noise of R1
= thermal noise of R2
RS
e1 =
e2 =
VS
B) Noise in Inverting Gain Configuration
Noise at the output:
R2
2
2
2
R2
R2
R2
R1 + RS
2
EO
2
2
2
e12 + e2
+
es
= 1 +
en
+
R1
R1 + RS
R1 + RS
EO
RS
4kTRS
4kTR1
4kTR2
Where eS
=
= thermal noise of RS
= thermal noise of R1
= thermal noise of R2
VS
e1 =
e2 =
For the OPAx140 series of operational amplifiers at 1 kHz, en = 5.1 nV/√ Hz.
Figure 7-2. Noise Calculation in Gain Configurations
7.3.6 Phase-Reversal Protection
The OPA140, OPA2140, and OPA4140 family has internal phase-reversal protection. Many FET- and bipolar-
input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This
condition is most often encountered in noninverting circuits when the input is driven beyond the specified
common-mode voltage range, causing the output to reverse into the opposite rail. The input circuitry of the
OPA140, OPA2140, and OPA4140 prevents phase reversal with excessive common-mode voltage; instead, the
output limits into the appropriate rail (see No Phase Reversal).
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7.3.7 Thermal Protection
The OPAx140 series of op amps are capable of driving 2-kΩ loads with power-supply voltages of up to ±18
V over the specified temperature range. In a single-supply configuration, where the load is connected to the
negative supply voltage, the minimum load resistance is 2.8 kΩ at a supply voltage of 36 V. For lower supply
voltages (either single-supply or symmetrical supplies), a lower load resistance may be used, as long as the
output current does not exceed 13 mA; otherwise, the device short circuit current protection circuit may activate.
Internal power dissipation increases when operating at high supply voltages. Copper leadframe construction
used in the OPA140, OPA2140, and OPA4140 series devices improves heat dissipation compared to
conventional materials. Printed-circuit-board (PCB) layout can also help reduce a possible increase in junction
temperature. Wide copper traces help dissipate the heat by acting as an additional heatsink. Temperature rise
can be further minimized by soldering the devices directly to the PCB rather than using a socket.
Although the output current is limited by internal protection circuitry, accidental shorting of one or more output
channels of a device can result in excessive heating. For instance, when an output is shorted to mid-supply, the
typical short-circuit current of 36 mA leads to an internal power dissipation of over 600 mW at a supply of ±18 V.
In the case of a dual OPA2140 in an 8-pin VSSOP package (thermal resistance θJA = 180°C/W), such power
dissipation would lead the die temperature to be 220°C above ambient temperature, when both channels are
shorted. This temperature increase significantly decreases the operating life of the device.
To prevent excessive heating, the OPAx140 series has an internal thermal shutdown circuit that shuts down
the device if the die temperature exceeds approximately 180°C. When this thermal shutdown circuit activates,
a built-in hysteresis of 15°C makes sure that the die temperature must drop to approximately 165°C before the
device switches on again.
Additional consideration should be given to the combination of maximum operating voltage, maximum operating
temperature, load, and package type. Figure 7-3 and Figure 7-4 show several practical considerations when
evaluating the OPA2140 (dual version) and the OPA4140 (quad version).
As an example, the OPA4140 has a maximum total quiescent current of 10.8 mA (2.7 mA/channel) over
temperature. The 14-pin TSSOP package has a typical thermal resistance of 135°C/W. This parameter means
that because the junction temperature should not exceed 150°C to provide reliable operation, either the supply
voltage must be reduced, or the ambient temperature should remain low enough so that the junction temperature
does not exceed 150°C. This condition is illustrated in Figure 7-3 for various package types. Moreover, resistive
loading of the output causes additional power dissipation and thus self-heating, which also must be considered
when establishing the maximum supply voltage or operating temperature. To this end, Figure 7-4 shows the
maximum supply voltage versus temperature for a worst-case dc load resistance of 2 kΩ.
20
18
16
14
12
10
8
20
18
16
14
12
10
8
6
6
TSSOP Quad
SOIC Quad
MSOP Dual
SOIC Dual
TSSOP Quad
SOIC Quad
MSOP Dual
SOIC Dual
4
4
2
2
0
0
80
90
100
110
120
130
140
150
160
80
90
100
110
120
130
140
150
160
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 7-3. Maximum Supply Voltage vs
Figure 7-4. Maximum Supply Voltage vs
Temperature (OPA2140 and OPA4140), Quiescent
Condition
Temperature (OPA2140 and OPA4140), Maximum
DC Load
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7.3.8 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress
event. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application shows an illustration
of the ESD circuits contained in the OPAx140 series (indicated by the dashed line area). The ESD protection
circuitry involves several current-steering diodes connected from the input and output pins and routed back to
the internal power-supply lines, where they meet at an absorption device internal to the operational amplifier.
This protection circuitry is intended to remain inactive during normal circuit operation.
TVS(2)
RF
+VS
+V
OPA140
RI
ESD Current-
Steering Diodes
-In
(3)
Out
Op Amp
Core
RS
+In
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
-V
-VS
TVS(2)
(1) VIN = +VS + 500 mV.
(2) TVS: +VS(max) > VTVSBR (Min) > +VS
(3) Suggested value approximately 1 kΩ.
Figure 7-5. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the
OPAx140 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device
quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as the one Equivalent Internal ESD Circuitry and
Its Relation to a Typical Circuit Application shows, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
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an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk
that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through steering diode paths and rarely involves the absorption device.
Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application depicts a specific example
where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500 mV or more. Much of what
happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input
steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly
higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10
mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier,
and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise
to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V.
Again, it depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If
the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the
input source through the current steering diodes. This state is not a normal bias condition; the amplifier most
likely will not operate normally. If the supplies are low impedance, then the current through the steering diodes
can become quite high. The current level depends on the ability of the input source to deliver current, and any
resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be
added to the supply pins as shown in Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit
Application. The Zener voltage must be selected such that the diode does not turn on during normal operation.
However, its Zener voltage should be low enough so that the Zener diode conducts if the supply pin begins to
rise above the safe operating supply voltage level.
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7.3.9 EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of
RF signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has
a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but
this section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
•
•
•
Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance
EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input
terminal with no complex interactions from other components or connecting PCB traces. Figure 7-6
120
PRF = -10 dbm
VS = ê12 V
VCM = 0 V
100
80
60
40
20
0
10
100
Frequency (MHz)
1k
10k
Figure 7-6. OPA2140 EMIRR
The EMIRR IN+ of the OPA2140 is plotted versus frequency as shown in .If available, any dual and quad op
amp device versions have nearly similar EMIRR IN+ performance. The OPA2140 unity-gain bandwidth is
11 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the op amp
bandwidth.
For more information, see the EMI Rejection Ratio of Operational Amplifiers Application Report, available for
download from www.ti.com.
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Table 7-1 lists the EMIRR IN+ values for the OPA2140 at particular frequencies commonly encountered in real-
world applications. Applications listed in Table 7-1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 7-1. OPA2140 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
53.1 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
72.2 dB
80.7 dB
86.8 dB
91.7 dB
96.6 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
7.3.10 EMIRR +IN Test Configuration
Figure 7-7 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
op amp noninverting input terminal using a transmission line. The op amp is configured in a unity gain
buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large
impedance mismatch at the op amp input causes a voltage reflection; however, this effect is characterized and
accounted for when determining the EMIRR IN+. The resulting DC offset voltage is sampled and measured
by the multimeter. The LPF isolates the multimeter from residual RF signals that may interfere with multimeter
accuracy.
Ambient temperature: 25˘C
+VS
œ
50 ꢀ
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
-VS
Sample /
Averaging
Digital Multimeter
Not shown: 0.1 µF and 10 µF
supply decoupling
Frequency Sweep: 201 pt. Log
Figure 7-7. EMIRR +IN Test Configuration
7.4 Device Functional Modes
The OPAx140 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx140 is 36 V (±18 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPA140, OPA2140, and OPA4140 are unity-gain stable, operational amplifiers with very low noise, input
bias current, and input offset voltage. Applications with noisy or high-impedance power supplies require
decoupling capacitors placed close to the device pins. In most cases, 0.1-μF capacitors are adequate. Designers
can easily use the rail-to-rail output swing and input range that includes V– to take advantage of the low-noise
characteristics of JFET amplifiers while also interfacing to modern, single-supply, precision data converters.
8.2 Typical Application
R4
2.94 kꢀ
C5
1 nF
œ
R1
590 ꢀ
R3
499 ꢀ
Output
+
Input
OPA140
C2
39 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. 25-kHz Low-pass Filter
8.2.1 Design Requirements
Lowpass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPAx140 are an excellent choice to construct high-speed, high-precision active filters. Figure 8-1 shows a
second-order, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
•
•
•
Gain = 5 V/V (inverting gain)
Low-pass cutoff frequency = 25 kHz
Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in. Use Equation 1 to
calculate the voltage transfer function.
-1 R1R3C2C5
Output
Input
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
2
1
3
4
3 4 2 5
(1)
This circuit produces a signal inversion. For this circuit, the gain at DC and the lowpass cutoff frequency are
calculated by Equation 2:
R4
Gain =
R1
1
fC
=
1 R R C C
(
3 4 2 5
)
2p
(2)
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Software tools are readily available to simplify filter design. The WEBENCH® Filter Designer is a simple,
powerful, and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create
optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor
partners.
Available as a web based tool from the WEBENCH Design Center, the WEBENCH Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
8.2.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 8-2. OPAx140 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
9 Power Supply Recommendations
The OPAx140 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in Section 6.8.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Section 6.1.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 10.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As illustrated in Figure 10-1, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
For best performance, TI recommends cleaning the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-1. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ SImulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI simulation softwate provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 WEBENCH Filter Designer Tool
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
11.1.1.3 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
•
•
•
•
•
•
Texas Instruments, Circuit Board Layout Techniques
Texas Instruments, Op Amps for Everyone design reference
Texas Instruments, OPA140, OPA2140, OPA4140 EMI Immunity Performance technical brief
Texas Instruments, Compensate Transimpedance Amplifiers Intuitively application report
Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis
Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis
Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters
Texas Instruments, Op Amp Performance Analysis application bulletin
Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
Texas Instruments, Tuning in Amplifiers application bulletin
Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report
Texas Instruments, Feedback Plots Define Op Amp AC Performance application bulletin
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers Application Report application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
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11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA140AID
OPA140AIDBVR
OPA140AIDBVT
OPA140AIDGKR
OPA140AIDGKT
OPA140AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
D
DBV
DBV
DGK
DGK
D
8
5
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA140
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
50 RoHS & Green
2500 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
O140
5
O140
8
Call TI | NIPDAU
Call TI | NIPDAU
NIPDAU
(140, O140)
140
8
8
OPA140
O2140A
2140
OPA2140AID
SOIC
D
8
NIPDAU
OPA2140AIDGKR
OPA2140AIDGKT
OPA2140AIDR
OPA4140AID
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
NIPDAU
8
NIPDAU
2140
8
NIPDAU
O2140A
O4140A
O4140A
O4140A
O4140A
SOIC
D
14
14
14
14
8
NIPDAU
OPA4140AIDR
OPA4140AIPW
OPA4140AIPWR
POPA2140AIDRGR
SOIC
D
NIPDAU
TSSOP
TSSOP
SON
PW
PW
DRG
NIPDAU
NIPDAU
3000
Non-RoHS &
Non-Green
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2021
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA140AIDBVR
OPA140AIDBVT
OPA140AIDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
3000
250
180.0
180.0
330.0
330.0
180.0
330.0
330.0
330.0
8.4
3.23
3.23
6.4
5.3
5.3
6.4
6.5
6.9
3.17
3.17
5.2
3.4
3.4
5.2
9.0
5.6
1.37
1.37
2.1
1.4
1.4
2.1
2.1
1.6
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
Q1
Q1
Q1
8.4
8.0
8
2500
2500
250
12.4
12.4
12.4
12.4
16.4
12.4
12.0
12.0
12.0
12.0
16.0
12.0
OPA2140AIDGKR
OPA2140AIDGKT
OPA2140AIDR
OPA4140AIDR
OPA4140AIPWR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
2500
2000
SOIC
D
14
14
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA140AIDBVR
OPA140AIDBVT
OPA140AIDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
3000
250
202.0
202.0
853.0
853.0
210.0
853.0
853.0
853.0
201.0
201.0
449.0
449.0
185.0
449.0
449.0
449.0
28.0
28.0
35.0
35.0
35.0
35.0
35.0
35.0
8
2500
2500
250
OPA2140AIDGKR
OPA2140AIDGKT
OPA2140AIDR
OPA4140AIDR
OPA4140AIPWR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
2500
2000
SOIC
D
14
14
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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