OPA145IDBVT [TI]
OPAx145 High-Precision, Low-Noise, Rail-to-Rail Output, 5.5-MHz JFET Operational Amplifiers;
| 型号： | OPA145IDBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPAx145 High-Precision, Low-Noise, Rail-to-Rail Output, 5.5-MHz JFET Operational Amplifiers |
| 文件： | 总42页 (文件大小：2963K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA145,,OPA2145
SBOS427E – JUNE 2017 – REVISED OCTOBER 2020
OPAx145 High-Precision, Low-Noise, Rail-to-Rail Output, 5.5-MHz
JFET Operational Amplifiers
1 Features
3 Description
•
Best bandwidth and slew-rate-to-power ratio:
The OPA145 and OPA2145 (OPAx145) devices are
part of a family of low-power JFET input amplifier that
have excellent drift, low current noise, and pico-
ampere input bias current. These features make the
OPZx145 an excellent choice for amplifying small
signals from high-impedance sensors.
– gain-bandwidth product: 5.5 MHz
– Slew rate: 20 V/μs
– Low supply current: 475 µA (maximum)
High precision:
– Very low offset: 150 μV (maximum)
– Very low offset drift: 1 μV/°C (maximum)
Low input bias current: 2 pA
•
The rail-to-rail output swing interfaces to modern,
single-supply, precision, analog-to-digital converters
(ADCs) and digital-to-analog converters (DACs). In
addition, the input range that includes V– allows
designers to simplify power management and take
advantage of the single-supply, low-noise JFET
architecture.
•
•
Excellent noise performance:
– Very low voltage noise: 7 nV/√Hz
– Very low current noise: 0.8 fA/√ Hz
Input-voltage range includes V– supply
Single-supply operation: 4.5 V to 36 V
Dual-supply operation: ±2.25 V to ±18 V
•
•
•
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
2.90 mm × 1.60 mm
4.90 mm × 3.91 mm
2 Applications
SOIC (8)
OPA145
VSSOP (8)
•
•
•
•
•
•
•
•
Semiconductor test
SOT-23 (5)
Lab and field instrumentation
Source measurement unit (SMU)
Weigh scale
Intra-DC interconnect (metro)
Merchant network and server PSU
DC power supply, ac source, electronic load
Data acquisition (DAQ)
SOIC (8) (Preview)
OPA2145
VSSOP (8) (Preview) 3.00 mm × 3.00 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
R1
3
1.5
0
50 kꢀ
C1
9 pF
R5
22 ꢁ
+10V
+10V
œ
œ
R3
180 ꢁ
OPA145
+
2.5 V to 5 V 2.7 V to 3.6 V
OPA145
+
C3 C5
432p 200p
GND
GND
REF
AINP
AVDD
GND
GND
² • VREF
GND
ADS8867
AINN
C4 C6
432p 200p
+
-1.5
-3
GND
OPA145
+
R4
180 ꢁ
œ
OPA145
Fast Silicon
PIN Photodiode
R6
22 ꢁ
+10V
œ
+10V
5 ꢀA
3.8 pF
2.5 mW/cm2
Photovoltaic Mode
C2
9 pF
0
5
10
15
20
œ20
œ15
œ10
œ5
Copyright © 2017, Texas Instruments Incorporated
Input Common-mode Voltage (V)
C001
R2
50 kꢀ
OPAx145 Precision JFET Technology Offers
Excellent Linear Input Impedance
OPAx145 Excels in 16-bit, 100-kSPS Fully
Differential Transimpedance Imaging Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA145,, OPA2145
SBOS427E – JUNE 2017 – REVISED OCTOBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information: OPA145 ................................... 5
6.5 Thermal Information: OPA2145 ................................. 5
6.6 Electrical Characteristics: VS = 4.5 V to 36 V;
±2.25 V to ±18 V ...........................................................6
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................22
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 23
8.3 System Examples..................................................... 24
9 Power Supply Recommendations................................26
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Device Support........................................................28
11.2 Documentation Support.......................................... 28
11.3 Receiving Notification of Documentation Updates..28
11.4 Support Resources................................................. 29
11.5 Trademarks............................................................. 29
11.6 Electrostatic Discharge Caution..............................29
11.7 Glossary..................................................................29
12 Mechanical, Packaging, and Orderable
Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2020) to Revision E (October 2020)
Page
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added OPA2145 advanced information (preview) DGK (VSSOP-8) package and associated content to data
sheet...................................................................................................................................................................1
Deleted Operating Voltage section; redundant information.............................................................................. 16
•
Changes from Revision C (July 2018) to Revision D (June 2020)
Added OPA2145 advanced information (preview) device D (SOIC-8) package and associated content to data
sheet...................................................................................................................................................................1
Page
•
Changes from Revision B (May 2018) to Revision C (July 2018)
Page
Deleted "preview" from information re: DBV (SOT-23) package, now released ................................................1
Changed status of data sheet to production data ..............................................................................................1
•
•
Changes from Revision A (March 2018) to Revision B (May 2018)
Page
•
Deleted "preview" from information re: DGK (VSSOP) package, now released ................................................1
Changes from Revision * (June 2017) to Revision A (March 2018)
Page
•
Added preview of DBV and DGK packages; removed content regarding future device releases ..................... 1
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SBOS427E – JUNE 2017 – REVISED OCTOBER 2020
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5 Pin Configuration and Functions
NC
œIN
+IN
Vœ
1
2
3
4
8
7
6
5
NC
V+
OUT
Vœ
1
2
3
5
V+
œ
OUT
NC
+
+IN
4
œIN
Not to scale
Not to scale
Figure 5-2. OPA145: DBV (5-Pin SOT-23) Package,
Top View
Figure 5-1. OPA145: D (8-Pin SOIC) and DGK (8-Pin
VSSOP) Packages, Top View
Table 5-1. Pin Functions: OPA145
PIN
OPA145
I/O
DESCRIPTION
NAME
D (SOIC),
DGK (VSSOP)
DBV (SOT-23)
–IN
+IN
NC
OUT
V–
2
4
3
I
Inverting input
3
I
Noninverting input
1, 5, 8
—
1
—
O
—
—
No internal connection (can be left floating)
Output
6
4
7
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
OUT A
1
2
3
4
8
7
6
5
V+
œIN A
+IN A
Vœ
OUT B
œIN B
+IN B
Not to scale
Figure 5-3. OPA2145: D (PREVIEW 8-Pin SOIC) and DGK (PREVIEW 8-Pin VSSOP) Packages, Top View
Table 5-2. Pin Functions: OPA2145
PIN
OPA2145
I/O
DESCRIPTION
NAME
D (SOIC),
DGK (VSSOP)
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
2
3
6
5
1
7
4
8
I
I
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Output channel A
I
I
O
O
—
—
Output channel B
Negative supply
V+
Positive supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
±20
UNIT
Dual supply
VS
Supply voltage, (V+) – (V–)
Signal input pins(2)
V
Single supply
Voltage
40
(V–) – 0.5
(V+) + 0.5
±10
V
Current
mA
ISC
TA
Output short-circuit(3)
Operating temperature
Junction temperature
Storage temperature
Continuous Continuous
–55
150
150
150
°C
°C
°C
TJ
TSTG
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.25
4.5
NOM
±15
30
MAX
±18
36
UNIT
Dual supply
VS
TA
Supply voltage, (V+) – (V–)
Ambient temperature
V
Single supply
–40
25
125
°C
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6.4 Thermal Information: OPA145
OPA145
THERMAL METRIC(1)
D (SOIC)
8 PINS
136
DGK (VSSOP)
DBV (SOT)
5 PINS
205
UNIT
8 PINS
143
47
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
74
200
62
64
113
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19.7
54.8
N/A
5.3
38.2
ΨJB
62.8
N/A
104.9
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2145
OPA2145
THERMAL METRIC(1)
D (SOIC)
8 PINS
118.7
52.3
DGK (VSSOP)
8 PINS
163.9
53.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
63.5
85.0
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.7
5.9
ΨJB
62.4
83.7
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, seethe Semiconductorand IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V
at TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = ±18 V
±40
±150
±280
±350
VOS
Offset voltage, RTI
VS = ±18 V, TA = 0°C to +85°C
μV
VS = ±18 V, TA = –40°C to +125°C
VS = ±18 V, TA = 0°C to +85°C
D and DGK Packages
±0.4
±0.4
±1
±1.2
±1.4
±1.5
±0.3
±0.5
±2
VS = ±18 V, TA = 0°C to +85°C
DBV Package
dVOS/dT
Drift
μV/°C
VS = ±18 V, TA = –40°C to +125°C
D and DGK Packages
±0.5
VS = ±18 V, TA = –40°C to +125°C
DBV Package
±0.5
VS = ±2.25 V to ±18 V
D Package Only
±0.06
±0.06
VS = ±2.25 V to ±18 V
DGK and DBV Packages
PSRR
Power-supply rejection ratio
μV/V
VS = ±2.25 V to ±18 V,
TA = –40°C to +125°C
INPUT BIAS CURRENT
±2
±2
±10
±600
±10
pA
nA
pA
nA
IB
Input bias current
TA = 0°C to +85°C
TA = –40°C to +125°C
±10
IOS
Input offset current
Input voltage noise
TA = 0°C to +85°C
±600
±10
TA = –40°C to +125°C
NOISE
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 10 Hz
320
60
9
nVPP
nVRMS
en
In
Input voltage noise density
Input current noise density
f = 100 Hz
7.2
7
nV/√Hz
fA/√Hz
V
f = 1 kHz
f = 1 kHz
0.8
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
TA = –40°C to +125°C
(V–) –0.1
126
(V+)–3.5
VS = ±18 V,
VCM = (V–) –0.1 V to (V+) – 3.5 V
140
CMRR
Common-mode rejection ratio
dB
VS = ±18 V,
VCM = (V–) –0.1 V to (V+) – 3.5 V,
TA = –40°C to +125°C
118
INPUT IMPEDANCE
Differential
1013 || 5
Ω || pF
Common-mode
VCM = (V–) –0.1 V to (V+) –3.5 V
1013 || 4.3
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6.6 Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V (continued)
at TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 10 kΩ
D Package Only
118
110
123
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 10 kΩ
DGK and DBV Packages
123
110
AOL
Open-loop voltage gain
dB
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 2 kΩ
106
104
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 2 kΩ, TA = –40°C to +125°C
FREQUENCY RESPONSE
BW
SR
Gain bandwidth product
5.5
20
MHz
V/μs
Slew rate
12 bits
16 bits
10-V Step, G = +1
1.6
Settling time
μs
10-V Step, G = +1
6
THD+N
Total harmonic distortion and noise
Overload recovery time
1 kHz, G = +1, VO = 3.5 VRMS
0.0001%
600
ns
OUTPUT
RL = 10 kΩ, AOL ≥ 108 dB,
TA = –40°C to +125°C,
See Figure 6-24 and Figure 6-25
(V–) + 0.1
(V–) + 0.3
(V+) – 0.1
(V+) – 0.3
Linear output voltage swing range
V
RL = 2 kΩ, AOL ≥ 108 dB,
TA = –40°C to +125°C,
See Figure 6-24 and Figure 6-25
RL = 10 kΩ
75
80
RL = 10 kΩ, OPA2145
RL = 10 kΩ, TA = –40°C to +125°C
RL = 2 kΩ
90
210
230
RL = 2 kΩ, OPA2145
VO
Voltage output swing from rail
mV
RL = 2 kΩ,TA = –40°C to +125°C
OPA145ID Package Only
250
350
RL = 2 kΩ,TA = –40°C to +125°C
OPA145IDGK and DBV Packages,
OPA2145
ISC
Short-circuit current
Capacitive load drive
±20
mA
Ω
CLOAD
See Figure 6-27
150
f = 1 MHz, IO = 0 mA (See Figure
6-26)
RO
Open-loop output impedance
POWER SUPPLY
IO = 0 mA
445
475
590
655
IQ
Quiescent current (per amplifier)
TA = 0°C to +85°C
TA = –40°C to +125°C
µA
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6.7 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 6-1. Table of Graphs
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
Figure 6-1
Offset Voltage Drift Distribution From –40°C to +125°C
Input Bias Current Production Distribution
Input Offset Current Production Distribution
Offset Voltage vs Temperature
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Power Supply
Figure 6-6
Figure 6-7
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Figure 6-8
Figure 6-9
Input Bias Current vs Common-Mode Voltage
Input Bias Current and Offset vs Temperature
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency
Figure 6-10
Figure 6-11
Figure 6-12
Figure 6-13
Figure 6-14
Figure 6-15
Figure 6-16
Figure 6-17
Figure 6-18
Figure 6-19
Figure 6-20
Figure 6-21
Figure 6-22
Figure 6-23
Figure 6-24, Figure 6-25
Figure 6-26
Figure 6-27
Figure 6-28
Figure 6-29
Figure 6-30
Figure 6-31, Figure 6-32
Figure 6-33, Figure 6-34
Figure 6-35
Figure 6-36
Figure 6-37
Figure 6-38
CMRR vs Temperature
PSRR vs Temperature
0.1-Hz to 10-Hz Voltage Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open-Loop Gain vs Temperature (10-kΩ)
Open-Loop Gain vs Temperature (2-kΩ)
DC Open-Loop Gain vs Output Voltage Swing Relative to Supply
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
No Phase Reversal
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (10-mV Step)
Large-Signal Step Response (10-V Step)
Settling Time
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
15
10
5
20
15
10
5
0
0
Input Offset Voltage Drift (µV/°C)
Offset Voltage (µV)
C002
C001
Figure 6-1. Offset Voltage Production Distribution
Figure 6-2. Offset Voltage Drift Distribution From –40°C to
+125°C
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
Input Bias Current (pA)
Input Offset Current (pA)
C013
C013
Figure 6-3. Input Bias Current Production Distribution
Figure 6-4. Input Offset Current Production Distribution
400
300
150
125
100
75
200
50
100
25
0
0
œ25
œ50
œ75
œ100
œ100
œ200
œ300
œ400
VCM = 14.5 V
VCM = œ 18.1 V
œ125
œ150
0
25
50
75
100 125 150
0
5
10
15
20
œ75 œ50 œ25
œ20
œ15
œ10
œ5
Temperature (°C)
Input Common-mode Voltage (V)
C001
C003
5 Typical Units
Figure 6-5. Offset Voltage vs Temperature
5 Typical Units
Figure 6-6. Offset Voltage vs Common-Mode Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
150
120
100
80
180
Open-loop Gain
150
120
90
100
50
60
0
40
60
VS
=
2.25 V
Phase
œ50
œ100
œ150
20
30
0
0
œ20
-30
10M
0
9
18
Supply Voltage (V)
27
36
1
10
100
1k
10k
100k
1M
C001
Frequency (Hz)
C001
5 Typical Units
Figure 6-7. Offset Voltage vs Supply Voltage
Figure 6-8. Open-Loop Gain and Phase vs Frequency
3
60
40
20
0
G = +1
G= -1
G= +10
1.5
0
-1.5
-3
-20
100
1k
10k
100k
1M
10M
0
5
10
15
20
œ20
œ15
œ10
œ5
Frequency (Hz)
Input Common-mode Voltage (V)
C004
C001
Figure 6-9. Closed-Loop Gain vs Frequency
Figure 6-10. Input Bias Current vs Common-Mode Voltage
10000
1V
1000
100
10
Sourcing
100mV
IBN
IBP
-40°C
25°C
Sinking
10mV
1mV
IOS
85°C
125°C
1
1
10
100
0
25
50
75
100 125 150
œ75 œ50 œ25
Output Current (mA)
Temperature (°C)
C019
C001
Figure 6-12. Output Voltage Swing vs Output Current (Maximum
Supply)
Figure 6-11. Input Bias Current and Offset vs Temperature
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
160
150
140
130
120
110
100
0.01
160
140
120
100
80
CMRR
+PSRR
œPSRR
0.1
60
1
40
20
0
10
1
10
100
1k
10k
100k
1M
10M
0
25
50
75 100 125 150
œ75 œ50 œ25
Frequency (Hz)
Temperature (°C)
C004
C001
Figure 6-13. CMRR and PSRR vs Frequency
Figure 6-14. CMRR vs Temperature
180
160
140
120
100
0.001
0.01
0.1
1
10
Time (1 s/div)
0
25
50
75 100 125 150
œ75 œ50 œ25
Temperature (°C)
C001
C017
Figure 6-15. PSRR vs Temperature
Figure 6-16. 0.1-Hz to 10-Hz Voltage Noise
100
10
1
0.1
-60
G = -1, 2k-ꢀ Load
G = -1, 600-ꢀ Load
G = -1, 10k-ꢀ Load
0.01
-80
G = +1, 2k-ꢀ Load
G = +1, 600-ꢀ Load
G = +1, 10k-ꢀ Load
0.001
-100
-120
-140
0.0001
0.00001
0.1
1
10
100
1k
10k
100k
20
200
2k
20k
Frequency (Hz)
Frequency (Hz)
C002
C004
VOUT = 3.5
VRMS, BW = 90 kHz
Figure 6-17. Input Voltage Noise Spectral Density vs Frequency
Figure 6-18. THD+N Ratio vs Frequency
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
500
0.1
0.01
-60
400
300
200
100
0
-80
0.001
-100
-120
-140
VS
=
2.25 V
G = -1, 600-ꢀ Load
G = -1, 2k-ꢀ Load
G = -1, 10k-ꢀ Load
G = +1, 600-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 10k-ꢀ Load
0.0001
0.00001
0.001
0.01
0.1
1
10
0
9
18
Supply Voltage (V)
27
36
Output Amplitude (VRMS
)
C004
C001
f = 1 kHz
BW = 90 kHz
Figure 6-19. THD+N vs Output Amplitude
Figure 6-20. Quiescent Current vs Supply Voltage
1000
900
800
700
600
500
400
300
200
100
0
140
130
120
110
100
0.1
VS
=
18 V
2.25 V
75
VS
=
18 V
1
VS
=
2.25 V
VS
=
10
0
25
50
75
100 125 150
0
25
50
100
125
œ75 œ50 œ25
œ50
œ25
Temperature (°C)
Temperature (°C)
C001
C001
10-kΩ Load
Figure 6-22. Open-Loop Gain vs Temperature
Figure 6-21. Quiescent Current vs Temperature
140
130
120
110
100
0.1
140
120
RL = 10 kΩ
100
80
60
40
20
0
VS
=
18 V
1
–40°C
–5°C
RL = 2 kΩ
25°C
85°C
125°C
VS
=
2.25 V
75
10
0.01
0.1
Output Voltage Swing from Rail (V)
1
0
25
50
100
125
œ50
œ25
Temperature (°C)
C001
C001
VS = ±18 V
2-kΩ Load
Figure 6-23. Open-Loop Gain vs Temperature)
Figure 6-24. Open-Loop Gain vs Output Voltage Swing to
Supply
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1k
140
120
RL = 10 kΩ
100
80
100
–40°C
60
–5°C
40
25°C
RL = 2 kΩ
85°C
20
125°C
0
10
0.01
0.1
1
10
100
1k
10k
100k
1M
10M
100M
Output Voltage Swing from Rail (V)
Frequency (Hz)
C001
C021
VS = ±2.25 V
Figure 6-25. Open-Loop Gain vs Output Voltage Swing to
Supply
Figure 6-26. Open-Loop Output Impedance vs Frequency
50
VIN
45
G = +1
40
35
30
25
20
15
VOUT
10
G = –1
5
0
Time (45 ms/div)
10
100
1000
Capacitive Load (pF)
C004
C017
10-mV Step
Figure 6-27. Small-Signal Overshoot vs Capacitive Load
Figure 6-28. No Phase Reversal
VOUT
VIN
VIN
VOUT
Time (100 ns/div)
Time (100 ns/div)
C017
C017
Figure 6-29. Positive Overload Recovery
Figure 6-30. Negative Overload Recovery
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Output
Input
Output
Input
Time (200 ns/div)
Time (200 ns/div)
C017
C017
G = +1
10-mV Step
G = –1
Figure 6-31. Small-Signal Step Response (10-mV Step)
Figure 6-32. Small-Signal Step Response
Output
Input
Output
Input
Time (2 µs/div)
Time (2 µs/div)
C017
C017
10-V Step
G = –1
10-V Step
G = +1
Figure 6-33. Large-Signal Step Response
Figure 6-34. Large-Signal Step Response
40
30
20
10
0
12-bit Settling = ±2.44 mV
t = 0
Rising Edge
Sinking
Sourcing
Falling Edge
Time (250 ns/div)
0
25
50
75
100
125
150
œ75
œ50
œ25
Temperature (°C)
C001
C017
12-bit settling on 10-V step = ±2.44 mV
Figure 6-35. Settling Time (10-V Step)
Figure 6-36. Short-Circuit Current vs Temperature
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
40
35
30
25
20
15
10
5
140
120
100
80
Maximum output voltage without
slew-rate induced distortion.
VS
=
18V
60
40
VS
=
2.25V
20
0
0
1k
10k
100k
1M
10M
10M
100M
Frequency (Hz)
1000M
Frequency (Hz)
C001
C004
PRF = –10 dBm
Figure 6-38. EMIRR vs Frequency
Figure 6-37. Maximum Output Voltage Amplitude vs Frequency
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7 Detailed Description
7.1 Overview
The OPA145 and OPA2145 (OPAx145) operational amplifiers are part of a family of low-power JFET input
amplifiers that feature superior drift performance and low input bias current. The rail-to-rail output swing and
input range that includes V– allow designers to use the low-noise characteristics of JFET amplifier while also
interfacing to modern, single-supply, precision, analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs). The OPAx145 achieve 5.5-MHz gain-bandwidth product and 20-V/μs slew rate and consume
only 445 µA (typical) of quiescent current, making these devices an excellent choice for low-power applications.
These devices operate on a single 4.5-V to 36-V supply or dual ±2.25-V to ±18-V supplies.
The OPAx145 are fully specified from –40°C to +125°C for use in the most challenging environments. The
single-channel OPA145 is available in 5-pin SOT-23, 8-pin SOIC, and 8-pin VSSOP packages. The dual-channel
OPA2145 is available in 8-pin SOIC and 8-pin VSSOP packages.
Section 7.2 shows the simplified diagram of the OPAx145.
7.2 Functional Block Diagram
V+
Pre-Output Driver
OUT
IN–
IN+
V–
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7.3 Feature Description
7.3.1 Capacitive Load and Stability
The dynamic characteristics of the OPAx145 have been optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50 Ω,
for example) in series with the output.
Figure 6-27 illustrates the effects on small-signal overshoot for several capacitive loads. Also, see Feedback
Plots Define Op Amp AC Performance, available for download from the TI website, for details of analysis
techniques and application circuits.
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7.3.2 Output Current Limit
The output current of the OPAx145 is limited by internal circuitry to +20 mA (sinking) and –20 mA (sourcing) to
protect the device if the output is accidentally shorted. This short-circuit current depends on temperature, as
shown in Figure 6-36.
7.3.3 Noise Performance
Figure 7-1 shows the total circuit noise for varying source impedances with the operational amplifier in a unity-
gain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPAx145 and OPAx211 are shown with total circuit noise calculated. The op amp contributes both a voltage
noise component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest
noise op amp for a given application depends on the source impedance. For low source impedance, current
noise is negligible, and voltage noise generally dominates. The OPAx145 has both low voltage noise and
extremely low current noise because of the FET input of the op amp. As a result, the current noise contribution of
the OPAx145 is negligible for any practical source impedance, which makes it the better choice for applications
with high source impedance.
10µ
OPA211
1µ
100n
OPA145
10n
1n
RS = 3.8 kΩ
Resistor Noise
0.1n
1
10
100
1k
10k
100k
1M
10M
Source Resistance, RS (Ω)
C003
NOTE: For a source resistance, RS, greater than 3.8 kΩ, the OPAx145 is a lower-noise option compared to the OPA211, as shown in
Figure 7-1.
Figure 7-1. Noise Performance of the OPAx145 and OPA211 in Unity-Gain Buffer Configuration
Equation 1 can be used to calculate the total noise at the output of the amplifier. A plot can be created using this
equation to quickly compare the noise performance of two different amplifiers when used with different source
resistances, as is shown in Figure 7-1.
2
2
EO = en + (in ìRS )2 + 4kTRS
(1)
where:
•
•
•
•
•
en = voltage noise
In = current noise
RS = source impedance
k = Boltzmann's constant = 1.38 × 10–23 J/K
T = temperature in kelvins (K)
For more details on calculating noise, see Section 7.3.4.
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7.3.4 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 7-1. The source impedance is usually fixed; consequently, select the
op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 7-2 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPAx145 means that the current noise contribution can be neglected.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
(A) Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
42
41 „ 42
2
2
2
2
¨
: ;
1
:
;
:
;
:
;
>
?
84/5
'
1
= l1 + p „ A5 + A0 + kA4 2 o + E0 „ 45 + lE0 „ d
hp
æ4
1
41
41 + 42
GND
œ
EO
8
: ;
2
A = 4 „ G$ „ 6(-) „ 45
d
h
¥
Thermal noise of RS
+
5
*V
¾
RS
41 „ 42
8
: ;
3
A4
= ¨4 „ G$ „ 6(-) „ d
2
h
d
h
Thermal noise of R1 || R2
æ4
1
41 + 42
*V
¾
+
,
h
VS
Source
GND
G$ = 1.38065 „ 10F23
: ;
4
d
œ
Boltzmann Constant
-
Temperature in kelvins
: ;
>
?
-
5
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
:
;
42
45 + 41 „ 42
'
1
= l1 +
p „ A0 2 + kA4
o2 + FE0 „ H
+4 æ4
5 2
IG
¨
: ;
6
:
;
>
84/5
?
1
45 + 41
45 + 41 + 42
RS
œ
EO
:
;
45 + 41 „ 42
8
+
: ;
7
¨
4 „ G$ „ 6(-) „ H
A4
=
I
d
h
Thermal noise of (R1 + RS) || R2
+4 æ4
5
1
2
45 + 41 + 42
*V
¾
+
VS
œ
,
GND
G$ = 1.38065 „ 10F23
d
h
: ;
8
Boltzmann Constant
Source
GND
-
: ;
9
>
?
6(-) = 237.15 + 6(°%)
-
Temperature in kelvins
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Where: eN is the voltage noise of the amplifier. For the OPAx145 operational amplifier, eN = 7 nV/√Hz at 1 kHz.
Where: iN is the current noise of the amplifier. For the OPAx145 operational amplifier, iN = 0.8 fA/√Hz at 1 kHz.
NOTE: For additional resources on noise calculations visit TI's Precision Labs Series.
Figure 7-2. Noise Calculation in Gain Configurations
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7.3.5 Phase-Reversal Protection
The OPAx145 has internal phase-reversal protection. Many FET-input and bipolar-input op amps exhibit a phase
reversal when the input is driven beyond its linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input circuitry of the OPAx145 prevents phase reversal
with excessive common-mode voltage; instead, the output limits into the appropriate rail (see Figure 6-28).
7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful.
See Figure 7-3 for an illustration of the ESD circuits contained in the OPAx145 (indicated by the dashed line
area). The ESD protection circuitry involves several current-steering diodes connected from the input and output
pins and routed back to the internal power-supply lines, where the power supply is connected to an absorption
device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal
circuit operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent
pulse that discharges through a semiconductor device. The ESD protection circuits are designed to provide a
current path around the operational amplifier core to prevent the amplifier from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device has a trigger, or threshold voltage, that is greater than the normal operating voltage of the
OPAx145 but less than the device breakdown voltage level. After this threshold is exceeded, the absorption
device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit, such as the one Figure 7-3 shows, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occurs, there is a risk that some of the internal ESD protection circuits may be biased on, and
conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption
device.
Figure 7-3 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher V IN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier,
and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise
to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. The answer depends on the supply characteristic while at 0 V, or at a
level less than the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source through the current steering diodes. This state is
not a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance,
then the current through the steering diodes can become quite high. The current level depends on the ability of
the input source to deliver current, and any resistance in the input path.
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If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be
added to the supply pins as shown in Figure 7-3. The Zener voltage must be selected so that the diode does not
turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
TVS(2)
RF
+VS
+V
RI
ESD Current-
-In
Steering Diodes
(3)
Out
Op Amp
Core
RS
+In
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
-V
-VS
TVS(2)
(1) VIN = +VS + 500 mV.
(2) TVS: +VS(max) > VTVSBR (Min) > +VS
(3) Suggested value approximately 1 kΩ.
Figure 7-3. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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7.3.7 EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a
higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this
section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
•
•
•
Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance.
EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input
terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier result in adverse effects, as
the amplifier would not have sufficient loop gain to correct for signals with spectral content outside the amplifier
bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected dc offsets,
transient voltages, or other unknown behavior. Be sure to properly shield and isolate sensitive analog nodes
from noisy radio signals and digital clocks and interfaces. Figure 7-5 shows the effect of conducted EMI to the
power supplies on the input offset voltage of OPAx145.
The EMIRR IN+ of the OPAx145 is plotted versus frequency as shown in Figure 7-4. The OPAx145 unity-gain
bandwidth is 5.5 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the
op amp bandwidth.See EMI Rejection Ratio of Operational Amplifiers, available for download from www.ti.com.
50
140
Vœ Supply
120
0
100
œ50
80
V+ Supply
œ100
œ150
œ200
60
40
20
0
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
1000M
Frequency (Hz)
C006
C004
Figure 7-5. OPAx145 EMI-Induced Input Offset
Voltage (Power Supplies)
Figure 7-4. OPAx145 EMIRR IN+
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Table 7-1 lists the EMIRR IN+ values for the OPAx145 at particular frequencies commonly encountered in real-
world applications. Applications listed in Table 7-1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 7-1. OPAx145 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
54 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
68 dB
86 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
107 dB
100 dB
105 dB
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
7.3.8 EMIRR +IN Test Configuration
Figure 7-6 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the op amp
noninverting input terminal using a transmission line. The op amp is configured in a unity-gain buffer topology
with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance
mismatch at the op amp input causes a voltage reflection; however, this effect is characterized and accounted
for when determining the EMIRR IN+. The resulting DC offset voltage is sampled and measured by the
multimeter. The LPF isolates the multimeter from residual RF signals that may interfere with multimeter
accuracy.
Ambient temperature: 25˘C
+VS
œ
50 ꢀ
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
-VS
Sample /
Averaging
Digital Multimeter
Not shown: 0.1 µF and 10 µF
supply decoupling
Frequency Sweep: 201 pt. Log
Figure 7-6. EMIRR +IN Test Configuration
7.4 Device Functional Modes
The OPAx145 has a single functional mode and is operational when the power-supply voltage is greater than 4.5
V (±2.25 V). The maximum power supply voltage for the OPAx145 is 36 V (±18 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx145 are unity-gain stable operational amplifiers with low noise, low input-bias current, and low input-
offset voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors placed
close to the device pins. In most cases, 0.1-μF capacitors are adequate. Designers can easily use the rail-to-rail
output swing and input range that includes V– to take advantage of the low-noise characteristics of JFET
amplifiers while also interfacing to modern, single-supply, precision data converters.
8.2 Typical Application
R4
2.94 kꢀ
C5
1 nF
œ
R1
590 ꢀ
R3
499 ꢀ
Output
+
Input
OPA145
C2
39 nF
Copyright © 2017, Texas Instruments Incorporated
Figure 8-1. 25-kHz Low-Pass Filter
8.2.1 Design Requirements
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPAx145 are designed to construct high-speed, high-precision active filters. Figure 8-1 shows a second-
order, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
•
•
•
Gain = 5 V/V (inverting gain)
Low-pass cutoff frequency = 25 kHz
Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 8-1. Use Equation 2
to calculate the voltage transfer function.
-1 R1R3C2C5
Output
Input
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
2
1
3
4
3 4 2 5
(2)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 3:
R4
Gain =
R1
1
fC
=
1 R R C C
(
3 4 2 5
)
2p
(3)
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For systems which have different filter parameters or require specific system optimization, such as minimizing
the system noise, an alternative device may be desired. A list of recommended alternatives can be found in
Table 8-1.
Table 8-1. Alternative Devices
FEATURES
PRODUCT
OPA140
OPA209
OPA827
OPA376
OPA191
Low-power, 10-MHz FET input industrial op amp
2.2-nV/√ Hz, low-power, 36-V op amp in SOT-23 package
Low-noise, high-precision, 22-MHz, 4-nV/√ Hz JFET-input op amp
Low-noise, low IQ precision CMOS op amp
Low-power, precision, CMOS, rail-to-rail input/output, low-offset, low-bias op amp
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer lets designers create optimized
filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows designers
to design, optimize, and simulate complete multistage active filter solutions within minutes.
8.2.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 8-2. OPAx145 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
8.3 System Examples
8.3.1 16-Bit, 100-kSPS, Fully Differential Transimpedance Imaging and Measurement
The OPAx145 are used in a differential transimpedance (I-V) measurement application capable of driving the
ADS8867, a 16-bit, microPower, truly-differential ADC, at its maximum conversion rate of 100 kSPS with an
acquisition time of 1200 ns and conversion time of 8800 ns. The first stage supports a forward bandwidth of
493.5 kHz with 100 kΩ of transimpedance gain, enabling the photodiode to fully charge and settle to ±38 µV
(±1/2 LSB on 5-V ADC reference voltage) within the conversion time of the ADC. The differential nature of the
system provides several advantages such as double the transimpedance gain compared to a single-ended
system, improved signal-to-noise ratio, easy interfacing to high-precision, fully-differential ADCs, and additional
protection against inductively-coupled noise and interference. Additionally, capacitively-coupled common-mode
transients can be minimized using low-impedance termination resistors RTERM1 and RTERM2
.
The second stage provides the reverse bandwidth required for settling to 16-bit accuracy after the internal
sampling capacitor of the successive-approximation-register (SAR) ADC is connected to the second stage. The
two OPAx145 amplifiers in the second stage are configured as buffers for maximum closed-loop bandwidth, and
their stability is optimized using R3, C3 and R4, C4 by creating a snubber that reduces the open-loop output
impedance (see Figure 6-26). C5 and C6 are provided as a charge reservoir for the internal sampling capacitor
of the ADC, and R5 and R6 are tuned to optimize the phase margin of the second stage to drive the output
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capacitance. This two-stage approach enables compatibility with a wide selection of high output-impedance
sensors while still maintaining 16-bit settling performance. Furthermore, the first stage can be designed with
sufficient phase margin to drive twisted-pair transmission lines in remote measurement systems. Proper design
of the transmission line reduces the interference of other signals over long distances. Figure 8-4 shows the
settling performance of the system described previously and in Figure 8-3 — the settling time during the
acquisition cycle is shown for settling successfully to 0 µA from 5 µs to 6.2 µs. At 6.3 µs, the photodiode current
is changed to 5 µA (full-scale) and settles during the conversion cycle of the ADC (6.2 µs to 15 µs), and is then
acquired successfully from 15 µs to 16.2 µs.
R1
50 kꢀ
GND
C1
9 pF
R5
22 ꢁ
+10V
RTERM1
1 kꢁ
+10V
œ
œ
R3
180 ꢁ
OPA145
+
2.7 V to 3.6 V
AVDD
2.5 V to 5 V
OPA145
+
C3 C5
432p 200p
GND
GND
REF
GND
GND
AINP
² • VREF
GND
ADS8867
AINN
C4 C6
432p 200p
Twisted Pair
+
GND
OPA145
R4
180 ꢁ
+
œ
OPA145
Fast Silicon
PIN Photodiode
R6
22 ꢁ
œ
+10V
+10V
RTERM2
1 kꢁ
5 ꢀA
3.8 pF
2.5 mW/cm2
Photovoltaic Mode
C2
9 pF
Copyright © 2017, Texas Instruments Incorporated
GND
R2
50 kꢀ
Figure 8-3. 16-bit, 100-kSPS, Fully Differential Transimpedance Schematic
500
Acquisition Stop
+1/2-LSB
Error Signal
400
300
200
100
0
-100
-200
-300
-400
-500
-1/2-LSB
Acquisition Start
0
5
10
15
20
Time (µs)
C005
Figure 8-4. 16-bit, 100-kSPS, Fully Differential Transimpedance Settling Performance
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9 Power Supply Recommendations
The OPAx145 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –
40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in Section 6.7.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Section 6.1
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Section 10.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information, see The
PCB is a component of op amp design technical brief.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
•
•
•
Place the external components as close as possible to the device. As illustrated in Figure 10-1, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
For best performance, TI recommends cleaning the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
+V
R3
C3
C4
1
2
3
4
NC
œIN
+IN
Vœ
NC
V+
8
7
6
5
R1
R2
INœ
œ
IN+
OUT
OUT
NC
+
-V
C1
C2
R4
Place bypass
capacitors as close to
IC as possible
Use ground pours for
shielding the input
signal pairs
GND
C3
C4
R3
INœ
+V
1
NC
œIN
+IN
Vœ
NC
V+
8
R1
2
3
4
7
6
5
OUT
NC
OUT
R2
IN+
GND
R4
-V
Place components
close to device and to
each other to reduce
parasitic errors
C1
C2
Use a low-
ESR,ceramic bypass
capacitor
Copyright © 2017, Texas Instruments Incorporated
Figure 10-1. Operational Amplifier Board Layout for Difference Amplifier Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ SImulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI software provides all the conventional
dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 WEBENCH Filter Designer Tool
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
11.1.1.3 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
•
•
•
•
•
Texas Instruments, The PCB is a component of op amp design
Texas Instruments, OPA140, OPA2140, OPA4140 EMI Immunity Performance
Texas Instruments, Compensate Transimpedance Amplifiers Intuitively
Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis
Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis
Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters
Texas Instruments, Op Amp Performance Analysis
Texas Instruments, Single-Supply Operation of Operational Amplifiers
Texas Instruments, Tuning in Amplifiers
Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes
Texas Instruments, Feedback Plots Define Op Amp AC Performance
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA145ID
ACTIVE
SOIC
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
D
8
5
5
8
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA145
OPA145IDBVR
OPA145IDBVT
OPA145IDGKR
OPA145IDGKT
OPA145IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DGK
DGK
D
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
1IB2
Green (RoHS
& no Sb/Br)
1IB2
2500
250
Green (RoHS
& no Sb/Br)
NIPDAUAG
NIPDAUAG
NIPDAU
1I4Q
Green (RoHS
& no Sb/Br)
1I4Q
2500
Green (RoHS
& no Sb/Br)
OPA145
OPA2145IDGKR
OPA2145IDGKT
POPA2145ID
PREVIEW
PREVIEW
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
75
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
POPA2145IDGKT
ACTIVE
VSSOP
DGK
8
250
TBD
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2020
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA145IDBVR
OPA145IDBVT
OPA145IDGKR
OPA145IDGKT
OPA145IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
8
8
8
3000
250
180.0
180.0
330.0
330.0
330.0
8.4
8.4
3.23
3.23
5.3
3.17
3.17
3.4
1.37
1.37
1.4
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
2500
250
12.4
12.4
12.4
12.0
12.0
12.0
5.3
3.4
1.4
2500
6.4
5.2
2.1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA145IDBVR
OPA145IDBVT
OPA145IDGKR
OPA145IDGKT
OPA145IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
8
8
8
3000
250
213.0
213.0
366.0
366.0
853.0
191.0
191.0
364.0
364.0
449.0
35.0
35.0
50.0
50.0
35.0
2500
250
2500
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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