OPA1622IDRCR [TI]
具有高性能、低 THD+N 和双极输入的 SoundPlus™ 音频运算放大器 | DRC | 10 | -40 to 125;
| 型号： | OPA1622IDRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有高性能、低 THD+N 和双极输入的 SoundPlus™ 音频运算放大器 | DRC | 10 | -40 to 125 放大器 运算放大器 |
| 文件： | 总37页 (文件大小：2688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA1622
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
Burr-Brown Audio
OPA1622 SoundPlus™ 高保真、双极输入音频运算放大器
1 特性
3 说明
1
•
高保真音质
超低噪声：1kHz 时为 2.8nV/√Hz
OPA1622 是一款双通道、双极输入、 SoundPlus™音
频运算放大器。该器件在 1kHz 频率下拥有
•
•
2.8nV/√Hz 的超低噪声密度和 –119.2dB 的超低
THD+N，同时还能够以 100mW 的输出功率驱动一个
32Ω 负载。OPA1622 具有极高的交流电源抑制比
(PSRR) 和共模抑制比 (CMRR) 技术规格，可消除来
自电源的噪声，因此非常适合便携音频 应用。此外，
该器件还具有 +145mA/–130mA 的高输出驱动能力。
超低总谐波失真 + 噪声 (THD+N)：
–119dB（142mW/通道至 32Ω/通道）
•
宽增益带宽产品：
32MHz (G = +1000)
•
•
•
•
•
高转换率：10V/μs
高容性负载驱动能力：> 600pF
高开环增益：136dB（600Ω 负载）
低静态电流：每通道 2.6mA
OPA1622 支持 ±2V 到 ±18V 的宽电源电压范围，每通
道电源电流仅为 2.6mA。OPA1622 运算放大器的单位
增益稳定，在宽范围负载条件下可保持出色的动态性
能。OPA1622 具有关断模式，允许放大器从正常运行
状态切换至一个待机电流典型值低于 5µA 的状态。此
关断特性专门用于消除进入或退出关断模式时的喀哒和
噼啪噪声。
可降低喀哒和噼啪噪声的低功耗关断模式：每通道
5μA
•
•
•
短路保护
宽电源电压范围：±2V 至 ±18V
采用小型超薄小外形尺寸无引线 (VSON)-10 封装
2 应用
OPA1622 内部 采用 独特布局，即使在过驱或过载条
件下也可在通道间实现最低串扰和零交互。此器件的额
定温度介于 –40°C 至 +125°C 之间。
•
•
•
•
•
•
高保真 (HiFi) 耳机驱动器
专业音频设备
模数混合控制台
器件信息(1)
音频测试和测量
器件型号
OPA1622
封装
VSON (10)
封装尺寸（标称值）
高端 蓝光碟™播放器
高端影音 (A/V) 接收器
3.00mm × 3.00mm
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
OPA1622 应用于高保真耳机驱动器
快速傅立叶变换 (FFT)：1kHz、32Ω 负载、50mW
C1 470 pF
0
œ20
œ40
œ60
œ80
R1
R2
ROUT
VAC
499 ꢀ
768 ꢀ
-
Headphone
Output
+
VDC
OPA1622
VAC
œ100
R3
ROUT
-133.6 dBc (Second Harmonic)
œ120
œ140
œ160
œ180
499 ꢀ
R4
768 ꢀ
C2
470 pF
Audio DAC
Copyright © 2016, Texas Instruments Incorporated
0
5k
10k
15k
20k
Frequency (Hz)
C005
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS727
OPA1622
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 22
Power Supply Recommendations...................... 26
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: ........................................ 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 器件和文档支持 ..................................................... 27
11.1 器件支持................................................................ 27
11.2 文档支持................................................................ 27
11.3 社区资源................................................................ 27
11.4 商标....................................................................... 27
11.5 静电放电警告......................................................... 28
11.6 Glossary................................................................ 28
12 机械、封装和可订购信息....................................... 28
7
4 修订历史记录
Changes from Revision A (November 2015) to Revision B
Page
•
•
•
增加了 TI 参考设计 ................................................................................................................................................................ 1
Changed pin number of V+ pin in Pin Functions table .......................................................................................................... 3
Changed format of Supply voltage parameter in Recommended Operating Conditions table .............................................. 4
Changes from Original (November 2015) to Revision A
Page
•
已从“产品预览”更改为“量产数据” ............................................................................................................................................ 1
2
Copyright © 2015–2016, Texas Instruments Incorporated
OPA1622
www.ti.com.cn
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
+INA
V+
1
2
3
4
5
10 œINA
œ
œ
9
8
7
6
OUTA
EN
GND
Vœ
OUTB
œINB
+INB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
EN
NO.
3
—
I
Connect to ground
8
Shutdown (logic low), enable (logic high)
Noninverting input, channel A
Inverting input, channel A
Noninverting input, channel B
Inverting input, channel B
Output, channel A
+IN A
–IN A
+IN B
–IN B
OUT A
OUT B
V+
1
I
10
5
I
I
6
I
9
O
O
—
—
7
Output, channel B
2
Positive (highest) power supply
Negative (lowest) power supply
V–
4
Exposed thermal die pad on underside; connect thermal die pad to V–.
Soldering the thermal pad improves heat dissipation and provides specified performance.
Thermal pad
Copyright © 2015–2016, Texas Instruments Incorporated
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OPA1622
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Supply voltage, VS = (V+) – (V–)
Voltage
Input voltage (signal inputs, enable, ground)
Input differential voltage
Input current (all pins except power-supply pins)
Output short-circuit(2)
(V–) – 0.5
(V+) + 0.5
±0.5
±10
mA
Current
Continuous
125
Operating, TA
–55
–65
Temperature
Junction, TJ
200
°C
Storage, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4
NOM
MAX
36
UNIT
Single-supply
Dual-supply
Supply voltage, (V+) – (V–)
Specified temperature
V
±2
±18
125
–40
°C
6.4 Thermal Information
OPA1622
THERMAL METRIC(1)
DRC (SON)
10 PINS
47.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
58.1
22.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
22.2
RθJC(bot)
4.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015–2016, Texas Instruments Incorporated
OPA1622
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ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
6.5 Electrical Characteristics:
at TA = +25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.000024%
–132
G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 2 kΩ,
80-kHz measurement bandwidth
dB
dB
dB
dB
dB
0.000025%
–132
G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 600 Ω,
80-kHz measurement bandwidth
0.000071%
–123
Total harmonic distortion +
noise
G = 1, f = 1 kHz, POUT = 10 mW, RL = 128 Ω,
80-kHz measurement bandwidth
THD+N
0.000149%
–116
G = 1, f = 1 kHz, POUT = 10 mW, RL = 32 Ω,
80-kHz measurement bandwidth
0.000214%
–113
G = 1, f = 1 kHz, POUT = 10 mW, RL = 16 Ω,
80-kHz measurement bandwidth
SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz),
G = 1, VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement
bandwidth
0.000018%
–135
dB
dB
IMD
Intermodulation distortion
0.00005%
–126
CCIF twin-tone (19 kHz and 20 kHz), G = 1,
VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement bandwidth
FREQUENCY RESPONSE
G = 1000
G = 1
32
8
GBW
SR
Gain-bandwidth product
MHz
Slew rate
G = –1
10
V/μs
MHz
ns
Full-power bandwidth(1)
Overload recovery time
Channel separation (dual)
VO = 1 VP
G = –10
f = 1 kHz
1.6
300
140
dB
NOISE
Input voltage noise
f = 20 Hz to 20 kHz
f = 10 Hz
2.1
10
4
μVPP
en
Input voltage noise density(2)
f = 100 Hz
f = 1 kHz
nV/√Hz
2.8
2.5
0.8
f = 10 Hz
In
Input current noise density
pA/√Hz
f = 1 kHz
OFFSET VOLTAGE
±100
±500
±600
2.5
VOS
Input offset voltage
μV
TA = –40°C to +125°C
TA = –40°C to +125°C
dVOS/dT Input offset voltage drift(2)
0.5
0.1
μV/°C
μV/V
PSRR
Power-supply rejection ratio
3
INPUT BIAS CURRENT
1.2
2.0
2.2
IB
Input bias current
Input offset current
μA
TA = –40°C to +125°C(2)
TA = –40°C to +125°C(2)
±10
±50
±80
IOS
nA
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio
(V–) + 1.5
110
(V+) – 1
V
CMRR
(V–) + 1.5 V ≤ VCM ≤ (V+) – 1 V, TA = –40°C to +125°C
127
dB
(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
(2) Specified by design and characterization.
Copyright © 2015–2016, Texas Instruments Incorporated
5
OPA1622
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
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Electrical Characteristics: (continued)
at TA = +25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT IMPEDANCE
Differential
60k || 0.8
Ω || pF
Ω || pF
Common-mode
500M || 0.9
OPEN-LOOP GAIN
(V–) + 2 V ≤ VO ≤ (V+) – 2 V, RL = 32 Ω, VS = ± 5 V
114
120
120
136
AOL
Open-loop voltage gain
dB
(V–) + 1.5 V ≤ VO ≤ (V+) – 1.5 V, RL = 600 Ω, VS = ± 18 V
OUTPUT
No load
Positive rail
800
900
800
900
RL = 600 Ω
VO
Voltage output swing from rail
mV
No load
Negative rail
RL = 600 Ω
IOUT
ZO
Output current
See 图 38 and 图 39
See 图 40
mA
Ω
Open-loop output impedance
Short-circuit current
Capacitive load drive
ISC
VS = ±18 V
+145 / –130
See 图 24
mA
pF
CLOAD
ENABLE PIN
0.82
0.78
VIH
Logic high threshold
V
TA = –40°C to +125°C
0.95
VIL
IIH
Logic low threshold
Input current
V
TA = –40°C to +125°C
VEN = 1.8 V
0.65
1.5
2.6
5
μA
POWER SUPPLY
3.3
4.2
10
VEN = 2.0 V, IOUT = 0 A
TA = –40°C to +125°C(2)
mA
Quiescent current
(per channel)
IQ
VEN = 0 V, IOUT = 0 A
μA
6
版权 © 2015–2016, Texas Instruments Incorporated
OPA1622
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ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
6.6 Typical Characteristics
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
20
18
16
14
12
10
8
20
15
10
5
6
4
2
0
0
Offset Voltage Drift (µV/°C)
Offset Voltage (µV)
C013
C013
9250 channels
50 channels
图 1. Input Offset Voltage Histogram
图 2. Input Offset Voltage Drift Histogram
300
œ60
œ62
œ64
œ66
œ68
œ70
œ72
œ74
œ76
œ78
œ80
VCM = -16.5 V
200
100
VCM = 17 V
0
œ100
œ200
œ300
0
10
20
œ20
œ10
0
25
50
75
100 125 150
œ75 œ50 œ25
VCM (V)
Temperature (°C)
C001
C001
4 typical units
图 4. Input Offset Voltage vs Common-Mode Voltage
图 3. Input Offset Voltage vs Temperature
100
10
1
10
1
+31
-31
0.1
1
10
100
1k
10k 100k
1M
10M 100M
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
Frequency (Hz)
C307
C306
图 5. Input Voltage Noise Spectral Density vs Frequency
图 6. Input Current Noise Spectral Density vs Frequency
版权 © 2015–2016, Texas Instruments Incorporated
7
OPA1622
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
1000
100
10
Source Resistor Noise Contribution
Total Noise
1
Voltage Noise Contribution
Current Noise Contribution
0.1
Time (2 s/div)
10
100
1k
10k
100k
1M
Source Resistance (ꢀ)
C017
C302
图 7. 0.1-Hz to 10-Hz Noise
图 8. Voltage Noise vs Source Resistance
18
140
225
16
120
100
80
VS = ±15V
14
12
10
8
180
135
90
60
40
6
VS = ±5V
20
4
VS = ±2V
0
2
0
œ20
45
10k
100k
1M
10M
1
10
100
1k
10k 100k 1M 10M 100M
Frequency (Hz)
Frequency (Hz)
C303
C005
图 9. Maximum Output Voltage vs Frequency
图 10. Open-Loop Gain and Phase vs Frequency
5.0
4.0
5.0
4.0
3.0
2.0
1.0
0.0
VS = ±2 V
VS = ±2 V
3.0
2.0
1.0
0.0
VS = ±18 V
VS = ±18 V
œ1.0
œ2.0
œ3.0
œ4.0
œ5.0
œ1.0
œ2.0
œ3.0
œ4.0
œ5.0
0
25
50
75
100 125 150
0
25
50
75
100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
600-Ω load
图 11. Open-Loop Gain vs Temperature
2-kΩ load
图 12. Open-Loop Gain vs Temperature
8
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ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
40
0.01
0.001
-80
G = +10
G = -1, 600-ꢀ Load
G = -1
G = +1
G = -1, 2k-ꢀ Load
G = -1, 10k-ꢀ Load
G = +1, 600-ꢀ Load
20
0
-100
G = +1, 2k-ꢀ Load
G = +1, 10k-ꢀ Load
0.0001
0.00001
-120
-20
-140
20k
100
1k
10k
100k
1M
10M
20
200
2k
Frequency (Hz)
Frequency (Hz)
C004
C004
C004
C004
3.5 VRMS, 80-kHz measurement bandwidth
图 13. Closed-Loop Gain vs Frequency
图 14. THD+N Ratio vs Frequency
0.1
-60
0.1
0.01
-60
G = -1, 128-ꢀ Load
G = -1, 32-ꢀ Load
G = -1, 16-ꢀ Load
G = +1, 128-ꢀ Load
G = +1, 32-ꢀ Load
G = +1, 16-ꢀ Load
0.01
-80
-80
Inverting
0.001
0.0001
-100
-120
-140
0.001
-100
-120
-140
0.0001
0.00001
Noninverting
2k-ꢀ Load
600-ꢀ Load
0.00001
20
200
2k
20k
0.01
0.1
1
10
Frequency (Hz)
Output Amplitude (VRMS
)
C004
10 mW, 80-kHz measurement bandwidth
1 kHz, 80-kHz measurement bandwidth
图 15. THD+N Ratio vs Frequency
图 16. THD+N Ratio vs Output Amplitude
0.1
0.01
-60
0.1
-60
2k-ꢀ Load
32-ꢀ Load
-80
0.01
0.001
-80
Inverting
SMPTE
0.001
-100
-120
-140
-100
-120
-140
Noninverting
0.0001
0.00001
0.0001
0.00001
128-ꢀ Load
32-ꢀ Load
16-ꢀ Load
CCIF
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Amplitude (VRMS
)
Output Amplitude (VRMS
)
C004
1 kHz, 80-kHz measurement bandwidth
90-kHz measurement bandwidth
图 18. Intermodulation Distortion vs Output Amplitude
图 17. THD+N Ratio vs Output Amplitude
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
160
140
120
100
80
-80
No Load
PSRR+
32-ꢀ Load
600-ꢀ Load
PSRR-
-100
-120
-140
-160
60
40
20
0
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C004
C115
图 19. Channel Separation vs Frequency
图 20. PSRR vs Frequency (Referred to Input)
5
4
140
120
100
80
3
2
1
0
60
-1
-2
-3
-4
-5
40
20
0
0
25
50
75
100 125 150
œ75 œ50 œ25
1
10
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
C001
C004
图 21. PSRR vs Temperature
图 22. CMRR vs Frequency (Referred to Input)
1
0.8
0.6
0.4
0.2
0
90
80
70
60
50
40
30
20
10
0
VS = ±2 V, (Vœ) +1.5 ≤ VCM ≤ (V+) œ 1 V
G = +1
G = -1
VS = ±18 V, (Vœ) +1.5 ≤ VCM ≤ (V+) œ 1V
-0.2
-0.4
-0.6
-0.8
-1
0
200
400
600
800
1000
0
25
50
75
100 125 150
œ75 œ50 œ25
Capacitive Load (pF)
Temperature (°C)
C308
C001
图 24. Phase Margin vs Capacitive Load
图 23. CMRR vs Temperature
10
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ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
Time (2.5 ꢀs/div)
Time (2.5 ꢀs/div)
C017
C017
G = 1, 10 mV
G = 1, 10 V
图 25. Small-Signal Step Response
图 26. Large-Signal Step Response
VOUT
VIN
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
C017
C017
G = –10
G = –10
图 27. Negative Overload Recovery
图 28. Positive Overload Recovery
1.5
1.4
1.3
1.2
1.1
1
VOUT
VIN
IB-
IB+
0.9
Time (500 ms/div)
0
25
50
75
100
125
œ50
œ25
Temperature (ºC)
C017
C304
图 29. No Phase Reversal
图 30. IB vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
5
1.5
1.4
1.3
1.2
1.1
1
4
3
2
1
0
25
50
75
100
125
œ50
-1.5
0
œ25
-20
-10
0
10
20
Temperature (ºC)
Common-Mode Voltage (V)
C305
C001
VS = ±18 V
图 31. IOS vs Temperature
图 32. IB vs Common-Mode Voltage
5
4.5
4
1.3
1.25
1.2
3.5
3
VS = ±18 V
VS = ±2 V
2.5
2
1.5
1
1.15
1.1
0.5
0
0
25
50
75
100 125 150
œ75 œ50 œ25
-1
-0.5
0
0.5
1
1.5
Temperature (°C)
Common-Mode Voltage (V)
C001
C002
VS = ±2 V
图 34. Quiescent Current vs Temperature
图 33. IB vs Common-Mode Voltage
5
4
3
2
1
0
3
2.5
2
125ºC
85ºC
1.5
1
25ºC
-40ºC
0.5
0
0.5
1
1.5
2
2
4
6
8
10
12
14
16
18
20
Enable Voltage (V)
Supply Voltage (V)
C002
C001
图 36. Quiescent Current vs Enable Voltage
图 35. Quiescent Current vs Supply Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
18
16
14
12
10
8
200
180
ISC, Source
160
140
120
6
ISC, Sink
125°C
25°C
100
4
80
60
85°C
œ40°C
2
0
0
20
40
60
80 100 120 140 160 180 200
0
25
50
75
100 125 150
œ75 œ50 œ25
IO (mA)
C001
Temperature (°C)
C001
图 38. Positive Output Voltage vs Output Current
图 37. Short-Circuit Current vs Temperature
0
-2
100
10
1
125°C
25°C
-4
85°C
-6
œ40°C
-8
-10
-12
-14
-16
-18
0
20
40
60
80 100 120 140 160 180 200
1
10
100
1k
10k 100k 1M
10M 100M
IO (mA)
C001
Frequency (Hz)
C001
图 39. Negative Output Voltage vs Output Current
图 40. Open-Loop Output Impedance vs Frequency
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7 Detailed Description
7.1 Overview
The OPA1622, dual, bipolar-input, audio operational amplifier uses a unique internal topology to deliver high
output current with extremely low distortion while consuming minimal supply current. A single gain stage
architecture, combining a high-gain transconductance input stage and a unity gain output stage, allows the
OPA1622 to achieve an open-loop gain of 136 dB, even with 600-Ω loads.
The output stage of the OPA1622 is designed specifically to source and sink large amounts of current without
degrading amplifier linearity. High-order distortion harmonics, produced by output stage crossover distortion, are
greatly reduced with this design. The OPA1622 output stage also provides exceptionally low open-loop output
impedance that improves stability with capacitive loads and is protected against short-circuit events.
A separate enable circuit maintains control of the input and output stage when the amplifier is placed into its
shutdown mode and limits transients at the amplifier output when transitioning to and from this state. The enable
circuit features logic levels referenced to the amplifier ground pin. This configuration simplifies the interface
between the amplifier and the ground-referenced GPIO pins of microcontrollers. The addition of a ground pin to
the amplifier provides several additional benefits. For example, the compensation capacitor between the input
and output stages of the OPA1622 is referenced to the ground pin, greatly improving PSRR.
7.2 Functional Block Diagram
Short-Circuit Current Limit
-
+
High-Gain Input Stage
+IN
+
OUT
-
-IN
High-Current Output
Stage
Compensation
Capacitor
GND
EN
-
+
Enable Circuitry
Copyright © 2016, Texas Instruments Incorporated
图 41. OPA1622 Simplified Schematic
7.3 Feature Description
7.3.1 Power Dissipation
The OPA1622 is capable of high output current with power-supply voltages up to ±18 V. Internal power
dissipation increases when operating at high supply voltages. The power dissipated in the op amp (POPA) is
calculated using 公式 1:
VOUT
POPA = V - V
ìI
= V - V
ì
(
)
(
)
+
OUT
OUT
+
OUT
RL
(1)
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Feature Description (接下页)
In order to calculate the worst-case power dissipation in the op amp, the ac and dc cases must be considered
separately.
In the case of constant output current (dc) to a resistive load, the maximum power dissipation in the op amp
occurs when the output voltage is half the positive supply voltage. This calculation assumes that the op amp is
sourcing current from the positive supply to a grounded load. If the op amp sinks current from a grounded load,
modify 公式 2 to include the negative supply voltage instead of the positive.
2
V
V+
≈
’
+
POPA(MAX _DC) = POPA ∆
=
÷
◊
2
4RL
«
(2)
The maximum power dissipation in the op amp for a sinusoidal output current (ac) to a resistive load occurs
when the peak output voltage is 2/π times the supply voltage, given symmetrical supply voltages:
2
2V
2∂ V+
≈
’
+
POPA(MAX _ AC) = POPA ∆
=
÷
◊
p2 ∂RL
p
«
(3)
The dominant pathway for the OPA1622 to dissipate heat is through the package thermal pad and pins to the
PCB. Copper leadframe construction used in the OPA1622 improves heat dissipation compared to conventional
materials. PCB layout greatly affects thermal performance. Connect the OPA1622 package thermal pad to a
copper pour at the most negative supply potential. This copper pour can be connected to a larger copper plane
within the PCB using vias to improve power dissipation. 图 42 shows an analogous thermal circuit that can be
used for approximating the junction temperature of the OPA1622. The power dissipated in the OPA1622 is
represented by current source PD; the ambient temperature is represented by voltage source 25ºC; and the
junction-to-board and board-to-ambient thermal resistances are represented by resistors θJB and θBA
,
respectively. The board-to-ambient thermal resistance is unique to every application. The sum of θJB and θBA is
the junction-to-ambient thermal resistance of the system. The value for junction-to-ambient thermal resistance
reported in the Thermal Information table is determined using the JEDEC standard test PCB. The voltages in the
analogous thermal circuit at the points TJ and TPCB represent the OPA1622 junction and PCB temperatures,
respectively.
TJ
ꢀJB (22.0ºC/W)
TPCB
PD
ꢀBA
25ºC
图 42. Approximate Thermal System Model of the OPA1622 Soldered to a PCB.
7.3.2 Thermal Shutdown
If the junction temperature of the OPA1622 exceeds 175ºC, a thermal shutdown circuit disables the amplifier in
order to protect the device from damage. The amplifier is automatically re-enabled after the junction temperature
falls below approximately 160ºC. If the condition that caused excessive power dissipation has not been removed,
the amplifier oscillates between a shutdown and enabled state until the output fault is corrected.
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Feature Description (接下页)
7.3.3 Enable Pin
The enable pin (EN) of the OPA1622 is used to toggle the amplifier enabled and disabled states. The logic levels
defining these two states are: VEN ≤ 0.78 V (shutdown mode), and VEN ≥ 0.82 V (enabled). These threshold
levels are referenced to the device ground pin. The enable pin can be driven by a GPIO pin from the system
controller, discrete logic gates, or can be connected directly to the V+ supply. Do not leave the enable pin
floating because the amplifier is prevented from being enabled. Likewise, do not place GPIO pins used to control
the enable pin in a high-impedance state because this placement also prevents the amplifier from being enabled.
A small current flows into the enable pin when a voltage is applied. Using the simplified internal schematic shown
in 图 43, use 公式 4 to estimate the enable pin current:
VEN - 0.7 V
700 kꢀ
IEN
=
(4)
As illustrated in 图 43, the enable pin is protected by diodes to the amplifier power supplies. Do not connect the
enable pin to voltages outside the limits defined in the Specifications section.
To
Amplifier
VCC
500 kꢀ
EN
VEE
VCC
200 kꢀ
GND
VEE
图 43. Enable Pin Simplified Internal Schematic
7.3.4 Ground Pin
The inclusion of a ground pin in the OPA1622 architecture allows the internal enable circuitry to be referenced to
the system ground, eliminating the need for level shifting circuitry in many applications. The internal amplifier
compensation capacitors are also referenced to this pin, greatly increasing the ac PSRR. For highest
performance, connect the ground pin to a low-impedance reference point with minimal noise present. As shown
in 图 43, the ground pin is protected by ESD diodes to the amplifier power supplies. Do not connect the ground
pin to voltages outside the limits defined in the Specifications section.
7.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. 图 44 shows the ESD circuits contained in the OPA1622. The ESD protection circuitry involves several
current-steering diodes connected from the input and output pins and routed back to the internal power-supply
lines, where they meet at an absorption device internal to the operational amplifier. This protection circuitry is
intended to remain inactive during normal circuit operation.
16
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Feature Description (接下页)
V+
Power Supply
ESD Cell
EN
+IN
+
œ
OUT
œ IN
GND
Vœ
图 44. Equivalent Internal ESD Circuitry
7.3.6 Input Protection
The input pins of the OPA1622 are protected from excessive differential voltage with back-to-back diodes, as 图
45 shows. In most circuit applications, the input protection circuitry has no consequence. However, in low-gain
or G = +1 circuits, fast-ramping input signals can forward bias these diodes because the output of the amplifier
cannot respond quickly enough to the input ramp. If the input signal is fast enough to create this forward-bias
condition, the input signal current must be limited to 10 mA or less. If the input signal current is not inherently
limited, use an input series resistor (RI) or a feedback resistor (RF) to limit the signal input current. This input
series resistor degrades the low-noise performance of the OPA1622 and is examined in the Noise Performance
section. 图 45 shows an example configuration when both current-limiting input and feedback resistors are used.
RF
–
Device
Output
RI
+
Input
图 45. Pulsed Operation
7.4 Device Functional Modes
The OPA1622 has two operating modes determined by the voltage between the enable and ground pins: a
shutdown mode (VEN ≤ 0.78V) and an enabled mode (VEN ≥ 0.82V). The measured datasheet performance
parameters specified in the Typical Characteristics and Specifications sections are given with the amplifier in the
enabled mode, unless otherwise noted.
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Device Functional Modes (接下页)
7.4.1 Shutdown Mode
When the enable pin voltage is below the logic low threshold, the OPA1622 enters a shutdown mode with
minimal power consumption. In this state the output transistors of the amplifier are not powered on. However, do
not consider the amplifier output to be high-impedance. Applying signals to the output of the OPA1622 while the
device is in the shutdown mode can parasitically power the output stage, causing the OPA1622 output to draw
current.
The OPA1622 enable circuitry limits transients at the output when transitioning into or out of shutdown mode.
However, small output transients do still accompany this transition, as illustrated in 图 46 and 图 47. Note that in
both figures the time scale is 1 µs per division, indicating that the output transients are extremely brief in nature,
and therefore not likely to be audible in headphone applications.
Enable (2 V/div)
Enable (2 V/div)
Output (20 mV/div)
Output (20 mV/div)
Time (1 ꢀs/div)
Time (1 ꢀs/div)
C001
C002
图 46. OPA1622 Output Voltage When Enable Pin
Transitions High (32-Ω Load Connected)
图 47. OPA1622 Output Voltage When Enable Pin
Transitions Low (32-Ω Load Connected)
7.4.2 Output Transients During Power Up and Power Down
To minimize the possibility of output transients that might produce an audible click or pop, ramp the supply
voltages for the OPA1622 symmetrically to their nominal values. Asymmetrical supply ramping can cause output
transients during power up that can be audible in headphone applications. If possible, hold the enable pin low
while the power supplies are ramping up or down. If the enable pin is not being independently controlled (for
example, by a GPIO pin), use a voltage divider to hold the enable pin voltage below the logic-high threshold until
the power supplies reach the specified minimum voltage, as shown in 图 48.
VCC
22.1 kꢀ
To enable
pin on IC
10.7 kꢀ
图 48. Voltage Divider Used to Hold Enable Low at Power-Up or Power-Down
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low noise and distortion of the OPA1622 make the device well suited for a variety of applications in
professional and consumer audio products. However, these same performance metrics also make the OPA1622
useful for industrial, test-and-measurement, and data-acquisition applications. The example shown here is only
one possible application where the OPA1622 provides exceptional performance.
8.1.1 Noise Performance
图 49 shows the total circuit noise for varying source impedances with the op amp in a unity-gain configuration
(no feedback resistor network, and therefore no additional noise contributions).
The OPA1622 is shown with total circuit noise calculated. The op amp contributes both a voltage noise
component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current, and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest
noise op amp for a given application depends on the source impedance. For low source impedance, current
noise is negligible, and voltage noise generally dominates. The low voltage and current noise of the OPA1622 op
amp make the device an excellent choice for use in applications where the source impedance is less than 10 kΩ.
8.1.1.1 Noise Calculations
The equations in 图 50 show the calculation of the total circuit noise using these parameters:
•
•
•
•
•
en = voltage noise
In = current noise
RS = source impedance
k = Boltzmann’s constant = 1.38 × 10–23 J/K
T = temperature in kelvins (K)
8.1.1.2 Application Curve
1000
100
10
Source Resistor Noise Contribution
Total Noise
1
Voltage Noise Contribution
Current Noise Contribution
0.1
10
100
1k
10k
100k
1M
Source Resistance (ꢀ)
C302
图 49. Noise Performance of the OPA1622 in a Unity-Gain Buffer Configuration
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Application Information (接下页)
8.1.1.3 Basic Noise Calculations
Designing low-noise op amp circuits requires careful consideration of a variety of possible noise contributors,
such as noise from the signal source, noise generated in the op amp, and noise from the feedback network
resistors. The total noise of the circuit is the root sum squared combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. 图 49 plots this function. The source impedance is usually fixed; consequently, select the op amp and
the feedback resistors to minimize the respective contributions to the total noise.
图 50 shows both inverting and noninverting op amp circuit configurations with gain. In circuit configurations with
gain, the feedback network resistors also contribute noise.
The current noise of the op amp reacts with the feedback resistors to create additional noise components.
Choose feedback resistor values that make these noise sources negligible. The equations for total noise are
shown for both configurations.
Noise in Noninverting Gain Configuration
Noise at the output:
R2
é
ù2
ú
2 é
1+
ù2
ú
R2
R2
2
)
2
2
2
2
EO = 1+
en + e12 + e2 + i R
+ eS + i R
(
(
)
ê
ê
n
2
n
S
R1 û
R1 û
R1
ë
ë
EO
where
é
ù
ú
R2
· eS
=
4kTRS ´ 1+
= thermal noise of R
S
RS
ê
R1 û
ë
é
ê
ë
ù
ú
R2
VS
· e1 = 4kTR ´
= thermal noise of R
1
1
R1 û
· e2 = 4kTR2 = thermal noise of R2
Noise in Inverting Gain Configuration
Noise at the output:
R2
é
ù2
ú
R2
2
)
2
2
2
2
EO = 1+
en + e12 + e2 + i R
+ eS
(
ê
n
2
R1 + RS û
R1
ë
EO
RS
where
é
ê
ë
ù
ú
R2
· eS
=
4kTRS
´
= thermal noise of R
VS
S
R1 + RS û
é
ê
ë
ù
ú
R2
· e1 = 4kTR ´
= thermal noise of R
1
1
R1 + RS û
· e2 = 4kTR2 = thermal noise of R2
For the OPA1622 at 1 kHz, en = 2.8 nV/√Hz and in = 800 fA/√Hz.
图 50. Noise Calculation in Gain Configurations
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Application Information (接下页)
8.1.2 Total Harmonic Distortion Measurements
The distortion produced by OPA1622 is below the measurement limit of many commercially-available distortion
analyzers. However, a special test circuit, as shown in 图 51, can be used to extend the measurement
capabilities.
R1
R2
Device
Under Test
R2
R1
Gain(Signal) = 1+
œ
R3
+
R2
R1 || R3
Gain(Distortion) = 1+
Generator
Output
Analyzer
Input
Load
Audio
Analyzer
图 51. Distortion Test Circuit
Consider op amp distortion an internal error source that is referred to the input. 图 51 shows a circuit that causes
the op amp distortion to be 101 times (approximately 40 dB) greater than that normally produced by the op amp.
The addition of R3 to the otherwise standard noninverting amplifier configuration alters the feedback factor or
noise gain of the circuit. The closed-loop gain is unchanged, but the feedback available for error correction is
reduced by a factor of 101, thus extending the resolution by 101. Note that the input signal and load applied to
the op amp are the same as with conventional feedback without R3. Keep the value of R3 small to minimize its
effect on the distortion measurements.
Verify the validity of this technique by duplicating measurements at high gain or high frequency where the
distortion is within the measurement capability of the test equipment.
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8.2 Typical Application
The low distortion and high output-current capabilities of the OPA1622 make this device an excellent choice for
headphone-amplifier applications in portable or studio applications. These applications typically employ an audio
digital-to-analog converter (DAC) and a separate headphone amplifier circuit connected to the DAC output. High-
performance audio DACs can have an output signal that is either a varying current or voltage. Voltage output
configurations require less external circuitry, and therefore have advantages in cost, power consumption, and
solution size. However, these configurations can offer slightly lower performance than current output
configurations. Differential outputs are standard on both types of DACs. Differential outputs double the output
signal levels that can be delivered on a single, low-voltage supply, and also allow for even-harmonics common to
both outputs to be cancelled by external circuitry. A simplified representation of a voltage-output audio DAC is
shown in 图 52. Two ac voltage sources (VAC) deliver the output signal to the complementary outputs through
their associated output impedances (ROUT). Both output signals have a dc component as well, represented by dc
voltage source VDC. The headphone amplifier circuit connected to the output of an audio DAC must convert the
differential output into a single-ended signal and be capable of producing signals of sufficient amplitude at the
headphones to achieve reasonable listening levels.
C1 470 pF
R1
R2
ROUT
VAC
499 ꢀ
768 ꢀ
-
Headphone
Output
+
VDC
OPA1622
VAC
R3
ROUT
499 ꢀ
R4
768 ꢀ
C2
470 pF
Audio DAC
Copyright © 2016, Texas Instruments Incorporated
图 52. OPA1622 Used as a Headphone Amplifier for a Voltage-Output Audio DAC
8.2.1 Design Requirements
•
•
•
•
±5-V power supplies
150-mW output power (32-Ω load)
< –115-dB THD+N at maximum output (32-Ω load)
< 0.01-dB magnitude deviation (20 Hz to 20 kHz)
8.2.2 Detailed Design Procedure
图 52 shows a schematic of a headphone amplifier circuit for voltage output DACs. An op amp is configured as a
difference amplifier that converts the differential output voltage to single-ended. The values of the resistors in the
difference amplifier circuit are determined by the specifications of the DAC, such as output voltage and output
impedance, as well as the maximum output voltage desired at the headphone output. The op amp chosen must
be capable of delivering the necessary current to the headphones and remain stable into typical headphone
loads that can have capacitances as high as 400 pF. The following design process uses a hypothetical DAC with
common values of output voltage and impedance for the design process. The specifications of the DAC are
shown in 表 1:
表 1. Audio DAC Specifications Used for the Design Process
PARAMETER
VALUE
2 VRMS
200 Ω
Maximum differential output voltage
Output impedance (ROUT
)
Output dc offset
1.65 V
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The gain of the difference amplifier in 图 52 is determined by the resistor values, and includes the output
impedance of the DAC. For R2 = R4 and R1 = R3, the output voltage of the headphone amplifier circuit is shown
in 公式 5:
R2
VOUT = V
DAC R1 + ROUT
(5)
The output voltage required for headphones depends on the headphone impedance, as well as the headphone
efficiency (η), a measure of the sound pressure level (SPL, measured in dB) for a certain input power level
(typically given at 1 mW). The headphone SPL at other power levels is calculated using 公式 6:
P
≈
’
IN
SPL(dB) = h +10log
∆
«
÷
◊
1 mW
where
•
•
η = efficiency
PIN = input power to the headphones
(6)
图 53 shows the input power required to produce certain SPLs for different headphone efficiencies. Typically,
over-the-ear style headphones have lower efficiencies than in-ear types with 95 dB/mW being a common value.
150
140
130
120
110
100
90-dB/mW
90
80
70
60
95-dB/mW
100-dB/mW
105-dB/mW
110-dB/mW
115-dB/mW
0.01
0.1
1
10
100
1000
Input Power (mW)
C001
图 53. Sound Pressure Level vs Input Power for Headphones of Various Efficiencies
In-ear headphones can have efficiencies of 115 dB/mW or greater, and therefore have much lower power
requirements. The output power goal for this design is 150 mW; sufficient power to produce extremely loud
sound pressure levels in a wide range of headphones. A 32-Ω headphone impedance is used for this
requirement because 32 Ω is a very common value in headphones for portable applications. 公式 7 shows the
voltage required for 32-Ω headphones:
VO = PìR = 150 mW ì32 ꢀ = 2.191 VRMS
(7)
A tradeoff exists when selecting resistor values for this design. First, high resistor values contribute additional
noise to the circuit, degrading the audio performance. However, extremely low resistor values draw excessive
current from the DAC, increasing distortion. A value of 499 Ω is used for resistors R1 and R3 as a reasonable
compromise between these two considerations. Resistor R2 and R4 can then be calculated as shown in 公式 8:
R2
R2
VOUT = V
ç1.095 =
ç R2 = 765.4 ꢀ ç 768 ꢀ
DAC R1 +ROUT
499 ꢀ + 200 ꢀ
(8)
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In order to accommodate higher impedance headphones, increase the gain of the circuit to produce greater
output voltages. However, increasing the gain also increases the noise of the circuit and limits the dynamic range
of the circuit into lower impedance headphones. For this reason, some designers choose to select the
headphone amplifier gain by using a switch.
Capacitors C1 and C2 limit the bandwidth of the circuit to prevent the unnecessary amplification of interfering
signals. The maximum value of these capacitors is determined by the limitations on frequency response
magnitude deviation detailed in the Design Requirements section. C1 and C2 combine with resistors R2 and R4 to
form a pole, as shown in 公式 9:
1
fP =
2p(R2,R4 )(C1,C2 )
(9)
Calculate the minimum pole frequency allowable to meet the magnitude deviation requirements using 公式 10:
f
20 kHz
fP í
í
í 416.6 kHz
2
2
1
1
≈
’
≈
’
-1
-1
∆
«
÷
∆
«
÷
◊
G
0.999
◊
where
•
G represents the gain in decimal for a –0.01-dB deviation at 20 kHz.
(10)
Use 公式 11 to calculate the upper limit for the value of C1 and C2 in order to meet the goal for minimal
magnitude deviation at 20 kHz.
1
1
C1,C2 Ç
Ç
Ç 497 pF ç 470 pF
2p(R2,R4)F
2p(768 ꢀ)(416.6 kHz)
P
(11)
8.2.3 Application Curves
The circuit described in 图 52 is constructed using 0.1% tolerance thin-film resistors (0603 package) and surface-
mount film capacitors. The performance of the circuit is measured using a high-performance audio analyzer and
is displayed in 图 54 through 图 59. The maximum output power for three common headphone impedances is
shown in 表 2
表 2. Maximum Output Power and THD+N Before Clipping for Common Headphone Impedances
LOAD IMPEDANCE
MAXIMUM OUTPUT POWER BEFORE CLIPPING
(mW)
THD+N AT MAXIMUM OUTPUT POWER
(dB)
(Ω)
16
32
95
–114.2
–118.7
–119.4
150
11.3
600
The maximum output power delivered to low impedance headphone loads (16 Ω and 32 Ω) is limited by the
output current capabilities of the amplifier. For the 600-Ω case, the maximum power delivered is limited by the
output voltage capability of the amplifier and depends greatly on the power-supply voltages used. 图 55 shows
the maximum output voltage achievable for each load before the onset of clipping (±5-V supplies), indicated by a
sharp increase in distortion.
As more current is delivered by the output transistors of an amplifier, additional distortion is produced. At low
frequencies, this distortion is corrected by the feedback loop of the amplifier. However, as the loop gain of the
amplifier begins to decline at high frequencies, the overall distortion begins to climb. The unique output stage
design of the OPA1622 greatly reduces the additional distortion at high frequency when delivering large currents,
as shown in 图 56. High-ordered harmonics (above the 2nd and 3rd) are also kept to a minimal level at high
output powers, as shown in 图 57 through 图 59.
24
版权 © 2015–2016, Texas Instruments Incorporated
OPA1622
www.ti.com.cn
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
3
0.1
0.01
-60
2.5
2
-80
0.001
-100
16-ꢀ Load
1.5
0.0001
0.00001
-120
32-ꢀ Load
600-ꢀ Load
1
-140
10
100
1k
10k
0.01
0.1
1
Frequency (Hz)
Output Voltage (VRMS)
C001
C002
22.4-kHz measurement bandwidth
图 54. Headphone Amplifier Transfer Function
图 55. THD+N vs Output Voltage for Headphone Loads
0
œ20
œ40
œ60
œ80
0.01
-80
16-ꢀ Load
600-ꢀ Load
32-ꢀ Load
0.001
-100
œ100
-134 dBc (Second Harmonic)
œ120
œ140
œ160
œ180
0.0001
-120
10
100
1k
10k
0
5k
10k
15k
20k
Frequency (Hz)
Frequency (Hz)
C003
C004
90-kHz measurement bandwidth, 1-VRMS output
图 56. THD+N vs Frequency for Headphone Loads
1 kHz, 32-Ω load, 10 mW
图 57. Output Spectrum
0
0
œ20
œ20
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ180
œ100
œ120
œ140
œ160
œ180
-126 dBc (Third Harmonic)
-133.6 dBc (Second Harmonic)
0
5k
10k
15k
20k
0
5k
10k
15k
20k
Frequency (Hz)
Frequency (Hz)
C005
C006
1 kHz, 32-Ω load, 50 mW
1 kHz, 32-Ω load, 150 mW
图 58. Output Spectrum
图 59. Output Spectrum
版权 © 2015–2016, Texas Instruments Incorporated
25
OPA1622
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
www.ti.com.cn
9 Power Supply Recommendations
The OPA1622 op amp operates from ±2-V to ±18-V supplies, while maintaining excellent performance. However,
some applications do not require equal positive and negative output voltage swing. With the OPA1622, power-
supply voltages do not need to be equal. For example, the positive supply could be set to +25 V with the
negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. Key parameters are
specified over the temperature range of TA = –40°C to +125°C. Parameters that vary with operating voltage or
temperature are shown in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications. The bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry, because noise can propagate into analog circuitry through the power
pins of the circuit as a whole and the op amp specifically.
•
•
Connect the IC ground pin to a low-impedance, low-noise, system reference point, such as an analog ground.
Place the external components as close to the device as possible. As shown in 图 60, keep feedback
resistors close to the inverting input to minimize parasitic capacitance and the feedback loop area.
•
•
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
For proper amplifier function, connect the package thermal pad to the most negative supply voltage (VEE).
10.2 Layout Example
IN-
IN+
Place feedback
resistors to minimize
feedback loop area
GND
VEE
Place bypass
capacitors as close to
IC as possible
+IN
V+
-IN
OUT
EN
œ
A
OUT
IC ground pin
connected to low-
impedance, low-noise
system ground
ENABLE
GND
B
Vœ
OUT
-IN
OUT
œ
+IN
VEE
Copper pour for thermal
pad must be connected to
negative supply (VEE)
GND
IN+
IN-
图 60. Operational Amplifier Board Layout for a Difference Amplifier Configuration
26
版权 © 2015–2016, Texas Instruments Incorporated
OPA1622
www.ti.com.cn
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 TI 高精度设计
欲获取 TI 高精度设计，请访问 http://www.ti.com.cn/ww/analog/precision-designs/。TI 高精度设计是由 TI 公司高
精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选择、仿真、完整印刷电路板
(PCB) 电路原理图和布局布线、物料清单以及性能测量结果。
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
《反馈曲线图定义运算放大器交流性能》，SBOA015
《电路板布局布线技巧》，SLOA089
《用于电压输出音频 DAC 的耳机放大器参考设计》，TIDUAW1
《面向耳机应用的差分放大器稳定化 处理》,SLYT630
《降低 CMOS 模拟开关的失真度》，SLYT612
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
SoundPlus, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
蓝光碟 is a trademark of Blu-ray Disc Association.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
版权 © 2015–2016, Texas Instruments Incorporated
27
OPA1622
ZHCSEE5B –NOVEMBER 2015–REVISED MAY 2016
www.ti.com.cn
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
28
版权 © 2015–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1622IDRCR
OPA1622IDRCT
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
O1622
O1622
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1622IDRCR
OPA1622IDRCT
VSON
VSON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA1622IDRCR
OPA1622IDRCT
VSON
VSON
DRC
DRC
10
10
3000
250
335.0
182.0
335.0
182.0
25.0
20.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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