OPA1656ID [TI]
SoundPlus™ 超低噪声和失真、Burr-Brown™ 音频运算放大器 | D | 8 | -40 to 125;
| 型号： | OPA1656ID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SoundPlus™ 超低噪声和失真、Burr-Brown™ 音频运算放大器 | D | 8 | -40 to 125 放大器 光电二极管 运算放大器 |
| 文件： | 总43页 (文件大小：3326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA1655, OPA1656
ZHCSJH0C –MARCH 2019 –REVISED SEPTEMBER 2022
OPA165x 超低噪声、低失真、FET 输入、
Burr-Brown™ 音频运算放大器
1 特性
3 说明
• 超低噪声：
OPA1655 和 OPA1656 (OPA165x) 是 Burr-Brown™ 运
算放大器，专为音频和工业应用而设计，在这些应用中
保持信号保真度至关重要。FET 输入架构可达到
2.9nV/√Hz 的低电压噪声密度和 6fA/√Hz 电流噪声密
度，能够在各种电路内将噪声降到超低。OPA165x 采
用高带宽和高开环增益设计，在 20kHz 时的失真率低
至 0.000035% (–129dB) 并且可提高全音频带宽内的
音频信号保真。该器件还具有出色的输出电流驱动功
能，在 2kΩ 负载下提供 250mV 电源电压范围内的轨
到轨输出摆幅，并且可以提供100mA 输出电流。
– 电压噪声：10 kHz 时为2.9nV/√Hz
– 电流噪声：1 kHz 时为6 fA/√Hz
• 低失真：
– 1kHz 时为0.000029% (–131dB)
– 20kHz 时为0.000035% (–129dB)
• 高开环增益：150dB
• 高输出电流：100mA
• 低输入偏置电流：10pA
• 压摆率：24 V/μs
• 增益带宽积：53 MHz
• 轨到轨输出
• 宽电源电压范围：
±2.25V 至±18V 或4.5V 至36V
• 静态电流：每通道3.9 mA
OPA165x 可在 ±2.25V 至 ±18V 的超宽电源电压范围
内工作，也可在仅为 3.9mA 的电源电流（4.5V 至
36V）下工作，从而满足许多类型的音频产品的电源限
制。它的额定工作温度范围为–40°C 至+125°C。
器件信息
封装(1)
2 应用
器件型号
OPA1655
OPA1656
通道
D (SOIC, 8)
• 专业麦克风和无线系统
• 专业音频混合器/控制平面
• 吉他放大器和其他乐器放大器
• A/V 接收器
• 书架立体声音响系统
• 专业音频放大器
单通道
双通道
DBV（SOT-23，5)
D（SOIC，8）
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• DJ 设备
• 转盘
• 特殊功能模块
Pad
100
10
1
Bass
–
Input
+
–
+
Output
OPA165x
OPA165x
Treble
主动Baxandall 音调控制
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
C020
超低输入电压噪声
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS901
OPA1655, OPA1656
ZHCSJH0C –MARCH 2019 –REVISED SEPTEMBER 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................19
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Applications.................................................. 21
8.3 Power Supply Recommendations.............................28
8.4 Layout....................................................................... 28
9 Device and Documentation Support............................30
9.1 Device Support......................................................... 30
9.2 Documentation Support............................................ 31
9.3 接收文档更新通知..................................................... 31
9.4 支持资源....................................................................31
9.5 Trademarks...............................................................31
9.6 Electrostatic Discharge Caution................................31
9.7 术语表....................................................................... 31
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information: OPA1655.................................. 5
6.5 Thermal Information: OPA1656.................................. 5
6.6 Electrical Characteristics.............................................6
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................16
Information.................................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (December 2021) to Revision C (September 2022)
Page
• 将OPA1655 DBV (SOT-23, 5) 封装从“预发布”更改为“量产数据”（正在供货）........................................1
Changes from Revision A (July 2019) to Revision B (December 2021)
Page
• 添加了OPA1655 器件的量产数据（正在供货）和相关内容...............................................................................1
Changes from Revision * (March 2019) to Revision A (July 2019)
Page
• 将器件状态从“预告信息（预发布）”更改为“量产数据（正在供货）”.........................................................1
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5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
NC
–IN
+IN
V–
1
2
3
4
8
7
6
5
NC
V+
–
+IN
4
œIN
+
OUT
NC
Not to scale
图5-2. OPA1655 DBV (5-Pin SOT-23) Package,
Not to scale
Top View
图5-1. OPA1655 D (8-Pin SOIC) Package, Top View
Pin Functions: OPA1655
PIN
NO.
DBV (SOT-23)
TYPE
DESCRIPTION
NAME
D (SOIC)
2
3
6
4
7
4
3
1
2
5
Input
Input
Inverting input
–IN
+IN
OUT
V–
V+
Noninverting input
Output
Power
Power
Output
Negative (lowest) power supply
Positive (highest) power supply
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
图5-3. OPA1656 D (8-Pin SOIC) Package, Top View
Pin Functions: OPA1656
PIN
TYPE
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
Input
Input
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
3
6
Input
5
Input
1
Output
Output
Power
Power
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Supply voltage, VS = (V+) –(V–)
Voltage
Input
(V+) + 0.5
10
V
(V–) –0.5
–10
Input (all pins except power-supply pins)
mA
Current
Output short-circuit(2)
Continuous
Operating, TA
125
150
150
°C
°C
°C
–55
Temperature
Junction, TJ
Storage, Tstg
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to VS / 2 (groundinsymmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allowssafemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allowssafemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single supply
Dual supply
VS
TA
Supply voltage
±2.25
–40
±18
125
Operating temperature
°C
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6.4 Thermal Information: OPA1655
OPA1655
THERMAL METRIC(1)
D (SOIC)
8 PINS
120.9
58.9
DBV (SOT23)
5 PINS
143.4
68.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
65.1
39.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13.5
20.4
ψJT
64.2
39.0
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA1656
OPA1656
THERMAL METRIC(1)
D (SOIC)
8 PINS
119.9
51.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
65.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.0
ψJT
64.2
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
at TA = 25°C, VS = ±18 V, RL = 2 kΩ, and VCM = VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.000029%
–131
G = 1, RL = 600 Ω, VO = 3.5 VRMS, f = 1 kHz,
80-kHz measurement bandwidth
dB
dB
dB
dB
dB
dB
0.0001%
–120
G = 1, RL = 600 Ω, VO = 3.5 VRMS, f = 20 kHz,
80-kHz measurement bandwidth
THD+N
Total harmonic distortion + noise
0.000029%
–131
G = 1, RL = 2 kΩ, VO = 3.5 VRMS, f = 1 kHz,
80-kHz measurement bandwidth
0.000035%
–129
G = 1, RL = 2 kΩ, VO = 3.5 VRMS, f = 20 kHz,
80-kHz measurement bandwidth
0.000018%
–135
SMPTE/DIN two-tone, 4:1
(60 Hz and 7 kHz)
G = 1
IMD
Intermodulation distortion
VO = 3.5 VRMS
CCIF twin-tone
0.000020%
–134
(19 kHz and 20 kHz)
FREQUENCY RESPONSE
Gain-bandwidth product
G = 100
53
20
MHz
MHz
V/µs
MHz
ns
GBW
SR
Unity gain bandwidth
Slew rate
G = 1
24
G = –1, 10-V step
VO = 1 VP
G = –10
Full-power bandwidth(1)
Overload recovery time
Channel separation
Settling time
3.8
100
f = 1 kHz
dB
–135
800
ns
0.01%, G = –1, 10-V step
NOISE
f = 20 Hz to 20 kHz
f = 0.1 Hz to 10 Hz
f = 100 Hz
0.53
1.9
11.8
4.3
2.9
6
µVRMS
µVPP
Input voltage noise
nV/√Hz
en
Input voltage noise density
Input current noise density
f = 1 kHz
nV/√Hz
fA/√Hz
f = 10 kHz
in
OFFSET VOLTAGE
f = 1 kHz
VOS
Input offset voltage
VS = ±2.25 V to ±18 V
±0.5
0.3
±1
2
mV
VS = ±2.25 V to ±18 V
TA = –40°C to +125°C
dVOS/dT
PSRR
Input offset voltage drift(2)
Power-supply rejection ratio
µV/°C
µV/V
VS = ±2.25 V to ±18 V
0.3
5
INPUT BIAS CURRENT
OPA1655
VCM = 0 V
±10
±10
±10
±10
IB
Input bias current(3)
pA
pA
OPA1656
±20
±20
OPA1655
VCM = 0 V
IOS
Input offset current
OPA1656
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio
V
(V–)
(V+) –2.25
CMRR
106
120
dB
(V–) ≤VCM ≤(V+) –2.25
INPUT IMPEDANCE
Differential
Common-mode
OPEN-LOOP GAIN
100 || 9.1
6 || 1.9
MΩ|| pF
1012Ω|| pF
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6.6 Electrical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ, and VCM = VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(V–) + 1.3 V ≤VO ≤(V+) –1.3 V
RL = 600 Ω
134
150
AOL
Open-loop voltage gain
dB
(V–) + 0.5 V ≤VO ≤(V+) –0.5 V
RL = 2 kΩ
134
154
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6.6 Electrical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ, and VCM = VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VO
Voltage output
V
(V–) + 0.25
(V+) –0.25
ZO
Open-loop output impedance
Short-circuit current(4)
Capacitive load drive
f = 1 MHz
26
±100
100
Ω
mA
pF
ISC
CL
POWER SUPPLY
IO = 0 A, VS = ±2.25 V to ±18 V
3.9
4.6
5.0
IQ Quiescent current (per channel)
mA
IO = 0 A, TA = –40°C to +125°C(2)
(1) Full-power bandwidth = SR / (2π× VP), where SR = slew rate.
(2) Specified by design and characterization.
(3) Input bias current test conditions can vary from nominal ambient conditions as a result of junction temperature differences.
(4) One channel at a time.
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6.7 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
100
10
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Time (1 s/div)
C020
D029
图6-1. Input Voltage Noise Density vs Frequency
图6-2. 0.1-Hz to 10-Hz Noise
1000
50
40
30
20
10
0
Voltage Noise Contribution
Resistor Noise Contribution
Current Noise Contribution
Total Noise Contribution
Vs=ê18 V
Vs=ê15 V
Vs=ê2.25 V
500
200
100
50
20
10
5
2
1
0.5
0.2
0.1
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k
100k
1M
Source Resistance (W)
D113
D120
图6-4. Maximum Output Voltage vs Frequency
图6-3. Voltage Noise vs Source Resistance
180
150
120
90
180
150
120
90
60
40
20
0
Gain
Phase
G = +1
G= -1
G= +10
G= +100
60
60
30
30
0
0
-30
-30
-20
100m
1
10
100
1k
Frequency (Hz)
10k 100k 1M 10M
100
1k
10k 100k
Frequency (Hz)
1M
10M
D104
D106
CL = 10 pF
CL = 10 pF
图6-5. Open-Loop Gain and Phase vs Frequency
图6-6. Closed-Loop Gain vs Frequency
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
0.01
-80
1
-40
G = -1, 600-W Load
G = -1, 600-W Load
G = -1, 2k-W Load
G = -1, 10k-W Load
G = +1, 600-W Load
G = +1, 2k-W Load
G = +1, 10k-W Load
G = -1, 2k-W Load
G = -1, 10k-W Load
G = +1, 600-W Load
G = +1, 2k-W Load
G = +1, 10k-W Load
0.1
-60
0.001
-100
-120
-140
0.01
-80
0.001
0.0001
1E-5
-100
-120
-140
0.0001
0.00001
20
100
1k
Frequency (Hz)
10k 20k
100m
1
Output Amplitude (VRMS)
10
D109
D110
VOUT = 3 VRMS
Bandwidth = 80 kHz
f = 1 kHz
Bandwidth = 80 kHz
图6-7. THD+N Ratio vs Frequency
图6-8. THD+N Ratio vs Output Amplitude
0.001
0.0005
-100
-120
-140
-160
-180
-200
0.005
G = -1, HD2
G = -1, HD3
G = -1, HD4
G = -1, HD5
G = +1, HD2
G = +1, HD3
G = +1, HD4
G = +1, HD5
G = -1, VIN = 1 VPP (0.354 VRMS
)
)
)
)
0.003
0.002
G = -1, VIN = 5 VPP (1.768 VRMS
0.0002
0.0001
5E-5
G = +1, VIN = 1 VPP (0.354 VRMS
G = +1, VIN = 5 VPP (1.768 VRMS
0.001
0.0007
0.0005
-100
-120
2E-5
1E-5
5E-6
0.0003
0.0002
2E-6
1E-6
5E-7
0.0001
7E-5
5E-5
2E-7
1E-7
5E-8
3E-5
2E-5
2E-8
1E-8
20
100
1k
Frequency (Hz)
10k 20k
ê5
ê10
ê18
VS (V)
D111
D141
VOUT = 3 VRMS
Bandwidth = 80 kHz
f = 1 kHz
Bandwidth = 80 kHz
RL = 2 kΩ
图6-9. Individual Harmonic Amplitude vs Frequency
图6-10. THD+N vs Supply Voltage
0.1
0.01
-60
0
CCIF
SMPTE
-20
-40
-80
-60
-80
0.001
0.0001
1E-5
-100
-120
-140
-100
-120
-140
-160
-180
-200
10m
100m
Output Amplitude (VRMS
1
10
20
100
1k
Frequency (Hz)
10k
50k
)
D140
D142
Bandwidth = 80 kHz
G = 1, VOUT = 3 VRMS
Bandwidth = 80 kHz
RL = 2 kΩ
图6-11. Intermodulation Distortion vs Amplitude
图6-12. FFT, 1-kHz Sine Wave
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
1k
10k
Frequency (Hz)
80k
0
20k
40k
Frequency (Hz)
60k
80k
D143
D143
G = 1, VOUT = 3 VRMS
Bandwidth = 80 kHz
VOUT = 3 VRMS
Bandwidth = 80 kHz
RL = 2 kΩ
RL = 2 kΩ
图6-13. FFT, 10-kHz Sine Wave
图6-14. FFT, CCIF Input (19 kHz + 20 kHz)
-60
-80
160
140
120
100
80
PSRR+
PSRR-
CMRR
-100
-120
-140
-160
-180
60
40
20
0
1k
10k
100k
Frequency (Hz)
1M
10M
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D114
D107
VOUT = 3 VRMS
G = 1
图6-15. Channel Separation vs Frequency
图6-16. CMRR and PSRR vs Frequency (Referred to Input)
147
146
145
144
143
126
125
124
123
122
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D028
D027
图6-17. Power Supply Rejection Ratio vs Temperature
图6-18. Common Mode Rejection Ratio vs Temperature
(Referred to Input)
(Referred to Input)
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
15
10
5
30
25
20
15
10
5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-1000 -750 -500 -250
0
250
500
750 1000
Offset Voltage Drift (mV/èC)
Input Offset Voltage (mV)
D004
D001
Count = 32
Count = 7955
图6-20. Input Offset Voltage Drift Distribution
图6-19. Input Offset Voltage Distribution
1
0.5
0
100
75
-40èC
50
25
0
-25
-50
-75
-100
-0.5
-1
125èC
25èC
85èC
-18 -15 -12 -9 -6 -3
0
3
6
Input Common-Mode Voltage (V)
9
12 15 18
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D019
D017
5 typical units shown
图6-21. Input Offset vs Temperature
图6-22. Input Offset vs Common Mode Voltage
VIN
VOUT
VIN
VOUT
Time (1 ms/div)
Time (1 ms/div)
D137
D135
G = 1
CL = 20 pF
CL = 100 pF
G = –1
图6-23. Small-Signal Step Response (100 mV)
图6-24. Small-Signal Step Response (100 mV)
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
VIN
VOUT
VIN
VOUT
Time (1 ms/div)
Time (1 ms/div)
D136
D139
G = 1
CL = 100 pF
CL = 100 pF
RL = 2 kΩ
G = –1
图6-25. Large-Signal Step Response
图6-26. Large-Signal Step Response
158
156
154
152
150
148
146
144
100
50
IB+
IB-
IOS
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature(èC)
D024
D033
图6-28. IB and IOS vs Temperature
图6-27. Open-Loop Gain vs Temperature
30
20
10
0
4
3.9
3.8
3.7
3.6
IB-
IB+
IOS
VS = 4.5 V
VS = 36 V
-10
-20
-30
-18 -15 -12 -9 -6 -3
0
3
6
Input Common-Mode Voltage (V)
9
12 15 18
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D023
D031
图6-29. IB and IOS vs Common-Mode Voltage
图6-30. Supply Current vs Temperature
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
4.5
18
17
16
15
14
13
12
4
25èC
-40èC
3.5
3
125èC
2.5
2
85èC
1.5
0
4
8
12
16
20
Supply Voltage (V)
24
28
32
36
0
10 20 30 40 50 60 70 80 90 100 110 120
Output Current (mA)
D030
D025
图6-31. Supply Current vs Supply Voltage
85èC
图6-32. Output Voltage vs Output Current (Sourcing)
-12
-13
-14
-15
-16
-17
-18
140
Sinking
Sourcing
132
124
116
108
100
92
125èC
84
25èC
76
-40èC
68
60
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
0
10 20 30 40 50 60 70 80 90 100 110 120
Output Current (mA)
D041
D026
图6-34. Short-Circuit Current vs Temperature
图6-33. Output Voltage vs Output Current (Sinking)
75
100
90
80
70
60
50
40
30
20
10
RISO = 0 W
RISO = 25 W
RISO = 50 W
50
25
0
-25
10
100
Load Capacitance, CL (pF)
1000
10
100
Load Capacitance, CL (pF)
500
D037
D105
G = 1
G = 1
图6-36. Percent Overshoot vs Capacitive Load
图6-35. Phase Margin vs Capacitive Load
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
60
RISO = 0 W
RISO = 25 W
RISO = 50 W
50
40
30
20
10
0
VIN
VOUT
Time (400 ns/div)
10
100
Load Capacitance, CL (pF)
1000
D134
D131
G = –10
G = –1
图6-38. Negative Overload Recovery
图6-37. Percent Overshoot vs Capacitive Load
1000
100
10
VIN
VOUT
1
0.1
Time (400 ns/div)
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D138
D112
G = –10
图6-40. Open-Loop Output Impedance vs Frequency
图6-39. Positive Overload Recovery
VIN
VOUT
Time (400 ns/div)
D138
G = 1
图6-41. No Phase Reversal
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7 Detailed Description
7.1 Overview
The OPA1655 and OPA1656 (OPA165x) use a three-gain-stage architecture to achieve very low noise and
distortion. The Functional Block Diagram shows a simplified schematic of the OPA165x (one channel shown).
The devices consist of a low-noise input stage and feedforward pathway coupled to a high-current output stage.
This topology exhibits superior distortion performance under a wide range of loading conditions compared to
other operational amplifiers.
7.2 Functional Block Diagram
Feed-
forward
Path
CM1
CM2
+IN
Output
Stage
Input
Stage
Gain
Stage
OUT
-IN
7.3 Feature Description
7.3.1 Phase Reversal Protection
The OPA165x have internal phase-reversal protection. Many op amps exhibit phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The input of the OPA165x prevents phase reversal with excessive common-mode voltage.
Instead, the appropriate rail limits the output voltage. This performance is shown in 图7-1.
20
15
10
5
0
-5
-10
-15
VIN
VOUT
-20
Time (125 ꢀs/div)
C004
图7-1. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
7.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
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A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. 图
7-2 illustrates the ESD circuits contained in the OPA165x (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the
operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
TVS
RF
+VS
R1
RS
20 Ω
20 Ω
INœ
IN+
+
Power-Supply
ESD Cell
RL
+
VIN
œ
œVS
TVS
图7-2. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA165x
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit, as shown in 图 7-2, the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
图 7-2 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
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If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the
current through the steering diodes can become quite high. The current level depends on the ability of the input
source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see 图 7-2. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
7.3.3 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this document provides the EMIRR IN+, which specifically describes the EMIRR performance
when the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the
noninverting input is tested for EMIRR for the following three reasons:
• Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
• The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
• EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to the
noninverting input pin with no complex interactions from other components or connecting PCB traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in the EMI Rejection Ratio of
Operational Amplifiers application report, available for download at www.ti.com.
The EMIRR IN+ of the OPA165x is plotted versus frequency in 图 7-3. If available, any dual and quad
operational amplifier device versions have nearly identical EMIRR IN+ performance. The OPA165x unity-gain
bandwidth is 20 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the
operational amplifier bandwidth.
140
120
100
80
60
40
20
10M
100M
Frequency (Hz)
1G
10G
D115
图7-3. OPA165x EMIRR vs Frequency
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表 7-1 lists the EMIRR IN+ values for the OPA165x at particular frequencies commonly encountered in real-
world applications. Applications listed in 表 7-1 can be centered on or operated near the particular frequency
shown. This information can be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
表7-1. OPA165x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, UHF
36 dB
GSM, radio communication and navigation, GPS (to 1.6 GHz), ISM,
aeronautical mobile, UHF
900 MHz
42 dB
1.8 GHz
2.4 GHz
3.6 GHz
GSM, mobile personal comm. broadband, satellite, L-band
52 dB
64 dB
67 dB
802.11b/g/n, Bluetooth® mobile personal comm., ISM, amateur radio and satellite, S-band
Radiolocation, aero comm./nav., satellite, mobile, S-band
802.11a/n, aero communication and navigation, mobile communication,
space and satellite operation, C-band
5 GHz
77 dB
7.3.3.1 EMIRR IN+ Test Configuration
图 7-4 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the operational
amplifier noninverting input pin using a transmission line. The operational amplifier is configured in a unity-gain
buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large
impedance mismatch at the operational amplifier input causes a voltage reflection; however, this effect is
characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is sampled
and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can interfere with
multimeter accuracy. See the EMI Rejection Ratio of Operational Amplifiers application report for more details.
Ambient temperature: 25˘C
+VS
œ
50 ꢀ
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
-VS
Sample /
Averaging
Digital Multimeter
Not shown: 0.1 µF and 10 µF
supply decoupling
Frequency Sweep: 201 pt. Log
图7-4. EMIRR IN+ Test Configuration Schematic
7.4 Device Functional Modes
The OPA165x have a single functional mode and are operational when the power-supply voltage is greater than
4.5 V. The maximum specified power-supply voltage for the OPA165x is 36 V.
In all cases, the common-mode voltage must be maintained within the specified range. In addition, key
parameters are specified over the temperature range of TA = –40°C to +125°C.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
8.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
图 8-1 shows noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations
with gain, the feedback network resistors contribute noise. In general, the current noise of the op amp reacts with
the feedback resistors to create additional noise components.
The selected feedback resistor values make these noise sources negligible. Low impedance feedback resistors
load the output of the amplifier. The equations for total noise are shown for both configurations.
(A) Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
42
41 „ 42
A0 + kA4 2 o2
+
E0 „ 45 + lE0 „ d
hp
2
2
2
¨
: ;
1
:
;
:
;
:
;
>
?
84/5
'
1
= l1 + p „ A5
+
æ4
1
41
41 + 42
GND
œ
EO
8
: ;
2
A5
=
4 „ G$ „ 6(-) „ 45
¥
d
h
Thermal noise of RS
+
*V
¾
RS
4
1 „ 42
8
: ;
3
¨
4 „ G$ „ 6(-) „ d
A4
=
2
h
d
h
Thermal noise of R1 || R2
æ4
1
41 + 42
*V
¾
+
,
h
VS
Source
GND
G$ = 1.38065 „ 10F23
: ;
4
d
œ
Boltzmann Constant
-
Temperature in kelvins
: ;
>
?
-
5
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
:
;
42
45 + 41 „ 42
'
1
= l1 +
p „ A0 2 + kA4
2 o2 + FE0 „ H
+4 æ4
5
IG
¨
: ;
6
:
;
>
84/5
?
1
45 + 41
45 + 41 + 42
RS
œ
EO
:
;
45 + 41 „ 42
8
+
: ;
7
¨
4 „ G$ „ 6(-) „ H
A4
=
I
d
h
Thermal noise of (R1 + RS) || R2
+4 æ4
5
1
2
45 + 41 + 42
*V
¾
+
VS
œ
,
GND
G$ = 1.38065 „ 10F23
d
h
: ;
8
Boltzmann Constant
Source
GND
-
: ;
9
>
?
6(-) = 237.15 + 6(°%)
-
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
where
• eN is the voltage noise of the amplifier. For the OPA165x, eN = 4.3 nV/√Hz at 1 kHz.
• iN is the current noise of the amplifier. For the OPA165x, iN = 6 fA/√Hz at 1 kHz.
Note: For additional resources on noise calculations, see TI's Precision Labs Series.
图8-1. Noise Calculation in Gain Configurations
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8.2 Typical Applications
8.2.1 Preamplifier Circuit for Vinyl Record Playback With Moving-Magnet Phono Cartridges
The noise and distortion performance of the OPA165x is exceptional in applications with high source
impedances, which makes these devices an excellent choice in preamplifier circuits for moving magnet phono
cartridges. The high source impedance of the cartridge, and high gain required by the RIAA playback curve at
low frequency, requires an amplifier with both low input current noise and low input voltage noise.
15 V
C5
100
MM Phono Input
R5
100
F
OPA165x
+
–
+IN
IN
Output
R1
47 k
C1
150 pF
VOUT
R6
100 k
15 V
R2
R3
118 k
10 k
C2
27 nF
C3
7.5 nF
R4
127
C4
100
F
图8-2. Preamplifier Circuit for Vinyl Record Playback With Moving-Magnet Phono Cartridges
(Single Channel Shown)
8.2.1.1 Design Requirements
• Gain: 40 dB (1 kHz)
• RIAA accuracy: ±0.5 dB (100 Hz to 20 kHz)
• Power supplies: ±15 V
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8.2.1.2 Detailed Design Procedure
Vinyl records are recorded using an equalization curve specified by the Recording Institute Association of
America (RIAA). The purpose of this equalization curve is to decrease the amount of space occupied by a
groove on the record and therefore maximize the amount of information able to be stored. Proper playback of
music stored on the record requires a preamplifier circuit that applies the inverse transfer function of the
recording equalization curve. The combination of the recording equalization and the playback equalization
results in a flat frequency response over the audio range, as 图8-3 shows.
20
15
Playback Curve
10
5
0
Combined Response
-5
-10
Recording Curve
-15
-20
10
100
1000
10000
Frequency (Hz)
C009
图8-3. RIAA Recording and Playback Curves Normalized at 1 kHz
The basic RIAA playback curve implements three time constants: 75 μs, 380 μs, and 3180 μs. An IEC
amendment was later added to the playback curve and implements a pole in the curve at 20 Hz with the intent of
protecting loudspeakers from excessive low frequency content. Rather than strictly adhering to the IEC
amendment, this design moves this pole to a lower frequency to improve low frequency response and still
provide protection for loudspeakers.
Resistor R1 and capacitor C1 are selected to provide the proper input impedance for the moving magnet
cartridge. Cartridge loading is specified by the manufacturer in the cartridge datasheet and is absolutely crucial
for proper response at high frequency. 47 kΩis a common value for the input resistor, and the capacitive loading
is usually specified from 200 pF to 300 pF per channel. This capacitive loading specification includes the
capacitance of the cable connecting the turntable to the preamplifier, as well as any additional parasitic
capacitances at the preamplifier input. Therefore, the value of C1 must be less than the loading specification to
account for these additional capacitances.
The output network consisting of R5, R6, and C5 serves to ac couple the preamplifier circuit to any subsequent
electronics in the signal path. 100-Ω resistor R5 limits in-rush current into coupling capacitor C5 and prevents
parasitic capacitance from cabling from causing instability. R6 prevents charge accumulation on C5. Capacitor
C5 is chosen to be the same value as C4; for simplicity however, the value of C5 must be large enough to avoid
attenuating low-frequency information.
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The feedback resistor elements must be selected to provide the correct response within the audio bandwidth. In
order to achieve the correct frequency response, the passive components in 图8-2 must satisfy 方程式1, 方程式
2, and 方程式3:
R × C = 3180 μs
(1)
(2)
(3)
2
2
R × C = 75 μs
3
3
R
R
× C + C = 318 μs
2
3 2 3
R2, R3, and R4 must also be selected to meet the design requirements for gain. The gain at 1 kHz is determined
by subtracting 20 dB from gain of the circuit at very low-frequency (near dc), as shown in 方程式4:
A
= A − 20 dB
(4)
1kHz
LF
Therefore, the low frequency gain of the circuit must be 60 dB to meet the goal of 40 dB at 1 kHz and is
determined by resistors R2, R3, and R4 as shown in 方程式5:
R
+ R
2
3
A
= 1 +
= 1000 60 dB
(5)
LF
R
4
Because there are multiple combinations of passive components that satisfy these equations, a spreadsheet or
other software calculation tool is the easiest method to examine resistor and capacitor combinations.
Capacitor C4 forces the gain of the circuit to unity at dc in order to limit the offset voltage at the output of the
preamplifier circuit. The high-pass corner frequency created by this capacitor is calculated by 方程式6:
1
F
=
(6)
HP
2πR C
4 4
The circuit described in 图 8-2 is constructed with 1% tolerance resistors and 5% tolerance NP0, C0G ceramic
capacitors without any additional hand sorting. The large value of C4 typically requires an electrolytic type to be
used. However, electrolytic capacitors have the potential to introduce distortion into the signal path. This circuit is
constructed using a bipolar electrolytic capacitor specifically intended for audio applications.
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8.2.1.3 Application Curves
The deviation from the ideal RIAA transfer function curve is shown in 图 8-4 and normalized to an ideal gain of
40 dB at 1 kHz. The measured gain at 1 kHz is 0.05 dB less than the design goal, and the maximum deviation
from 100 Hz to 20 kHz is 0.18 dB. The deviation from the ideal curve can be improved by hand-sorting resistor
and capacitor values to their ideal values. The value of C4 can also be increased to reduce the deviation at low
frequency.
A spectrum of the preamplifier output signal is shown in 图 8-5 for a 10 mVRMS, 1-kHz input signal (1-VRMS
output). All distortion harmonics are below the preamplifier noise floor.
1.5
1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0.5
0
-100
-110
-120
-130
-140
-150
-160
-0.5
100
1k
Frequency (Hz)
10k
10
100
1k
Frequency (Hz)
10k
D201
D202
图8-5. Output Spectrum for a 10-mVRMS
1‑kHz Input Signal
,
图8-4. Measured Deviation
From Ideal RIAA Response
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8.2.2 Composite Headphone Amplifier
图 8-6 shows the BUF634A buffer inside the feedback loop of the OPA165x to increase the available output
current for low-impedance headphones. If the BUF634A is used in wide-bandwidth mode, no additional
components beyond the feedback resistors are required to maintain loop stability.
12 V
100
0.1
F
F
0.1
F
OPA165x
+
–
Input
Output
BUF634A
R1
100 k
0.1
F
RBW
0.1
F
100
F
12 V
R3
R2
500
500
图8-6. Composite Headphone Amplifier (Single-Channel Shown)
8.2.2.1 Application Curves
-85
0
-30
249 W RL
32 W RL
16 W RL
249 W RL
-90
-60
-95
-90
-100
-105
-110
-120
-150
-180
20 Hz
100 Hz
1 kHz
20 kHz
0
5000
10000
Frequency (Hz)
15000
20000
Frequency (Hz)
C051
C052
图8-7. THD+N vs Frequency for a
5‑VPP (1.77‑VRMS) Input Signal
图8-8. FFT for a 5-VPP (1.77-VRMS),
1‑kHz Input Signal
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8.2.3 Baxandall Tone Control
图 8-9 gives an example of ultra-low noise and THD tone control. This circuit provides 20 dB of gain at the first
stage, followed by two separate tone controls for bass and treble. The passive circuit is designed to yield a flat
gain response with the potentiometers both set to 50%.
Bass
100 k
1.69 k
15.4 k
11 k
11 k
10 nF
10 nF
10 µF
–
15 V
11 k
Input
+
–
Output
1/2
OPA1656
10 µF
1/2
OPA1656
+
4.7 nF
1.69 k
15 V
3.65 k
3.65 k
500 k
Treble
图8-9. Dual Potentiometer Baxandall Tone Control
8.2.3.1 Application Curves
40
10% Bass / 90% Treble
50% Bass / 50% Treble
90% Bass / 10% Treble
36
32
28
24
20
16
12
8
4
0
100
1k
Frequency (Hz)
10k
D203
图8-10. Amplitude vs Frequency for Various Tone-Control Settings
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8.2.4 Guitar Input to XLR Output
The OPA165x are an excellent choice for guitar input circuits as a result of the high input impedance and ultra-
low noise performance. 图8-11 gives an example of a basic guitar input circuit to differential XLR schematic. The
logarithmic taper potentiometer shown in this circuit provides 6 dB of gain at 0%, and 40 dB of gain at 100%.
The rail-to-rail output swing of the OPA165x allows for a high amplitude swing at the outputs of the differentially
configured amplifiers, while maintaining very low distortion performance. A 10-µF dc blocking capacitor is used
in the feedback of the noninverting stage to remove any dc offset as a result of the amplifier offset voltage.
However, this dc blocking capacitor can be eliminated for applications that are not sensitive to low dc offsets.
100 k
10 µF
1 k
1 k
10 pF
¼ Inch
Jack
–
+
49
1/2
OPA1656
1 M
XLR
Output
1 k
1 k
10 pF
5 V
–
49
1/2
+
OPA1656
5 V
图8-11. Guitar Input to XLR Output Schematic
8.2.4.1 Application Curves
0.1
0.08
0.06
0.04
0.02
0
3.3
3
Input Voltage
Output Voltage 1
Output Voltage 2
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.12
-0.14
-0.16
-0.18
-0.2
-0.3
-0.6
-0.9
-1.2
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
D200
图8-12. 1-kHz Input Signal Transient Simulation
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8.3 Power Supply Recommendations
The OPA165x are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
The OPA165x operate with as little as 4.5 V between the supplies and with up to 36 V between the supplies.
However, some applications do not require equal positive and negative output voltage swing. With the OPA165x,
power-supply voltages are not required to be equal. For example, the positive supply can be set to 25 V with the
negative supply at –5 V.
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Physically
separate digital and analog grounds, observing the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in 图8-13, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
8.4.1.1 Power Dissipation
The OPA165x op amps are capable of driving 600-Ω loads with a power-supply voltage up to ±18 V and full
operating temperature range. Internal power dissipation increases when operating at high supply voltages.
Copper leadframe construction used in the OPA165x improves heat dissipation compared to conventional
materials. Circuit board layout can also help minimize junction temperature rise. Wide copper traces help
dissipate the heat by acting as an additional heat sink. Temperature rise can be further minimized by soldering
the devices to the circuit board rather than using a socket.
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8.4.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors.
Output A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUTPUT A
V+
RF
Output B
GND
-IN A
+IN A
Vœ
OUTPUT B
-IN B
RF
RG
GND
VIN A
RG
+IN B
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor. Place as
close to the device
as possible.
VSœ
Ground (GND) plane on another layer
as possible.
图8-13. Operational Amplifier Board Layout for Noninverting Configuration
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案，可降低开发成本并缩短上市时间。
9.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
备注
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
9.1.1.3 DIP-Adapter-EVM
Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and
inexpensive way to interface with small, surface-mount devices. Connect any supported op amp using the
included Samtec terminal strips or wire them directly to existing circuits. The DIP-Adapter-EVM kit supports the
following industry-standard packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT-23-6,
SOT-23-5 and SOT-23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6).
9.1.1.4 DIYAMP-EVM
The DIYAMP-EVM is a unique evaluation module (EVM) that provides real-world amplifier circuits, enabling the
user to quickly evaluate design concepts and verify simulations. This EVM is available in three industry-standard
packages (SC70, SOT23, and SOIC) and 12 popular amplifier configurations, including amplifiers, filters, stability
compensation, and comparator configurations for both single and dual supplies.
9.1.1.5 TI Reference Designs
TI reference designs are analog solutions created by TI’s precision analog applications experts. TI reference
designs offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill
of materials, and measured performance of many useful circuits. TI reference designs are available online at
https://www.ti.com/reference-designs.
9.1.1.6 Filter Design Tool
The filter design tool is a simple, powerful, and easy-to-use active filter design program. The filter design tool
allows the user to create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the Design tools and simulation web page, the filter design tool allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
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9.2 Documentation Support
9.2.1 Related Documentation
The following documents are recommended for reference when using the OPA165x, and are available for
download at www.ti.com.
• Texas Instruments, Source Resistance and Noise Considerations in Amplifiers technical brief
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
• Texas Instruments, Op Amp Performance Analysis application bulletin
• Texas Instruments, Compensate Transimpedance Amplifiers Intuitively application report
• Texas Instruments, Tuning in Amplifiers application bulletin
• Texas Instruments, Feedback Plots Define Op Amp AC Performance application bulletin
• Texas Instruments, Active Volume Control for Professional Audio design guide
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
Burr-Brown™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1655DBVR
OPA1655DBVT
OPA1655DR
OPA1656ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2R8Q
2R8Q
Samples
Samples
Samples
Samples
Samples
SN
NIPDAU
NIPDAU
NIPDAU
OP1655
OP1656
OP1656
SOIC
D
OPA1656IDR
SOIC
D
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1655DBVR
OPA1655DBVT
OPA1655DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
8
3000
250
178.0
178.0
330.0
330.0
9.0
9.0
3.3
3.3
6.4
6.4
3.2
3.2
5.2
5.2
1.4
1.4
2.1
2.1
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
3000
2500
12.4
12.4
12.0
12.0
OPA1656IDR
SOIC
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA1655DBVR
OPA1655DBVT
OPA1655DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
8
3000
250
190.0
190.0
356.0
356.0
190.0
190.0
356.0
356.0
30.0
30.0
35.0
35.0
3000
2500
OPA1656IDR
SOIC
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA1656ID
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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