OPA1662AIDRQ1 [TI]
汽车类 Sound Plus、低功耗、低噪声和失真、音频运算放大器 | D | 8 | -40 to 85;
| 型号： | OPA1662AIDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 Sound Plus、低功耗、低噪声和失真、音频运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总34页 (文件大小：1982K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA1662-Q1
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
OPA1662-Q1 双路 3.3 nV/√Hz 噪声、0.00006% THD+N、RRO、双极输
入音频运算放大器
1 特性
3 说明
1
•
•
符合汽车应用 标准
具有符合 AEC-Q100 标准的下列结果
OPA1662-Q1 是一个双路双极输入运算放大器，非常
适合作为信息娱乐和组合仪表系统中 高级音频设备的
外部放大器。音频系统所面临的首要任务是要确保清
晰、高质量的输出信号，这意味着要最大程度地减少进
入到信号中的任何噪声。OPA1662-Q1 可提供低噪声
密度和 0.00006% 的超低失真 (1kHz)，能够最大限度
地增大信号输出。此外，该运算放大器在 2kΩ 负载下
还可提供 600mV 范围内的轨至轨输出摆幅。宽余量可
确保输出信号不发生削波，并由此保护音频质量。
–
–
–
器件温度等级 3 级：环境工作温度范围为
–40°C 至 85°C
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
器件组件充电模式 (CDM) ESD 分类等级 C3B
•
•
•
•
•
•
•
•
低噪声： 1kHz 下为 3.3nV/√Hz
低失真：1kHz下为 0.00006%
低静态电流：每通道 1.5mA
转换率：17V/μs
OPA1662-Q1 可在 ±1.5V 至 ±18V，或者 3V 至 36V
这一非常宽的电源电压范围内运行，每通道电源电流仅
为 1.5mA。宽电源范围使得器件获得了设计灵活性，
因为它既可以从由电池驱动的功率放大器进行集成，也
可以从由 ADC 到 DAC 驱动的功率放大器进行集成，
以实现低功耗 应用。此外，该器件还具有 ±30mA 的
高输出驱动能力，可作为低功耗应用的唯一 音频放大
器，例如用于仪表组提示音。
宽增益带宽：22MHz (G = 1)
单位增益稳定
轨至轨输出
宽电源电压范围：±1.5V 至 ±18V，
或 3V 至 36V
•
小型封装尺寸：
两种封装类型：8 引脚 SOIC 和 VSSOP
器件信息(1)
2 应用
器件型号
封装
SOIC (8)
VSSOP (8)
封装尺寸（标称值）
4.90mm x 3.91mm
3.00mm × 3.00mm
•
•
•
•
•
汽车
OPA1662-Q1
车载音频
高级音频设备
外部音频放大器
车身控制模块
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
输入电压噪声密度和输入电流噪声密度与频率间的关系
THD+N 比与频率间的关系
100
10
1
100
10
1
0.01
Voltage Noise
Current Noise
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V,RL = 600Ω
G = +1V/V,RL = 2kΩ
G = −1V/V,RL = 600Ω
G = −1V/V,RL = 2kΩ
0.001
0.0001
VOUT = 3VRMS
BW = 80kHz
0.1
0.1
100k
1
10
100
1k
10k
0.00001
Frequency (Hz)
G001
20
100
1k
Frequency (Hz)
10k 20k
G007
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS805
OPA1662-Q1
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
7.1 Absolute Maximum Ratings ...................................... 3
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics: VS = ±15 V....................... 4
7.6 Electrical Characteristics: VS = 5 V........................... 5
7.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
11.3 Power Dissipation ................................................. 23
12 器件和文档支持 ..................................................... 24
12.1 文档支持................................................................ 24
12.2 接收文档更新通知 ................................................. 24
12.3 社区资源................................................................ 24
12.4 商标....................................................................... 24
12.5 静电放电警告......................................................... 24
12.6 Glossary................................................................ 24
13 机械、封装和可订购信息....................................... 24
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (October 2012) to Revision C
Page
•
添加了 ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和
文档支持 部分以及机械、封装和可订购信息 部分。............................................................................................................... 1
•
•
删除了订购信息 表，请参见数据表末尾的 POA ..................................................................................................................... 1
已更改 （说明部分中的第二句） ............................................................................................................................................ 1
Changes from Revision A (September 2012) to Revision B
Page
•
•
在订购信息 表中，将预览中 OPA1662AIDRQ1 的顶端标记更改为了 O1662Q ..................................................................... 1
1 级更改为了 3 级（“特性”部分）........................................................................................................................................... 1
Changes from Original (July 2012) to Revision A
Page
•
将器件从预览（2 页）改为生产状态，本修订版包含了标准长度文档。................................................................................. 1
2
版权 © 2012–2016, Texas Instruments Incorporated
OPA1662-Q1
www.ti.com.cn
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
5 说明 （续）
此外，该器件还 具备 两个通道均使用完全独立的电路，可实现低串扰，即便在过驱动或过载时也不受每个通道间
相互作用的影响。借助此功能，客户可轻松驱动两个不同的音频信号，因为信号之间不会相互影响。
OPA1662-Q1 提供 22MHz 的宽带宽和 17V/µs 的高转换率，可用于 SMPS 器件或电机驱动器中纹波电流的高侧和
低侧感应。作为一个电流传感器，OPA1662-Q1 可作为峰值电流模式控制使用，借助该运算放大器，可为系统提供
稳定性并可实现更高带宽。OPA1662-Q1 可应用于车身控制模块和通常使用电机的 HEV 或 EV 转换器。
6 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
A
OUT B
-IN B
+IN B
B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
+IN A
–IN A
+IN B
–IN B
OUT_A
OUT_B
V–
NO.
3
I
I
Noninverting input channel A
Inverting input channel A
Noninverting input channel B
Inverting input channel B
Output, channel A
2
5
I
6
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Supply voltage, (V+) – (V–)
Input voltage
(V–) – 0.5
(V+) + 0.5
±10
V
Input current (all pins except power-supply pins)
Output short-circuit(2)
mA
Continuous
Operating ambient temperature
Junction temperature, TJ
–40
125
200
150
°C
°C
°C
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
Copyright © 2012–2016, Texas Instruments Incorporated
3
OPA1662-Q1
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
www.ti.com.cn
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
±2000
±750
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
VS
TA
Supply voltage, (V+) – (V–)
3 (±1.5) 36 (±18)
Operating ambient temperature
–40
125
°C
7.4 Thermal Information
OPA1662-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
156.3
85.5
DGK (VSSOP)
8 PINS
225.4
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
78.8
64.9
110.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
33.8
14.6
ψJB
64.3
108.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics: VS = ±15 V
TA = 25°C, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.00006%
–124
THD+N
IMD
Total harmonic distortion + noise
Intermodulation distortion
G = 1, f = 1 kHz, VO = 3 VRMS
SMPTE two-tone, 4:1 (60 Hz
dB
dB
dB
dB
0.00004%
–128
and 7 kHz)
0.00004%
–128
DIM 30 (3-kHz square wave
and 15-kHz sine wave)
G = 1, VO = 3 VRMS
0.00004%
–128
CCIF twin-tone (19 kHz and
20 kHz)
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
G = 1
22
17
MHz
V/µs
MHz
µs
Slew rate
G = –1
Full power bandwidth(1)
Overload recovery time
Channel separation (dual and quad)
VO = 1 VP
G = –10
f = 1 kHz
2.7
1
–120
dB
NOISE
en
Input voltage noise
f = 20 Hz to 20 kHz
f = 1 kHz
2.8
3.3
5
µVPP
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
Input voltage noise density
f = 100 Hz
f = 1 kHz
1
In
Input current noise density
f = 100 Hz
2
(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
4
Copyright © 2012–2016, Texas Instruments Incorporated
OPA1662-Q1
www.ti.com.cn
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
Electrical Characteristics: VS = ±15 V (continued)
TA = 25°C, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = ±1.5 V to ±18 V
VS = ±1.5 V to ±18 V, TA = –40°C to 85°(2)
±0.5
2
±1.5
8
mV
VOS
Input offset voltage
µV/°C
µV/V
PSRR
Power-supply rejection ratio
VS = ±1.5 V to ±18 V
1
3
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
VCM = 0 V
VCM = 0 V
600
±25
1200
±100
nA
nA
IOS
INPUT VOLTAGE
VCM
Common-mode voltage
Common-mode rejection ratio
(V–) + 0.5
106
(V+) – 1
V
CMRR
114
dB
INPUT IMPEDANCE
Differential resistance
170
2
kΩ
pF
kΩ
pF
Differential capacitance
Common-mode resistance
Common-mode capacitance
600
2.5
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V, RL = 2 kΩ
RL = 2 kΩ
106
114
dB
OUTPUT
VOUT
IOUT
Output voltage
(V–) + 0.6
(V+) – 0.6
V
Output current
See Typical Characteristics
mA
Ω
ZO
Open-loop output impedance
Short-circuit current(3)
Capacitive load drive
See Typical Characteristics
ISC
±50
200
mA
pF
CLOAD
POWER SUPPLY
VS
Specified voltage
±1.5
±18
1.8
2
V
IOUT = 0 A
IOUT = 0 A, TA = –40°C to 85°(2)
1.5
mA
mA
Quiescent current
(per channel)
IQ
TEMPERATURE
Specified temperature
–40
85
°C
(2) Specified by design and characterization.
(3) One channel at a time.
7.6 Electrical Characteristics: VS = 5 V
TA = 25°C, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETERTEST
CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.0001%
–120
THD+N
IMD
Total harmonic distortion + noise
Intermodulation distortion
G = 1, f = 1 kHz, VO = 3 VRMS
SMPTE two-tone, 4:1 (60 Hz
dB
dB
dB
dB
0.00004%
–128
and 7 kHz)
0.00004%
–128
DIM 30 (3-kHz square wave
and 15-kHz sine wave)
G = 1, VO = 3 VRMS
0.00004%
–128
CCIF twin-tone (19 kHz and
20 kHz)
Copyright © 2012–2016, Texas Instruments Incorporated
5
OPA1662-Q1
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
www.ti.com.cn
Electrical Characteristics: VS = 5 V (continued)
TA = 25°C, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETERTEST
CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
Slew rate
Full power bandwidth(1)
Overload recovery time
Channel separation (dual and quad)
G = 1
20
13
MHz
V/µs
MHz
µs
G = –1
VO = 1 VP
G = –10
f = 1 kHz
2
1
–120
dB
NOISE
en
Input voltage noise
f = 20 Hz to 20 kHz
f = 1 kHz
3.3
3.3
5
µVPP
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
Input voltage noise density
f = 100 Hz
f = 1 kHz
1
In
Input current noise density
f = 100 Hz
2
OFFSET VOLTAGE
VS = ±1.5 V to ±18 V
VS = ±1.5 V to ±18 V, TA = –40°C to 85°(2)
±0.5
2
±1.5
8
mV
VOS
Input offset voltage
Power-supply rejection ratio
µV/°C
µV/V
PSRR
VS = ±1.5 V to ±18 V
1
3
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
VCM = 0 V
VCM = 0 V
600
±25
1200
±100
nA
nA
IOS
INPUT VOLTAGE
VCM
Common-mode voltage
Common-mode rejection ratio
(V–) + 0.5
86
(V+) – 1
V
CMRR
100
dB
INPUT IMPEDANCE
Differential resistance
170
2
kΩ
pF
kΩ
pF
Differential capacitance
Common-mode resistance
Common-mode capacitance
600
2.5
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V, RL = 2 kΩ
RL = 2 kΩ
90
100
dB
OUTPUT
VOUT
IOUT
Output voltage
(V–) + 0.6
(V+) – 0.6
V
Output current
See \
mA
Ω
ZO
Open-loop output impedance
Short-circuit current(3)
Capacitive load drive
See Typical Characteristics
ISC
±40
200
mA
pF
CLOAD
POWER SUPPLY
VS
Specified voltage
±1.5
±18
1.7
2
V
IOUT = 0 A
IOUT = 0 A, TA = –40°C to 85°(2)
1.4
mA
mA
IQ
Quiescent current (per channel)
TEMPERATURE
Specified temperature
–40
85
°C
(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
(2) Specified by design and characterization.
(3) One channel at a time.
6
Copyright © 2012–2016, Texas Instruments Incorporated
OPA1662-Q1
www.ti.com.cn
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
7.7 Typical Characteristics
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
100
10
1
100
10
1
Voltage Noise
Current Noise
0.1
0.1
100k
1
10
100
1k
10k
Time (1s/div)
G002
Frequency (Hz)
G001
Figure 2. 0.1-Hz to 10-Hz Noise
Figure 1. Input Voltage Noise Density and Input Current
Noise Density vs Frequency
15
12
10
8
10k
Eo2 = en2 + (inRS)2 + 4KTRS
VS = ± 15 V
EO
1k
RS
OPA166x
100
OPA165x
VS = ± 5 V
5
10
2
VS = ± 1.5 V
Resistor Noise
0
10k
1
100
100k
Frequency (Hz)
1M
10M
1k
10k
100k
1M
G004
G003
Source Resistance (W)
Figure 4. Maximum Output Voltage vs Frequency
Figure 3. Voltage Noise vs Source Resistance
140
120
100
80
180
40
CL = 100pF
Gain = −1V/V
Gain = +1V/V
Gain = +10V/V
135
20
0
60
90
45
0
40
20
Gain
Phase
0
−20
−20
10
100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
G005
G006
Figure 5. Gain and Phase vs Frequency
Figure 6. Closed-Loop Gain vs Frequency
Copyright © 2012–2016, Texas Instruments Incorporated
7
OPA1662-Q1
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
0.01
0.01
0.001
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V,RL = 600Ω
G = +1V/V,RL = 2kΩ
G = −1V/V,RL = 600Ω
G = −1V/V,RL = 2kΩ
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V,RL = 600Ω
G = +1V/V,RL = 2kΩ
G = −1V/V,RL = 600Ω
G = −1V/V,RL = 2kΩ
0.001
0.0001
0.0001
VOUT = 1VRMS
VOUT = 3VRMS
BW = 80kHz
BW = 80kHz
VS = ± 2.5V
0.00001
0.00001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
G007
G038
Figure 7. THD+N Ratio vs Frequency
Figure 8. THD+N Ratio vs Frequency
0.01
0.01
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V,RL = 600Ω
G = +1V/V,RL = 2kΩ
G = −1V/V,RL = 600Ω
G = −1V/V,RL = 2kΩ
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V,RL = 600Ω
G = +1V/V,RL = 2kΩ
G = −1V/V,RL = 600Ω
G = −1V/V,RL = 2kΩ
0.001
0.001
0.0001
0.0001
VOUT = 1VRMS
VOUT = 3VRMS
BW = 500kHz
BW = 500kHz
VS = ± 2.5V
0.00001
0.00001
20
100
1k
10k
100k
20
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
G009
G039
Figure 9. THD+N Ratio vs Frequency
Figure 10. THD+N Ratio vs Frequency
0.01
0.01
RS = 0 W
RS = 30 W
VOUT = 3 VRMS
BW = 500 kHz
+15V
OPA1662-Q1
-15V
+15V
OPA1662-Q1
-15V
RSOURCE
RSOURCE
RS = 60 W
RS = 1 kW
RL
RL
0.001
0.0001
0.001
0.0001
RS = 0 W
RS = 30 W
RS = 60 W
RS = 1 kW
VOUT = 3 VRMS
BW = 80 kHz
0.00001
0.00001
20
100
1k
10k 20k
20
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
G008
G010
Figure 11. THD+N Ratio vs Frequency
Figure 12. THD+N Ratio vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
0.01
0.001
0.0001
1E-5
0.01
DIM 30: 3 kHz - Square Wave, 15 kHz Sine Wave
CCIF Twin Tone: 19 kHz and 20 kHz
SMPTE: Two - Tone 4:1, 60 Hz and 7 kHz
f = 1 kHz
0.001
BW = 80 kHz
RS = 0 Ω
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V,RL = 600Ω
G = +1V/V,RL = 2kΩ
G = −1V/V,RL = 600Ω
G = −1V/V,RL = 2kΩ
0.0001
G = +1 V/V
0.1
0.00001
1
10
20
1m
10m
100m
1
10 20
Output Amplitude (Vrms)
D001
Output Amplitude (Vrms)
G011
Figure 14. Intermodulation Distortion vs Output Amplitude
Figure 13. THD+N Ratio vs Output Amplitude
−80
−100
−120
−140
−160
140
VOUT = 3 VRMS
Gain = +1 V/V
120
100
80
60
40
+PSRR
−PSRR
CMRR
20
0
100
1k
10k
100k
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
G013
G014
Figure 15. Channel Separation vs Frequency
Figure 16. CMRR and PSRR vs Frequency
(Referred to Input)
VIN
VOUT
VIN
VOUT
G = +1 V/V
CL = 10 pF
VS = ±1.5 V
G = +1 V/V
CL = 10 pF
Time (1 ms/div)
G015
Time (1 ms/div)
G040
Figure 17. Small-Signal Step Response
Figure 18. Small-Signal Step Response
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
G = −1 V/V
CL = 10 pF
VS = ±1.5 V
VIN
VOUT
VIN
VOUT
G = −1 V/V
CL = 10 pF
Time (1 ms/div)
G016
Time (1 ms/div)
G041
Figure 20. Small-Signal Step Response
Figure 19. Small-Signal Step Response
VIN
VOUT
VIN
VOUT
G = +1 V/V
CL = 10 pF
RF = 1 kW
G = +1 V/V
CL = 10 pF
VS = ±1.5 V
Time (1 ms/div)
Time (1 ms/div)
G032
G017
Figure 22. Large-Signal Step Response
Figure 21. Large-Signal Step Response
VIN
VOUT
VIN
VOUT
G = −1 V/V
CL = 10 pF
VS = ±1.5 V
G = −1 V/V
CL = 10 pF
Time (1 ms/div)
Time (1 ms/div)
G035
G018
Figure 23. Large-Signal Step Response
Figure 24. Large-Signal Step Response
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
50
VOUT = 100 mVPP
50
45
40
35
30
25
20
15
10
5
RF = 2 kW
RI = 2 kW
+15 V
45
+15 V
G = +1 V/V
RS
RS
OPA1662-Q1
40
OPA1662-Q1
CL
RL
CL
35
30
25
20
15
10
5
-15 V
-15 V
RS = 0 W
RS = 25 W
RS = 50 W
RS = 0 W
RS = 25 W
RS = 50 W
VOUT = 100 mVPP
G = −1 V/V
0
0
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Capacitance (pF)
Capacitance (pF)
G019
G020
Figure 25. Small-Signal Overshoot vs Capacitive Load
Figure 26. Small-Signal Overshoot vs Capacitive Load
50
50
RS = 0 W
RS = 25 W
RS = 50 W
+15 V
45
45
RS
OPA1662-Q1
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
VOUT = 100 mVPP
RL
CL
G = −1 V/V
VS = ±1.5 V
-15 V
RS = 0 W
RS = 25 W
RS = 50 W
VOUT = 100 mVPP
RF = 2 kW
RI = 2 kW
G = +1 V/V
VS = ±1.5 V
+15 V
RS
OPA1662-Q1
CL
-15 V
0
0
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Capacitance (pF)
Capacitance (pF)
G034
G033
Figure 27. Small-Signal Overshoot vs Capacitive Load
Figure 28. Small-Signal Overshoot vs Capacitive Load
50
50
CF
VS = ±18 V
VS = ±1.5 V
G = +1 V/V
VIN = 100 mVPP
45
45
RF = 2 kW
RI = 2 kW
40
35
30
25
20
15
40
35
30
25
20
15
10
5
+15 V
VOUT = 100 mVPP
RS
G = +1 V/V
CL = 100 pF
OPA1662-Q1
CL
-15 V
10
VS = ± 18 V
VS = ± 1.5 V
5
0
0
0
50
100
150
200
250
300
350
400
0
1
2
3
4
5
Capacitance (pF)
Capacitance (pF)
G037
G021
Figure 30. Percent Overshoot vs Capacitive Load
Figure 29. Small-Signal Overshoot vs Feedback Capacitor
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
90
4
3.5
3
RL = 10 kΩ
RL = 2 kΩ
RL = 600 Ω
80
70
60
50
40
30
20
2.5
2
1.5
1
0.5
0
VS = ± 18 V
VS = ± 1.5 V
10
−0.5
−1
0
0
50
100
150
200
250
300
350
400
−40
−15
10
35
60
85
110
135
Capacitance (pF)
Temperature (°C)
G036
G022
Figure 31. Phase Margin vs Capacitive Load
Figure 32. Open-Loop Gain vs Temperature
400
200
200
0
IOS
IBP
IBN
0
−200
−400
−600
−800
−200
−400
−600
−800
−1000
−Ib
+Ib
Ios
−40
−15
10
35
60
85
110
135
−18 −14 −10
−6
−2
2
6
10
14
18
Temperature (°C)
Common−Mode Voltage (V)
G023
G024
Figure 33. IB and IOS vs Temperature
Figure 34. IB and IOS vs Common-Mode Voltage
1.8
3
2.5
2
1.7
1.6
1.5
1.4
1.3
1.2
1.5
1
0.5
0
−40
−15
10
35
60
85
110
135
0
4
8
12
16
20
24
28
32
36
40
Temperature (°C)
Supply Voltage (V)
G025
G026
Figure 35. Supply Current vs Temperature
Figure 36. Supply Current vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
60
20
15
55
50
45
40
10
−55°C
−40°C
−25°C
0°C
5
0
+25°C
+85°C
−5
−10
−15
−20
35
+Isc
−Isc
30
−40
−15
10
35
60
85
110
135
20
25
30
35
40
45
50
55
60
Temperature (°C)
G027
Output Current (mA)
G028
Figure 37. Short-Circuit Current vs Temperature
Figure 38. Output Voltage vs Output Current
VIN
VOUT
VIN
VOUT
G = −10 V/V
G = −10 V/V
Time (0.5 ms/div)
Time (0.5 ms/div)
G029
G031
Figure 39. Positive Overload Recovery
Figure 40. Negative Overload Recovery
1k
100
10
VOUT
VIN
1
10
100
1k
10k
100k
1M
Time (250 ms/div)
Frequency (Hz)
G042
G030
Figure 42. No Phase Reversal
Figure 41. Open-Loop Output Impedance vs Frequency
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8 Detailed Description
8.1 Overview
The OPA1662-Q1 operational amplifier achieves a low 3.3 nV/√Hz noise density with an ultra-low distortion of
0.00006% at 1 kHz that makes the device suitable for audio application. This device has a wide supply range
with excellent PSRR, making it a suitable option for applications that are battery powered without regulation.
8.2 Functional Block Diagram
V+
IN-
IN+
Pre-Output Driver
OUT
V-
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Figure 43. OPA1662-Q1 Simplified Schematic
8.3 Feature Description
8.3.1 Operating Voltage
The OPA1662-Q1 op amp operates from ±1.5-V to ±18-V supplies while maintaining excellent performance. The
OPA1662-Q1 can operate with as little as 3 V between the supplies and up to 36 V between the supplies.
However, some applications do not require equal positive and negative output voltage swing. With the
OPA1662‑Q1 device, power-supply voltages do not need to be equal. For example, the positive supply could be
set to 25 V with the negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. In addition, key
parameters are assured over the specified temperature of TA = –40°C to 85°C. Parameters that vary significantly
with operating voltage or temperature are shown in the Typical Characteristics.
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Feature Description (continued)
8.3.2 Input Protection
The input terminals of the OPA1662-Q1 are protected from excessive differential voltage with back-to-back
diodes, as Figure 44 illustrates. In most circuit applications, the input protection circuitry has no consequence.
However, in low-gain or G = 1 circuits, fast ramping input signals can forward bias these diodes because the
output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to
create this forward bias condition, the input signal current must be limited to 10 mA or less. If the input signal
current is not inherently limited, an input series resistor (RI) or a feedback resistor (RF) can be used to limit the
signal input current. This resistor degrades the low-noise performance of the OPA1662-Q1 and is examined in
Noise Performance. Figure 44 shows an example configuration when both current-limiting input and feedback
resistors are used.
RF
-
OPA1662-Q1
Output
RI
+
Input
Figure 44. Pulsed Operation
8.3.3 Noise Performance
Figure 45 shows the total circuit noise for varying source impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and therefore no additional noise contributions).
The OPA1662-Q1 (GBW = 22 MHz, G = 1) is shown with total circuit noise calculated. The op amp itself
contributes both a voltage noise component and a current noise component. The voltage noise is commonly
modeled as a time-varying component of the offset voltage. The current noise is similarly modeled as the time-
varying component of the input bias current and reacts with the source resistance to create a voltage component
of noise. Therefore, the lowest noise op amp for a given application depends on the source impedance. For low
source impedance, current noise is negligible, and voltage noise generally dominates. The low voltage noise of
the OPA1662-Q1 op amp makes them a better choice for low source impedances of less than 1 kΩ.
10k
Eo2 = en2 + (inRS)2 + 4KTRS
EO
1k
RS
OPA166x
100
OPA165x
10
Resistor Noise
1
100
1k
10k
100k
1M
G003
Source Resistance (W)
The equation calculates total circuit noise, where:
•
•
•
•
•
en is the voltage noise
in is the current noise
RS is the source impedance
k is Boltzmann’s constant = 1.38 × 10–23 J/K
T is the temperature in Kelvins (K)
Figure 45. Noise Performance of the OPA1662-Q1 in Unity-Gain Buffer Configuration
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Feature Description (continued)
8.3.4 Basic Noise Calculations
Design of low-noise op amp circuits requires careful consideration of a variety of possible noise contributors:
noise from the signal source, noise generated in the op amp, and noise from the feedback network resistors. The
total noise of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. Figure 45 plots this equation. The source impedance is usually fixed; consequently, select the op
amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 46 illustrates both inverting and noninverting op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. The current noise of the op amp
reacts with the feedback resistors to create additional noise components. The feedback resistor values can
generally be chosen to make these noise sources negligible. The equations for total noise are shown for both
configurations.
A) Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
2
R2
R1
R2
R1
R2
R1
2
EO
2
en
2
2
es
e12 + e2
+
R1
1 +
1 +
=
+
EO
4kTRS
4kTR1
4kTR2
Where eS
=
= thermal noise of RS
= thermal noise of R1
= thermal noise of R2
RS
e1 =
e2 =
VS
B) Noise in Inverting Gain Configuration
Noise at the output:
R2
2
2
2
R2
R2
R2
R1 + RS
2
EO
2
2
2
e12 + e2
+
es
= 1 +
en
+
R1
R1 + RS
R1 + RS
EO
RS
4kTRS
4kTR1
4kTR2
Where eS
=
= thermal noise of RS
= thermal noise of R1
= thermal noise of R2
VS
e1 =
e2 =
For the OPA1662-Q1 op amp at 1 kHz, en = 3.3 nV/√Hz.
Figure 46. Noise Calculation in Gain Configurations
8.3.5 Total Harmonic Distortion Measurements
The OPA1662-Q1 op amp has excellent distortion characteristics. THD + noise is below 0.0006% (G = 1,
VO = 3 VRMS, BW = 80 kHz) throughout the audio frequency range, 20 Hz to 20 kHz, with a 2-kΩ load (see
Figure 7 for characteristic performance).
The distortion produced by the OPA1662-Q1 op amp is below the measurement limit of many commercially
available distortion analyzers. However, a special test circuit (such as Figure 47 shows) can be used to extend
the measurement capabilities.
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Op amp distortion can be considered an internal error source that can be referred to the input. Figure 47 shows a
circuit that causes the op amp distortion to be gained up (see the table in Figure 47 for the distortion gain factor
for various signal gains). The addition of R3 to the otherwise standard noninverting amplifier configuration alters
the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged, but the feedback available for
error correction is reduced by the distortion gain factor, thus extending the resolution by the same amount. The
input signal and load applied to the op amp are the same as with conventional feedback without R3. The value of
R3 must be kept small to minimize its effect on the distortion measurements.
The validity of this technique can be verified by duplicating measurements at high gain or high frequency where
the distortion is within the measurement capability of the test equipment. Measurements for this data sheet were
made with an Audio Precision System Two distortion and noise analyzer, which greatly simplifies such repetitive
measurements. The measurement technique can, however, be performed with manual distortion measurement
instruments.
8.3.6 Capacitive Loads
The dynamic characteristics of the OPA1662-Q1 have been optimized for commonly encountered gains, loads,
and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the
phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads
must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (RS equal to
50 Ω, for example) in series with the output.
This small series resistor also prevents excess power dissipation if the output of the device becomes shorted.
Figure 25 illustrates a graph of Small-Signal Overshoot vs Capacitive Load for several values of RS. Also see
Applications Bulletin: Feedback Plots Define Op Amp AC Performance for details of analysis techniques and
application circuits.
R1
R2
SIGNAL DISTORTION
R1
R2
R3
GAIN
+1
GAIN
101
¥
1 kW
10 W
R3
OPA1662-Q1
VO = 3 VRMS
-1
101
4.99 kW 4.99 kW 49.9 W
549 W 4.99 kW 49.9 W
R2
R1
Signal Gain = 1+
+10
110
R2
Distortion Gain = 1+
R1 II R3
Generator
Output
Analyzer
Input
Audio Precision
System Two(1)
Load
with PC Controller
(1) For measurement bandwidth, see Figure 7 through Figure 12.
Figure 47. Distortion Test Circuit
8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress
event. Figure 48 illustrates the ESD circuits contained in the OPA1662-Q1 (indicated by the dashed line area).
The ESD protection circuitry involves several current-steering diodes connected from the input and output pins
and routed back to the internal power-supply lines, where they meet at an absorption device internal to the
operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device internal to the OPA1662-Q1 triggers when a fast ESD voltage pulse is impressed across
the supply pins. Once triggered, it quickly activates, clamping the ESD pulse to a safe voltage level.
When the operational amplifier connects into a circuit such as that illustrated in Figure 48, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occurs, there is a risk that some of the internal ESD protection circuits may be biased on, and
conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption
device.
Figure 48 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, TI recommends that applications limit the input current to
10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings. In extreme but rare cases, the absorption
device triggers on while +VS and –VS are applied. If this event happens, a direct current path is established
between the +VS and –VS supplies. The power dissipation of the absorption device is quickly exceeded, and the
extreme internal heating destroys the operational amplifier.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, it depends on the supply characteristic while at 0 V, or at a
level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier
supply current may be supplied by the input source through the current steering diodes. This state is not a
normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then
the current through the steering diodes can become quite high. The current level depends on the ability of the
input source to deliver current, and any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be
added to the supply pins as shown in Figure 48.
The Zener voltage must be selected such that the diode does not turn on during normal operation. However, its
Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above the
safe operating supply voltage level.
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TVS
RF
+VS
+V
OPA1662-Q1
RI
ESD Current-
Steering Diodes
-In
Out
Op-Amp
Core
RS
+In
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
-V
-VS
TVS
(1) VIN = +VS + 500 mV.
Figure 48. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application (Single
Channel Shown)
8.4 Device Functional Modes
The OPA1662-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
3 V (±1.5 V). The maximum power supply voltage for the OPA1662-Q1 is 36 V (±18 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPA1662-Q1 is a unity-gain stable, precision dual op amp with very low noise. Applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate. Figure 43 shows a simplified schematic of the OPA1662-Q1 (one channel shown) while
Figure 49 shows an additional application idea.
9.2 Typical Application
820 W
R
2200 pF
C
+VA
(+15 V)
0.1 mF
330 W
IOUTL+
OPA1662-Q1
R3
2700 pF
C2
-VA
(-15 V)
680 W
620 W
0.1 mF
+VA
(+15 V)
0.1 mF
R1
R2
Audio DAC
with Differential
Current
Outputs
100 W
L Ch
Output
820 W
OPA1662-Q1
PCM1794A-Q1
8200 pF
VO
C1
2200 pF
-VA
(-15 V)
0.1 mF
0.1 mF
+VA
(+15 V)
680 W
620 W
R1
R2
IOUTL-
OPA1662-Q1
2700 pF
R3
330 W
C2
-VA
(-15 V)
0.1 mF
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Figure 49. Audio DAC Current to Voltage Converter and Output Filter
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Typical Application (continued)
9.2.1 Design Requirements
Table 1 lists the design parameters for this example.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Supply voltage
±15 V to ±36 V
0 mA to 30 mA
1%
Differential input currents
Resistors value tolerance
Ceramic capacitor
XR5 or XR7 50 V
9.2.2 Detailed Design Procedure
This circuit is designed for converting differential input current into a single ended output voltage. The resistor
values are chosen to be relatively low for minimizing the total circuit noise. The filtering capacitors are chosen to
maintain adequate bandwidth from 10 Hz to 20 kHz for audio signals.
The first stage converts the audio DAC output current into a voltage with a gain calculated by Equation 1:
R
1+ RCS
where
•
•
•
R = 820 Ω
C = 2200 pF
S is Laplace variable
(1)
1
2pRC
RC filters the audio DAC output ripple and cutoff frequency =
= 80 KHz
The second differential stage transfer function is calculated by Equation 2:
æ
ç
ç
ö
÷
÷
R3
R1
1
R2R3
ç
÷
1+
C2S + 2R2R3C1C2S2
ç
÷
R1/ /R2 / /R3
è
ø
(2)
R2R3
1+
C2S + 2R2R3C1C2S2
The denominator of this transfer function
general form is calculated by Equation 3:
R1/ /R2 / /R3
is a quadratic equation and the
S
S2
1+
+
2
Qwo
Qwo
where
•
•
ωo = 2πFo is the resonance frequency
and Q is the quality factor
(3)
(4)
(5)
The gain peak depends on the quality factor in Equation 4:
C1
1
Q = R1/ /R2 / /R3 2
´
R2R3 C2
The resonance frequency is calculated by Equation 5:
1
wo = 2pFo =
2R2R3C1C2
These equations help to maintain adequate bandwidth and keep the differential gain flat so the quality factor is
from 0.7 to 1. The resonance frequency must be at least twice the desired bandwidth.
The chosen components give a quality factor of 0.89 and a resonance frequency of 53 KHz.
Copyright © 2012–2016, Texas Instruments Incorporated
21
OPA1662-Q1
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
www.ti.com.cn
The overall transfer function is shown in Equation 6:
vo
R
R3
1
= ´
IoutL + - IoutL - 1+ RCS R1
´
R2R3
1+
C2S + 2R2R3C1C2S2
R1/ /R2 / /R3
(6)
RR3
DC gain =
The
1 and is 398 mV/mA.
The poles are at 53 KHz and 80 KHz.
9.2.3 Application Curves
CH1 = positive input current IOUTL+ = 1.5 V / 150 Ω
CH2 = negative input current IOUTL– = 1.5 V / 150 Ω
CH3 = output single-ended voltage
CH1 = positive input current IOUTL+ = 1.5 V / 150 Ω
CH2 = negative input current IOUTL– = 1.5 V / 150 Ω
CH3 = output single-ended voltage
Figure 50. Output Voltage at 10 mApp and 10 Hz
Figure 51. Output Voltage at 10 mApp and 20 KHz
10 Power Supply Recommendations
The OPA1662-Q1 is specified for operation from 3 V to 36 V (±1.5 V to 18 V) and at an ambient operating
temperature from –40°C to 85°C. Parameters that can exhibit significant variance with regard to operating
voltage or temperature are presented in Typical Characteristics.
11 Layout
11.1 Layout Guidelines
The OPA1662-Q1 is a unity-gain stable, precision dual op amp with very low noise. To realize the full operational
performance of the device, good high-frequency printed-circuit board (PCB) layout practices are required. Low-
loss, 0.1-µF bypass capacitors must be connected between each supply pin and ground as close to the device
as possible. The bypass capacitor traces must be designed for minimum inductance.
22
Copyright © 2012–2016, Texas Instruments Incorporated
OPA1662-Q1
www.ti.com.cn
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
11.2 Layout Example
1
2
3
4
8
7
6
5
0.1 mF
0.1 mF
Dbꢀ plan
Figure 52. Layout Recommendation
11.3 Power Dissipation
The OPA1662-Q1 op amp is capable of driving 2-kΩ loads with a power-supply voltage up to ±18 V and full
operating temperature range. Internal power dissipation increases when operating at high supply voltages.
Copper leadframe construction used in the OPA1662-Q1 op amp improves heat dissipation compared to
conventional materials. Circuit board layout can also help minimize junction temperature rise. Wide copper traces
help dissipate the heat by acting as an additional heat sink. Temperature rise can be further minimized by
soldering the devices to the circuit board rather than using a socket.
版权 © 2012–2016, Texas Instruments Incorporated
23
OPA1662-Q1
ZHCSA99C –JULY 2012–REVISED AUGUST 2016
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
《应用 公告：反馈曲线图定义运算放大器交流性能》(SBOA015)
《用于电流输出音频 DAC 的高功率高保真耳机放大器参考设计》(TIDU672)
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
24
版权 © 2012–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1662AIDGKRQ1
OPA1662AIDRQ1
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
OUUI
O1662Q
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1662AIDGKRQ1
OPA1662AIDRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
6.4
3.4
5.2
1.4
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA1662AIDGKRQ1
OPA1662AIDRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
366.0
356.0
364.0
356.0
50.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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