OPA1671IDBVR [TI]
单电源、高带宽 (13MHz)、低噪声 (7nV/RtHz)、RRIO 音频运算放大器 | DBV | 5 | -40 to 125;
| 型号： | OPA1671IDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单电源、高带宽 (13MHz)、低噪声 (7nV/RtHz)、RRIO 音频运算放大器 | DBV | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总32页 (文件大小：1766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA1671
ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
OPA1671 13MHz、低噪声、轨至轨、音频运算放大器
1 特性
3 说明
1
•
低噪声：
频率为 10kHz 时为 4nV/√Hz
频率为 1kHz 时为 4.7fA/√Hz
OPA1671 是一款宽带宽、低噪声、低失真音频运算放
大器，可提供轨至轨输入和输出操作。该器件可提供低
电压噪声、电流噪声和输入电容的完美组合，从而能够
在各种音频和工业 应用中提供高性能。OPA1671 的独
特内部拓扑可提供极低的失真 (-109dB)，同时仅消耗
940µA 的电源电流。OPA1671 的高带宽 (13MHz) 和
高压摆率 (5V/µs) 使该器件成为高增益音频和工业信号
调节的绝佳选择。
•
•
•
•
•
低失真：-109dB (0.00035%)
宽增益带宽：13MHz
轨至轨输入和输出
低电源电压运行范围：1.7V 至 5.5V
低输入电容
–
–
差模：6pF
OPA1671 采用 SC-70 和 SOT-23 封装，可在 –40°C
至 +125°C 的工业温度范围内正常工作。
共模：2.5pF
•
•
•
低输入偏置电流：10pA
器件信息(1)
低功耗电源电流：940µA
行业标准封装：SC-70 和 SOT-23
器件型号
OPA1671
封装
SC-70 (5)
SOT-23 (5)
封装尺寸（标称值）
2.00mm × 1.25mm
2.90mm × 1.60mm
2 应用
•
•
•
•
•
麦克风前置放大器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
辅助线路输入和输出
有源滤波器电路
跨阻放大器
电压缓冲器
驻极体麦克风前置放大器
OPA1671 电压噪声密度
5 V
1000
1.58 kΩ
10 µF
10 kΩ
10 µF
100 kΩ 5 V
100
10
1
Electret
Microphone
OPA1671
+
Output
Microphone
Cable
œ
100 kΩ
10 µF
10 µF
499 kΩ
4.9 kΩ
15 pF
10
100
1k
Frequency (Hz)
10k
100k
OPA1
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS931
OPA1671
ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
8
9
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 17
Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 器件支持................................................................ 20
11.2 文档支持................................................................ 20
11.3 接收文档更新通知 ................................................. 20
11.4 社区资源................................................................ 20
11.5 商标....................................................................... 21
11.6 静电放电警告......................................................... 21
11.7 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (January 2019) to Revision B
Page
•
•
已添加 向数据表中添加了 SOT-23 (DBV) 封装和相关内容 .................................................................................................... 1
Added input offset voltage specification for VCM = (V+), (V–)................................................................................................. 5
Changes from Original (November 2018) to Revision A
Page
•
已更改 将预告信息（预览）更改为生产数据（正在供货）..................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
OPA1671
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ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
5 Pin Configuration and Functions
DBV and DCK Packages
5-Pin SOT-23 and SC-70
Top View
OUT
Vœ
1
2
3
5
V+
+IN
4
œIN
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
4
–IN
+IN
I
Inverting input
3
I
Noninverting input
OUT
V–
1
O
—
—
Output
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
Copyright © 2019, Texas Instruments Incorporated
3
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ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6
UNIT
V
Supply voltage, VS = (V+) – (V–)
Input voltage
(V–) –0.3
(V+) +0.3
V
Output short-circuit(2)
Continuous
Operating temperature, TA
Storage temperature, Tstg
–55
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
2000
500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7 (±0.85)
–40
NOM
MAX
5.5 (±2.75)
125
UNIT
V
Supply voltage, VS = (V+) – (V–)
Specified temperature, TA
°C
6.4 Thermal Information
OPA1671
THERMAL METRIC(1)
DBV (SOT-23)
DCK (SC-70)
5 PINS
214.7
127.1
60.0
UNIT
5 PINS
187.1
107.4
57.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
33.5
33.4
ΨJB
57.1
59.8
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
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ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
6.5 Electrical Characteristics
at VS = ±0.85 V to ±2.75 V (VS = 1.7 V to 5.5 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.00035%
–109
Total harmonic distortion
+ noise
THD+N
IMD
G = 1, f = 1 kHz, VO = 1 VRMS, VS = 5.5 V
dB
dB
dB
0.00158%
–96
SMPTE/DIN Two-Tone,
4:1, (60 Hz and 7 kHz)
Intermodulation distortion G = 1, VO = 1 VRMS, VS = 5.5 V
0.0005%
–106
CCIF Two-Tone (19 kHz
and 20 kHz)
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
13
5
MHz
Slew rate
4-V step, G = 1
V/μs
To 0.1%, 2-V step , G = 1
To 0.01%, 2-V step , G = 1
VIN × gain > VS
0.75
1
tS
Settling time
μs
μs
Overload recovery time
0.35
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
2.4
45
7
μVPP
Input voltage noise
density
eN
f = 1 kHz
nV/√Hz
fA/√Hz
f = 10 kHz
f = 1 kHz
4.0
4.7
iN
Input current noise
OFFSET VOLTAGE
VCM = (V+)
VCM = (V–)
±1.6
±1.6
VOS
Input offset voltage
mV
±0.25
±0.25
±0.3
±1.25
TA = –40°C to 125°C
TA = –40°C to 125°C
dVOS/dT
PSRR
Input offset voltage drift
±2.2
μV/°C
μV/V
Input offset voltage versus
power supply
VCM = (V–)
±30
±130
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
±10
±10
pA
V
IOS
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
V–
V+
VS = 1.7 V, (V–) < VCM < (V+) – 1.25 V
VS = 5.5 V, (V–) < VCM < (V+) – 1.25 V
VS = 1.7 V, VCM = 0 V to 1.7 V
74
80
60
68
91
96
Common-mode rejection
ratio
CMRR
dB
88
VS = 5.5 V, VCM = 0 V to 5.5 V
102
INPUT CAPACITANCE
1013 || 6
ZID
Differential
MΩ || pF
GΩ || pF
1013 || 2.5
ZICM
Common-mode
OPEN-LOOP GAIN
97
97
113
106
112
105
(V–) + 50 mV < VO < (V+) –
50 mV, RL = 10 kΩ
TA = –40°C to 125°C
TA = –40°C to 125°C
AOL
Open-loop voltage gain
dB
(V–) + 200 mV < VO < (V+) –
200 mV, RL = 2 kΩ
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ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
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Electrical Characteristics (continued)
at VS = ±0.85 V to ±2.75 V (VS = 1.7 V to 5.5 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Voltage output swing from
rail
VS = 5.5 V, RL = 10 kΩ
10
20
mV
mA
Sinking, VS = 5.5 V
Sourcing, VS = 5.5 V
–57
66
ISC
Short-circuit current
POWER SUPPLY
Quiescent current per
IO = 0 mA
0.94
1.3
1.4
IQ
mA
amplifier
IO = 0 mA, TA = –40°C to 125°C
6
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ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
6.6 Typical Characteristics
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
10
8
10
8
6
6
4
4
2
2
0
-1000
0
-1000
-500
0
500
1000
-500
0
500
1000
Offset Voltage (mV)
Offset Voltage (mV)
VOSH
VOSL
N = 9904
VS = ±2.75 V
N = 9904
VS = ±0.85 V
图 1. Offset Voltage Production Distribution
图 2. Offset Voltage Production Distribution
25
20
15
10
5
1250
1000
750
500
250
0
-250
-500
-750
-1000
-1250
0
-2.25
-1.5
-0.75
0
0.75
1.5
2.25
-50
-25
0
25
50
75
100
125
Offset Drift (mV/èC)
Temperature (èC)
vosd
vosv
N = 65
N = 5
5 typical units
图 3. Offset Voltage Drift Distribution
图 4. Offset Voltage vs Temperature
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
240
225
210
195
180
165
150
135
120
105
90
75
60
45
30
15
0
1250
1000
750
Gain
Phase
500
250
0
-250
-500
-750
-1000
-1250
100m
1
10
100
1k
Frequency (Hz)
10k 100k 1M
10M
-3 -2.4 -1.8 -1.2 -0.6
0
Common-mode Voltage (V)
0.6 1.2 1.8 2.4
3
Aol_
vosv
N = 65
图 5. Offset Voltage vs Common Mode Voltage
图 6. Open-Loop Gain and Phase vs Frequency
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
2
50
40
30
20
10
0
G = +1
0
G = -1
G = +10
G = +100
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
IB-
IB+
IOS
-10
-20
1k
10k
100k
Frequency (Hz)
1M
10M
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D006
ibvs
图 7. Closed-Loop Gain and Phase vs Frequency
图 8. Input Bias Current vs Temperature
0
3
-40èC
25èC
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
-1.5
-1.8
-2.1
-2.4
-2.7
-3
85èC
125èC
-40èC
25èC
85èC
125èC
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
Output Current (mA)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
Output Current (mA)
claw
claw
VS = ±2.75 V
VS = ±2.75 V
图 9. Output Voltage Swing vs Sourcing Output Current
图 10. Output Voltage Swing vs Sinking Output Current
(Maximum Supply)
(Maximum Supply)
100
CMRR
80
60
40
20
Time (1 s/div)
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D027
D007
图 12. 0.1-Hz to 10-Hz Noise
图 11. CMRR vs Frequency
8
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ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
Typical Characteristics (接下页)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
1000
100
10
0.01
0.001
0.0001
1E-5
-80
G = -1
G = +1
-100
-120
-140
1
10
100
1k
Frequency (Hz)
10k
100k
100
1k
Frequency (Hz)
10k
OPA1
OPA1
BW = 80 kHz
VO = 1 VRMS
图 13. Input Voltage Noise Spectral Density
图 14. THD+N Ratio vs Frequency
vs Frequency
1
0.1
-40
1
0.1
-40
RL = 600 W
RL = 2 kW
RL = 10 kW
RL = 600 W
RL = 2 kW
RL = 10 kW
-60
-60
0.01
-80
0.01
-80
0.001
-100
-120
0.001
-100
-120
0.0001
0.0001
1m
10m 100m
Output Amplitude (VRMS
1
1m
10m 100m
Output Amplitude (VRMS
1
)
)
D010
D010
Gain = 1
BW = 80 kHz
Gain = –1
BW = 80 kHz
fTEST = 1 kHz
fTEST = 1 kHz
图 15. THD+N vs Output Amplitude
图 16. THD+N vs Output Amplitude
1.4
1.2
1
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
0.5 0.75
1
1.25 1.5 1.75
Supply Voltage (V)
2
2.25 2.5 2.75
Temperature (èC)
iqvs
iqvs
5 typical units
5 typical units
图 18. Quiescent Current vs Supply
图 17. Quiescent Current vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
1000
100
10
130
120
110
100
90
1
10
1
10
100
1k 10k 100k
Frequency (Hz)
1M
10M 100M
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
aolv
Open
图 19. Open-Loop Gain vs Temperature
图 20. Open-Loop Output Impedance vs Frequency
60
50
40
30
20
10
0
VIN (V)
VOUT (V)
RISO = 0 W
RISO = 24.9 W
RISO = 49.9 W
Time (100 ms/div)
10
100
Capactiance (pF)
1000 2000
D033
D031
10-mV Step
图 22. No Phase Reversal
图 21. Small-Signal Overshoot vs Capacitive Load
VIN
VOUT
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
D034
D034
图 23. Positive Overload Recovery
图 24. Negative Overload Recovery
10
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
VIN
VOUT
VIN
VOUT
Time (1 ms/div)
Time (1 ms/div)
D035
D035
10-mV step
G = +1
10-mV step
G = –1
图 25. Small-Signal Step Response
图 26. Small-Signal Step Response
75
70
65
60
55
50
45
40
35
Falling
Rising
Sinking
Sourcing
Time (1 ms/div)
-50
-25
0
25
50
75
100
125
Temperature (èC)
D037
iscv
2-V Step
图 27. Settling Time
图 28. Short-Circuit Current vs Temperature
8
Vs = ê2.75 V
Vs = ê0.85 V
6
4
2
0
100
1k
10k 100k
Frequency (Hz)
1M
10M
D012
图 29. Maximum Output Voltage vs Frequency
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7 Detailed Description
7.1 Overview
The OPA1671 is a rail-to-rail input, very low noise operational amplifier (op amp). The OPA1671 operates from
1.7 V to 5.5 V, is unity-gain stable, and is designed for a wide range of audio and general-purpose applications.
The OPA1671 strengths also include 13-MHz bandwidth and 4.0-nV/√Hz noise spectral density, with very low
input bias current (10 pA). These strengths make the OPA1671 a great choice for a preamplifier in microphone
circuits, sensor modules and buffering high-fidelity, digital-to-analog converters (DACs).
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN-
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V-
(Ground)
12
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7.3 Feature Description
7.3.1 Operating Voltage
The OPA1671 op amp can be used with single or dual supplies from an operating range of VS = 1.7 V (±0.85 V)
up to 5.5 V (±2.75 V).
CAUTION
Supply voltages greater than 6 V can permanently damage the device (see Absolute
Maximum Ratings)
Key parameters that vary over the supply voltage or temperature range are shown in the Typical Characteristics
section.
7.3.2 Input Bias Current
Typically, input bias current is approximately ±10 pA. Input voltages exceeding the power supplies, however, can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in 图 30.
Unlike many operational amplifiers, there are no diodes connected between the positive and negative input
terminals. As a result, differential voltages up to the full supply voltage do not cause any significantly higher
current flow into the inputs.
Current-limiting resistor
required if input voltage
exceeds supply rails by
> 0.3 V.
+5 V
IOVERLOAD
10 mA max
VOUT
VIN
5 kΩ
图 30. Input Current Protection
7.3.3 Common-Mode Voltage Range
The OPA1671 features true rail-to-rail inputs, allowing full common mode operation from the negative supply
voltage to the positive supply voltage. This full common mode operation is achieved with complimentary N-
channel and P-channel differential input pairs. The N-channel pair is active for input voltages close to the positive
rail, typically (V+) – 1.25 V to (V+) The P-channel is active for common-mode inputs from (V–) to (V+) – 1.25 V.
There is a small transition region, typically from (V+) – 1.25 V to (V+) – 1 V. In this region, the offset voltage
transitions between the P-channel and N-channel offset values. 图 5 shows the difference between offset in the P
and N regions.
版权 © 2019, Texas Instruments Incorporated
13
OPA1671
ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
Feature Description (接下页)
7.3.4 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to EMI. If conducted EMI enters the operational amplifier, the dc
offset at the amplifier output can shift from its nominal value when EMI is present. This shift is a result of signal
rectification associated with the internal semiconductor junctions. Although all operational amplifier pin functions
can be affected by EMI, the input pins are likely to be the most susceptible. The OPA1671 operational amplifier
incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both common-mode and
differential-mode filtering are provided by the input filter. The filter is designed for a cutoff frequency of
approximately 20 MHz (–3 dB), with a rolloff of 20 dB per decade.
120
100
80
60
40
20
10M
100M
Frequency (Hz)
1G
10G
EMIR
图 31. OPA1671 EMIRR vs Frequency
表 1. OPA1671 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
30 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
38 dB
60 dB
59 dB
90 dB
100 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
7.4 Device Functional Modes
The OPA1671 has a single functional mode and is operational when the power-supply voltage is greater than 1.7
V (±0.85 V). The maximum specified power-supply voltage for the OPA1671 is 5.5 V (±2.75 V).
14
版权 © 2019, Texas Instruments Incorporated
OPA1671
www.ti.com.cn
ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA1671 is a low-noise, rail-to-rail input and output operational amplifier specifically designed for portable
applications. The device operates from 1.7 V to 5.5 V, is unity-gain stable, and suitable for a wide range of audio
and general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to
any point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
OPA1671 device to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes the device a great choice
for driving sampling analog-to-digital converters (ADCs).
8.1.1 Capacitive Loads
The dynamic characteristics of the OPA1671 amplifiers are optimized for commonly encountered gains, loads,
and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the
phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads
must be isolated from the output. Add a small resistor (for example, RS = 50 Ω) in series with the output to isolate
heavier capacitive loads.
8.1.2 Noise Performance
图 31 shows the total circuit noise for varying source impedances with the operational amplifier in a unity-gain
configuration (with no feedback resistor network and therefore no additional noise contributions). The op amp
itself contributes a voltage noise component and a current noise component. The voltage noise is commonly
modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying
component of the input bias current and reacts with the source resistance to create a voltage component of
noise. For a CMOS-input device, the noise resulting from the input current is negligible; therefore, the total noise
is dominated by the voltage noise of the OPA1671 at low source resistance, and the resistor noise > 1 kΩ.
图 31 shows the calculation of the total circuit noise, with these parameters:
•
•
•
•
en = voltage noise
RS = source impedance
k = Boltzmann's constant = 1.38 × 10–23 J/K
T = temperature in kelvins (K)
For more details on calculating noise, see Basic Noise Calculations.
200
Source Resistor Noise
OPA1671 Voltage Noise
Total Noise
100
70
50
30
20
10
7
5
3
2
1
1
2 3 5 10 20
100
1000
10000 100000 1000000
Source Resistance (W)
OPA1
图 32. Noise Performance of the OPA1671 in a Unity-Gain Buffer Configuration
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15
OPA1671
ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
Application Information (接下页)
8.1.3 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in 图 31. The source impedance is typically fixed; consequently, select the op
amp and the feedback resistors to minimize the respective contributions to the total noise.
图 33 shows noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations
with gain, the feedback network resistors contribute noise. In general, the current noise of the op amp reacts with
the feedback resistors to create additional noise components.
The selected feedback resistor values make these noise sources negligible. Low impedance feedback resistors
load the output of the amplifier. The equations for total noise are shown for both configurations.
(A) Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
42
41 „ 42
2
2
2
2
¨
: ;
1
:
;
:
;
:
;
>
?
84/5
'
1
= l1 + p „ A5 + A0 + kA4 2 o + E0 „ 45 + lE0 „ d
hp
æ4
1
41
41 + 42
GND
œ
EO
8
: ;
2
A = 4 „ G$ „ 6(-) „ 45
d
h
¥
Thermal noise of RS
+
5
*V
¾
RS
41 „ 42
8
: ;
3
A4
= ¨4 „ G$ „ 6(-) „ d
2
h
d
h
Thermal noise of R1 || R2
æ4
1
41 + 42
*V
¾
+
,
h
VS
Source
GND
G$ = 1.38065 „ 10F23
: ;
4
d
œ
Boltzmann Constant
-
Temperature in kelvins
: ;
>
?
-
5
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
:
;
42
45 + 41 „ 42
'
1
= l1 +
p „ A0 2 + kA4
o2 + FE0 „ H
+4 æ4
5 2
IG
¨
: ;
6
:
;
>
84/5
?
1
45 + 41
45 + 41 + 42
RS
œ
EO
:
;
45 + 41 „ 42
8
+
: ;
7
¨
4 „ G$ „ 6(-) „ H
A4
=
I
d
h
Thermal noise of (R1 + RS) || R2
+4 æ4
5
1
2
45 + 41 + 42
*V
¾
+
VS
œ
,
GND
G$ = 1.38065 „ 10F23
d
h
: ;
8
Boltzmann Constant
Source
GND
-
: ;
9
>
?
6(-) = 237.15 + 6(°%)
-
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
(1) eN is the voltage noise of the amplifier. For the OPA1671 series of operational amplifiers, eN = 4.0 nV/√Hz at 10 kHz.
(2) iN is the current noise of the amplifier. For the OPA1671 series of operational amplifiers, iN = 4.5 fA/√Hz at 1 kHz.
(3) For additional resources on noise calculations, see TI's Precision Labs Series.
图 33. Noise Calculation in Gain Configurations
16
版权 © 2019, Texas Instruments Incorporated
OPA1671
www.ti.com.cn
ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
8.2 Typical Application
This design uses an OPA1671 as a preamplifier for an electret microphone. Electret microphone types are
common in many audio applications of varying performance levels. The OPA1671 offers very low noise in a tiny
package, and is designed for use in electret preamplifier circuits.
图 34 shows the solution.
5 V
R1
1.58 kΩ
C1
10 µF
5 V
R2
10 kꢀ
R3
100 kꢀ
Electret
Microphone
OPA1671
+
Output
Microphone
Cable
C2
1 µF
œ
R4
100 kꢀ
C5
10 µF
R6
499 kΩ
C3
10 µF
R5
4.9 kΩ
C4
15 pF
图 34. Electret Preamplifier Schematic
8.2.1 Design Requirements
This solution has the following requirements:
•
•
•
•
•
Supply voltage: 5 V
Gain: 100 V/V
Frequency response: 3 dB from 20 Hz to 20 kHz
Output: 2.5 V ±1 V
Output noise density: < 1 µV/√Hz at 10 kHz
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17
OPA1671
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www.ti.com.cn
Typical Application (接下页)
8.2.2 Detailed Design Procedure
The preamplifier circuit uses a noninverting gain configuration to allow for high input impedance, with
independent gain-setting resistor values. DC bypass is accomplished with C2 and C3, with the low frequency
poles set by C2, R4, C3 and R5; see 公式 1 and 公式 2.
1
pL1
=
= 3.18 Hz
2p ∂ R || R ∂C
2
3
4
(1)
(2)
1
pL2
=
= 3.23 Hz
2p ∂R5 ∂C2
The filter cutoff frequency is determined by a higher frequency pole, set by R5 and C4.
1
pH
=
= 21.3 kHz
2p ∂R6 ∂C4
(3)
The gain of the circuit in the passband is set by R5 and R6.
R6
A V/V =
= 100 40 dB
(
)
(
)
R5
(4)
The ouput noise of the circuit (ignoring the electret microphone intrinsic noise and impedance) is the RSS
average noise contribution from R5 and the input voltage noise of OPA1671. R5 was selected for minimal noise
contribution without requiring a dc blocking cap. (C3) larger than 10 µF. See 公式 5 for the output noise density
calculation at 10 kHz.
eN_OUT = Input Referred Noise∂Gain = 4kTR 2 + VN_10k ∂100 = 0.96 ꢀV/ Hz
2
(
)
5
(5)
8.2.3 Application Curves
50
45
40
35
30
25
20
15
10
5
10
8
6
4
0
-5
2
-10
-15
-20
0
1
2 3 5 710 20 50 100 1000
Frequency (Hz)
10000
100000
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
OPTA1
OPA1
图 35. Electret Microphone Preamplifier Transfer Function
图 36. Electret Microphone Preamplifier Output Noise
Density
18
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OPA1671
www.ti.com.cn
ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
9 Power Supply Recommendations
The OPA1671 device is specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V).
10 Layout
10.1 Layout Guidelines
Paying attention to good layout practice is always recommended. Keep traces short and, when possible, use a
printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as
possible. Place a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout
the analog circuit to improve performance and provide benefits such as reducing the electromagnetic interference
(EMI) susceptibility.
10.2 Layout Example
Minimize
parasitic
inductance by
placing bypass
capacitor close
CBYPASS
VOUT
to V+.
OUT
V+
V-
+IN -IN
Keep high
impedance
input signal
away from
noisy traces.
VIN
RF
Route trace
under package
for output to
feedback
resistor
connection.
图 37. OPA1671 Layout Example
版权 © 2019, Texas Instruments Incorporated
19
OPA1671
ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA-TI™ 是一款基于 SPICE 引擎的电路仿真程序，简单易用并且功能强大。TINA-TI™ 是 TINA™软件的一款免
费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI™ 提供所有传统
的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI™ 提供全面的后处理能力，便于用户以多种方式获得结果，用户可从 Analog eLab Design Center（模拟
电子实验室设计中心）免费下载。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的功能，从而构建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI™ 软件。请下载 TINA-
TI™ 文件夹中的免费 TINA-TI™ 软件。
11.2 文档支持
11.2.1 相关文档
如需相关文档，请参阅：
•
•
德州仪器 (TI)，《电路板布局技巧》
德州仪器 (TI)，《模拟工程师电路设计指导手册》
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
20
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OPA1671
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ZHCSJ01B –JANUARY 2019–REVISED AUGUST 2019
11.5 商标
TINA-TI, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1671IDBVR
OPA1671IDBVT
OPA1671IDCKR
OPA1671IDCKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1X6T
1X6T
1D3
Samples
Samples
Samples
Samples
NIPDAU | SN
NIPDAU
SC70
NIPDAU
1D3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1671IDBVR
OPA1671IDBVT
OPA1671IDCKR
OPA1671IDCKT
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
3000
250
180.0
180.0
178.0
178.0
8.4
8.4
9.0
9.0
3.2
3.2
2.4
2.4
3.2
3.2
2.5
2.5
1.4
1.4
1.2
1.2
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
3000
250
SC70
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA1671IDBVR
OPA1671IDBVT
OPA1671IDCKR
OPA1671IDCKT
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
3000
250
210.0
210.0
190.0
190.0
185.0
185.0
190.0
190.0
35.0
35.0
30.0
30.0
3000
250
SC70
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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