OPA1688IDR [TI]
36V、10MHz、低失真高驱动轨到轨输出音频运算放大器 | D | 8 | -40 to 85;
| 型号： | OPA1688IDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 36V、10MHz、低失真高驱动轨到轨输出音频运算放大器 | D | 8 | -40 to 85 放大器 驱动 运算放大器 |
| 文件： | 总42页 (文件大小：3428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA1688
SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
OPA1688 36-V, Single-Supply, 10-MHz, Rail-to-Rail Output,
SoundPlus™ Audio Operational Amplifier
1 Features
3 Description
•
•
THD+N, 50 mW, 32 Ω, 1 kHz, –109 dB
Wide supply range:
The OPA1688 36-V, single-supply, low-noise
SoundPlus™ audio operational amplifier is capable of
operating on supplies ranging from 4.5 V (±2.25 V) to
36 V (±18 V). This latest addition of a high-voltage
audio operational amplifier in conjunction with the
OPA16xx devices provide a family of bandwidth,
noise, and power options to meet the needs of a wide
variety of applications. The OPA1688 is available in
a WSON micropackage, and offers low offset, drift,
and quiescent current. This device also offers wide
bandwidth, fast slew rate, and high output current
drive capability.
– 4.5 V to 36 V, ±2.25 V to ±18 V
Low offset voltage: ±0.25 mV
Low offset drift: ±0.5 µV/°C
Gain bandwidth: 10 MHz
Low input bias current: ±10 pA
Low quiescent current: 1.6 mA per amplifier
Low noise: 8 nV/√Hz
EMI- and RFI-filtered inputs
Input range includes negative supply
Input range operates to positive supply
Rail-to-rail output
High common-mode rejection: 120 dB
Packages:
•
•
•
•
•
•
•
•
•
•
•
•
Unlike most op amps that are specified at only one
supply voltage, the OPA1688 is specified from 4.5 V
to 36 V. Input signals beyond the supply rails do not
cause phase reversal. The input can operate 100 mV
below the negative rail and within 2 V of the top rail
during normal operation. Note that this device can
operate with full rail-to-rail input 100 mV beyond the
top rail, but with reduced performance within 2 V of
the top rail.
– Industry-standard SOIC-8
– micro WSON-8
2 Applications
•
•
•
•
•
•
•
•
•
Professional microphones and wireless systems
Professional audio mixer and control surface
Guitar amp and other music instrument amps
A/V receiver
Bookshelf stereo system
Professional audio amplifier (rack mount)
DJ equipment
The OPA1688 is specified from –40°C to +85°C.
Device Information
PART NUMBER
OPA1688
PACKAGE(1)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
SOIC (8)
WSON (8)
Turntable
Special function module
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
C1
1
-40
47pF
R1
768
R2
750
ROUT
0.1
-60
Inverting
–5 V
VAC
–
+
Headphone
Output
0.01
-80
+
OPA1688
VDC
Noninverting
16-ꢀ Load
VAC
R3
768
5 V
ROUT
0.001
-100
-120
32-ꢀ Load
C2
47pF
R4
ROUT
Audio DAC
750
128-ꢀ Load
0.0001
0.001
0.01
0.1
Amplitude (VRMS
1
10
Headphone Amplifier Circuit Configuration
)
C004
Superior THD Performance
(f = 1 kHz, BW = 80 kHz, VS = ±5 V)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1688
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................19
9 Applications and Implementation................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................26
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................28
12.1 Device Support....................................................... 28
12.2 Documentation Support.......................................... 28
12.3 Receiving Notification of Documentation Updates..28
12.4 Support Resources................................................. 28
12.5 Trademarks.............................................................29
12.6 Electrostatic Discharge Caution..............................29
12.7 Glossary..................................................................29
13 Mechanical, Packaging, and Orderable
Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (September 2015) to Revision A (June 2022)
Page
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added operating temperature to Recommended Operating Conditions table; moved from Electrical
Characteristics table........................................................................................................................................... 4
Deleted redundant power supply row from Electrical Characteristics table; content already listed in
Recommended Operating Conditions table........................................................................................................5
Deleted redundant specified temperature row from Electrical Characteristics table; content already listed in
Recommended Operating Conditions table........................................................................................................5
Deleted operating temperature row from Electrical Characteristics table; moved content to Recommended
Operating Conditions table................................................................................................................................. 5
•
•
•
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
5 Device Comparison Table
QUIESCENT CURRENT
GAIN BANDWIDTH PRODUCT
VOLTAGE NOISE DENSITY
(en)
DEVICE
OPA1688
OPA165x
OPA166x
(IQ)
(GBP)
10 MHz
18 MHz
22 MHz
1650 µA
2000 µA
1500 µA
8 nV/√Hz
4.5 nV/√Hz
3.3 nV/√Hz
6 Pin Configuration and Functions
+IN A
V+
1
2
3
4
8
7
6
5
-IN A
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
A
B
OUT B
-IN B
+IN B
OUT A
OUT B
-IN B
V-
+IN B
Figure 6-1. D (SOIC-8) Package, Top View
Figure 6-2. DRG (WSON-8) Package, Top View
Table 6-1. Pin Functions
PIN
NO.
D
DRG
NAME
–IN A
(SOIC)
(WSON)
TYPE
Input
DESCRIPTION
2
6
3
5
1
7
4
8
8
5
1
4
7
6
3
2
Inverting input, channel A
–IN B
+IN A
+IN B
OUT A
OUT B
V–
Input
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Output, channel A
Input
Input
Output
Output
Power
Power
Output, channel B
Negative (lowest) power supply
Positive (highest) power supply
V+
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage, VS
±20 (40, single supply)
Common-mode
Voltage(2)
(V–) – 0.5
(V+) + 0.5
V
Signal input pins
Output short circuit(3)
Temperature
Differential(4)
±0.5
V
Current
±10
mA
Continuous
150
Temperature range
Junction temperature
Storage, Tstg
–55
–65
°C
°C
°C
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Transient conditions that exceed these voltage ratings should be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
(4) See Section 8.4.2 section for more information.
7.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5 (±2.25)
–40
NOM
MAX
UNIT
V
Supply voltage, VS (V+ – V–)
Specified temperature
36 (±18)
85
°C
Operating temperature
–55
125
°C
7.4 Thermal Information
OPA1688
THERMAL METRIC(1)
D (SOIC)
DRG (WSON)
UNIT
8 PINS
116.1
69.8
8 PINS
63.2
63.5
36.5
1.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.5
ψJB
56.1
36.6
6.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
7.5 Electrical Characteristics
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.00005%
–126
G = 1, f = 1 kHz, VO = 3.5 VRMS , RL = 2 kΩ
G = 1, f = 1 kHz, VO = 3.5 VRMS , RL = 600 Ω
G = 1, f = 1 kHz, PO = 10 mW, RL = 128 Ω
G = 1, f = 1 kHz, PO = 10 mW, RL = 32 Ω
G = 1, f = 1 kHz, PO = 10 mW, RL = 16 Ω
dB
dB
dB
dB
dB
0.000051%
–126
0.000153%
–116
Total harmonic distortion
+ noise
THD+N
0.000357%
–109
0.000616%
–104
FREQUENCY RESPONSE
GBP
SR
Gain bandwidth product
G = 1
10
8
MHz
V/µs
MHz
ns
Slew rate
G = 1
Full-power bandwidth(1)
Overload recovery time
VO = 1 VPP
VIN × gain > VS
1.3
200
Channel separation
(dual)
f = 1 kHz
–120
3
dB
µs
tS
Settling time
To 0.1%, V S = ±18 V, G = 1, 10-V step
NOISE
En
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 100 Hz
2.5
14
8
µVPP
Input voltage noise
density(2)
en
in
nV/√Hz
f = 1 kHz
Input current noise
density
f = 1 kHz
1.8
fA/√Hz
OFFSET VOLTAGE
TA = 25°C
±0.25
±1.5
±1.6
±2
VOS
Input offset voltage
mV
TA = –40°C to +85°C
TA = –40°C to +85°C
dVOS/dT
PSRR
VOS over temperature(2)
±0.5
±1
µV/°C
µV/V
µV/V
Power-supply rejection
ratio
TA = –40°C to +85°C
At dc
±2.5
Channel separation, dc
0.1
INPUT BIAS CURRENT
TA = 25°C
±10
±3
±20
±1.5
±7
pA
nA
pA
pA
IB
Input bias current
TA = –40°C to +85°C
TA = 25°C
IOS
Input offset current
TA = –40°C to +85°C
±250
INPUT VOLTAGE RANGE
Common-mode voltage
VCM
(V–) – 0.1 V
(V+) – 2 V
V
range(3)
VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +85°C
90
104
120
Common-mode rejection
ratio
CMRR
dB
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +85°C
104
INPUT IMPEDANCE
Differential
Common-mode
100 || 7
6 || 1.5
MΩ || pF
1012Ω || pF
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
(V–) + 0.35 V < VO < (V+) – 0.35 V, RL = 10 kΩ,
TA = –40°C to +85°C
108
130
118
AOL
Open-loop voltage gain
dB
(V–) + 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ,
TA = –40°C to +85°C
OUTPUT
IL = ±1 mA
(V–) + 0.1 V
(V+) – 0.1 V
Voltage output swing
from rail
VO
VS = 36 V, RL = 10 kΩ
VS = 36 V, RL = 2 kΩ
70
90
mV
Ω
330
400
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A
60
ISC
Short-circuit current
Capacitive load drive
±75
mA
pF
CLOAD
See Section 7.6
POWER SUPPLY
IO = 0 A
1.6
1.8
2
Quiescent current per
amplifier
IQ
mA
IO = 0 A, TA = –40°C to +85°C
(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
(2) Specified by design and characterization.
(3) Common-mode range can extend to the top rail with reduced performance.
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7.6 Typical Characteristics
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 7-1. List of Typical Characteristics
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
Figure 7-1
Offset Voltage Drift Distribution
Figure 7-2
Offset Voltage vs Temperature (VS = ±18 V)
Offset Voltage vs Common-Mode Voltage (VS = ±18 V)
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Offset Voltage vs Power Supply
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Input Bias Current vs Common-Mode Voltage
Input Bias Current vs Temperature
Figure 7-7
Figure 7-8
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred-to-Input)
CMRR vs Temperature
Figure 7-9
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Figure 7-20
Figure 7-21
Figure 7-22
Figure 7-23
Figure 7-24
Figure 7-25, Figure 7-26
Figure 7-27, Figure 7-28
Figure 7-29, Figure 7-30
Figure 7-31
Figure 7-32
Figure 7-33
Figure 7-34
Figure 7-35
Figure 7-36
Figure 7-37
Figure 7-38
Figure 7-39
Figure 7-40
Figure 7-41
Figure 7-42
Figure 7-43
PSRR vs Temperature
0.1-Hz to 10-Hz Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
THD+N vs Frequency
THD+N vs Amplitude
Quiescent Current vs Temperature
Quiescent Current vs Supply Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (10 mV, G = –1)
Small-Signal Step Response (10 mV, G = 1)
Small-Signal Step Response (100 mV, G = –1)
Small-Signal Step Response (100 mV, G = 1)
Large-Signal Step Response (10 V, G = –1)
Large-Signal Step Response (10 V, G = 1)
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
No Phase Reversal
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
Channel Separation vs Frequency
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
7.6 Typical Characteristics
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
25
20
15
10
5
25
20
15
10
5
0
0
Offset Voltage Drift (µV/°C)
Offset Voltage (mV)
C013
C013
Distribution taken from 5185 amplifiers
Distribution taken from 47 amplifiers, TA = –40°C to +125°C
Figure 7-1. Offset Voltage Production Distribution
Figure 7-2. Offset Voltage Drift Production Distribution
250
200
150
100
50
225
150
75
VCM = 16 V
VCM = -18.1 V
0
0
œ50
œ100
œ150
œ200
œ250
œ75
œ150
œ225
œ75 œ50 œ25
0
25
50
75
100 125 150
œ20
œ15
œ10
œ5
0
5
10
15
20
Temperature (°C)
VCM (V)
C001
C001
5 typical units shown, VS = ±18 V
5 typical units shown, VS = ±18 V
Figure 7-3. Offset Voltage vs Temperature
Figure 7-4. Offset Voltage vs Common-Mode Voltage
20
10
500
400
Vs = 2.25 V
300
0
200
100
-10
-20
-30
-40
-50
0
œ100
œ200
œ300
œ400
œ500
14
15
16
17
18
0
2
4
6
8
10
12
14
16
18
VCM (V)
VSUPPLY (V)
C001
C001
5 typical units shown, VS = ±18 V
5 typical units shown, VS = ±2.25 V to ±18 V
Figure 7-6. Offset Voltage vs Power Supply
Figure 7-5. Offset Voltage vs Common-Mode Voltage (Upper
Stage)
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7.6 Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
12
10
8
8000
5500
3000
500
IB+
IB -
IbP
Ios
6
IbN
4
2
0
Ios
œ2
œ4
œ2000
-18 -13.5
-9
-4.5
0
4.5
9
13.5
18
œ50
œ25
0
25
50
75
100
125
150
VCM (V)
Temperature (°C)
C001
C001
TA = 25°C
Figure 7-7. Input Bias Current vs Common-Mode Voltage
Figure 7-8. Input Bias Current vs Temperature
(V+) +1
140
(V+)
(V+) -1
(V+) -2
(V+) -3
(V+) -4
(V+) -5
(V-) +5
(V-) +4
(V-) +3
(V-) +2
(V-) +1
(V-)
25°C
CMRR
PSRR+
120
100
80
60
40
20
0
40°C
125°C
85°C
PSRR-
85°C
125°C
40°C
25°C
(V-) -1
1
10
100
1k
10k
100k
1M
0
10
20
30
40
50
60
70
80
90 100
Frequency (Hz)
C006
C011
Output Current (mA)
Figure 7-10. CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 7-9. Output Voltage Swing vs Output Current (Maximum
Supply)
30
10
8
20
VS
=
2.25 V, -2.35 V ≤ VCM ≤ 0.25 V
6
10
0
4
2
0
VS = ±18 V, -18.1 V ≤ VCM ≤ 16 V
œ10
œ2
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C001
C001
Figure 7-11. CMRR vs Temperature
Figure 7-12. PSRR vs Temperature
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7.6 Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1000
100
10
1
Time (1 s/div)
0.1
1
10
100
1k
10k
100k
C001
C002
Frequency (Hz)
Peak-to-peak noise = 1.70 µVPP
Figure 7-13. 0.1-Hz to 10-Hz Noise
Figure 7-14. Input Voltage Noise Spectral Density vs Frequency
0.01
0.001
-80
1.
-40
G = +1 V/V, 10-kꢀ Load
G = +1 V/V, 2-kꢀ Load
G = -1 V/V, 10-kꢀ Load
G = -1 V/V, 2-kꢀ Load
G = -1 V/V, 600-ꢀ Load
G = +1 V/V, 600-ꢀ Load
G = +1 V/V, 10-kꢀ Load
G = +1 V/V, 2-kꢀ Load
G = +1 V/V, 600-ꢀ Load
G = -1 V/V, 10-kꢀ Load
G = -1 V/V, 2-kꢀ Load
G = -1 V/V, 600-ꢀ Load
0.1
-60
-100
-120
-140
0.01
-80
0.001
0.0001
0.00001
-100
-120
-140
0.0001
0.00001
10
100
1k
10k
0.01
0.1
1
10
Frequency (Hz)
Output Amplitude (VRMS)
C007
C008
VOUT = 3.5 VRMS, BW = 50 kHz
f = 1 kHz, BW = 80 kHz
Figure 7-15. THD+N Ratio vs Frequency
Figure 7-16. THD+N vs Output Amplitude
0.1
0.01
-60
1
0.1
-40
G = -1, 16-ꢀ Load
G = -1, 32-ꢀ Load
G = -1, 128-ꢀ Load
G = +1, 16-ꢀ Load
G = +1, 32-ꢀ Load
G = +1, 128-ꢀ Load
-60
-80
Inverting
0.01
-80
Noninverting
0.001
0.0001
-100
-120
16-ꢀ Load
32-ꢀ Load
128-ꢀ Load
0.001
-100
-120
0.0001
0.001
0.01
0.1
1
10
10
100
1000
10000
Amplitude (VRMS
)
Frequency (Hz)
C004
C003
f = 1 kHz, BW = 80 kHz, VS = ±5 V
POUT = 10 mW, BW = 80 kHz, VS = ±5 V
Figure 7-18. THD+N vs Amplitude
Figure 7-17. THD+N vs Frequency
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7.6 Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
2
1.8
1.6
1.4
1.2
1
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
Vs = 18 V
Vs = 2.25 V
œ75 œ50 œ25
0
25
50
75
100 125 150
0
4
8
12
16
20
24
28
32
36
Temperature (°C)
Supply Voltage (V)
C001
C001
Figure 7-19. Quiescent Current vs Temperature
Figure 7-20. Quiescent Current vs Supply Voltage
140
120
100
80
180
25
20
15
10
5
135
90
45
0
Open-loop Gain
Phase
60
0
40
-5
20
-10
G = +1
0
-15
-20
G = -10
G = -1
œ20
1
10
100
1k
10k
100k
1M
10M
1000
10k
100k
1M
10M
C003
Frequency (Hz)
Frequency (Hz)
C004
CLOAD = 15 pF
Figure 7-22. Closed-Loop Gain vs Frequency
Figure 7-21. Open-Loop Gain and Phase vs Frequency
2
1000
1.5
100
10
1
1
Vs = 4.5 V
0.5
Vs = 36 V
0
-0.5
-1
0
œ75 œ50 œ25
0
25
50
75
100 125 150
10
100
1k
10k
100k
1M
10M
100M
Temperature (°C)
Frequency (Hz)
C001
C016
RL = 10 kΩ
Figure 7-23. Open-Loop Gain vs Temperature
Figure 7-24. Open-Loop Output Impedance vs Frequency
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7.6 Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
60
50
40
30
20
10
0
50
40
30
20
10
0
ROUT = 0 ꢀ
ROUT= 0 ꢀ
R = 25 ꢀ
RO = 25
OUT
R
= 25 ꢀ
RO = 25
OUT
RRO = 5=050 ꢀ
OUT
RO = 50
ROUT= 50 ꢀ
0
100
200
300
400
500
0
100
200
300
400
500
Capacitive Load (pF)
Capacitive Load (pF)
C013
C013
G = –1
G = 1
Figure 7-25. Small-Signal Overshoot vs Capacitive Load
Figure 7-26. Small-Signal Overshoot vs Capacitive Load
(100‑mV Output Step)
(100‑mV Output Step)
VOUT
VOUT
VIN
VIN
Time (1 ꢀs/div)
Time (1 ꢀs/div)
C009
C011
Figure 7-28. Positive Overload Recovery (Zoomed In)
Figure 7-27. Positive Overload Recovery
VIN
VIN
VOUT
VOUT
Time (1 ꢀs/div)
Time (1 ꢀs/div)
C010
C010
Figure 7-29. Negative Overload Recovery
Figure 7-30. Negative Overload Recovery (Zoomed In)
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7.6 Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Time (200 ns/div)
Time (200 ns/div)
C006
C006
C005
C014
C014
C014
10 mV, G = –1, RL = 1 kΩ, CL = 10 pF
10 mV, G = 1, CL = 10 pF
Figure 7-31. Small-Signal Step Response
Figure 7-32. Small-Signal Step Response
Time (200 ns/div)
Time (200 ns/div)
100 mV, G = –1, RL = 1 kΩ, CL = 10 pF
100 mV, G = 1, CL = 10 pF
Figure 7-33. Small-Signal Step Response
Figure 7-34. Small-Signal Step Response
Time (500 ns/div)
Time (500 ns/div)
10 V, G = –1, RL = 1 kΩ, CL = 10 pF
10 V, G = 1, CL = 10 pF
Figure 7-35. Large-Signal Step Response
Figure 7-36. Large-Signal Step Response
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7.6 Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
20
15
10
5
20
15
10
5
0
0
-5
œ5
-10
-15
-20
œ10
œ15
œ20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (ꢀs)
Time (ꢀs)
C034
C030
G = 1, CL = 10 pF, 0.1% settling = ±10 mV
G = 1, CL = 10 pF, 0.1% settling = ±10 mV
Figure 7-37. Large-Signal Settling Time (10‑V Positive Step)
Figure 7-38. Large-Signal Settling Time (10‑V Negative Step)
100
VOUT
75
ISC, Sink ± 18 V
50
ISC, Source 18 V
25
VIN
0
Time (200 ꢀs/div)
œ75 œ50 œ25
0
25
50
75
100 125 150
C011
Temperature (°C)
C001
Figure 7-39. No Phase Reversal
Figure 7-40. Short-Circuit Current vs Temperature
160
140
120
100
80
30
VS
= 15 V
Maximum output voltage without
slew-rate induced distortion.
25
20
15
10
5
VS
VS
=
5 V
60
40
=
2.25 V
20
0
0
10k
100k
1M
Frequency (Hz)
10M
10M
100M
Frequency (Hz)
1G
10G
C017
C033
PRF = –10 dBm, VSUPPLY = ±18 V, VCM = 0 V
Figure 7-41. Maximum Output Voltage vs Frequency
Figure 7-42. EMIRR vs Frequency
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7.6 Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0
œ20
œ40
œ60
œ80
œ100
œ120
œ140
œ160
100
1k
10k
100k
1M
10M
Frequency (Hz)
C027
Figure 7-43. Channel Separation vs Frequency
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8 Detailed Description
8.1 Overview
The OPA1688 op amp provides high overall performance, making the device an excellent choice for many
general-purpose applications. The excellent offset drift of only 1.5 µV/°C (max) provides excellent stability over
the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
Section 8.2 shows the simplified diagram of the OPA1688 design. The design topology is a highly-optimized,
three-stage amplifier with an active-feedforward gain stage.
8.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
OUT
Output
Stage
-IN
NCH
Input Stage
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8.3 Feature Description
8.3.1 EMI Rejection
The OPA1688 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPA1688 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
8-1 shows the results of this testing on the OPA1688. Table 8-1 shows the EMIRR IN+ values for the OPA1688
at particular frequencies commonly encountered in real-world applications. Applications listed in Table 8-1 can
be centered on or operated near the particular frequency shown. Detailed information can also be found in the
EMI Rejection Ratio of Operational Amplifiers application report, available for download from www.ti.com.
160
140
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1G
10G
C017
PRF = –10 dBm, VSUPPLY = ±18 V, VCM = 0 V
Figure 8-1. EMIRR Testing
Table 8-1. OPA1688 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, and ultrahigh
frequency (UHF) applications
400 MHz
47.6 dB
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, and UHF
applications
900 MHz
1.8 GHz
2.4 GHz
58.5 dB
68 dB
GSM applications, mobile personal communications, broadband, satellite, and L-
band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite, and
S-band (2 GHz to 4 GHz)
69.2 dB
3.6 GHz
5.0 GHz
Radiolocation, aero communication and navigation, satellite, mobile, and S-band
82.9 dB
114 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, and C-band (4 GHz to 8 GHz)
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8.3.2 Phase-Reversal Protection
The OPA1688 has internal phase-reversal protection. Many op amps exhibit phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The input of the OPA1688 prevents phase reversal with excessive common-mode voltage.
Instead, the appropriate rail limits the output voltage. Figure 8-2 shows this performance.
VOUT
VIN
Time (200 ꢀs/div)
C011
Figure 8-2. No Phase Reversal
8.3.3 Capacitive Load and Stability
The dynamic characteristics of the OPA1688 are optimized for commonly-used operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier
and may lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the
output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT = 50 Ω) in series
with the output. Figure 8-3 and Figure 8-4 show graphs of small-signal overshoot versus capacitive load for
several values of ROUT; see the Feedback Plots Define Op Amp AC Performance application bulletin, available
for download from www.ti.com, for details of analysis techniques and application circuits.
60
50
40
30
20
10
0
50
40
30
20
10
0
ROUT = 0 ꢀ
ROUT= 0 ꢀ
R = 25 ꢀ
RO = 25
OUT
R
= 25 ꢀ
RO = 25
OUT
RRO = 5=050 ꢀ
OUT
RO = 50
ROUT= 50 ꢀ
0
100
200
300
400
500
0
100
200
300
400
500
Capacitive Load (pF)
Capacitive Load (pF)
C013
C013
G = –1
G = 1
Figure 8-3. Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step)
Figure 8-4. Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step)
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8.4 Device Functional Modes
8.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPA1688 extends 100 mV below the negative rail and within 2 V
of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance
within 2 V of the top rail. Table 8-2 summarizes the typical performance in this range.
Table 8-2. Typical Performance Range (VS = ±18 V)
PARAMETER
MIN
TYP
MAX
UNIT
V
Input common-mode voltage
Offset voltage
(V+) – 2
(V+) + 0.1
5
10
70
60
4
mV
Offset voltage vs temperature (TA = –40°C to 85°C)
Common-mode rejection
Open-loop gain
µV/°C
dB
dB
Gain bandwidth product (GBP)
Slew rate
MHz
V/µs
nV/√Hz
4
Noise at f = 1 kHz
22
8.4.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful.
Figure 8-5 illustrates the ESD circuits contained in the OPA1688 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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TVS
RF
+VS
R1
RS
2.5 kΩ
2.5 kΩ
INœ
IN+
+
Power-Supply
ESD Cell
ID
RL
+
VIN
œ
œVS
TVS
Figure 8-5. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or
more steering diodes. Depending on the path that the current takes, the absorption device can activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA1688
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (Figure 8-5), the ESD protection components are intended
to remain inactive and do not become involved in the application circuit operation. However, circumstances may
arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there
is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
Figure 8-5 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS)
by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can
sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high
current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (+VS or –VS) are at 0 V. Again, this question depends on the supply characteristic when at
0 V, or at a level below the input-signal amplitude. If the supplies appear as high impedance, then the input
source supplies the operational amplifier current through the current-steering diodes. This state is not a normal
bias condition; most likely, the amplifier will not operate normally. If the supplies are low impedance, then the
current through the steering diodes can become quite high. The current level depends on the ability of the input
source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external zener diodes to the
supply pins; see Figure 8-5. Select the zener voltage so that the diode does not turn on during normal operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The OPA1688 input pins are protected from excessive differential voltage with back-to-back diodes; see Figure
8-5. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits,
fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond
rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the
input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor
can be used to limit the input signal current. This input series resistor degrades the low-noise performance of the
OPA1688. Figure 8-5 illustrates an example configuration that implements a current-limiting feedback resistor.
8.4.3 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from the saturated state to
the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds
the rated operating voltage, either resulting from the high input voltage or the high gain. After the device enters
the saturation region, the charge carriers in the output devices need time to return back to the normal state. After
the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus,
the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew
time. The overload recovery time for the OPA1688 is approximately 200 ns.
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPA1688 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the specifications
apply from –40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
9.2 Typical Application
9.2.1 Headphone Amplifier Circuit Configuration
This application example highlights only a few of the circuits where the OPA1688 can be used.
C1
47pF
R1
768
R2
750
ROUT
–5 V
VAC
–
+
Headphone
Output
+
OPA1688
VDC
VAC
R3
768
5 V
ROUT
C2
47pF
R4
ROUT
Audio DAC
750
Figure 9-1. Headphone Amplifier Circuit Configuration for Audio DACs that Output a Differential Voltage
(Single Channel Shown)
9.2.1.1 Design Requirements
The design requirements are:
•
•
•
•
Supply voltage: 10 V (±5 V)
Headphone loads: 16 Ω to 600 Ω
THD+N: > 100 dB (1-kHz fundamental, 1 VRMS in 32 Ω, 22.4-kHz measurement bandwidth)
Output power (before clipping): 50 mW into 32 Ω
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9.2.1.2 Detailed Design Procedure
The OPA1688 offers an excellent combination of specifications for headphone amplifier circuits (such as low
noise, low distortion, capacitive load stability, and relatively high output current). Furthermore, the low-power
supply current and small package options make the OPA1688 an excellent choice for headphone amplifiers
in portable devices. A common headphone amplifier circuit for audio digital-to-analog converters (DACs) with
differential voltage outputs is illustrated in Figure 9-1. This circuit converts the differential voltage output of
the DAC to a single-ended, ground-referenced signal and provides the additional current necessary for low-
impedance headphones. For R2 = R4 and R1 = R3, the output voltage of the circuit is given by Equation 1:
R2
VOUT = 2ì VAC
R1 + ROUT
(1)
where
•
•
ROUT is the output impedance of the DAC
2 × VAC is the unloaded differential output voltage
The output voltage required for headphones depends on the headphone impedance as well as the headphone
efficiency. Both values can be provided by the headphone manufacturer, with headphone efficiency usually given
as a sound pressure level (SPL) produced with 1 mW of input power and denoted by the Greek letter η. The SPL
at other input power levels can be calculated from the efficiency specification using Equation 2:
P
≈
’
IN
SPL (dB) =h +10 log
∆
«
÷
◊
1 mW
(2)
At extremely high power levels, the accuracy of this calculation decreases as a result of secondary effects in the
headphone drivers. Figure 9-2 allows the SPL produced by a pair of headphones of a known sensitivity to be
estimated for a given input power.
10000
90-dB SPL
100-dB SPL
110-dB SPL
120-dB SPL
95-dB SPL
105-dB SPL
115-dB SPL
1000
100
10
1
0.1
0.01
90
95
100
105
110
115
Headphone Efficiency (dB/mW)
C001
Figure 9-2. SPLs Produced for Various Headphone Efficiencies and Input Power Levels
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For example, a pair of headphones with a 95-dB/mW sensitivity given a 3-mW input signal produces a 100-dB
SPL. If these headphones have a nominal impedance of 32 Ω, then Equation 3 and Equation 4 describe the
voltage and current from the headphone amplifier, respectively:
V = P ìRHP = 3 mW ì32 W = 310 mVRMS
IN
(3)
P
3 mW
IN
I =
=
= 9.68 mARMS
RHP
32 W
(4)
Headphones can present a capacitive load at high frequencies that can destabilize the headphone amplifier
circuit. Many headphone amplifiers use a resistor in series with the output to maintain stability; however this
solution also compromises audio quality. The OPA1688 is able to maintain stability into large capacitive loads;
therefore, a series output resistor is not necessary in the headphone amplifier circuit. TINA-TI™ simulations
illustrate that the circuit in Figure 9-1 has a phase margin of approximately 50° with a 400-pF load connected
directly to the amplifier output.
9.2.1.3 Application Curves
The headphone amplifier circuit in Figure 9-1 is tested with three common headphone impedances: 16 Ω, 32 Ω,
and 600 Ω. The total harmonic distortion and noise (THD+N) for increasing output voltages is given in Figure
9-3. This measurement is performed with a 1-kHz input signal and a measurement bandwidth of 22.4 kHz. The
maximum output power and THD+N before clipping are given in Table 9-1. The maximum output power into
low-impedance headphones is limited by the output current capabilities of the amplifier. For high-impedance
headphones (600 Ω), the output voltage capabilities of the amplifier are the limiting factor. The circuit in Figure
9-1 is tested using ±5-V supplies that are common in many portable systems. However, using higher supply
voltages increases the output power into 600-Ω headphones.
0
-20
-40
-60
-80
16.2 ꢀ
-100
32.4 ꢀ
600 ꢀ
-120
0.001
0.01
0.1
1
10
Amplitude (VRMS
)
C002
Input signal = 1 kHz, measurement bandwidth = 22.4 kHz
Figure 9-3. THD+N for Increasing Output Voltages Into Three Load Impedances
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Table 9-1. Maximum Output Power and THD+N Before Clipping for Different Load Impedances
MAXIMUM OUTPUT POWER BEFORE
CLIPPING (mW)
THD+N AT MAXIMUM OUTPUT POWER
(dB)
LOAD IMPEDANCE (Ω)
16
32
32
50
16
–104.1
–109.5
–117.8
600
Figure 9-4, Figure 9-5, and Figure 9-6 further illustrate the exceptional performance of the OPA1688 as a
headphone amplifier.
Figure 9-4 shows the THD+N over frequency for a 500-mVRMS output signal into the same three load
impedances previously tested.
0
16.2 ꢀ
32.4 ꢀ
600 ꢀ
œ20
œ40
œ60
œ80
œ100
œ120
10
100
1000
10000
Frequency (Hz)
C003
90-kHz measurement bandwidth
Figure 9-4. THD+N Measured over Frequency for a 500-mVRMS Output Level
Figure 9-5 and Figure 9-6 show the output spectrum of the OPA1688 at low (1 mW) and high (50 mW) output
power levels into a 32-Ω load. The distortion harmonics in both cases are approximately 120 dB below the
fundamental.
0
œ20
0
œ20
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ100
œ120
œ140
œ160
0
5000
10000
15000
20000
0
5000
10000
15000
20000
Frequency (Hz)
Frequency (Hz)
C001
C001
Third harmonic is dominant at a level of –117.6 dB relative to
the fundamental
Highest harmonic is the second harmonic at –119 dB below
the fundamental
Figure 9-5. Output Spectrum of a 1-mW, 1-kHz
Tone into a 32-Ω Load
Figure 9-6. Output Spectrum of a 50‑mW, 1‑kHz
Tone Into a 32‑Ω Load, Immediately Below the
Onset of Clipping
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
10 Power Supply Recommendations
The OPA1688 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in Section 7.6.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see also Section 7.1.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see also Section
11.
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better
than in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Figure 11-1 illustrates how keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 11-1. Operational Amplifier Board Layout for a Noninverting Configuration
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
12.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
12.2 Documentation Support
12.2.1 Related Documentation
•
•
•
•
Texas Instruments, Feedback Plots Define Op Amp AC Performance application note
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note
Texas Instruments, Op Amps for Everyone application note
Texas Instruments, Capacitive Load Drive Solution Using an Isolation Resistor reference design
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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SBOS724A – SEPTEMBER 2015 – REVISED JUNE 2022
12.5 Trademarks
SoundPlus™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: OPA1688
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1688ID
OPA1688IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SON
SON
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
O1688A
Samples
Samples
Samples
Samples
D
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
O1688A
OP1688
OP1688
OPA1688IDRGR
OPA1688IDRGT
DRG
DRG
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1688IDR
OPA1688IDRGR
OPA1688IDRGT
SOIC
SON
SON
D
8
8
8
2500
3000
250
330.0
330.0
180.0
12.4
12.4
12.4
6.4
3.3
3.3
5.2
3.3
3.3
2.1
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q2
Q2
DRG
DRG
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA1688IDR
OPA1688IDRGR
OPA1688IDRGT
SOIC
SON
SON
D
8
8
8
2500
3000
250
356.0
346.0
210.0
356.0
346.0
185.0
35.0
33.0
35.0
DRG
DRG
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA1688ID
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRG0008A
WSON - 0.8 mm max height
SCALE 5.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
EXPOSED
THERMAL PAD
1.2 0.1
4
1
5
8
2X
1.5
2 0.1
6X 0.5
0.3
8X
0.2
0.1
0.08
0.6
0.4
PIN 1 ID
8X
C A B
C
4218885/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.2)
SYMM
8X (0.7)
1
8
8X (0.25)
SYMM
(2)
(0.75)
5
6X (0.5)
4
(R0.05) TYP
(
0.2) VIA
TYP
(0.35)
(2.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218885/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.7)
8
8X (0.25)
1
SYMM
(1.79)
6X (0.5)
4
5
(R0.05) TYP
(1.13)
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218885/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023, Texas Instruments Incorporated
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