OPA1692ID [TI]
SoundPlus™ 低功耗、低噪声、高性能双路双极输入音频运算放大器 | D | 8 | -40 to 125;
| 型号： | OPA1692ID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SoundPlus™ 低功耗、低噪声、高性能双路双极输入音频运算放大器 | D | 8 | -40 to 125 放大器 光电二极管 运算放大器 |
| 文件： | 总43页 (文件大小：1647K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA1692
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
OPA1692 低功耗、低噪声和低失真
SoundPlus™音频运算放大器
1 特性
3 说明
1
•
•
•
低噪声：1kHz 时为 4.2nV/√Hz
OPA169x 运算放大器将低功耗放大器的性能提高到一
个新的层次，实现了 4.2nV/√Hz 的低噪声密度和
–127dB (1kHz) 的低失真。该运算放大器在 2kΩ 负载
下还提供 200mV 电源轨范围内的轨至轨输出摆幅，从
而增加余量并实现动态范围最大化。这些器件有
±50mA 的高输出驱动能力。
低失真：1kHz 时为 –127dB
低静态电流：
每通道 650µA
•
•
•
•
•
压摆率： 23V/μs
宽增益带宽：5.1MHz
单位增益稳定
OPA169x 运算放大器可在 ±1.75V 至 ±18V 或 3.5V 至
36V （每通道的电源电流为 650µA）的宽电源电压范
围内工作，具有稳定的单位增益，在各种负载条件下可
提供出色的动态行为。
轨至轨输出
宽电源电压范围：
±1.75V 至 ±18V 或 3.5V 至 36V
2 应用
OPA169x 运算放大器的额定工作温度范围为 –40°C 至
125°C。
•
•
•
•
•
•
无线耳机
无线音频监控系统
便携式无线电和耳机
便携式音效处理器
便携式录音系统
USB 音频外设
器件信息(1)
器件编号
OPA1692
封装
VSSOP (8)
SOIC (8)
封装尺寸（标称值）
3.00mm × 3.00mm
4.90mm × 3.91mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
3 线制驻极体麦克风的前置放大器
THD + N 与频率之间的关系（3 VRMS，2kΩ 负载）
5 V
5 V
0.1
-60
0.1 ꢁF
Primo EM-173
Microphone
Competitor A
Competitor B
Competitor C
OPA1692
C1
0.1 ꢁF
R3
100 ꢀ
OPA1692
+
Output
Microphone
Cable
0.01
-80
œ
R1
5.9 kꢀ
R2
100 kꢀ
C2
100 pF
0.1 ꢁF
-5 V
0.001
-100
-120
-140
R4 100 kꢀ
R5 1.1 kꢀ
C3
1 ꢁF
0.0001
0.00001
R6 100 ꢀ
C4 6.8 nF
Copyright © 2017, Texas Instruments Incorporated
10
100
1k
Frequency (Hz)
10k
C001
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS566
OPA1692
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
www.ti.com.cn
目录
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 24
8.3 Other Application Examples.................................... 27
Power Supply Recommendations...................... 29
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: OPA1692 ................................ 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 30
10.3 Power Dissipation ................................................. 30
11 器件和文档支持 ..................................................... 31
11.1 器件支持................................................................ 31
11.2 文档支持................................................................ 31
11.3 相关链接................................................................ 32
11.4 接收文档更新通知 ................................................. 32
11.5 社区资源................................................................ 32
11.6 商标....................................................................... 32
11.7 静电放电警告......................................................... 32
11.8 术语表 ................................................................... 32
12 机械、封装和可订购信息....................................... 32
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (September 2018) to Revision C
Page
•
Changed -40℃ to 125℃ Iq to 975 µA................................................................................................................................... 6
Changes from Revision A (December 2017) to Revision B
Page
•
•
Changed IOS VCM = 0 MAX from "±10" to "±15" nA ............................................................................................................. 5
Changed IOS TA = –40°C to 125°C MAX from "±15" to "±20" nA.......................................................................................... 5
Changes from Original (June 2017) to Revision A
Page
•
已更改 将数据表状态从“预告信息”更改成了“生产数据” .......................................................................................................... 1
2
Copyright © 2017–2018, Texas Instruments Incorporated
OPA1692
www.ti.com.cn
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
5 Pin Configuration and Functions
OPA1692 D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Pin Functions: OPA1692
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
3
6
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
Copyright © 2017–2018, Texas Instruments Incorporated
3
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ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Supply voltage, VS = (V+) – (V–)
Voltage
Input
(V–) – 0.5
–10
(V+) + 0.5
10
Input (all pins except power-supply pins)
Output short-circuit(2)
mA
Current
Continuous
–55
Continuous
125
Operating, TA
Temperature
Junction, TJ
Storage, Tstg
200
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.5
NOM
MAX
36
UNIT
V
Single supply
Split supply
VS
TA
Supply voltage
±1.75
–40
±18
85
Operating temperature
°C
6.4 Thermal Information: OPA1692
OPA1692
THERMAL METRIC(1)
D (SOIC)
DGK (VSSOP)
UNIT
8 PINS
123.6
63.4
8 PINS
162.2
56.9
83.2
6.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
67.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
16.0
ψJB
66.3
81.6
N/A
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017–2018, Texas Instruments Incorporated
OPA1692
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ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
6.5 Electrical Characteristics
at TA = 25°C, VS = ±18 V, RL = 2 kΩ, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
G = 1, f = 20 kHz, RL = 2kΩ, VO = 3 VRMS
G = 1, f = 1 kHz, RL = 2kΩ, VO = 3 VRMS
G = 1,
-118
dB
dB
THD+N
Total harmonic distortion + noise
–127
Intermodulation distortion
Intermodulation distortion
Intermodulation distortion
Intermodulation distortion
0.00005%
-126
VO = 3 VRMS
SMPTE/DIN two-tone, 4:1
(60 Hz and 7 kHz)
G = 1,
dB
dB
VO = 3 VRMS
IMD
G = 1,
CCIF twin-tone
0.0002
-114
VO = 3 VRMS
(19 kHz and 20 kHz)
G = 1,
CCIF twin-tone
VO = 3 VRMS
(19 kHz and 20 kHz)
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
G = 100
G = –1
5.1
23
MHz
V/µs
MHz
ns
Slew rate
Full power bandwidth(1)
Overload recovery time
Channel separation (dual and quad)
VO = 1 VP
G = –10
f = 1 kHz
3.66
250
–145
dB
NOISE
en
Input voltage noise
Input voltage noise
f = 0.1 to 10 Hz
f = 20 Hz to 20 kHz
f = 1 kHz
130
3.9
nVPP
µVPP
en
4.2
Input voltage noise density
Input current noise density
nV/rtHz
pA/rtHz
f = 100 Hz
4.5
f = 1 kHz
0.37
0.4
In
f = 100 Hz
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±1.75 V to ±18 V
±0.25
±0.8
±1.0
5
mV
mV
VS = ±1.75 V to ±18 V
VS = ±1.75 V to ±18 V, TA = –40°C to +125°C(2)
VOS
Input offset voltage
0.5
0.1
µV/°C
µV/V
µV/V
PSRR
PSRR
Power-supply rejection ratio
Power-supply rejection ratio
VS = ±1.75 V to ±18 V
TA = –40°C to +125°C(2)
1.5
2.25
INPUT BIAS CURRENT
IB
Input bias current
VCM = 0 V
300
±2
550
600
±15
±20
nA
nA
nA
nA
TA = –40°C to +125°C
VCM = 0 V
IOS
Input offset current
TA = –40°C to +125°C
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
(V–) + 1.5
(V+) – 0.5
V
CMRR
CMRR
Common-mode rejection ratio
Common-mode rejection ratio
(V–) + 1.5 V ≤ VCM ≤ (V+) – 0.5 V
0.1
1
4
uV/V
uV/V
TA = –40°C to +125°C
INPUT IMPEDANCE
Differential Resistance
350
1.5
kΩ
pF
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
350
1.6
MΩ
pF
OPEN-LOOP GAIN
AOL
AOL
Open-loop voltage gain
Open-loop voltage gain
TA = –40°C to +125°C
110
120
140
140
dB
dB
(V–) + 0.2 V ≤ VO ≤ (V+) – 0.2 V, RL = 2 kΩ
(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
(2) Specified by design and characterization.
Copyright © 2017–2018, Texas Instruments Incorporated
5
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ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
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Electrical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VOUT
IOUT
Voltage output
RL = 2 kΩ
-17.8
17.8
V
Output current
See Figure 46 , Figure 47
mA
Ω
ZO
Open-loop output impedance
Short-circuit current(3)
Capacitive load drive
See Figure 14
ISC
±50
200
mA
pF
CLOAD
POWER SUPPLY
Quiescent current
(per channel)
IOUT = 0 A
IOUT = 0 A, TA = –40°C to +125°C(2)
650
650
750
975
µA
µA
IQ
(3) One channel at a time.
6
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ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
6.6 Typical Characteristics
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
30
25
20
15
10
5
30
25
20
15
10
5
0
0
Input Offset Voltage (mV)
Input Offset Voltage Delta (mV)
N = 1160
Mean = –139.2 µV
Std. Dev. = 105.4 µV
N = 580
Mean = 17 µV
Std. Dev. = 145.2 µV
图 1. Input Offset Voltage Distribution
图 2. Input Offset Voltage Matching (Ch. A – Ch. B)
40
35
30
25
20
15
10
5
20
15
10
5
0
0
Input Bias Current (nA)
Input Offset Voltage Drift (mV/èC)
N = 1160
Mean = 301.5 nA
Std. Dev. = 7.03 nA
图 4. Input Bias Current Distribution
图 3. Offset Voltage Drift Distribution
25
20
15
10
5
30
25
20
15
10
5
0
0
Input Offset Current (nA)
Power Supply Current (mA)
N = 1160
Mean = 0.07 nA
Std. Dev. = 1.58 nA
N = 1160
Mean = 664.6 µA
Std. Dev. = 6.98 µA
图 5. Input Offset Current Distribution
图 6. Power Supply Current Distribution
版权 © 2017–2018, Texas Instruments Incorporated
7
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
150
120
90
200
160
120
80
30
20
10
0
Gain
Phase
G = 1
G = -1
G = 11
60
30
40
-10
-20
0
0
-30
100m
-40
1
10
100
1k
10k 100k 1M 10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
图 7. Open-Loop Gain and Phase vs Frequency
图 8. Closed-Loop Gain vs Frequency
160
140
120
100
80
100
10
1
10
Input Voltage Noise
Input Current Noise
PSRR-
PSRR+
CMRR
1
60
40
20
0.1
10M
0
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C001
图 9. CMRR and PSRR vs Frequency (Referred to Input)
图 10. Input Voltage Noise Spectral Density
1000
Voltage Noise Contribution
Source Resistor Noise Contribution
Current Noise Contribution
100
10
1
Total Noise
0.1
10
100
1k
10k
100k
1M
Time (1 s/div)
Source Resistance (O)
C001
图 12. 0.1-Hz to 10-Hz Voltage Noise
图 11. Voltage Noise vs Source Resistance
8
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OPA1692
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ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
1000
100
10
20
VS = ±15 V
18
VS = ±5 V
VS = ±1.75 V
16
14
12
10
8
6
4
2
0
1
10k
100k
Frequency (Hz)
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
C001
C001
图 13. Maximum Output Voltage vs Frequency
图 14. Open-Loop Output Impedance vs Frequency
60
90
80
70
60
50
40
30
RISO = 0 W
RISO = 25 W
RISO = 50 W
50
40
30
20
10
0
-10
-20
20
20
10
100
1000
100
Capactiance (pF)
1000
2000
Capacitive Load (pF)
G = 1
G = 1
10-mV input step
图 15. Phase Margin vs Capacitive Load
图 16. Overshoot vs Capacitive Load
60
55
50
45
40
35
30
25
20
15
-100
-110
-120
-130
-140
RISO = 0 W
RISO = 25 W
RISO = 50 W
G = 1
G = -1
20
100
Capactiance (pF)
1000
2000
100
VOUT = 3 VRMS
图 18. THD + N Ratio vs Frequency
1k
10k
Frequency (Hz)
G = –1
10-mV input step
80-kHz bandwidth
图 17. Overshoot vs Capacitive Load
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
-100
-20
-40
G=+1
G=-1
G = 1
G = -1
-110
-120
-130
-140
-60
-80
-100
-120
100
1k
10k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
VOUT = 3 VRMS
RL = 600 Ω
80-kHz bandwidth
VOUT = 3 VRMS
500-kHz bandwidth
图 19. THD + N Ratio vs Frequency
图 20. THD + N Ratio vs Frequency
-100
-100
-120
-140
-160
-180
HD2
HD2
HD3
HD4
HD5
HD3
HD4
HD5
-120
-140
-160
-180
100
1k
10k
100
1k
10k
80-kHz bandwidth
Frequency (Hz)
Frequency (Hz)
VOUT = 3 VRMS
G = 1
80-kHz bandwidth
VOUT = 3 VRMS
G = –1
图 21. Distortion Harmonics vs Frequency
图 22. Distortion Harmonics vs Frequency
-20
-40
-20
-40
G = 1
G = -1
G = 1
G = -1
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
1m
f = 1 kHz
图 23. THD + N Ratio vs Output Amplitude
10m
100m
Amplitude (VRMS
1
10
1m
10m
100m
Amplitude (VRMS)
1
10
)
80-kHz bandwidth
f = 1 kHz
RL = 600 Ω
80-kHz bandwidth
图 24. THD + N Ratio vs Output Amplitude
10
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ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
-70
-60
-80
-75
-80
-85
-90
-100
-120
-140
-160
-180
-95
-100
-105
-110
-115
-120
CCIF
SMPTE
-125
-130
0.01
0.1
1
10
1k
10k
100k
1M
10M
Output Amplitude (VRMS
)
Frequency (Hz)
80-kHz bandwidth
图 25. Intermodulation Distortion vs Output Amplitude
图 26. Channel Separation vs Frequency
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
5000
10000
15000
20000
0
50000
100000
Frequency (Hz)
Frequency (Hz)
f = 1 kHz
VO = 3 VRMS
RL = 600 Ω
f = 20 kHz
VO = 3 VRMS
RL = 600 Ω
图 27. 1-kHz Output Spectrum
图 28. 20-kHz Output Spectrum
VIN
VOUT
VIN
VOUT
Time (1 ms/div)
Time (1 ms/div)
100-pF
capacitive load
10-mV input
100-pF
capacitive load
10-mV input
G = 1
G = –1
step
step
图 29. Small-Signal Step Response
图 30. Small-Signal Step Response
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
VIN
VIN
VOUT
VOUT
Time (1 ms/div)
Time (1 ms/div)
10-V input step
100-pF
capacitive load
100-pF
capacitive load
10-V input step
G = 1
G = –1
图 31. Large-Signal Step Response
图 32. Large-Signal Step Response
1000
800
Rising
Falling
600
400
200
0
-200
-400
-600
-800
-1000
Time (1 ms/div)
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
5 typical units
图 33. Settling Time
图 34. Input Offset Voltage vs Temperature
-300
-200
-100
0
150
140
130
120
110
100
90
VS = ê18 V
VS = ê1.75 V
0.1
1
100
200
300
10
100
80
-75
-50
-25
0
25
50
75
100 125 150
-20
-15
-10
-5
0
5
10
15
20
Temperature (èC)
Input Common-mode Voltage (V)
5 typical units
图 36. CMRR vs Temperature
图 35. Input Offset Voltage vs Common-Mode Voltage
12
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
140
130
120
110
100
0.1
180
170
160
150
140
130
120
0.001
VS = ê1.75 V
VS = ê18 V
0.01
0.1
1
1
10
-75
-50
-25
0
25
50
75
100 125 150
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
Temperature (èC)
图 38. Open-Loop Gain vs Temperature
图 37. PSRR vs Temperature
450
400
350
300
250
200
150
100
50
40
30
IB+
IB-
IOS
20
10
0
-10
-20
-30
-40
0
-40
-20
0
20
40
60
80
100 120 140
-20
-15
-10
-5
0
5
10
15
20
Temperature(C)
Input Common-mode Voltage (V)
图 39. Input Bias and Offset Current vs Temperature
图 40. IB vs Common-Mode Voltage
10
5
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-5
VS = ê18 V
VS = ê1.75 V
-10
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-75
-50
-25
0
25
50
75
100 125 150
Input Common-mode Voltage (V)
Temperature (èC)
VS = ±1.75 V
图 41. IB vs Common-Mode Voltage
图 42. Supply Current vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
180
160
140
120
100
80
0.001
0.01
0.1
1
1
-40èC
-5èC
25èC
85èC
125èC
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
100
1k
60
40
0.01
10k
1
0.1
0
5
10
15
20
25
30
35
40
Output Voltage Swing from Rail (V)
Supply Voltage (V)
图 44. Open-Loop Gain vs Output Voltage
图 43. Supply Current vs Supply Voltage
180
170
160
150
140
130
120
110
100
90
0.001
0.01
0.1
1
20
15
10
5
-40èC
-5èC
25èC
85èC
125èC
10
80
70
60
100
1k
-40èC
0èC
25èC
85èC
125èC
50
40
0.01
10k
0
0.1
1
0
10
20
30
40
50
60
70 75
Output Voltage Swing from Rail (V)
Output Current (mA)
VS = ±1.75 V
Sourcing
图 45. Open-Loop Gain vs Output Voltage
图 46. Output Voltage vs Output Current
0
-5
80
70
60
50
40
30
20
10
0
-40èC
0èC
25èC
85èC
125èC
Sinking
Sourcing
-10
-15
-20
0
10
20
30
40
50
60
70 75
-75
-50
-25
0
25
50
75
100 125 150
Output Current (mA)
Temperature (èC)
Sinking
图 47. Output Voltage vs Output Current
图 48. Short-Circuit Current vs Temperature
14
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
VOUT
VIN
VOUT
VIN
Time (500 ns/div)
Time (500 ns/div)
图 49. Negative Overload Recovery
图 50. Positive Overload Recovery
VOUT
VIN
Time (100 ms/div)
图 51. No Phase Reversal
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7 Detailed Description
7.1 Overview
The OPA169x amplifiers are unity-gain stable, dual and quad op amps with low noise. The Functional Block
Diagram shows a simplified schematic of the OPA169x (one channel shown). The device consists of a very low
noise input stage with a folded cascode and a rail-to-rail output stage. A proprietary distortion reduction
technology allows the OPA169x family of amplifiers to achieve significantly lower distortion than other op amps
that consume the equal or greater power supply current.
7.2 Functional Block Diagram
V+
Pre-Driver and
Distortion
Cancellation
IN-
IN+
OUT
Copyright © 2017, Texas Instruments Incorporated
V-
7.3 Feature Description
7.3.1 Distortion Reduction
Amplifiers use feedback to reduce the amount of distortion they introduce to the signal path. Increasing the
amount of feedback available for distortion reduction typically requires an increase in the power supply current of
the amplifier. This is not acceptable in low-power amplifiers targeting applications that require low distortion.
0.1
-60
Competitor A
Competitor B
Competitor C
OPA1692
0.01
-80
0.001
-100
-120
-140
0.0001
0.00001
10
100
1k
Frequency (Hz)
10k
C001
图 53. Comparison of THD + N vs Frequency for Multiple Low-Power Amplifiers
16
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Feature Description (接下页)
The OPA169x family of amplifiers uses a proprietary technology to reduce signal distortion that does not increase
the power supply current. The distortion cancellation technique reduces odd-order harmonic distortion, which is
produced by the input transistor pair of the amplifier. As 图 53 shows, the impact to THD + N is significant,
especially at high frequencies where the OPA169x devices exhibit over 30-dB lower distortion than competitor
amplifiers at similar power supply current levels.
7.3.2 Phase Reversal Protection
The OPA169x family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, reverses the output into the
opposite rail. The input of the OPA169x prevents phase reversal with excessive common-mode voltage. Instead,
the appropriate rail limits the output voltage. This performance is shown in 图 54.
VOUT
VIN
Time (100 ms/div)
图 54. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
7.3.3 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. 图
55 illustrates the ESD circuits contained in the OPA169x (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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Feature Description (接下页)
TVS
RF
+VS
R1
250 Ω
250 Ω
INœ
RS
IN+
+
Power-Supply
ESD Cell
ID
RL
+
VIN
œ
œVS
TVS
Copyright © 2016, Texas Instruments Incorporated
图 55. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA169x but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see 图 55), the ESD protection components are intended
to remain inactive and are not involved in the application-circuit operation. However, circumstances may arise
where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a
risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
图 55 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
18
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Feature Description (接下页)
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. This question depends on the supply characteristic when at 0 V, or at a
level below the input signal amplitude. If the supplies appear as high impedance, then the input source supplies
the operational amplifier current through the current-steering diodes. This state is not a normal bias condition;
most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current through
the steering diodes can become quite high. The current level depends on the ability of the input source to deliver
current and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see 图 55. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe operating, supply voltage level.
7.4 Device Functional Modes
7.4.1 Operating Voltage
The OPA169x series op amps operate from ±1.75 V to ±18 V supplies while maintaining excellent performance.
The OPA169x series operates with as little as 3.5 V between the supplies and with up to 36 V between the
supplies. However, some applications do not require equal positive and negative output voltage swing. With the
OPA169x series, power-supply voltages are not required to be equal. For example, the positive supply can be
set to 25 V with the negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. Key parameters are
assured over the specified temperature range of TA = –40°C to 125°C. Parameters that vary significantly with
operating voltage or temperature are shown in the Typical Characteristics.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Capacitive Loads
The dynamic characteristics of the OPA169x amplifiers are optimized for commonly encountered gains, loads,
and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the
phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads
must be isolated from the output. Add a small resistor (RS equal to 50 Ω, for example) in series with the output to
isolate heavier capacitive loads.
8.1.2 Noise Performance
图 56 shows the total circuit noise for varying source impedances with the operational amplifier in a unity-gain
configuration (with no feedback resistor network and therefore no additional noise contributions). The op amp
itself contributes a voltage noise component and a current noise component. The voltage noise is commonly
modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying
component of the input bias current and reacts with the source resistance to create a voltage component of
noise. Therefore, the lowest noise op amp for a given application depends on the source impedance. For low
source impedance, current noise is negligible, and voltage noise generally dominates. The OPA169x has low
voltage noise and low current noise. As a result, the current noise contribution of the OPA169x series is
negligible for source impedances less than 100 kΩ.
图 56 shows the calculation of the total circuit noise, with these parameters:
•
•
•
•
•
en = voltage noise
In = current noise
RS = source impedance
k = Boltzmann's constant = 1.38 × 10–23 J/K
T = temperature in degrees Kelvin (K)
For more details on calculating noise, see Basic Noise Calculations.
1000
Voltage Noise Contribution
Source Resistor Noise Contribution
Current Noise Contribution
100
10
1
Total Noise
0.1
10
100
1k
10k
100k
1M
Source Resistance (O)
C001
图 56. Noise Performance of the OPA169x in a Unity-Gain Buffer Configuration
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Application Information (接下页)
8.1.3 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in 图 56. The source impedance is typically fixed; consequently, select the op
amp and the feedback resistors to minimize the respective contributions to the total noise.
图 57 shows noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations
with gain, the feedback network resistors contribute noise. In general, the current noise of the op amp reacts with
the feedback resistors to create additional noise components.
The selected feedback resistor values make these noise sources negligible. Low impedance feedback resistors
load the output of the amplifier. The equations for total noise are shown for both configurations.
(A) Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
42
41 „ 42
2
2
2
2
¨
: ;
1
:
;
:
;
:
;
>
?
84/5
'
1
= l1 + p „ A5 + A0 + kA4 2 o + E0 „ 45 + lE0 „ d
hp
æ4
1
41
41 + 42
GND
œ
EO
8
: ;
2
A = 4 „ G$ „ 6(-) „ 45
d
h
¥
Thermal noise of RS
+
5
*V
¾
RS
41 „ 42
8
: ;
3
A4
= ¨4 „ G$ „ 6(-) „ d
2
h
d
h
Thermal noise of R1 || R2
æ4
1
41 + 42
*V
¾
+
,
h
VS
Source
GND
G$ = 1.38065 „ 10F23
: ;
4
d
œ
Boltzmann Constant
-
Temperature in kelvins
: ;
>
?
-
5
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
:
;
42
45 + 41 „ 42
'
1
= l1 +
p „ A0 2 + kA4
o2 + FE0 „ H
+4 æ4
5 2
IG
¨
: ;
6
:
;
>
84/5
?
1
45 + 41
45 + 41 + 42
RS
œ
EO
:
;
45 + 41 „ 42
8
+
: ;
7
¨
4 „ G$ „ 6(-) „ H
A4
=
I
d
h
Thermal noise of (R1 + RS) || R2
+4 æ4
5
1
2
45 + 41 + 42
*V
¾
+
VS
œ
,
GND
G$ = 1.38065 „ 10F23
d
h
: ;
8
Boltzmann Constant
Source
GND
-
: ;
9
>
?
6(-) = 237.15 + 6(°%)
-
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
(1) eN is the voltage noise of the amplifier. For the OPAx169x series of operational amplifiers, eN = 4.2 nV/√Hz at 1 kHz.
(2) iN is the current noise of the amplifier. For the OPA169x series of operational amplifiers, iN = 370 fA/√Hz at 1 kHz.
(3) For additional resources on noise calculations, see TI's Precision Labs Series.
图 57. Noise Calculation in Gain Configurations
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Application Information (接下页)
8.1.4 EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a
higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this
section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
•
•
•
Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit approximately
matching EMIRR performance
EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input
terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier result in adverse effects,
as the amplifier does not have sufficient loop gain to correct for signals with spectral content outside its
bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected DC
offsets, transient voltages, or other unknown behavior. Take care to properly shield and isolate sensitive
analog nodes from noisy radio signals and digital clocks and interfaces.
The EMIRR IN+ of the OPA169x amplifiers is plotted versus frequency as shown in 图 58. If available, any
dual and quad op amp device versions have nearly similar EMIRR IN+ performance. The OPA169x unity-
gain bandwidth is 5.1 MHz. EMIRR performance below this frequency denotes interfering signals that fall
within the op amp bandwidth.
See EMI Rejection Ratio of Operational Amplifiers, available for download from www.ti.com.
120
100
80
60
40
20
10M
100M
Frequency (Hz)
1G
10G
图 58. OPA169x EMIRR IN+
22
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表 1 lists the EMIRR IN+ values for the OPA169x at particular frequencies commonly encountered in real-world
applications. Applications listed in 表 1 may be centered on or operated near the particular frequency shown.
This information may be of special interest to designers working with these types of applications, or working in
other fields likely to encounter RF interference from broad sources, such as the industrial, scientific, and medical
(ISM) radio band.
表 1. OPA169x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
45.9 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
50.2 dB
70.7 dB
76.1 dB
94.1 dB
104.5 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
8.1.5 EMIRR +IN Test Configuration
图 59 shows the circuit configuration for testing the EMIRR IN+. An RF source connects to the op amp
noninverting input pin using a transmission line. The op amp is configured in a unity-gain buffer topology with the
output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at the
op amp input causes a voltage reflection; however, this effect is characterized and accounted for when
determining the EMIRR IN+. A multimeter samples and measures the resulting DC offset voltage. The LPF
isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
Ambient temperature: 25˘C
+VS
œ
50 ꢀ
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
-VS
Sample /
Averaging
Digital Multimeter
Not shown: 0.1 µF and 10 µF
supply decoupling
Frequency Sweep: 201 pt. Log
图 59. EMIRR +IN Test Configuration
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8.2 Typical Application
The low power consumption, noise, and distortion of the OPA169x family of audio operational amplifiers make
the family a viable option for a number of analog audio circuits. 图 60 shows one circuit example, which shows a
preamplifier circuit that is designed for high-performance electret microphones that use a 3-wire interface.
5 V
5 V
0.1 ꢁF
Primo EM-173
Microphone
C1
0.1 ꢁF
R3
100 ꢀ
OPA1692
+
Output
Microphone
Cable
œ
R1
R2
C2
5.9 kꢀ
100 kꢀ
100 pF
0.1 ꢁF
-5 V
R4 100 kꢀ
R5 1.1 kꢀ
C3
1 ꢁF
R6 100 ꢀ
C4 6.8 nF
Copyright © 2017, Texas Instruments Incorporated
图 60. Low-Noise Preamplifier for 3-Wire Electret Microphones
8.2.1 Design Requirements
•
•
•
•
•
Maximum Input Sound Pressure Level (SPL): 120 dB
–3-dB Bandwidth: 20 Hz to 20 kHz
Signal-to-Noise Ratio: > 75 dB
Power Supply Voltage: ± 5 V
Power Supply Current: < 1.5 mA
8.2.2 Detailed Design Procedure
The selected design requirements represent a high-performance wireless microphone application. Wireless
microphones typically use an electret microphone element, an analog pre-amplifier circuit, and transmit circuitry
which may use analog or digital methods of transmission. Because these devices are battery-powered, all
circuitry must be designed to consume as little power as possible, while still achieving very high audio
performance. The performance specifications for the microphone used in this design are shown in 表 2. This
microphone element uses a 3-wire connection scheme with separate connections for power, ground, and signal.
The microphone data sheet specifies that the signal line is terminated with a recommended 5.6-kΩ resistance
and a 5-V supply.
表 2. Primo EM-173 Microphone Specifications
PARAMETER
Sensitivity
VALUE
–37 dBV
600 Ω
Output impedance
Signal-to-noise ratio (SNR)
Maximum input sound pressure level
Operating voltage
80 dB
135 dB
5 V (3 V – 10 V)
600 µA
Operating current
R1, C1, and R2 provide the correct termination impedance for the microphone and AC-couple the microphone
signal to the amplifier input. R2 is selected with a large value (100 kΩ) so that a smaller AC-coupling capacitor
can be used (C1). The high-pass corner frequency produced by C1 and R2 must be set to 20 Hz using 公式 1:
1
1
20 Hz =
=
ç C1 = 79.6 nF ç 100 nF
2∂ p∂R2 ∂C1 2∂ p∂100 kW ∂C1
(1)
24
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R1 and R2 are in parallel for frequencies above 20 Hz. Therefore, select the value of R1 so that when in parallel
with R2, the combination results in a 5.6-kΩ resistance as specified in the microphone data sheet. 公式 2
calculates R1.
R1 ∂R2
R1 + R2 R1 +100 kW
R1 ∂100 kW
5.6 kW =
=
ç R1 = 5.9 kW
(2)
R3 and C2 form a low-pass filter to prevent the amplification of electromagnetic interference (EMI) signals. 公式 3
shows the corner frequency of this EMI filter.
1
1
f-3dB
=
=
= 15.9 MHz
2∂ p∂R3 ∂C2 2∂ p∂100 W ∂100 pF
(3)
The input bias current of the OPA1692 through the 100-kΩ input resistor (R2) and can potentially cause a large
offset voltage to appear at the output of the amplifier. One solution to this problem is to match the DC resistance
of the circuit at each input of the amplifier. R4 and C3 accomplish this goal by providing a DC-feedback path for
the amplifier (R4) which has the same resistance as the input resistor (R2). Capacitor C3 serves two functions.
First, at low-frequencies this capacitor is effectively an open circuit and therefore the gain of the amplifier is 1,
which reduces DC offsets at the output. At high frequencies where the impedance of the capacitor is low, the
feedback network of R5, R6, and C4 determine the gain of the amplifier.
The nominal gain of the preamplifier circuit is calculated by considering the output of the microphone at the
maximum input SPL. For this design, a maximum input SPL of 120 dB or [20 pascals (Pa)] is specified. The
microphone sensitivity is shown as –37 dBV, measured at 1-Pa air pressure. The output signal of the microphone
at 20-Pa air pressure can be calculated by converting the –37 dBV sensitivity specification to mV per pascal of
air pressure as shown in 公式 4:
-37 dBV
≈
’
÷
◊
VOUT(MIC) = 20 Paì10«∆
= 282.5 mVRMS = 399.5 mVp
20
(4)
The linear output voltage range of the OPA1692 extends to within 200 mV of each power supply. Therefore, on a
±5-V power supply, the linear output voltage range is ±4.8 V. The linear output voltage range of the amplifier and
the maximum output signal level of the microphone determine the gain of the amplifier, as shown in 公式 5:
VOUT(OPA1692)
4.8 VP
R5
R6
G =
=
= 12.015 (21.6 dB) = 1+
VOUT(MIC)
399.5 mVP
(5)
Selecting values of 1.1 kΩ and 100 Ω for R5 and R6, respectively, produce a nominal gain of 12 for the circuit,
allowing the full linear output swing of the amplifier to be used for the maximum input SPL. The feedback
capacitor (C4) limits the gain of the circuit at high frequencies beyond the range of human hearing. 公式 6 shows
the high-pass corner frequency that capacitor C4 produces:
1
1
20 kHz =
=
ç C4 = 7.23 nF ç 6.8 nF
2∂ p ∂R5 ∂C4 2∂ p ∂1.1 kW ∂C4
(6)
Lastly, by the low-frequency bandwidth requirement for the design and the gain determines the value of C3. The
high-pass corner frequency produced by this capacitor is affected by resistors R5 and R6 as shown in 公式 7:
≈
’
÷
R5
1
1
C = 1+
= 12
(
ç C3 = 955 nF ç1mF
)
∆
3
R6 2∂p∂R4 ∂ f-3dB
2∂ p∂100 kW∂20 Hz
«
◊
(7)
8.2.3 Application Curves
表 3 lists the performance of the preamplifier circuit in 图 60. The total power supply current of the circuit is a
combination of the 600 µA consumed by the microphone element itself and the 650 µA power-supply current of
the OPA1692. 图 61 shows the frequency response of the circuit. Comparing the output signal level of the
microphone for a 1-Pa input signal level to the A-weighted noise of the preamplifier circuit and microphone
determines the SNR of the circuit. For a 1-Pa input sound level, the microphone produces a 14.13 mVRMS signal.
The microphone has an SNR of 80 dB, which results in a RMS noise voltage of 1.41 µVRMS. The input-referred
A-weighted noise voltage of the preamplifier circuit is 600.6 nVRMS. The microphone and preamplifier noise must
be combined as a root sum of squares, which results in a total RMS noise voltage of 1.53 µVRMS and a total
circuit SNR of 79.3 dB. By selecting the OPA1692 for this design, this circuit achieves a high level of
performance with low power consumption.
版权 © 2017–2018, Texas Instruments Incorporated
25
OPA1692
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
www.ti.com.cn
表 3. Comparison of Design Requirements and Results
SPECIFICATION
Gain
DESIGN REQUIREMENT
12 V/V or 21.6 dB (120 dB Maximum Input SPL)
20 Hz to 20 kHz
DESIGN RESULT
11.79 V/V or 21.43 dB
24 Hz to 21 kHz
79.3 dB
–3-dB bandwidth
Signal-to-noise ratio
> 75 dB
Power supply current
(microphone and amplifier circuit)
< 1.5 mA
1.25 mA
100
10
1
10
100
1k
10k
100k
Frequency (Hz)
C001
图 61. Frequency Response of the Low-Noise Preamplifier for 3-Wire Electret Microphones
26
版权 © 2017–2018, Texas Instruments Incorporated
OPA1692
www.ti.com.cn
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
8.3 Other Application Examples
8.3.1 Two-Wire Electret Microphone Preamplifier
The circuit in 图 60 can be modified to accommodate two-wire electret microphones, as shown in 图 62. In two-
wire configurations, there is no resistor in series with the source of the internal JFET of the microphone. The
audio signal is output as a varying voltage across the biasing resistor (2.2 kΩ in 图 62) of the capsule. The
preamplifier input is AC-coupled to the biasing resistor through a 0.1-µF capacitor and 47-kΩ input resistor.
5 V
2.2
kꢀ
5 V
0.1 ꢁF
Electret
Microphone
½ OPA1692
+
0.1 ꢁF
100 ꢀ
Output
Microphone
Cable
œ
47
kꢀ
100
pF
0.1 ꢁF
47 kꢀ
-5 V
2.2 ꢁF
150 ꢀ
3.57 kꢀ
2.2 nF
图 62. Two-Wire Electret Microphone Preamplifier
版权 © 2017–2018, Texas Instruments Incorporated
27
OPA1692
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
www.ti.com.cn
Other Application Examples (接下页)
8.3.2 Battery-Powered Preamplifier for Professional Microphones
图 63 shows a preamplifier designed for portable applications that require low-noise, high common-mode
rejection, and long battery life. Both channels of the OPA1692 are configured as a two-op amp instrumentation
amplifier with a variable gain from 6 to 40 dB. An array of 1-kΩ resistors is recommended for the feedback
network because the excellent matching of these resistors ensure high common-mode rejection in the circuit. An
OPA171 is configured as a buffered power supply divider to provide a biasing voltage to the circuit, allowing the
system to operate properly on a single 9-V battery. The additional components at the OPA1692 inputs are for
phantom power, EMI, and ESD protection. The circuit consumes approximately 2 mA of quiescent power supply
current.
9 V
9 V
0.1 ꢀF
100 kꢁ
OPA171
+
VBIAS
œ
1 ꢀF
100 kꢁ
10-kꢁ Potentiometer
(Logarithmic)
20 ꢁ
1 kꢁ
VBIAS
Array of matched 1-kꢁ resistors
1 kꢁ
48 V Phantom Power
1 kꢁ
1 kꢁ
9 V
9 V
D1
0.1 ꢀF
47 kꢁ
10 V
6.8 kꢁ
6.8 kꢁ
D2
47 ꢀF
œ
œ
47 ꢀF
Microphone
Input
Output
+
+
68 ꢁ
68 ꢁ
30 ꢁ
100
pF
47 kꢁ
VBIAS
2.2 kꢁ
OPA1692
2
3
100
pF
1
22 kꢁ
68 ꢁ
100
pF
2.2 kꢁ
47 ꢀF
30 ꢁ
XLR Connector
Copyright © 2017, Texas Instruments Incorporated
D3
D4
图 63. Preamplifier for Professional Microphones Powered from a 9-V Battery
28
版权 © 2017–2018, Texas Instruments Incorporated
OPA1692
www.ti.com.cn
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
9 Power Supply Recommendations
The OPA169x are specified for operation from 3.5 V to 36 V (±1.75 V to ±18 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are shown in the Typical Characteristics section. Applications with noisy or high-impedance power supplies
require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Physically
separate digital and analog grounds, observing the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to
in parallel with the noisy trace.
•
•
•
Place the external components as close as possible to the device. As shown in 图 64, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
For best performance, TI recommends cleaning the PCB following assembly.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to
remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
版权 © 2017–2018, Texas Instruments Incorporated
29
OPA1692
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
www.ti.com.cn
10.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors.
Output A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUTPUT A
V+
RF
Output B
GND
-IN A
+IN A
Vœ
OUTPUT B
-IN B
RF
RG
GND
VIN B
VIN A
RG
+IN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor. Place as
close to the device
as possible.
VSœ
Ground (GND) plane on another layer
as possible.
图 64. Operational Amplifier Board Layout for Noninverting Configuration
10.3 Power Dissipation
The OPA169x series op amps are capable of driving 2-kΩ loads with a power-supply voltage up to ±18 V and full
operating temperature range. Internal power dissipation increases when operating at high supply voltages.
Copper leadframe construction used in the OPA169x series op amps improves heat dissipation compared to
conventional materials. Circuit board layouts minimize junction temperature rise. Wide copper traces help
dissipate the heat by acting as an additional heat sink. Temperature rise is further minimized by soldering the
devices to the circuit board rather than using a socket.
30
版权 © 2017–2018, Texas Instruments Incorporated
OPA1692
www.ti.com.cn
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。 TINA-TI™是 TINA 软件的
一款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有
传统的 SPICE 直流 (DC)、瞬态和频域分析以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 DIP 适配器 EVM
DIP 适配器 EVM 工具提供了一种简单而低成本的方式来针对小型表面贴装 IC 进行原型设计。评估工具适用于以下
TI 封装：D 或 U (SOIC-8)、PW (TSSOP-8)、DGK (VSSOP-8)、DBV（SOT23-6、SOT23-5 和 SOT23-3）、
DCK（SC70-6 和 SC70-5）以及 DRL (SOT563-6)。DIP 适配器 EVM 也可搭配引脚排使用或直接与现有电路相
连。
11.1.1.3 通用运算放大器评估模块 (EVM)
通用运放 EVM 是一系列通用空白电路板，可简化采用各种 IC 封装类型的电路板原型设计。借助评估模块电路板设
计，可以轻松快速地构造多种不同电路。共有
5
个模型可供选用，每个模型都对应一种特定封装类型。支持
PDIP、SOIC、VSSOP、TSSOP 和 SOT-23 封装。
注
这些电路板均为空白电路板，用户必须自行提供 IC。TI 建议您在订购通用运算放大器 EVM
时申请几个运算放大器器件样品。
11.1.1.4 智能放大器扬声器特性鉴定板评估模块
智能放大器扬声器特性鉴定板，与支持的 TI 智能放大器和 PurePath 控制台软件配合使用时，用户可测量扬声器偏
移、温度和其它参数以便与 TI 智能放大器产品配合使用。
11.1.1.5 TI 高精度设计
TI 高精度设计的模拟设计方案是由 TI 公司高精度模拟实验室设计 应用 专家创建的模拟解决方案，提供了许多实用
电路的工作原理、组件选择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。
欲获取 TI 高精度设计，请访问 http://www.ti.com.cn/ww/analog/precision-designs/。
11.1.1.6 WEBENCH®滤波器设计器
WEBENCH® 滤波器设计器是一款简单、功能强大且便于使用的有源滤波器设计程序。借助 WEBENCH 滤波器设
计器，用户可使用精选 TI 运算放大器和 TI 供应商合作伙伴提供的无源组件来构建最佳滤波器设计方案。
WEBENCH® 设计中心以基于网络的工具形式提供 WEBENCH® 滤波器设计器。用户通过该工具可在数分钟内完
成多级有源滤波器解决方案的设计、优化和仿真。
11.2 文档支持
11.2.1 相关文档
使用 OPA169x 时，建议参考下列相关文档。所有这些文档都可从 www.ti.com.cn 上下载（除非另有说明）。
版权 © 2017–2018, Texas Instruments Incorporated
31
OPA1692
ZHCSH60C –JUNE 2017–REVISED OCTOBER 2018
www.ti.com.cn
文档支持 (接下页)
•
•
•
•
•
•
《放大器源电阻和噪声注意事项》
《运算放大器的单电源操作》
《运算放大器性能分析》
《在放大器中进行调优》
《反馈曲线图定义运算放大器交流性能》
《适用于专业音频的有源音量控制》
11.3 相关链接
表 4 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品的快速链
接。
表 4. 相关链接
器件
产品文件夹
请单击此处
立即订购
技术文档
工具与软件
请单击此处
支持和社区
请单击此处
OPA1692
请单击此处
请单击此处
11.4 接收文档更新通知
如需接收文档更新通知，请访问 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.6 商标
SoundPlus, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
32
版权 © 2017–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1692ID
OPA1692IDGKR
OPA1692IDGKT
OPA1692IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OP1692
Samples
Samples
Samples
Samples
DGK
DGK
D
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
1692
1692
OP1692
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1692IDGKR
OPA1692IDGKT
OPA1692IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
6.4
3.4
3.4
5.2
1.4
1.4
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA1692IDGKR
OPA1692IDGKT
OPA1692IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
366.0
213.0
356.0
364.0
191.0
356.0
50.0
50.0
35.0
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA1692ID
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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Copyright © 2022，德州仪器 (TI) 公司
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