OPA170AQDBVRQ1 [TI]
汽车级、单路、36V、1.2MHz、低功耗运算放大器 | DBV | 5 | -40 to 125;
| 型号： | OPA170AQDBVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、单路、36V、1.2MHz、低功耗运算放大器 | DBV | 5 | -40 to 125 放大器 光电二极管 运算放大器 |
| 文件： | 总42页 (文件大小：1781K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
OPAx170-Q1 36V 单电源、低功耗、汽车级运算放大器
1 特性
3 说明
1
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列结果：
OPA170-Q1、OPA2170-Q1 和 OPA4170-Q1 器件
(OPAx170-Q1) 属于 36V、单电源、低噪声运算放大器
系列。该器件系列采用微型封装，可由电压介于 2.7V
(±1.35V) 至 36V (±18V) 之间的电源供电运行。此类器
件在确保静态电流较低的情况下提供良好的偏移、漂移
和带宽。
•
–
器件温度等级 1：环境工作温度范围为 –40°C
至 +125°C
–
–
器件 HBM ESD 分类等级 3A
带电器件模型 (CDM) ESD 分类等级 C5
•
•
•
•
•
•
•
•
•
•
•
电源电压范围：2.7V 至 36V，±1.35V 至 ±18V
低噪声：19 nV/√Hz
多数运算放大器仅有一个指定的电源电压，OPAx170-
Q1 系列运算放大器则有所不同，其可在 2.7V 至 36V
电压范围内额定运行。超过电源轨的输入信号不会导致
反相。OPAx170-Q1 系列在容性负载高达 300pF 时可
保持稳定。输入可在负电源轨以下 100mV 以及正电源
轨 2V 之内正常运行。请注意，这些器件可在正电源轨
之上 100mV 的满轨到轨输入上运行，但是在正电源轨
2V 内运行时，性能会受到影响。OPAx170-Q1 运算放
大器的额定工作温度范围为 -40°C 至 +125°C。
已过滤的射频干扰 (RFI) 输入
输入范围包括负电源
输入范围运行至正电源
轨到轨输出
增益带宽：1.2MHz
低静态电流：每个放大器 110µA
高共模抑制：120dB
低偏置电流：15pA（最大值）
通道数量：
器件信息(1)
封装
器件型号
OPA170-Q1
封装尺寸（标称值）
2.90mm × 1.60mm
3.00mm × 3.00mm
5.00mm x 4.40mm
–
–
–
OPA170-Q1 - 1 条
OPA2170-Q1 - 2 条
OPA4170-Q1 - 4 条
SOT-23 (5)
VSSOP (8)
OPA2170-Q1
OPA4170-Q1
TSSOP封装(14)
•
行业标准封装
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
•
•
•
•
汽车
混合动力汽车 (HEV) 和电动车 (EV) 动力传动
高级驾驶员辅助系统 (ADAS)
自动恒温控制
温度测量
应力计放大器
精密积分器
EMIRR IN+ 与频率间的关系
140
120
100
80
60
40
PRP = -10 dBm
VS
= 18 V
20
VCM = 0 V
0
10 M
100 M
Frequency (Hz)
1 G
10 G
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS834
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
目录
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 23
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application .................................................. 24
Power Supply Recommendations...................... 26
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings ............................................................ 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information: OPA170-Q1 ............................ 7
6.5 Thermal Information: OPA2170-Q1 .......................... 7
6.6 Thermal Information: OPA4170-Q1 .......................... 7
6.7 Electrical Characteristics........................................... 8
6.8 Typical Characteristics: Table of Graphs................ 10
6.9 Typical Characteristics............................................ 11
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ...................................... 19
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 27
11 器件和文档支持 ..................................................... 28
11.1 器件支持................................................................ 28
11.2 文档支持................................................................ 29
11.3 相关链接................................................................ 29
11.4 社区资源................................................................ 29
11.5 商标....................................................................... 29
11.6 静电放电警告......................................................... 29
11.7 Glossary................................................................ 29
12 机械、封装和可订购信息....................................... 30
7
4 修订历史记录
Changes from Revision A (March 2017) to Revision B
Page
•
•
•
•
•
•
•
•
•
已删除 从器件信息 表中删除了 8 引脚 SOIC、5 引脚 SOT、8 引脚 VSSOP 和 14 引脚 SOIC 封装.................................... 1
已更改 首页图 ........................................................................................................................................................................ 1
Deleted OPA170-Q1 D (SOIC) and DRL (SOT) pinout drawings and pinout table information............................................. 3
Deleted OPA2170-Q1 D (SOIC) and DCU (VSSOP Micro size packages ............................................................................ 4
Deleted OPA170-Q1 D (SOIC) pinout drawing ...................................................................................................................... 5
Deleted D (SOIC) and DRL (SOT) thermal information from OPA170-Q1 Thermal Information table ................................. 7
Deleted D (SOIC) and DCU (VSSOP) thermal information from OPA2170-Q1 Thermal Information table ......................... 7
Deleted D (SOIC) thermal information from OPA4170-Q1 Thermal Information table ......................................................... 7
已更改 values in 图 38 from 250 Ω to 2.5 kΩ ...................................................................................................................... 21
Changes from Original (December 2016) to Revision A
Page
•
•
•
•
•
已删除 说明中第一段的最后一句 ........................................................................................................................................... 1
Deleted static literature number in Thermal Information: OPA170-Q1 table note ................................................................. 7
Separated the IB and IOS test conditions for the OPA4170 in Electrical Characteristics table............................................. 8
已添加 additional text to Figure 8 title ................................................................................................................................. 12
已更改 "many specifications apply from –40°C to +125°C" to "many specifications apply from –40°C to +85°C" to
correct typo........................................................................................................................................................................... 26
2
Copyright © 2016–2017, Texas Instruments Incorporated
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
www.ti.com.cn
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
5 Pin Configuration and Functions
OPA170-Q1 DBV Package
5-Pin SOT-23
Top View
V+
OUT
1
2
3
5
4
V-
-IN
+IN
Table 1. Pin Functions: OPA170-Q1
PIN
I/O
DESCRIPTION
NAME
IN– (–IN)
IN+ (+IN)
OUT
NO.
4
I
Negative (inverting) input
Positive (noninverting) input
Output
3
I
1
O
—
—
V–
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
Copyright © 2016–2017, Texas Instruments Incorporated
3
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
OPA2170-Q1 DGK Package
8-Pin VSSOP
Top View
OUT A
1
2
3
4
8
7
6
5
V+
-IN A
+IN A
V-
OUT B
-IN B
+IN B
Table 2. Pin Functions: OPA2170-Q1
PIN
I/O
DESCRIPTION
NAME
–IN A
–IN B
+IN A
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input, channel A
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Output, channel A
6
3
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
4
Copyright © 2016–2017, Texas Instruments Incorporated
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
www.ti.com.cn
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
OPA4170-Q1 PW Package
14-Pin TSSOP
Top View
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
OUT C
Table 3. Pin Functions: OPA4170-Q1
PIN
NAME
–IN A
I/O
DESCRIPTION
NO.
2
I
I
Inverting input, channel A
–IN B
6
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Output, channel A
–IN C
–IN D
+IN A
+IN B
+IN C
+IN D
OUT A
OUT B
OUT C
OUT D
V–
9
I
13
3
I
I
5
I
10
12
1
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) power supply
Positive (highest) power supply
V+
Copyright © 2016–2017, Texas Instruments Incorporated
5
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
20
UNIT
V
Supply voltage
–20
Single supply voltage
40
V
Signal input pin voltage
Signal input pin current
Output short-circuit current(2)
Operating ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
(V–) – 0.5
–10
(V+) + 0.5
10
V
mA
Continuous
–55
150
150
150
°C
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
36
UNIT
VS
TA
Supply voltage (V+ – V–)
Operating temperature
2.7
V
–40
125
°C
6
Copyright © 2016–2017, Texas Instruments Incorporated
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
www.ti.com.cn
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
6.4 Thermal Information: OPA170-Q1
OPA170-Q1
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
245.8
133.9
83.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.2
ψJB
83.1
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2170-Q1
OPA2170-Q1
THERMAL METRIC(1)
DGK (VSSOP)
UNIT
8 PINS
180
55
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
130
5.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
120
—
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4170-Q1
OPA4170-Q1
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
106.9
24.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
59.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
54.3
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016–2017, Texas Instruments Incorporated
7
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
6.7 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
0.25
±1.8
±2
mV
mV
VOS
Input offset voltage
TA = –40°C to 125°C
TA = –40°C to 125°C
dVOS/dT Input offset voltage drift
±0.3
1
±2
µV/°C
Input offset voltage vs power
VS = 4 V to 36 V
TA = –40°C to 125°C
PSRR
supply
±5
µV/V
µV/V
Channel separation, dc
5
INPUT BIAS CURRENT
TA = 25°C
±8
±4
±15
pA
nA
pA
nA
TA = –40°C to 125°C (OPA170-Q1 and
OPA2170-Q1)
IB
Input bias current
Input offset current
±3.5
TA = –40°C to 125°C (OPA4170-Q1)
TA = 25°C
±16
±15
TA = –40°C to 125°C (OPA170-Q1 and
OPA2170-Q1)
IOS
±3.5
±16
TA = –40°C to 125°C (OPA4170-Q1)
NOISE
Input voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 100 Hz
2
22
19
µVPP
nV/√Hz
nV/√Hz
en
Input voltage noise density
ƒ = 1 kHz
INPUT VOLTAGE
VCM
Common-mode voltage range(1)
(V–) – 0.1
90
(V+) – 2
V
VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V
TA = –40°C to 125°C
104
120
dB
CMRR
Common-mode rejection ratio
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2
V
104
dB
TA = –40°C to 125°C
INPUT IMPEDANCE
Differential
100 || 3
6 || 3
MΩ || pF
1012 Ω ||
Common-mode
OPEN-LOOP GAIN
AOL Open-loop voltage gain
FREQUENCY RESPONSE
pF
VS = 4 V to 36 V
(V–) + 0.35 V < VO < (V+) – 0.35 V
TA = –40°C to 125°C
110
130
dB
GBP
SR
Gain bandwidth product
1.2
0.4
20
MHz
V/µs
µs
Slew rate
G = 1
To 0.1%, VS = ±18 V, G = 1 10-V step
tS
Settling time
To 0.01% (12-bit), VS = ±18 V, G = 1
10-V step
28
µs
µs
Overload recovery time
VIN × Gain > VS
2
THD+N
Total harmonic distortion + noise G = 1, ƒ = 1 kHz, VO = 3 VRMS
0.0002%
(1) The input range can be extended beyond (V+) – 2 V up to V+. For additional information, see Typical Characteristics and Application
and Implementation.
8
Copyright © 2016–2017, Texas Instruments Incorporated
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
www.ti.com.cn
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
Electrical Characteristics (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
IL = 0 mA
VS = 4 V to 36 V
10
mV
mV
mV
mV
Voltage output swing from
positive rail
VO
IL sourcing 1 mA
VS = 4 V to 36 V
115
IL = 0 mA
VS = 4 V to 36 V
8
Voltage output swing from
negative rail
VO
IL sinking 1 mA
VS = 4 V to 36 V
70
VS = 5 V
RL = 10 kΩ
TA = –40°C to 125°C
(V+) –
0.05
(V–) + 0.03
V
V
VO
Voltage output swing from rail
RL = 10 kΩ
AOL ≥ 110 dB
TA = –40°C to 125°C
(V+) –
0.35
(V–) + 0.35
–20
ISC
Short-circuit current
Capacitive load drive
17
mA
pF
CLOAD
See Typical Characteristics
ƒ = 1 MHz
IO = 0 A
RO
Open-loop output resistance
900
Ω
POWER SUPPLY
VS Specified voltage range
2.7
36
V
IO = 0 A
TA = 25°C
110
145
µA
IQ
Quiescent current per amplifier
IO = 0 A
155
µA
TA = –40°C to 125°C
TEMPERATURE
Specified range
–40
–55
125
150
°C
°C
Operating range
版权 © 2016–2017, Texas Instruments Incorporated
9
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
6.8 Typical Characteristics: Table of Graphs
表 4. Characteristic Performance Measurements
DESCRIPTION
FIGURE
图 1
Offset Voltage Production Distribution
Offset Voltage Drift Distribution
Offset Voltage vs Temperature
图 2
图 3
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Offset Voltage vs Power Supply
图 4
图 5
图 6
IB and IOS vs Common-Mode Voltage
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred-to-Input)
CMRR vs Temperature
图 7
图 8
图 9
图 10
图 11
图 12
图 13
图 14
图 15
图 16
图 17
图 18
图 19
图 20
图 21
图 22
图 23, 图 24
图 25
图 26
图 27
图 28, 图 29
图 30, 图 31
图 32
图 33
图 34
图 35
图 36
PSRR vs Temperature
0.1-Hz to 10-Hz Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Temperature
Quiescent Current vs Supply Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
No Phase Reversal
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (100 mV)
Large-Signal Step Response
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR IN+ vs Frequency
10
版权 © 2016–2017, Texas Instruments Incorporated
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
www.ti.com.cn
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
6.9 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
20
18
16
14
12
10
8
25
20
15
10
5
Distribution Taken From 400 Amplifiers
Distribution Taken From 104 Amplifiers
6
4
2
0
0
Offset Voltage (mV)
Offset Voltage Drift (mV/°C)
G001
G002
图 1. Offset Voltage Production Distribution
图 2. Offset Voltage Drift Distribution
1000
800
5 Typical Units Shown
600
400
200
0
−200
−400
−600
−800
−1000
VCM = -18.1 V
−50
−25
0
25
50
75
100
125
150
Temperature (°C)
Common-Mode Voltage (V)
G003
图 3. Offset Voltage vs Temperature
图 4. Offset Voltage vs Common-Mode Voltage
500
5 Typical Units Shown
300
100
-100
-300
-500
Normal
Operation
Common-Mode Voltage (V)
0
2
4
6
8
10
12
14
16
18
20
VSUPPLY (V)
D006
图 5. Offset Voltage vs Common-Mode Voltage
图 6. Offset Voltage vs Power Supply
(Upper Stage)
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11
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
12
2000
IB+
IB-
10
8
1500
1000
500
+IB
IOS
6
IOS
0
4
-IB
-500
-1000
2
VCM = 16.1 V
VCM = -18.1 V
0
-75 -50 -25
0
25
50
75
100 125 150
-20
-15
-10
-5
0
5
10
15
20
Temperature (°C)
VCM (V)
图 8. Input Bias Current vs Temperature for Single and Dual
图 7. IB and IOS vs Common-Mode Voltage
Versions
18
140
120
100
80
17
16
15
14.5
-14.5
-15
60
-40°C
+25°C
+125°C
40
-16
-17
-18
+PSRR
20
0
-PSRR
CMRR
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1k
10k
100k
1M
Output Current (mA)
Frequency (Hz)
图 9. Output Voltage Swing vs Output Current (Maximum
图 10. CMRR and PSRR vs Frequency
Supply)
(Referred to Input)
30
3
2
VS
VS
VS
=
=
=
1ꢀ35 V
2 V
VS = 2.7 V to 36 V
VS = 4 V to 36 V
25
20
15
10
5
18 V
1
0
-1
-2
-3
0
-75 -50 -25
0
25
50
75
100 125 150
Temperature (°C)
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
D012
图 11. CMRR vs Temperature
图 12. PSRR vs Temperature
12
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Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1000
100
10
1
1
10
100
1k
10k
100k
1M
Time (1 s/div)
Frequency (Hz)
G014
图 13. 0.1-Hz to 10-Hz Noise
图 14. Input Voltage Noise Spectral Density vs Frequency
0.01
0.001
-80
0.1
-60
VOUT = 3 VRMS
BW = 80 kHz
G = +1
RL = 10 kW
BW = 80 kHz
G = +1
RL = 10 kW
0.01
-80
-100
-120
-140
-100
-120
-140
0.001
0.0001
0.0001
0.00001
0.00001
10
100
1 k
10 k
100 k
0.01
0.1
1
10 20
Frequency (Hz)
Output Amplitude (VRMS
)
图 15. THD + N Ratio vs Frequency
图 16. THD + N vs Output Amplitude
140
130
120
110
100
90
VS
=
18 V
80
VS
=
1.35 V
125
70
Specified Supply-Voltage Range
60
-50
-25
0
25
50
75
Temperature (°C)
100
150
D017
图 18. Quiescent Current vs Supply Voltage
图 17. Quiescent Current vs Temperature
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Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
50
140
120
100
80
135
90
40
Gain
45
30
0
Phase
60
-45
-90
-135
-180
-225
-270
20
40
10
20
0
0
G = −1
G = 1
G = 100
-20
−10
−20
-40
0.1
1
10
100
1k
10k 100k
1M
10M
1k
10k
100k 1M
Frequency (Hz)
10M
100M
Frequency (Hz)
G020
图 19. Open-Loop Gain and Phase vs Frequency
图 20. Closed-Loop Gain vs Frequency
3
10 k
1 k
100
10
VS = 2.7 V
VS = 4 V
2.5
2
VS = 36 V
1.5
1
1
0.5
0
1 m
-75 -50 -25
0
25
50
75
100 125 150
1
10
100
1 k
10 k
100 k
1 M
10 M
Temperature (°C)
Frequency (Hz)
图 21. Open-Loop Gain vs Temperature
图 22. Open-Loop Output Impedance vs Frequency
RL = 10 kW
Ω
G = +1
+18
V
RF = 10 kW
RI = 10 kW
G = -1
ROUT
+18 V
OPAx170-Q1
ROUT
Ω
RL
CL
Ω
-18
V
OPAx170-Q1
-18 V
CL
Ω
Ω
Ω
Ω
100-mV output step
100-mV output step
图 24. Small-Signal Overshoot vs Capacitive Load
图 23. Small-Signal Overshoot vs Capacitive Load
14
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Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
+18 V
OPAx170-Q1
-18 V
37 VPP
Sine Wave
18ꢀ5 V)
(
20 kΩ
+18 V
2 kΩ
VOUT
OPAx170-Q1
VIN
-18 V
G = -10
Time (100 μs/div)
Time (10 μs/div)
图 25. No Phase Reversal
图 26. Positive Overload Recovery
20 kΩ
RL = 10 kΩ
CL = 10 pF
+18 V
2 kΩ
VOUT
OPAx170-Q1
VIN
-18 V
G = -10
G = +1
+18 V
OPAx170-Q1
-18 V
RL
CL
Time (10 μs/div)
Time (5 μs/div)
图 27. Negative Overload Recovery
图 28. Small-Signal Step Response (100-mV)
G = +1
RL = 10 kΩ
RL = 10 kΩ
CL = 10 pF
CL = 10 pF
RI = 2 kΩ RF = 2 kΩ
+18 V
OPAx170-Q1
CL
-18 V
G = -1
Time (50 μs/div)
Time (5 μs/div)
图 29. Small-Signal Step Response (100-mV)
图 30. Large-Signal Step Response
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Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
10
G = -1
RL = 10 kΩ
8
6
CL = 10 pF
4
12-Bit Settling
2
0
-2
-4
-6
-8
-10
(±1/2LSB = ±0.012%)
0
10
20
30
40
50
60
70
80
90 100
Time (50 μs/div)
Time (ms)
10-V positive step
图 31. Large-Signal Step Response
图 32. Large-Signal Settling Time
30
10
8
G = -1
ISC, Source
ISC, Sink
25
20
6
15
4
10
12-Bit Settling
2
5
0
0
−5
-2
-4
-6
-8
-10
(±1/2LSB = ±0.012%)
−10
−15
−20
−25
−30
0
10
20
30
40
50
60
−50
−25
0
25
50
75
100
125
150
Temperature (°C)
Time (ms)
G034
10-V negative step
10-V negative step
图 34. Short-Circuit Current vs Temperature
图 33. Large-Signal Settling Time
16
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Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
15
12.5
10
140
120
100
80
VS = ±15 V
Maximum output range without
slew−rate induced distortion
7.5
5
60
VS = ±5 V
40
PRP = -10 dBm
VS 18 V
VCM = 0 V
=
20
2.5
0
VS = ±1.35 V
0
10 M
100 M
Frequency (Hz)
1 G
10 G
1k
10k
100k
Frequency (Hz)
1M
10M
G035
图 36. EMIRR IN+ vs Frequency
图 35. Maximum Output Voltage vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx170-Q1 family of operational amplifiers provides high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 2 μV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL
.
7.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
OUT
Output
Stage
-IN
NCH
Input Stage
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Operating Characteristics
The OPAx170-Q1 family of amplifiers is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of
the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are listed in 表 4.
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Feature Description (接下页)
7.3.2 Phase-Reversal Protection
The OPAx170-Q1 family has an internal phase-reversal protection. Many operational amplifiers exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the OPAx170-Q1 prevents phase reversal with
excessive common-mode voltage. Instead, the output limits into the appropriate rail. 图 37 shows this
performance.
+18 V
OPAx170-Q1
-18 V
37 VPP
Sine Wave
18ꢀ5 V)
(
Time (100 μs/div)
图 37. No Phase Reversal
7.3.3 Electrical Overstress
Designers typically ask questions about the capability of an operational amplifier to withstand electrical
overstress. These questions typically focus on the device inputs, but may involve the supply voltage pins or the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD
events both before and during product assembly.
A good understanding of basic ESD circuitry and the relevance of the circuitry to an electrical overstress event is
helpful. 图 38 shows the ESD circuits (indicated by the dashed line area) in the OPAx170-Q1. The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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Feature Description (接下页)
TVS
RF
+VS
R1
2.5 kΩ
INœ
RS
2.5 kΩ
IN+
+
Power-Supply
ID
RL
ESD Cell
+
VIN
œ
œVS
TVS
图 38. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. The absorption device can activate depending on the path of the current. The absorption device
has a trigger (or threshold voltage) that is above the normal operating voltage of the OPAx170-Q1, but below the
device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and
clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see 图 38), the ESD protection components are intended
to remain inactive and do not become involved in the application circuit operation. However, circumstances may
arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there
is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
图 38 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Feature Description (接下页)
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see 图 38. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The OPAx170-Q1 input pins are protected from excessive differential voltage with back-to-back diodes, as shown
in 图 38. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1
circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,
limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can limit the input signal current. This input series resistor degrades the low-noise performance of the
OPAx170-Q1. 图 38 is an example configuration that implements a current-limiting feedback resistor.
7.3.4 Capacitive Load and Stability
The dynamic characteristics of the OPAx170-Q1 are optimized for common operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series
with the output. 图 39 and 图 40 are graphs showing small-signal overshoot versus capacitive load for several
values of ROUT. See Feedback Plots Define Op Amp AC Performance for details of analysis techniques and
application circuits.
Ω
RL = 10 kW
G = +1
+18 V
RF = 10 kW
RI = 10 kW
G = -1
ROUT
+18 V
OPAx170-Q1
ROUT
Ω
RL
CL
Ω
-18 V
OPAx170-Q1
-18 V
CL
Ω
Ω
Ω
Ω
100-mV output step
G = 1
100-mV output step
G = –1
图 39. Small-Signal Overshoot vs Capacitive Load
图 40. Small-Signal Overshoot vs Capacitive Load
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7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx170-Q1 series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in 表 5.
表 5. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply
PARAMETER
Input common-mode voltage
MIN
TYP
MAX
UNIT
V
(V+) – 2
(V+) + 0.1
7
12
mV
Offset voltage
vs temperature
µV/°C
dB
Common-mode rejection
Open-loop gain
65
60
dB
Gain-bandwidth product
Slew rate
0.3
0.3
MHz
V/µs
7.4.2 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from the
saturated state to the linear state. The output devices of the operational amplifier enter the saturation region
when the output voltage exceeds the rated operating voltage, either resulting from the high input voltage or the
high gain. After the device enters the saturation region, the charge carriers in the output devices need time to
return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to
slew at the normal slew rate. Thus, the propagation delay in case of an overload condition is the sum of the
overload recovery time and the slew time. The overload recovery time for the OPAx170-Q1 is approximately 2
µs.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx170-Q1 family of operational amplifiers provides high overall performance in a large number of
general-purpose applications. As with all amplifiers, applications with noisy or high-impedance power supplies
require decoupling capacitors placed close to the device pins. In most cases, capacitors with a value of 0.1 µF
are adequate. Follow the additional recommendations in the Layout Guidelines section to achieve the maximum
performance from this device. Many applications may introduce capacitive loading to the output of the amplifier
that may cause instability. Adding an isolation resistor between the amplifier output and the capacitive load
stabilizes the amplifier. The design process for selecting this resistor is shown in the Typical Application section.
8.2 Typical Application
This circuit can drive capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The
circuit uses an isolation resistor (RISO) to stabilize the output of an operational amplifier. RISO modifies the open-
loop gain of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
CLOAD
+
VIN
-VS
œ
图 41. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
•
•
•
Supply voltage: 30 V (±15 V)
Capacitive loads: 100-pF, 1000-pF, 0.01-μF, 0.1-μF, and 1-μF
Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
图 41 shows a unity-gain buffer driving a capacitive load. 公式 1 shows the transfer function for the circuit in 图
41. Not shown in 图 41 is the open-loop output resistance of the operational amplifier, RO.
1 + CLOAD × RISO × s
T(s) =
1 + R + R
× C
× s
o
ISO
LOAD
(1)
The transfer function in 公式 1 has a pole and a zero. The frequency of the pole (fp) is determined by (RO + RISO
)
and CLOAD. RISO and CLOAD determine the frequency of the zero (fz). A stable system is obtained by selecting
RISO, so the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB / decade. 图 42 depicts the
concept. The 1/β curve for a unity-gain buffer is 0 dB.
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Typical Application (接下页)
120
AOL
100
80
60
40
20
0
1
fp
=
2 ì Œ ì
R
+ Ro ì C
(
)
ISO
LOAD
40 dB
1
fz
=
2 ì Œ ì RISO ì CLOAD
1 dec
1/ꢀ
20 dB
dec
ROC =
100M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
图 42. Unity-Gain Amplifier With RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of R
. In addition to simulating the ROC, a robust stability analysis includes a
O
measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. 表 6
shows the overshoot percentage and ac gain peaking that correspond to 45° and 60° phase margins. For more
details on this design and other alternative devices that can be used in place of the OPAx170-Q1 family, see
Capacitive Load Drive Solution Using an Isolation Resistor.
表 6. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE
MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
8.8%
2.35 dB
0.28 dB
60°
8.2.3 Application Curve
Using the described methodology, the values of RISO that yield phase margins of 45º and 60º for various
capacitive loads were determined. 图 43 shows the results.
10000
45°Phase Margin
60°Phase Margin
1000
100
10
0.1
1
10
100
1000
Capacitive Load (nF)
C002
图 43. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
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9 Power Supply Recommendations
The OPAx170-Q1 family is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications
apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in 表 4.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-
impedance power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
•
•
•
Place the external components as close as possible to the device. As shown in 图 45, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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10.2 Layout Example
VIN
+
VOUT
RG
RF
图 44. Schematic Representation of a Noninverting Configuration
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
N/C
N/C
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Copyright © 2017, Texas Instruments Incorporated
图 45. Operational Amplifier Board Layout for a Noninverting Configuration
版权 © 2016–2017, Texas Instruments Incorporated
27
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。 TINA-TI™ 是 TINA 软件的
一款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有
传统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 WEBENCH® 设计中心免费下载，它提供全面的后续处理能力，使得用户能够以多种方式形成结果。
虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 DIP 适配器 EVM
DIP 适配器 EVM 工具提供了一种针对小型表面贴装器件进行原型设计的简易低成本方法。评估工具适用于以下 TI
封装：D 或 U (SOIC-8)、PW (TSSOP-8)、DGK (MSOP-8)、DBV（SOT-23-6、SOT-23-5 和 SOT-23-3）、DCK
（SC70-6 和 SC70-5）以及 DRL (SOT563-6)。DIP 适配器 EVM 也可搭配引脚排使用或直接与现有电路相连。
11.1.1.3 通用运算放大器评估模块 (EVM)
通用运放 EVM 是一系列通用空白电路板，可简化采用各种器件封装类型的电路板原型设计。借助评估模块电路板
设计，可以轻松快速地构造多种不同电路。共有
5
个模型可供选用，每个模型都对应一种特定封装类型。支持
PDIP、SOIC、MSOP、TSSOP 和 SOT-23 封装。
注
这些电路板均为空白电路板，用户必须自行提供相关器件。TI 建议您在订购通用运算放大器
EVM 时申请几个运算放大器器件样品。
11.1.1.4 TI 高精度设计
TI 高精度设计的模拟设计方案是由 TI 公司高精度模拟实验室设计 应用 专家创建的模拟解决方案，提供了许多实用
电路的工作原理、组件选择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。
欲获取 TI 高精度设计，请访问 http://www.ti.com.cn/ww/analog/precision-designs/。
28
版权 © 2016–2017, Texas Instruments Incorporated
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
www.ti.com.cn
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
器件支持 (接下页)
11.1.1.5 WEBENCH®滤波器设计器
WEBENCH®
滤波器设计器是一款简单、功能强大且便于使用的有源滤波器设计程序。WEBENCH®
Filter
Designer 允许用户通过选择 TI 运算放大器以及 TI 供应商合作伙伴的无源组件构建优化滤波器设计方案。
WEBENCH® 设计中心以基于网络的工具形式提供 WEBENCH® 滤波器设计器。用户通过该工具可在短时间内完
成多级有源滤波器解决方案的设计、优化和仿真。
11.2 文档支持
11.2.1 相关文档
相关文档如下（下载网站 www.ti.com.cn）：
•
•
《反馈曲线图定义运算放大器交流性能》
《采用隔离电阻的电容式负载驱动器解决方案》
11.3 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的
快速链接。
表 7. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
OPA170-Q1
OPA2170-Q1
OPA4170-Q1
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2016–2017, Texas Instruments Incorporated
29
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
ZHCSFP9B –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
30
版权 © 2016–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA170AQDBVRQ1
OPA2170AQDGKRQ1
OPA4170AQPWRQ1
ACTIVE
ACTIVE
ACTIVE
SOT-23
VSSOP
TSSOP
DBV
DGK
PW
5
8
3000 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
170Q
2170
NIPDAUAG
NIPDAU
14
4170Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA170AQDBVRQ1
OPA2170AQDGKRQ1
OPA4170AQPWRQ1
SOT-23
VSSOP
TSSOP
DBV
DGK
PW
5
8
3000
2500
2000
178.0
330.0
330.0
9.0
3.3
5.3
6.9
3.2
3.4
5.6
1.4
1.4
1.6
4.0
8.0
8.0
8.0
Q3
Q1
Q1
12.4
12.4
12.0
12.0
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA170AQDBVRQ1
OPA2170AQDGKRQ1
OPA4170AQPWRQ1
SOT-23
VSSOP
TSSOP
DBV
DGK
PW
5
8
3000
2500
2000
180.0
366.0
356.0
180.0
364.0
356.0
18.0
50.0
35.0
14
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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Copyright © 2023，德州仪器 (TI) 公司
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