OPA170ASDRLTEP [TI]
Enhanced product, single, 36-V, 1.2-MHz, low-power operational amplifier | DRL | 5 | -40 to 150;
| 型号： | OPA170ASDRLTEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Enhanced product, single, 36-V, 1.2-MHz, low-power operational amplifier | DRL | 5 | -40 to 150 放大器 光电二极管 |
| 文件： | 总21页 (文件大小：1807K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA170-EP
www.ti.com.cn
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
36V，单电源，低功耗运算放大器
查询样品: OPA170-EP
1
特性
2
•
•
•
•
•
•
•
•
•
•
•
电源范围：+2.7V 至 +36V，±1.35V 至 ±18V
说明
低噪声：19 nV/√Hz
已过滤的射频干扰 (RFI) 输入
输入范围包括负电源
输入范围运行至正电源
轨至轨输出
OPA170 是一款 36V，单电源，低噪声运算放大器，
此运算放大器特有一个微型封装，此封装能够在 +2.7V
(±1.35V) 至 +36V (±18V) 的电源范围内运行。 它们在
保证低静态电流的情况下提供令人满意的偏移、漂移和
带宽。
增益带宽：1.2MHz
与大多数只有一个额定电源电压的运算放大器不
同，OPA170 的额定电压范围为 +2.7V 至 +36V。 超
过电源轨的输入信号不会导致相位反转。 OPA170 在
电容负载高达 300pF 时保持稳定。 输入可在负电源轨
以下 100mV 以及正电源轨 2V 之内正常运行。 请注
意，这些器件可在正电源轨之上 100mV 的满轨到轨输
入上运行，但是在正电源轨 2V 之内运行时性能会受到
影响。
低静态电流：每个放大器 110µA
高共模抑制：120dB
低偏置电流：15pA（最大值）
微型封装：
–
单通道采用 5 引脚小外形尺寸晶体管 (SOT)553
封装
应用范围
OPA170 采用 SOT553-5 封装，额定温度范围介于 -
40°C 至 +150°C 之间。
•
•
•
•
•
•
•
•
•
电源模块内的跟踪放大器
商用电源
变频器放大器
桥式放大器
温度测量
Package Footprint (to Scale)
应力计放大器
精密积分器
电池供电仪器
测试设备
Package Height (to Scale)
支持国防、航空航天、和医疗应用
DRL (SOT553)
•
•
•
•
•
•
•
受控基线
针对 36V 运算放大器的最小封装
一个组装或测试场所
一个制造场所
(1)
支持扩展（-40°C 至 150°C）温度范围
延长的产品生命周期
延长的产品变更通知
产品可追溯性
(1) 可提供额外温度范围-请与厂家联系
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
English Data Sheet: SBOS598
OPA170-EP
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VID NUMBER
–40°C to 150°C
SOT553-5 - DRL
OPA170ASDRLTEP
SHN
V62/12627-01XE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PIN CONFIGURATIONS
DRL PACKAGE
SOT553-5
(TOP VIEW)
V+
IN+
V-
1
2
3
5
4
OUT
IN-
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
V
Supply voltage
±20, +40 (single supply)
Voltage
Signal input terminals
Current
Output short circuit(2)
Operating temperature
Storage temperature
Junction temperature
(V–) – 0.5 to (V+) + 0.5
V
±10
Continuous
–40 to +150
–65 to +150
+150
mA
°C
°C
°C
kV
V
Human body model (HBM)
ESD ratings
4
Charged device model (CDM)
750
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to ground, one amplifier per package.
THERMAL INFORMATION
OPA170
THERMAL METRIC(1)
DRL (SOT553)
5 PINS
226.8
80.3
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
θJC(top)
θJB
42.9
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
3.2
ψJB
42.5
θJC(bottom)
N/A
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
2
Copyright © 2012, Texas Instruments Incorporated
OPA170-EP
www.ti.com.cn
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +150°C.
At TA = +25°C, VCM = VOUT = VS/2, and RL = 10kΩ connected to VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Input offset voltage
Over temperature
Drift
VOS
0.25
±1.8
mV
mV
TJ = –40°C to +150°C
±2.5
dVOS/dT
PSRR
±0.3
1
µV/°C
µV/V
µV/V
vs power supply
Channel separation, dc
INPUT BIAS CURRENT
Input bias current
Over temperature
Input offset current
Over temperature
NOISE
VS = +4V to +36V
±5
dc
5
IB
±8
±4
±15
±8
pA
nA
pA
nA
TJ = –40°C to +150°C
TJ = –40°C to +150°C
IOS
±15
±8
Input voltage noise
f = 0.1Hz to 10Hz
f = 100Hz
2
22
19
µVPP
nV/√Hz
nV/√Hz
Input voltage noise density
en
f = 1kHz
INPUT VOLTAGE
Common-mode voltage range(1)
VCM
(V–) – 0.1V
(V+) – 2V
V
VS = ±2V, (V–) – 0.1V < VCM < (V+) – 2V
VS = ±18V, (V–) – 0.1V < VCM < (V+) – 2V
87
104
120
dB
dB
Common-mode rejection ratio
CMRR
100
INPUT IMPEDANCE
Differential
100 || 3
6 || 3
MΩ || pF
1012 Ω || pF
Common-mode
OPEN-LOOP GAIN
VS = +4V to +36V,
(V–) + 0.35V < VO < (V+) – 0.35V
Open-loop voltage gain
AOL
107
130
dB
FREQUENCY RESPONSE
Gain bandwidth product
Slew rate
GBP
SR
1.2
0.4
MHz
V/µs
µs
G = +1
To 0.1%, VS = ±18V, G = +1, 10V step
To 0.01% (12 bit), VS = ±18V, G = +1, 10V step
VIN × Gain > VS
20
Settling time
tS
28
µs
Overload recovery time
2
µs
Total harmonic distortion + noise
THD+N
G = +1, f = 1kHz, VO = 3VRMS
0.0002
%
(1) The input range can be extended beyond (V+) – 2V up to V+. See the Typical Characteristics and Application Information sections for
additional information.
Copyright © 2012, Texas Instruments Incorporated
3
OPA170-EP
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +150°C.
At TA = +25°C, VCM = VOUT = VS/2, and RL = 10kΩ connected to VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Voltage output swing from rail
VO
IL = 0mA, VS = +4V to +36V
IL sourcing 1mA, VS = +4V to +36V
IL = 0mA, VS = +4V to +36V
IL sinking 1mA, VS = +4V to +36V
VS = 5V, RL = 10kΩ
10
mV
mV
mV
mV
V
Positive rail
130
8
72
Negative Rail
(V–) + 0.03
(V–) + 0.35
(V+) – 0.05
(V+) – 0.35
Over temperature
RL = 10kΩ, AOL ≥ 107dB
V
Short-circuit current
Capacitive load drive
Open-loop output resistance
POWER SUPPLY
ISC
CLOAD
RO
+17/–20
mA
pF
Ω
See Typical Characteristics
900
f = 1MHz, IO = 0A
Specified voltage range
Quiescent current per amplifier
Over temperature
VS
IQ
+2.7
+36
145
160
V
IO = 0A
110
µA
µA
IO = 0A
TEMPERATURE
Specified range
–40
–40
+150
+150
°C
°C
Operating range
10000.00
1000.00
100.00
10.00
Electromigration Fail Mode
Wirebond Voiding
Fail Mode
1.00
0.10
80
100
120
140
160
180
200
Continuous TJ (°C)
(1) See datasheet for absolute maximum and minimum recommended operating conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) Enhanced plastic product disclaimer applies.
Figure 1. OPA170-EP Operating Life Derating Chart
4
Copyright © 2012, Texas Instruments Incorporated
OPA170-EP
www.ti.com.cn
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
TYPICAL CHARACTERISTICS
VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT DISTRIBUTION
20
18
16
14
12
10
8
25
20
15
10
5
Distribution Taken From 400 Amplifiers
Distribution Taken From 104 Amplifiers
6
4
2
0
0
Offset Voltage (µV)
Offset Voltage Drift (µV/°C)
G001
G002
Figure 2.
Figure 3.
OFFSET VOLTAGE vs TEMPERATURE
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
800
600
5 Typical Units Shown
VS = ±18V
400
200
0
−200
−400
−600
−800
VCM = - 18.1V
−50
−25
0
25
50
75
100
125
150
Temperature (°C)
Common-Mode Voltage (V)
G003
Figure 4.
Figure 5.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
(Upper Stage)
OFFSET VOLTAGE vs POWER SUPPLY
500
300
VSUPPLY = ±1.35V to ± 18V
5 Typical Units Shown
5 Typical Units Shown
100
−100
−300
−500
Normal
Operation
0
2
4
6
8
10
12
14
16
18
20
VSUPPLY (V)
Common-Mode Voltage (V)
G006
Figure 6.
Figure 7.
Copyright © 2012, Texas Instruments Incorporated
5
OPA170-EP
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted.
IB AND IOS vs COMMON-MODE VOLTAGE
INPUT BIAS CURRENT vs TEMPERATURE
3000
2500
2000
1500
1000
500
12
10
8
IB+
IB−
IOS
+IB
6
IOS
4
0
-IB
2
−500
−1000
VCM = 16.1V
10
VCM = -18.1V
-10 -5
0
−50
−25
0
25
50
75
100
125
150
-20
-15
0
5
15
20
Temperature (°C)
G008
VCM (V)
Figure 8.
Figure 9.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(Maximum Supply)
CMRR AND PSRR vs FREQUENCY
(Referred-to Input)
18
17
16
140
120
100
80
15
14.5
–14.5
–15
60
–40°C
+25°C
+125°C
+150°C
40
–16
–17
–18
+PSRR
-PSRR
CMRR
20
0
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1k
10k
100k
1M
Output Current (mA)
Frequency (Hz)
G009
Figure 10.
Figure 11.
CMRR vs TEMPERATURE
PSRR vs TEMPERATURE
30
3
2
VS = ±1.35V
VS = ±2V
VS = ±18V
VS = 2.7V to 36V
VS = 4V to 36V
25
20
15
10
5
1
0
−1
−2
−3
0
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
G011
G012
Figure 12.
Figure 13.
6
Copyright © 2012, Texas Instruments Incorporated
OPA170-EP
www.ti.com.cn
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted.
INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
0.1Hz TO 10Hz NOISE
1000
100
10
1
1
10
100
1k
10k
100k
1M
Frequency (Hz)
G014
Figure 14.
Figure 15.
THD+N RATIO vs FREQUENCY
THD+N vs OUTPUT AMPLITUDE
0.1
-60
0.01
0.001
-80
BW = 80kHz
G = +1
RL = 10kW
VOUT = 3VRMS
BW = 80kHz
G = +1
RL = 10kW
0.01
0.001
-80
-100
-120
-140
-100
-120
-140
0.0001
0.0001
0.00001
0.00001
0.01
0.1
1
10 20
10
100
1k
10k
100k
Output Amplitude (VRMS
)
Frequency (Hz)
Figure 16.
Figure 17.
QUIESCENT CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
140
130
120
110
100
90
VS = ±1.35V
VS = ±18V
80
70
60
50
40
−50
−25
0
25
50
75
100
125
150
Temperature (°C)
G017
Figure 18.
Figure 19.
Copyright © 2012, Texas Instruments Incorporated
7
OPA170-EP
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted.
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
CLOSED-LOOP GAIN vs FREQUENCY
50
40
140
120
100
80
135
90
Gain
45
30
0
20
Phase
60
-45
-90
-135
-180
-225
-270
40
10
20
0
0
G = −1
G = 1
G = 10
−10
−20
-20
-40
1k
10k
100k 1M
Frequency (Hz)
10M
100M
0.1
1
10
100
1k
10k 100k
1M
10M
G020
Frequency (Hz)
Figure 20.
Figure 21.
OPEN-LOOP GAIN vs TEMPERATURE
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
10k
3
VS = 2.7V
VS = 4V
2.5
2
1k
100
10
VS = 36V
1.5
1
1
0.5
0
1m
1
10
100
1k
10k
100k
1M
10M
-75 -50 -25
0
25
50
75
100 125 150
Frequency (Hz)
Temperature (°C)
Figure 22.
Figure 23.
SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD
(100mV Output Step)
SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD
(100mV Output Step)
W
W
G = +1
+18V
RF = 10kW
RI = 10kW
G = -1
ROUT
+18V
OPA170
ROUT
W
RL
CL
W
-18V
OPA170
CL
W
W
-18V
W
W
Figure 24.
Figure 25.
8
Copyright © 2012, Texas Instruments Incorporated
OPA170-EP
www.ti.com.cn
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted.
NO PHASE REVERSAL
POSITIVE OVERLOAD RECOVERY
+18V
OPA170
-18V
37VPP
Sine Wave
(±18.5V)
20kW
+18V
2kW
VOUT
OPA170
VIN
-18V
G = -10
Time (10ms/div)
Time (100ms/div)
Figure 26.
Figure 27.
SMALL-SIGNAL STEP RESPONSE
(100mV)
NEGATIVE OVERLOAD RECOVERY
20kW
RL = 10kW
+18V
2kW
CL = 10pF
VOUT
OPA170
VIN
-18V
G = -10
G = +1
+18V
OPA170
-18V
RL
CL
Time (10ms/div)
Time (5ms/div)
Figure 28.
Figure 29.
SMALL-SIGNAL STEP RESPONSE
(100mV)
LARGE-SIGNAL STEP RESPONSE
G = +1
RL = 10kW
CL = 10pF
RL = 10kW
CL = 10pF
RI = 2kW RF = 2kW
+18V
OPA170
CL
-18V
G = -1
Time (50ms/div)
Time (5ms/div)
Figure 30.
Figure 31.
Copyright © 2012, Texas Instruments Incorporated
9
OPA170-EP
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted.
LARGE-SIGNAL SETTLING TIME
(10V Positive Step)
LARGE-SIGNAL STEP RESPONSE
10
8
G = -1
RL = 10kW
CL = 10pF
6
4
12-Bit Settling
2
0
-2
-4
-6
-8
-10
(±1/2LSB = ±0.012%)
Time (50ms/div)
0
10
20
30
40
50
60
70
80
90 100
Time (ms)
Figure 32.
Figure 33.
LARGE-SIGNAL SETTLING TIME
(10V Negative Step)
SHORT-CIRCUIT CURRENT vs TEMPERATURE
30
10
8
G = -1
ISC, Source
ISC, Sink
25
20
6
15
4
10
12-Bit Settling
2
5
0
0
−5
-2
-4
-6
-8
-10
(±1/2LSB = ±0.012%)
−10
−15
−20
−25
−30
−50
−25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
Temperature (°C)
G034
Time (ms)
Figure 34.
Figure 35.
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
EMIRR IN+ vs FREQUENCY
15
140
VS = ±15 V
120
100
80
60
40
20
0
12.5
10
7.5
5
Maximum output range without
slew−rate induced distortion
VS = ±5 V
PRP = -10dBm
VS = ±18V
2.5
0
VS = ±1.35 V
VCM = 0V
1k
10k
100k
1M
10M
10M
100M
1G
10G
Frequency (Hz)
G035
Frequency (Hz)
Figure 36.
Figure 37.
10
Copyright © 2012, Texas Instruments Incorporated
OPA170-EP
www.ti.com.cn
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
APPLICATION INFORMATION
The OPA170 operational amplifier provides high
overall performance. This device is ideal for many
general-purpose applications. The excellent offset
drift of only 2µV/°C provides excellent stability over
the entire temperature range. In addition, the device
offers very good overall performance with high
CMRR, PSRR, and AOL. As with all amplifiers,
applications with noisy or high-impedance power
supplies require decoupling capacitors placed close
to the device pins. In most cases, 0.1µF capacitors
are adequate.
This device can operate with full rail-to-rail input
100mV beyond the positive rail, but with reduced
performance within 2V of the positive rail. The typical
performance in this range is summarized in Table 1.
PHASE-REVERSAL PROTECTION
The OPA170 has an internal phase-reversal
protection. Many op amps exhibit a phase reversal
when the input is driven beyond its linear common-
mode range. This condition is most often encountered
in noninverting circuits when the input is driven
beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail.
The input of the OPA170 prevents phase reversal
with excessive common-mode voltage. Instead, the
output limits into the appropriate rail. This
performance is shown in Figure 38.
OPERATING CHARACTERISTICS
The OPA170 is specified for operation from 2.7V to
36V (±1.35V to ±18V). Many of the specifications
apply from –40°C to +150°C. Parameters that can
exhibit significant variance with regard to operating
voltage or temperature are presented in the Typical
Characteristics.
+18V
OPA170
GENERAL LAYOUT GUIDELINES
-18V
37VPP
Sine Wave
(±18.5V)
For best operational performance of the device, good
printed circuit board (PCB) layout practices are
recommended. Low-loss, 0.1µF bypass capacitors
should be connected between each supply pin and
ground, placed as close to the device as possible. A
single bypass capacitor from V+ to ground is
applicable to single-supply applications.
Time (100ms/div)
COMMON-MODE VOLTAGE RANGE
The input common-mode voltage range of the
OPA170 extends 100mV below the negative rail and
within 2V of the positive rail for normal operation.
Figure 38. No Phase Reversal
Table 1. Typical Performance Range
PARAMETER
Input Common-Mode Voltage
Offset voltage
vs Temperature
MIN
TYP
MAX
UNIT
V
(V+) – 2
(V+) + 0.1
7
mV
12
65
60
0.3
0.3
µV/°C
dB
Common-mode rejection
Open-loop gain
dB
Gain-bandwidth product
Slew rate
MHz
V/µs
Copyright © 2012, Texas Instruments Incorporated
11
OPA170-EP
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
www.ti.com.cn
CAPACITIVE LOAD AND STABILITY
ELECTRICAL OVERSTRESS
The dynamic characteristics of the OPA170 have
been optimized for common operating conditions. The
combination of low closed-loop gain and high
capacitive loads decreases the phase margin of the
amplifier and can lead to gain peaking or oscillations.
As a result, heavier capacitive loads must be isolated
from the output. The simplest way to achieve this
isolation is to add a small resistor (for example, ROUT
equal to 50Ω) in series with the output. Figure 39 and
Figure 40 illustrate graphs of small-signal overshoot
Designers often ask questions about the capability of
an operational amplifier to withstand electrical
overstress. These questions tend to focus on the
device inputs, but may involve the supply voltage pins
or even the output pin. Each of these different pin
functions have electrical stress limits determined by
the voltage breakdown characteristics of the
particular semiconductor fabrication process and
specific circuits connected to the pin. Additionally,
internal electrostatic discharge (ESD) protection is
built into these circuits to protect them from
accidental ESD events both before and during
product assembly.
versus capacitive load for several values of ROUT
.
Also, refer to Applications Bulletin AB-028, Feedback
Plots Define Op Amp AC Performance (literature
number SBOA015, available for download from the TI
website), for details of analysis techniques and
application circuits.
These ESD protection diodes also provide in-circuit,
input overdrive protection, as long as the current is
limited to 10mA as stated in the Absolute Maximum
Ratings. Figure 41 shows how a series input resistor
may be added to the driven input to limit the input
current. The added resistor contributes thermal noise
at the amplifier input and its value should be kept to a
minimum in noise-sensitive applications.
W
V+
G = +1
+18V
IOVERLOAD
ROUT
OPA170
10mA max
VOUT
W
RL
CL
OPA170
-18V
W
VIN
W
5kW
Figure 41. Input Current Protection
Figure 39. Small-Signal Overshoot versus
Capacitive Load (100mV Output Step, G = +1)
An ESD event produces a short duration, high-
voltage pulse that is transformed into
a short
duration, high-current pulse as it discharges through
a semiconductor device. The ESD protection circuits
are designed to provide a current path around the
operational amplifier core to prevent it from being
damaged. The energy absorbed by the protection
circuitry is then dissipated as heat.
W
When the operational amplifier connects into a circuit,
the ESD protection components are intended to
remain inactive and not become involved in the
application circuit operation. However, circumstances
may arise where an applied voltage exceeds the
operating voltage range of a given pin. Should this
condition occur, there is a risk that some of the
internal ESD protection circuits may be biased on,
and conduct current. Any such current flow occurs
through ESD cells and rarely involves the absorption
device.
RF = 10kW
RI = 10kW
G = -1
+18V
ROUT
W
OPA170
CL
W
-18V
W
Figure 40. Small-Signal Overshoot versus
Capacitive Load (100mV Output Step, G = –1)
12
Copyright © 2012, Texas Instruments Incorporated
OPA170-EP
www.ti.com.cn
ZHCSAL5A –DECEMBER 2012–REVISED DECEMBER 2012
If there is an uncertainty about the ability of the
supply to absorb this current, external zener diodes
may be added to the supply pins. The zener voltage
must be selected such that the diode does not turn
on during normal operation. However, its zener
voltage should be low enough so that the zener diode
conducts if the supply pin begins to rise above the
safe operating supply voltage level.
Copyright © 2012, Texas Instruments Incorporated
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA170ASDRLTEP
V62/12627-01XE
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
DRL
DRL
5
5
250
250
RoHS & Green
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
DAQ
DAQ
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA170ASDRLTEP
SOT-5X3
DRL
5
250
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-5X3 DRL
SPQ
Length (mm) Width (mm) Height (mm)
202.0 201.0 28.0
OPA170ASDRLTEP
5
250
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0005A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
5
2X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
0.1
0.05
TYP
0.00
B
5X
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
5X
SYMM
SYMM
0.27
0.15
5X
0.1
0.05
C A B
0.4
0.2
5X
4220753/B 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0005A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
5X (0.67)
SYMM
1
5
5X (0.3)
SYMM
(1)
2X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4220753/B 12/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0005A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
5X (0.67)
SYMM
1
5
5X (0.3)
SYMM
(1)
2X (0.5)
3
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4220753/B 12/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2021 德州仪器半导体技术（上海）有限公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明