OPA180-Q1 [TI]
通过汽车级认证的 0.1μV/°C 漂移、低噪声、RRO、36V 零漂移运算放大器;
| 型号： | OPA180-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 通过汽车级认证的 0.1μV/°C 漂移、低噪声、RRO、36V 零漂移运算放大器 放大器 运算放大器 |
| 文件： | 总33页 (文件大小：1503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA180-Q1, OPA2180-Q1
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
OPAx180-Q1 0.1μV/°C 漂移、低噪声、轨至轨输出、36V 零漂移
运算放大器
1 特性
3 说明
1
•
符合汽车类应用的 要求
OPA180-Q1 和 OPA2180-Q1 运算放大器采用 TI 的专
有零漂移技术，可同时提供低失调电压 (75μV)，并随
时间推移和温度变化实现接近零漂移的性能。这些高精
度、低静态电流微型运算放大器提供高输入阻抗和摆幅
在电源轨 18mV 之内的轨至轨输出。输入共模范围包
括负电源轨。电压范围为 4V 至 36V（±2V 至 ±18V）
的单电源或双电源均可使用。
•
具有符合 AEC-Q100 标准的下列特性：
–
OPA180-Q1 器件温度等级 1：
–40°C 至 +125°C 环境运行温度范围
–
OPA2180-Q1 器件温度等级 2：
–40°C 至 +105°C 环境运行温度范围
–
–
–
–
–
–
–
–
器件 HBM ESD 分类等级 1C
器件 CDM ESD 分类等级 C5
宽电源电压：±2V 至 ±18V
低失调电压：75μV（最大值）
零漂移：0.1μV/°C
单通道和双通道版本均采用 VSSOP-8 封装。单封装产
品 (OPA180-Q1) 的额定温度范围为 –40°C 至 +125°
C，双封装 (OPA2180-Q1) 的额定温度范围为 –40°C
至 +105°C。
低噪声：10 nV/√Hz
极低 1/f 噪声
器件信息(1)
器件名称
OPA180-Q1
OPA2180-Q1
封装
VSSOP (8)
VSSOP (8)
封装尺寸（标称值）
3.00mm × 3.00mm
3.00mm × 3.00mm
出色的直流精度：
–
–
–
电源抑制比 (PSRR)；126dB
共模抑制比 (CMRR)：114dB
开环路增益 (AOL)：120dB
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
–
–
静态电流：525μA（最大值）
空白
空白
空白
轨至轨输出：
输入包括负电源轨
–
–
–
低偏置电流：250pA（典型值）
已过滤射频干扰 (RFI) 的输入
MicroSIZE 封装
低噪声
（峰值到峰值噪声 = 250nV）
2 应用范围
•
•
•
•
•
汽车高精度电流测量
车载充电器 (OBC)
电池管理系统 (BMS)
电机控制
牵引逆变器
Time (1 s/div)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS861
OPA180-Q1, OPA2180-Q1
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
www.ti.com.cn
目录
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Applications ................................................ 19
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information: OPA180-Q1 ............................ 7
7.5 Thermal Information: OPA2180-Q1 .......................... 7
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 相关链接................................................................ 25
12.2 商标....................................................................... 25
12.3 静电放电警告......................................................... 25
12.4 术语表 ................................................................... 25
13 机械、封装和可订购信息....................................... 25
7.6 Electrical Characteristics: VS = ±2 V to ±18 V (VS
=
4 V to 36 V)................................................................ 8
7.7 Typical Characteristics: Table of Graphs................ 10
7.8 Typical Characteristics............................................ 11
Detailed Description ............................................ 15
8
4 修订历史记录
Changes from Original (June 2017) to Revision A
Page
•
•
•
•
•
已添加 在特性 列表中添加了 OPA180-Q1 和 OPA4180-Q1 器件温度等级............................................................................ 1
已更改 在特性 列表中将 OPA2180-Q1 器件温度等级从等级 1 更改为等级 2 ........................................................................ 1
已更改 在特性 列表中将 OPA2180-Q1 环境运行温度范围从“–40°C 至 +105°C”更改为“–40°C 至 +125°C” .......................... 1
已更改 在说明 部分中将 OPA180-Q1 和 OPA4180-Q1 运行温度从“–40°C 至 +105°C”更改为“–40°C 至 +125°C” ............... 1
Changed input offset voltage drift temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
•
•
•
•
•
•
•
Changed power supply rejection ratio temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
Changed OPA180-Q1 input bias current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
Changed OPA180-Q1 input offset current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
Changed common-mode rejection ratio temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
Changed open-loop voltage gain temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in Electrical
Characteristics table ............................................................................................................................................................... 8
Changed voltage output swing from rail temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 9
Changed quiescent current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in Electrical
Characteristics table ............................................................................................................................................................... 9
•
•
已更改 operating temperature from "–40°C to +105°C" to " –40°C to +125°C" in Feature Description section .................. 16
Updated 图 34 ..................................................................................................................................................................... 22
2
Copyright © 2017–2018, Texas Instruments Incorporated
OPA180-Q1, OPA2180-Q1
www.ti.com.cn
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
5 Device Comparison Table
Table 1. Zero-Drift Amplifier Portfolio
OFFSET VOLTAGE
(µV)
OFFSET VOLTAGE DRIFT
BANDWIDTH
(MHz)
VERSION
PRODUCT
(µV/°C)
0.085
0.35
OPA188-Q1(4 V to 36 V)
OPA180-Q1 (4 V to 36 V)
OPA333 (5 V)
25
75
10
50
5
2
2
Single
0.05
0.35
0.9
1.6
2
OPA378 (5 V)
0.25
OPA735 (12 V)
0.05
OPA2188-Q1 (4 V to 36 V)
OPA2180-Q1 (4 V to 36 V)
OPA2333 (5 V)
25
75
10
50
5
0.085
0.35
2
Dual
0.05
0.35
0.9
1.6
2
OPA2378 (5 V)
0.25
OPA2735 (12 V)
0.05
OPA4188 (4 V to 36 V)
OPA4180 (4 V to 36 V)
OPA4330 (5 V)
25
75
50
0.085
0.35
Quad
2
0.25
0.35
Copyright © 2017–2018, Texas Instruments Incorporated
3
OPA180-Q1, OPA2180-Q1
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
www.ti.com.cn
6 Pin Configuration and Functions
OPA180-Q1 DGK Package
8-Pin VSSOP
Top View
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC(1)
V+
OUT
NC(1)
(1) NC- no internal connection
Pin Functions: OPA180-Q1
PIN
DESCRIPTION
NAME
–IN
NO.
2
Inverting input
+IN
NC
3
Noninverting input
No connection
1, 5, 8
OUT
V–
6
4
7
Output
Negative power supply
Positive power supply
V+
4
Copyright © 2017–2018, Texas Instruments Incorporated
OPA180-Q1, OPA2180-Q1
www.ti.com.cn
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
OPA2180-Q1 DGK Package
8-Pin VSSOP
Top View
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
A
OUT B
-IN B
+IN B
B
Pin Functions: OPA2180-Q1
PIN
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
6
5
1
7
Output, channel B
4
Negative power supply
Positive power supply
V+
8
Copyright © 2017–2018, Texas Instruments Incorporated
5
OPA180-Q1, OPA2180-Q1
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
±20, ±40
Supply voltage
V
(single-supply)
(V+) + 0.5
±10
Voltage
(V–) – 0.5
V
Signal input terminals
Current
mA
Output short-circuit(2)
Operating temperature
Continuous
125
–55
–65
°C
°C
°C
TJ
Junction temperature
Storage temperature
150
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
±1500
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted), RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS /
2, (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single-supply
Bipolar-supply
Supply voltage [(V+) – (V–)]
Operating temperature
±2.25
–40
±18
125
V
°C
6
Copyright © 2017–2018, Texas Instruments Incorporated
OPA180-Q1, OPA2180-Q1
www.ti.com.cn
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
7.4 Thermal Information: OPA180-Q1
OPA180-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
180.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
67.9
102.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
10.4
ψJB
100.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2180-Q1
OPA2180-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
159.3
37.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
48.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
ψJB
77.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2018, Texas Instruments Incorporated
7
OPA180-Q1, OPA2180-Q1
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
www.ti.com.cn
7.6 Electrical Characteristics: VS = ±2 V to ±18 V (VS = 4 V to 36 V)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VIO
Input offset voltage
15
75
μV
dVIO/dT
Input offset voltage drift
TA = –40°C to +125°C
0.1
0.35
μV/°C
VS = 4 V to 36 V
VCM = VS / 2
0.1
0.5
0.5
μV/V
μV/V
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C,
VS = 4 V to 36 V
VCM = VS / 2
Long-term stability
4(1)
1
μV
Channel separation, DC
μV/V
INPUT BIAS CURRENT
OPA2180-Q1
±0.25
±0.25
±0.5
±1
±5
nA
nA
nA
nA
nA
nA
nA
nA
OPA2180-Q1:
TA = –40°C to +105°C
18
18
6
IIB
Input bias current
OPA180-Q1
±1.7
±6
OPA180-Q1:
TA = –40°C to +125°C
OPA2180-Q1
±2
OPA2180-Q1:
TA = –40°C to +105°C
±2.5
±3.4
±3
IIO
Input offset current
OPA180-Q1
OPA180-Q1:
TA = –40°C to +125°C
6
NOISE
Input voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 1 kHz
0.25
10
μVPP
en
in
Input voltage noise density
Input current noise density
nV/√Hz
fA/√Hz
ƒ = 1 kHz
10
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
V–
(V+) – 1.5
V
(V–) < VCM < (V+) – 1.5 V
104
114
104
dB
CMRR
Common-mode rejection ratio
TA = –40°C to +125°C
(V–) + 0.5 V < VCM < (V+) – 1.5 V
100
dB
INPUT IMPEDANCE
zid
zic
Differential
Common-mode
100 || 6
6 || 9.5
MΩ || pF
1012 Ω || pF
OPEN-LOOP GAIN
(V–) + 500 mV < VO < (V+) – 500 mV
RL = 10 kΩ
110
104
120
114
dB
dB
AOL
Open-loop voltage gain
TA = –40°C to +125°C
(V–) + 500 mV < VO < (V+) – 500 mV
RL = 10 kΩ
FREQUENCY RESPONSE
GBW
SR
Gain bandwidth product
2
MHz
V/μs
μs
Slew rate
G = 1
0.8
0.1%
VS = ±18 V, G = 1, 10-V step
VS = ±18 V, G = 1, 10-V step
VIN × G = VS
22
ts
Settling time
0.01%
30
1
μs
tor
Overload recovery time
μs
THD+N
Total harmonic distortion + noise
ƒ = 1 kHz, G = 1, VOUT = 1 VRMS
0.0001%
(1) 1000-hour life test at 125°C demonstrated randomly distributed variation in the range of measurement limits, or approximately 4 μV.
8
Copyright © 2017–2018, Texas Instruments Incorporated
OPA180-Q1, OPA2180-Q1
www.ti.com.cn
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
Electrical Characteristics: VS = ±2 V to ±18 V (VS = 4 V to 36 V) (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
No load
8
18
mV
mV
RL = 10 kΩ
250
300
Voltage output swing from rail
TA = –40°C to +125°C
RL = 10 kΩ
325
360
mV
IOS
Short-circuit current
±18
120
1
mA
Ω
ro
Output resistance (open loop)
Capacitive load drive
ƒ = 2 MHz, IO = 0 mA
CLOAD
nF
POWER SUPPLY
VS
Operating voltage range
±2 (or 4)
±18 (or 36)
525
V
450
μA
IQ
Quiescent current (per amplifier)
TA = –40°C to +125°C
IO = 0 mA
600
μA
TEMPERATURE
Specified range
–40
–40
105
105
°C
°C
Operating range
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OPA180-Q1, OPA2180-Q1
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
www.ti.com.cn
7.7 Typical Characteristics: Table of Graphs
表 2. Characteristic Performance Measurements
DESCRIPTION
FIGURE
图 1
IB and IOS vs Common-Mode Voltage
Input Bias Current vs Temperature
图 2
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR vs Temperature
图 3
图 4
0.1-Hz to 10-Hz Noise
图 5
Input Voltage Noise Spectral Density vs Frequency
Open-Loop Gain and Phase vs Frequency
Open-Loop Gain vs Temperature
图 6
图 7
图 8
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
No Phase Reversal
图 9
图 10, 图 11
图 12
Positive Overload Recovery
图 13
Negative Overload Recovery
图 14
Small-Signal Step Response (100 mV)
Large-Signal Step Response
图 15, 图 16
图 17, 图 18
图 19
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Channel Separation vs Frequency
图 20
图 21
图 22
图 23
EMIRR IN+ vs Frequency
图 24
10
版权 © 2017–2018, Texas Instruments Incorporated
OPA180-Q1, OPA2180-Q1
www.ti.com.cn
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
7.8 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
4000
3000
2000
1000
0
500
400
300
200
100
0
IIB+
IIB-
IIO
+IIB
-IIB
IIO
-100
-200
-300
-1000
-2000
-55 -35 -15
5
25
45
65
85
105 125
-20
-15
-10
-5
0
5
10
15
20
Temperature (°C)
VCM (V)
图 2. Input Bias Current vs Temperature
图 1. IIB and IIO vs Common-Mode Voltage
20
19
40
35
30
25
20
15
10
5
(V-) < VCM < (V+) - 1.5 V
-40°C
(V-) + 0.5 V < VCM < (V+) - 1.5 V
85°C
18
125°C
17
16
15
14
-14
-15
-16
-17
-18
-19
-20
0
0
2
4
6
8
10 12 14 16 18 20 22 24
-55 -35 -15
5
25
45
65
85
105 125
Output Current (mA)
Temperature (°C)
VSUPPLY = ±2 V
图 3. Output Voltage Swing vs Output Current
图 4. CMRR vs Temperature
(Maximum Supply)
100
10
1
Time (1 s/div)
0.1
1
10
100
1k
10k
100k
Peak-to-Peak Noise = 250 nV
Frequency (Hz)
图 5. 0.1-Hz to 10-Hz Noise
图 6. Input Voltage Noise Spectral Density vs Frequency
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OPA180-Q1, OPA2180-Q1
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
www.ti.com.cn
Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
140
120
100
80
180
135
90
45
0
3
2.5
2
Gain
Phase
VSUPPLY = 4 V, RL = 10 kW
VSUPPLY = 36 V, RL = 10 kW
60
1.5
1
40
20
0
0.5
0
−20
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
G007
-55 -35 -15
5
25
45
65
85
105 125
Temperature (°C)
图 7. Open-Loop Gain and Phase vs Frequency
图 8. Open-Loop Gain vs Temperature
10k
40
35
30
25
20
15
10
5
ROUT = 0 W
ROUT = 25 W
ROUT = 50 W
1k
100
10
G = 1
18 V
ROUT
Device
1
RL
CL
-18 V
0
1m
1
10
100
1k
10k
100k
1M
10M
0
100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Capacitive Load (pF)
RL = 10 kΩ
图 9. Open-Loop Output Impedance vs Frequency
图 10. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
40
35
30
25
20
15
10
5
18 V
ROUT = 0 W
ROUT = 25 W
ROUT = 50 W
Device
-18 V
37 VPP
Sine Wave
(±18.5 V)
RF = 10 kW
RI = 10 kW
G = -1
18 V
ROUT
VI
Device
CL
VO
-18 V
0
Time (100 ms/div)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
RL = 10 kΩ
图 12. No Phase Reversal
图 11. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
12
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Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
VI
VO
20 kW
20 kW
18 V
2 kW
18 V
2 kW
VO
Device
VO
VI
Device
VI
-18 V
-18 V
G = -10
G = -10
VO
VI
Time (5 ms/div)
Time (5 ms/div)
图 13. Positive Overload Recovery
图 14. Negative Overload Recovery
RI = 2 kW RF = 2 kW
G = 1
+18 V
18 V
Device
Device
-18 V
RL
CL
CL
-18 V
G = -1
Time (20 ms/div)
Time (1 ms/div)
RL = 10 kΩ
CL = 10 pF
RL = 10 kΩ
CL = 10 pF
图 16. Small-Signal Step Response (100 mV)
图 15. Small-Signal Step Response
(100 mV)
Time (50 ms/div)
Time (50 ms/div)
G = 1
RL = 10 kΩ
CL = 10 pF
G = –1
RL = 10 kΩ
CL = 10 pF
图 17. Large-Signal Step Response
图 18. Large-Signal Step Response
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OPA180-Q1, OPA2180-Q1
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Typical Characteristics (接下页)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
10
10
8
8
6
6
4
4
12-Bit Settling
12-Bit Settling
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
(±1/2 LSB = ±0.024%)
(±1/2 LSB = ±0.024%)
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Time (ms)
Time (ms)
G = –1
G = –1
图 19. Large-Signal Settling Time (10-V Positive Step)
图 20. Large-Signal Settling Time (10-V Negative Step)
30
15
VS = ±15 V
20
10
12.5
10
7.5
5
Maximum output voltage without
slew-rate induced distortion.
ISC, Source
ISC, Sink
0
VS = ±5 V
-10
-20
-30
2.5
0
VS = ±2.25 V
-55 -35 -15
5
25
45
65
85
105 125
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
图 21. Short-Circuit Current vs Temperature
图 22. Maximum Output Voltage vs Frequency
-60
-70
160
140
120
100
80
Channel A to B
Channel B to A
-80
-90
-100
-110
-120
-130
-140
-150
60
40
20
0
1
10
100
1k
10k 100k
1M
10M 100M
10M
100M
Frequency (Hz)
1G
10G
Frequency (Hz)
图 23. Channel Separation vs Frequency
图 24. EMIRR IN+ vs Frequency
14
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8 Detailed Description
8.1 Overview
The OPAx180-Q1 family of operational amplifiers combine precision offset and drift with excellent overall
performance, making them designed for many precision applications. The precision offset drift of only 0.1 µV/°C
provides stability over the entire temperature range. In addition, the devices offer excellent overall performance
with high CMRR, PSRR, and AOL
.
As with all amplifiers, applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.
8.2 Functional Block Diagram
V+
C2
Notch
CHOP1
GM1
CHOP2
Filter
GM2
GM3
+
-
+
+
OUT
+IN
-IN
-
+
-
-
C1
+
-
GM_FF
Copyright © 2017, Texas Instruments Incorporated
V-
版权 © 2017–2018, Texas Instruments Incorporated
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OPA180-Q1, OPA2180-Q1
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8.3 Feature Description
8.3.1 Operating Characteristics
The OPAx180-Q1 family of amplifiers is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics.
8.3.2 EMI Rejection
The OPAx180-Q1 family uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely populated boards with a mix of analog
signal chain and digital components. EMI immunity can improve with circuit design techniques; the OPAx180-Q1
family benefits from these design improvements. Texas Instruments has developed the ability to accurately
measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from
10 MHz to 6 GHz. 图 25 shows the results of this testing on the OPAx180-Q1 family . For more detailed
information, see the EMI Rejection Ratio of Operational Amplifiers application report, available for download from
www.ti.com.
160
140
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1G
10G
图 25. OPAx180-Q1 EMIRR Testing
8.3.3 Phase-Reversal Protection
The OPAx180-Q1 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when
the input is driven beyond the linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The input of the OPAx180-Q1 prevents phase reversal with excessive
common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in 图 26.
18 V
Device
-18 V
37 VPP
Sine Wave
(±18.5 V)
VI
VO
Time (100 ms/div)
图 26. No Phase Reversal
16
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ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
Feature Description (接下页)
8.3.4 Capacitive Load and Stability
The dynamic characteristics of the OPAx180-Q1 are optimized for a range of common operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series
with the output. 图 27 and 图 28 illustrate graphs of small-signal overshoot versus capacitive load for several
values of ROUT. See the Feedback Plots Define Op Amp AC Performance, application report, available for
download from the TI website, for details of analysis techniques and application circuits.
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
ROUT = 0 W
ROUT = 25 W
ROUT = 50 W
ROUT = 0 W
ROUT = 25 W
ROUT = 50 W
G = 1
18
V
RF = 10 kW
RI = 10 kW
G = -1
ROUT
18 V
Device
ROUT
RL
CL
-18
V
Device
CL
-18 V
0
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
100-mV output
100-mV output
RL = 10 kΩ
RL = 10 kΩ
step
step
图 27. Small-Signal Overshoot Versus Capacitive Load
图 28. Small-Signal Overshoot Versus Capacitive Load
8.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in the Absolute Maximum Ratings table. 图 29 shows how a series input resistor may be added
to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input
and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10 mA max
VOUT
VIN
Device
5 kW
图 29. Input Current Protection
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse as the pulse discharges through a semiconductor device. The ESD protection circuits are designed
to provide a current path around the operational amplifier core to protect the core from damage. The energy
absorbed by the protection circuitry is then dissipated as heat.
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Feature Description (接下页)
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise when an
applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that
some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins. The zener voltage must be selected so the diode does not turn on during normal
operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe operating supply voltage level.
8.4 Device Functional Modes
The OPAx180-Q1, and OPA2180-Q1 devices are powered on when the supply is connected. These devices can
operate as a single-supply operational amplifier or dual-supply amplifier depending on the application. In single-
supply operation with V– at ground (0 V), V+ can be any value between 4 V and 36 V. In dual-supply operation,
the supply voltage difference between V– and V+ is from 4 V to 36 V. Typical examples of dual-supply
configuration are ±5 V, ±10 V, ±15 V, and ±18 V. However, the supplies must not be symmetrical. Less common
examples are V– at –3 V and V+ at 9 V, or V– at –16 V and V+ at 5 V. Any combination where the difference
between V– and V+ is at least 4 V and no greater than 36 V is within the normal operating capabilities of these
devices.
18
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9 Application and Implementation
9.1 Application Information
The OPAx180-Q1 family offers excellent DC precision and AC performance. These devices operate up to 36-V
supply rails and offer rail-to-rail output, ultra-low offset voltage, offset voltage drift and 2-MHz bandwidth. These
features make the OPAx180-Q1 a robust, high-performance amplifier for high-voltage industrial applications.
9.2 Typical Applications
These application examples highlight a few of the circuits where the OPAx180-Q1 family can be used.
9.2.1 Bipolar ±10-V Analog Output from a Unipolar Voltage Output DAC
This design is used for conditioning a unipolar digital-to-analog converter (DAC) into an accurate bipolar signal
source using the OPAx180-Q1 family and three resistors. The circuit is designed with reactive load stability in
mind, and is compensated to drive nearly any conventional capacitive load associated with long cable lengths.
RG1
RFB
CCOMP
VREF
RG2
VOUT
+
DAC8560
RISO
CLOAD
Device
Copyright © 2017, Texas Instruments Incorporated
图 30. Circuit Schematic
9.2.1.1 Design Requirements
The design requirements are as follows:
•
•
•
•
DAC Supply Voltage: 5-V DC
Amplifier Supply Voltage: ±15-V DC
Input: 3-Wire, 24-Bit SPI
Output: ±10-V DC
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OPA180-Q1, OPA2180-Q1
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Typical Applications (接下页)
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Component Selection
DAC: For convenience, devices with an external reference option or devices with accessible internal references
are desirable in this application because the reference creates an offset. The DAC selection in this design must
primarily be based on DC error contributions typically described by offset error, gain error, and integral
nonlinearity error. Occasionally, additional specifications are provided that summarize end-point errors of the
DAC typically called zero-code and full-scale errors. For AC applications, slew rate and settling time may require
additional consideration.
Amplifier: Amplifier input offset voltage (VIO) is a key consideration for this design. VIO of an operational amplifier
is a typical data sheet specification, but in-circuit performance is affected by drift over temperature, the common-
mode rejection ratio (CMRR), and power-supply rejection ratio (PSRR). Consideration must be given to these
parameters. For AC operation, additional considerations must be made for slew rate and settling time. Input bias
current (IIB) is also a factor, but typically the resistor network is implemented with sufficiently small resistor values
that the effects of input bias current are negligible.
Passive: Resistor matching for the op-amp resistor network is critical for the success of this design; components
with tight tolerances must be selected. For this design, 0.1% resistor values are implemented, but this constraint
may be adjusted based on application-specific design goals. Resistor matching contributes to offset error and
gain error in this design; see Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC for further details.
The tolerance of the RISOand CCOMP stability components is not critical, and 1% components are acceptable.
9.2.1.3 Application Curves
图 31. Full-Scale Output Waveform
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www.ti.com.cn
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
Typical Applications (接下页)
图 32. DC Transfer Characteristic
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIPD125, Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC
版权 © 2017–2018, Texas Instruments Incorporated
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OPA180-Q1, OPA2180-Q1
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9.2.2 Discrete INA + Attenuation
The OPAx180-Q1 family can be used as a high-voltage, high-impedance front-end for a precision, discrete
instrumentation amplifier with attenuation. The INA159 in 图 33 provides the attenuation that allows this circuit to
simply interface with 3.3-V or 5-V analog-to-digital converters (ADCs).
15 V
U2
½
VOUTP
OPA2180-Q1
3.3 V
R5
VDIFF / 2
-15 V
1 kW
Ref 1
Ref 2
RG
500 W
R7
U1
INA159
VOUT
+
1 kW
VCM
10
Sense
-15 V
-VDIFF / 2
U5
½
VOUTN
OPA2180-Q1
15 V
Copyright © 2017, Texas Instruments Incorporated
图 33. Discrete INA + Attenuation for ADC With a 3.3-V Supply
9.2.3 RTD Amplifier
The OPAx180-Q1 is excellent for use in analog linearization of resistance temperature detectors (RTDs). The
circuit below (图 34) combines the precision of the OPAx180-Q1 amplifier and the precision reference of the
REF5050 to linearize a Pt100 RTD.
15 V
(5 V)
Out
In
REF5050
1 µF
R2
49.1 kꢀ
GND
1 µF
GND
R1
4.99 kꢀ
R3
60.4 kꢀ
œ
0°C = 0 V
200°C = 5 V
VOUT
+
OPA2180-Q1
RTD
Pt100
R5
105.8 kꢀ
R4
1 kꢀ
GND
Copyright © 2017, Texas Instruments Incorporated
(1) R5 provides positive-varying excitation to linearize output.
图 34. RTD Amplifier with Linearization
22
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OPA180-Q1, OPA2180-Q1
www.ti.com.cn
ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
10 Power Supply Recommendations
The OPAx180-Q1 family is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply
from –40°C to +105°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Layout
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout .
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OPA180-Q1, OPA2180-Q1
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www.ti.com.cn
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep the input traces separate, it is much better to cross the sensitive
trace perpendicular as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in 图 35, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
图 35. Operational Amplifier Board Layout for Noninverting Configuration
24
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ZHCSGA5A –JUNE 2017–REVISED JUNE 2018
12 器件和文档支持
12.1 相关链接
表 3 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 3. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
OPA180-Q1
OPA2180-Q1
12.2 商标
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
25
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA180QDGKRQ1
OPA2180QDGKRQ1
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
180
NIPDAUAG
2180
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA180QDGKRQ1
OPA2180QDGKRQ1
VSSOP
VSSOP
DGK
DGK
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA180QDGKRQ1
OPA2180QDGKRQ1
VSSOP
VSSOP
DGK
DGK
8
8
2500
2500
366.0
366.0
364.0
364.0
50.0
50.0
Pack Materials-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
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