OPA2131UA/2K5G4 [TI]
General-Purpose FET-INPUT OPERATIONAL AMPLIFIERS;型号: | OPA2131UA/2K5G4 |
厂家: | TEXAS INSTRUMENTS |
描述: | General-Purpose FET-INPUT OPERATIONAL AMPLIFIERS 放大器 输入元件 光电二极管 |
文件: | 总18页 (文件大小:1041K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
OPA131
OPA2131
OPA4131
OP
A2
O
PA131
1
3
O
1
P
A
4
1
3
1
O
O
P
A
P
A
1
2
1
3
3
1
1
O
P
A
4
13
1
O
P
A
4
1
3
1
SBOS040A – NOVEMBER 1994 – REVISED DECEMBER 2002
General-Purpose
FET-INPUT OPERATIONAL AMPLIFIERS
FEATURES
ꢀ FET INPUT: IB = 50pA max
OPA131
ꢀ LOW OFFSET VOLTAGE: 750µV max
ꢀ WIDE SUPPLY RANGE: ±4.5V to ±18V
ꢀ SLEW RATE: 10V/µs
Offset Trim
1
2
3
4
8
7
6
5
NC
–In
+In
V–
V+
ꢀ WIDE BANDWIDTH: 4MHz
Output
Offset Trim
ꢀ EXCELLENT CAPACITIVE LOAD DRIVE
ꢀ SINGLE, DUAL, QUAD VERSIONS
DIP-8, SO-8
OPA2131
DESCRIPTION
The OPA131 series of FET-input op amps provides high
performance at low cost. Single, dual, and quad versions in
industry-standard pinouts allow cost-effective design op-
tions.
Out A
–In A
+In A
V–
1
2
3
4
8
7
6
5
V+
A
Out B
–In B
+In B
The OPA131 series offers excellent general-purpose perfor-
mance, including low offset voltage, drift, and good dynamic
characteristics.
B
Single, dual, and quad versions are available in DIP and SO
packages. Performance grades include commercial and in-
dustrial temperature ranges.
DIP-8, SO-8
OPA4131
OPA4131
Out A
1
2
3
4
5
6
7
8
16 Out D
15 –In D
14 +In D
13 V–
Out A
–In A
+In A
V+
1
2
3
4
5
6
7
14 Out D
13 –In D
12 +In D
11 V–
–In A
+In A
V+
A
D
C
A
D
C
+In B
–In B
Out B
NC
12 +In C
11 –In C
10 Out C
+In B
–In B
Out B
10 +In C
B
B
9
8
–In C
Out C
9
NC
DIP-14, SO-14
NC = No Connection
SOL-16
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Supply Voltage, V+ to V–.................................................................... 36V
Input Voltage .................................................. (V–) – 0.7V to (V+) + 0.7V
Output Short-Circuit(2) .............................................................. Continuous
Operating Temperature ..................................................–55°C to +125°C
Storage Temperature .....................................................–55°C to +125°C
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 10s) ................................................. 300°C
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) Short-circuit to ground, one amplifier per package.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
Single
OPA131
SO-8
"
SO-8
"
SO-8
"
D
"
D
"
D
"
–40°C to +85°C
OPA131UJ
OPA131UJ
OPA131UJ/2K5
OPA131UA
OPA131UA/2K5
OPA131U
Rails, 100
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Rails, 100
"
"
"
OPA131
–40°C to +85°C
OPA131UA
"
OPA131
"
"
"
–40°C to +85°C
OPA131U
"
"
OPA131U/2K5
Tape and Reel, 2500
Dual
OPA2131
"
OPA2131
SO-8
"
SO-8
D
"
D
–40°C to +85°C
OPA2131UJ
"
OPA2131UA
OPA2131UJ
OPA2131UJ/2K5
OPA2131UA
Rails, 100
Tape and Reel, 2500
Rails, 100
"
–40°C to +85°C
"
"
"
"
"
OPA2131UA/2K5
Tape and Reel, 2500
Quad
OPA4131
DIP-14
"
SOL-16
N
"
DW
"
D
"
–40°C to +85°C
OPA4131PJ
OPA4131PA
OPA4131UA
"
OPA4131NJ
OPA4131NA
OPA4131PJ
OPA4131PA
OPA4131UA
OPA4131UA/1K
OPA4131NJ
OPA4131NA
Rails, 25
Rails, 25
Rails, 48
"
"
OPA4131
–40°C to +85°C
"
OPA4131
"
"
"
Tape and Reel, 1000
Rails, 58
SOL-14
"
–40°C to +85°C
"
Rails, 58
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
OPA131, 2131, 4131
2
SBOS040A
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = ±15V, and RL = 2kΩ, unless otherwise noted.
OPA131UA
OPA2131UA
OPA131UJ
OPA2131UJ
OPA4131PA, UA, NA
OPA4131PJ, NJ
PARAMETER
CONDITION
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
OFFSET VOLTAGE
Input Offset Voltage
OPA131U model only
vs Temperature(1)
vs Power Supply
OPA131U model only
±0.2
±0.2
±2
50
50
±1
ꢀ
±1.5
mV
mV
µV/°C
µV/V
µV/V
0.75
±10
200
100
Operating Temperature Range
ꢀ
ꢀ
ꢀ
ꢀ
V
S = ±4.5V to ±18V
INPUT BIAS CURRENT(2)
Input Bias Current
vs Temperature
VCM = 0V
+5
±50
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
pA
pA
See Typical Characteristic
Input Offset Current
V
CM = 0V
±1
±50
NOISE
Input Voltage Noise
Noise Density, f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
Current Noise Density, f = 1kHz
21
16
15
15
3
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection
OPA131U model only
(V–) + 3
70
80
(V+) – 1
ꢀ
ꢀ
ꢀ
V
dB
dB
V
CM = –12V to +14V
80
86
ꢀ
INPUT IMPEDANCE
Differential
Common-Mode
1010 || 1
1012 || 3
ꢀ
ꢀ
Ω || pF
Ω || pF
VCM = 0V
OPEN-LOOP GAIN
Open-Loop Voltage Gain
OPA131U model only
VO = –12V to +12V
94
100
110
110
ꢀ
ꢀ
dB
dB
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time 0.1%
0.01%
4
10
1.5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MHz
V/µs
µs
µs
%
G = –1, 10V Step, CL = 100pF
G = –1, 10V Step, CL = 100pF
1kHz, G = 1, VO = 3.5Vrms
2
Total Harmonic Distortion + Noise
0.0008
OUTPUT
Voltage Output, Positive
Negative
Short-Circuit Current
(V+) – 3 (V+) – 2.5
(V–) + 3 (V–) + 2.5
±25
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
mA
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current (per amplifier)
±15
±4.5
ꢀ
ꢀ
V
V
mA
±18
±1.75
ꢀ
ꢀ
±2
IO = 0
±1.5
TEMPERATURE RANGE
Operating Range
Storage
–55
–55
+125
+125
–55
ꢀ
+125
ꢀ
°C
°C
Thermal Resistance, θJA
DIP-8
SO-8
DIP-14
SO-14, SOL-16
100
150
80
ꢀ
ꢀ
ꢀ
ꢀ
°C/W
°C/W
°C/W
°C/W
110
ꢀ Specifications same as OPA131UA.
NOTES: (1) Ensured by wafer test. (2) High-speed test at TJ = 25°C.
OPA131, 2131, 4131
3
SBOS040A
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±15V, and RL = 2kΩ, unless otherwise noted.
POWER SUPPLY AND COMMON-MODE REJECTION
vs FREQUENCY
OPEN-LOOP GAIN/PHASE vs FREQUENCY
120
0
120
100
80
60
40
20
0
120
100
80
60
40
20
0
100
80
+PSR
–45
–90
–135
–180
60
–PSR
40
CMR
20
G
0
–20
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
INPUT VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
CHANNEL SEPARATION vs FREQUENCY
1k
1k
160
140
120
100
80
RL = ∞
100
100
10
Voltage Noise
Dual and quad devices.
G = 1, all channels.
RL = 2kΩ
10
1
Quad measured channel
A to D or B to C—other
combinations yield improved
rejection.
Current Noise
1
10
100
1k
Frequency (Hz)
10k
100k
1
10
100
1k
10k
100k
1M
Frequency (Hz)
INPUT BIAS CURRENT
vs INPUT COMMON-MODE VOLTAGE
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
1k
10k
1k
Input bias current is a
function of the voltage
between the V– supply
and the inputs.
VCM = 0V
100
10
1
100
10
IB
IOS
VS = ±15V
1
0.1
0.01
VS = ±5V
–15
–10
–5
0
5
10
15
–75
–50
–25
0
25
50
75
100
125
Common-Mode Voltage (V)
Ambient Temperature (°C)
OPA131, 2131, 4131
4
SBOS040A
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = ±15V, and RL = 2kΩ, unless otherwise noted.
QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT
vs TEMPERATURE
OPEN-LOOP GAIN vs TEMPERATURE
120
1.8
1.6
1.4
1.2
1
40
30
20
10
0
IQ
ISC–
VS = ±15V
115
110
105
100
ISC+
IQ
VS = ±5V
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
Ambient Temperature (°C)
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
35
30
25
20
15
10
5
20
Typical production distribution
of packaged units. Single,
dual and quad units included.
Typical production distribution
of packaged units. Single,
dual and quad units included.
15
10
5
0
0
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
Offset Voltage Drift (µV/°C)
Offset Voltage (µV)
MAXIMUM OUTPUT VOLTAGE
vs FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
30
20
10
0
1
0.1
Bandwidth-
Limited
VS = ±15V
VO = 3.5Vrms
G = 100V/V
Maximum output voltage
without slew-rate induced
distortion.
0.01
G = 10V/V
G = 1V/V
100
VS = ±5V
0.001
0.0001
10k
100k
1M
10M
10
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
OPA131, 2131, 4131
5
SBOS040A
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TCASE = +25°C, VS = ±15V, and RL = 2kΩ, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
G = 1, CL = 300pF
SMALL-SIGNAL STEP RESPONSE
G =1, CL = 300pF
1µs/div
200ns/div
SMALL-SIGNAL OVERSHOOT
vs LOAD CAPACITANCE
SETTLING TIME vs CLOSED-LOOP GAIN
100
50
40
30
20
10
0
RL = 2kΩ
VO = 10V Step
RL = 2kΩ
CL = 100pF
Higher RL value
generally reduces
overshoot.
G = –1
G = +2
10
G = ±10
0.01%
G = 1
0.1%
1
–1
–10
–100
–1000
100pF
1nF
Load Capacitance
10nF
Closed-Loop Gain (V/V)
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
VIN = 15V
15
14
13
12
11
10
25°C
–55°C
125°C
–10
–11
–12
–13
–14
–15
25°C
125°C
–55°C
VIN = –15V
0
5
10
15
20
25
30
Output Current (mA)
OPA131, 2131, 4131
6
SBOS040A
www.ti.com
APPLICATIONS INFORMATION
V+
The OPA131 series op amps are unity-gain stable and
suitable for a wide range of general-purpose applications.
Power-supply pins should be bypassed with 10nF ceramic
capacitors or larger.
OPA131
(Single op amp only)
7
2
3
6
OPA131
5
The OPA131 series op amps are free from unexpected
output phase-reversal common with FET op amps. Many
FET-input op amps exhibit phase-reversal of the output when
the input common-mode voltage range is exceeded. This can
occur in voltage-follower circuits, causing serious problems
in control-loop applications. All circuitry is completely inde-
pendent in dual and quad versions, assuring normal behavior
when one amplifier in a package is overdriven or short-
circuited.
1
4
100kΩ
Trim Range: ±20mV typ
V–
FIGURE 1. OPA131 Offset Voltage Trim Circuit.
INPUT BIAS CURRENT
OFFSET VOLTAGE TRIM
The input bias current is approximately 5pA at room tem-
perature and increases with temperature as shown in the
typical characteristic “Input Bias Current vs Temperature.”
The OPA131 (single op amp version) provides offset volt-
age trim connections on pins 1 and 5. Offset voltage can be
adjusted by connecting a potentiometer as shown in Figure
1. This adjustment should be used only to null the offset of
the op amp, not system offset or offset produced by the
signal source.
Input bias current also varies with common-mode voltage
and power supply voltage. This variation is dependent on the
voltage between the negative power supply and the com-
mon-mode input voltage. The effect is shown in the typical
curve “Input Bias Current vs Common-Mode Voltage.”
OPA131, 2131, 4131
7
SBOS040A
www.ti.com
PACKAGE DRAWINGS
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.069 (1,75) MAX
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
16
DIM
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/E 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
OPA131, 2131, 4131
8
SBOS040A
www.ti.com
PACKAGE DRAWINGS (Cont.)
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0° – 8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
0.610
28
DIM
0.410
0.462
0.510
0.710
A MAX
A MIN
(10,41) (11,73) (12,95) (15,49) (18,03)
0.400
0.453
0.500
0.600
0.700
(10,16) (11,51) (12,70) (15,24) (17,78)
4040000 /E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
OPA131, 2131, 4131
9
SBOS040A
www.ti.com
PACKAGE DRAWINGS (Cont.)
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.035 (0,89) MAX
0.020 (0,51) MIN
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
M
14/18 PIN ONLY
4040049/D 02/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
OPA131, 2131, 4131
10
SBOS040A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
Drawing
OPA131P
OPA131PA
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
P
P
8
8
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
OPA131PJ
P
8
Call TI
Call TI
OPA131U
D
8
100
2500
100
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
Call TI
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Call TI
OPA131U/2K5
OPA131UA
ACTIVE
D
8
ACTIVE
D
8
OPA131UA/2K5
OPA131UJ
ACTIVE
D
8
2500
100
ACTIVE
D
8
OPA131UJ/2K5
OPA2131PA
OPA2131PJ
OPA2131UA
OPA2131UA/2K5
OPA2131UJ
OPA2131UJ/2K5
OPA4131NA
OPA4131NJ
OPA4131PA
OPA4131PJ
OPA4131UA
OPA4131UA/1K
ACTIVE
D
8
2500
OBSOLETE
OBSOLETE
ACTIVE
P
8
P
8
Call TI
Call TI
D
8
100
2500
100
2500
58
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
Call TI
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-235C-168 HR
Level-NA-NA-NA
Level-NA-NA-NA
Level-3-260C-168 HR
Level-3-260C-168 HR
ACTIVE
D
8
ACTIVE
D
8
ACTIVE
D
8
ACTIVE
D
14
14
14
14
16
16
ACTIVE
D
58
ACTIVE
N
25
ACTIVE
N
25
Call TI
ACTIVE
DW
DW
48
CU SNPB
CU SNPB
ACTIVE
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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