OPA2132U [TI]
具有 FET 输入的双路 SoundPlus™ 8MHz、5pA 高性能音频运算放大器 | D | 8 | -40 to 125;
| 型号： | OPA2132U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 FET 输入的双路 SoundPlus™ 8MHz、5pA 高性能音频运算放大器 | D | 8 | -40 to 125 放大器 PC 光电二极管 运算放大器 |
| 文件： | 总30页 (文件大小：810K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA132, OPA2132, OPA4132
SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
OPAx132 High-Speed FET-Input Operational Amplifiers
1 Features
3 Description
The OPAx132 series of FET-input operational
1
•
•
•
•
•
•
•
•
•
FET input: IB = 50 pA Maximum
Wide Bandwidth: 8 MHz
amplifiers provides highspeed and excellent DC
performance. The combination of high slew rate and
wide bandwidth provide fast settling time. Single,
dual, and quad versions have identical specifications
for maximum design flexibility. High performance
grades are available in the single and dual versions.
All are ideal for general-purpose, audio, data
High Slew Rate: 20 V/µs
Low Noise: 8nV/√Hz (1 kHz)
Low Distortion: 0.00008%)
High Open-loop Gain: 130 dB (600-Ω load)
Wide Supply Range: ±2.5 to ±18V
Low Offset Voltage: 500 µV Maximum
Single, Dual, and Quad Versions
acquisition
and
communications
applications,
especially where high source impedance is
encountered.
The OPAx132 operational amplifiers are easy to use
and free from phase inversion and overload problems
often found in common FET-input operational
amplifiers. Input cascode circuitry provides excellent
common-mode rejection and maintains low input bias
current over its wide input voltage range. The
OPAx132 series of operational amplifiers are stable in
unity gain and provide excellent dynamic behavior
over a wide range of load conditions, including high
load capacitance. Dual and quad versions feature
completely independent circuitry for lowest crosstalk
and freedom from interaction, even when overdriven
or overloaded.
2 Applications
•
•
•
•
•
•
SAR ADC Driver
Voltage Reference Buffer
Trans-impedance Amplifier
Photodiode Amplifier
Active Filters
Integrators
Low Noise JFET Input
1k
Single and dual versions are available in 8-pin DIP
and SO-8 surface-mount packages. Quad is available
in 14-pin DIP and SO-14 surface-mount packages. All
are specified for –40°C to 85°C operation
100
Voltage Noise
(1)
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
9.81 mm × 6.35 mm
4.90 mm × 3.91 mm
9.81 mm × 6.35 mm
4.90 mm × 3.91 mm
19.30 mm × 6.35 mm
8.65 mm × 3.91 mm
10
1
PDIP (8) (P)
OPAx132
SOIC (8) (D)
PDIP (8) (P)
SOIC (8) (D)
PDIP (14) (N)
SOIC (14) (D)
Current Noise
OPA2132
OPA4132
1
10
100
1k
Frequency (Hz)
10k
100k
1M
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA132, OPA2132, OPA4132
SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Electrical Characteristics........................................... 5
6.5 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 14
9
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1 Device Support .................................................... 16
11.2 Documentation Support ........................................ 16
11.3 Related Links ........................................................ 16
11.4 Trademarks........................................................... 16
11.5 Electrostatic Discharge Caution............................ 17
11.6 Glossary................................................................ 17
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2004) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
2
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SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
OPA132: P and D Packages
8-Pin PDIP and 8-Pin SOIC
Top View
OPA2132: P and D Packages
8-Pin PDIP and 8-Pin SOIC
Top View
Offset Trim
1
2
3
4
8
7
6
5
Offset Trim
V+
Out A
–In A
+In A
V–
1
2
3
4
8
7
6
5
V+
A
–In
+In
V–
Out B
–In B
+In B
B
Output
NC
8-Pin DIP, SO-8
8-Pin DIP, SO-8
OPA4132: P and D Packages
14-Pin PDIP and 14-Pin SOIC
Top View
Out A
–In A
+In A
V+
1
2
3
4
5
6
7
14 Out D
13 –In D
12 +In D
11 V–
A
D
+In B
–In B
Out B
10 +In C
B
C
9
8
–In C
Out C
14-Pin DIP
SO-14
Pin Functions OPA132
PIN
I/O
DESCRIPTION
NAME
NO.
1
Offset Trim
–In
I
I
Input offset voltage adjust
Inverting input
2
+In
3
I
Noninverting input
V–
4
—
—
O
—
I
Negative power supply
NC
5
No internal connection. Can be left floating.
Output
Output
V+
6
7
Positive power supply
Offset Trim
8
Input offset voltage adjust
Pin Functions OPA2132 and OPA4132
PIN
I/O
DESCRIPTION
OPA2132
NO.
OPA4132
NO.
NAME
Out A
–In A
+In A
V+
1
2
3
8
5
6
7
–
–
1
2
3
4
5
6
7
8
9
O
I
Output channel A
Inverting input channel A
Noninverting input channel A
Positive power supply
Noninverting input channel B
Inverting input channel B
Output channel B
I
—
I
+In B
–In B
Out B
Out C
–In C
I
O
O
I
Output channel C
Inverting input channel C
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Pin Functions OPA2132 and OPA4132 (continued)
PIN
I/O
DESCRIPTION
OPA2132
NO.
OPA4132
NO.
NAME
+In C
V–
–
4
–
–
–
10
11
12
13
14
I
—
I
Noninverting input channel C
Negative power supply
Noninverting input channel D
Inverting input channel D
Output channel D
+In D
–In D
Out D
I
O
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
36
UNIT
V
Supply voltage, V+ to V–
Input voltage
(V–) –0.7
(V+) +0.7
V
Output short-circuit(2)
Operation temperature
Junction temperature
Continuous
–40
125
150
125
°C
°C
°C
Tstg
Storage temperature
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
OPA132 in PDIP and SOIC Package, OPA2132 and OPA4132 in PDIP Package
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
OPA2132 in SOIC Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
OPA4132 in SOIC Package
V(ESD) Electrostatic discharge
Electrostatic discharge
V
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±200
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.5
–40
NOM
MAX
±18
85
UNIT
V
VS
TA
Supply voltage, VS = (V+) – (V–)
Specified temperature range
±15
°C
4
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SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
6.4 Electrical Characteristics
At TA = 25°C, VS = ±15 V, unless otherwise noted.
OPAx132PA, UA
OPA2132PA, UA
OPA4132PA, UA
OPAx132P, U
OPA2132P, U
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature(1)
vs Power Supply
±0.25
±2
±0.5
±10
15
±0.5
±2
±2
±10
30
mV
Operating temperature range
VS = ±2.5 V to ±18 V
µV/°C
µV/V
5
5
Channel Separation (dual and RL = 2 kΩ
quad)
0.2
0.2
µV/V
INPUT BIAS CURRENT
Input Bias Current(2)
vs Temperature
Input Offset Current(2)
NOISE
VCM = 0 V
VCM = 0 V
5
±50
±50
5
See Figure 5
±2
±50
±50
pA
pA
See Figure 5
±2
Input Voltage Noise
f = 10 Hz
23
10
8
23
10
8
f = 100 H
f = 1 kHz
f = 10 kHz
Noise Density
nV/√Hz
fA/√Hz
8
8
Current Noise
Density,
f = 1 kHz
3
3
INPUT VOLTAGE RANGE
(V–)
+2.5
(V+)
–2.5
(V–)
+2.5
(V+)
–2.5
Common-Mode Voltage Range
±13
100
±13
94
V
Common-Mode Rejection
INPUT IMPEDANCE
Differential
VCM = –12.5 V to 12.5 V
VCM = –12.5 V to 12.5 V
96
86
dB
1013 || 2
1013 || 6
1013 || 2
1013 || 6
Ω || pF
Ω || pF
Common-Mode
OPEN-LOOP GAIN
RL = 10 kΩ, VO = –14.5 V
to 13.8 V
110
110
110
120
126
130
104
104
104
120
120
120
RL = 2 kΩ, VO = –13.8 V
to 13.5 V
Open-Loop Voltage Gain
dB
RL = 600 Ω, VO = –12.8 V
to 12.5 V
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
8
8
MHz
V/µs
±20
±20
G = –1, 10 V Step,
CL = 100 pF
0.1%
Settling Time:
0.01%
0.7
1
0.7
1
µs
G = –1, 10 V Step,
CL = 100 pF
µs
µs
Overload Recovery Time
G = ±
0.5
0.00008%
0.00009%
0.5
0.00008%
0.00009%
RL = 2 kΩ
Total Harmonic Distortion +
Noise
1 kHz, G = 1,
VO = 3.5 Vrms
RL = 600 Ω
(1) Specified by wafer test.
(2) High-speed test at TJ = 25°C.
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Electrical Characteristics (continued)
At TA = 25°C, VS = ±15 V, unless otherwise noted.
OPAx132PA, UA
OPA2132PA, UA
OPA4132PA, UA
OPAx132P, U
OPA2132P, U
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
OUTPUT
(V+)
–1.2
(V+)
–0.9
(V+)
–1.2
(V+)
–0.9
Positive
RL = 10 kΩ
(V–)
+0.5
(V–)
+0.3
(V–)
+0.5
(V–)
+0.3
Negative
Positive
Negative
Positive
Negative
(V+)
–1.5
(V+)
–1.1
(V+)
–1.5
(V+)
–1.1
Voltage Output
RL= 2 kΩ
V
(V–)
+1.2
(V–)
+0.9
(V–)
+1.2
(V–)
+0.9
(V+)
–2.5
(V+)
–2.0
(V+)
–2.5
(V+)
–2.0
RL = 600 Ω
(V–)
+2.2
(V–)
+1.5
(V–)
+2.2
(V–)
+1.5
Short-Circuit Current
±40
±40
mA
Capacitive Load Drive (Stable
Operation)
See Figure 17
See Figure 17
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
±15
±4
±15
V
V
±2.5
±18
±2.5
±18
Quiescent Current
(per amplifier)
IO = 0
±4.8
±4
±4.8
mA
TEMPERATURE RANGE
Operating Range
Storage
–40
–40
85
–40
–40
85
°C
°C
125
125
6
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6.5 Typical Characteristics
At TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.
120
100
80
60
40
20
0
160
140
120
100
80
0
–PSR
–45
–90
–135
–180
Φ
60
40
+PSR
G
20
CMR
0
–20
10
100
1k
10k
100k
1M
0.1
1
10
100
1k
10k 100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 1. Open-Loop Gain and Phase vs Frequency
Figure 2. Power Supply and Common-Mode Rejection vs
Frequency
160
1k
RL = ∞
140
100
120
Voltage Noise
RL = 2kΩ
Dual and quad devices.
G = 1, all channels.
10
1
Quad measured channel
100
A to D or B to C—other
combinations yield improved
Current Noise
rejection.
80
100
1k
10k
100k
1
10
100
1k
Frequency (Hz)
10k
100k
1M
Frequency (Hz)
Figure 3. Input Voltage and Current Noise Spectral Density
vs Frequency
Figure 4. Channel Separation vs Frequency
100k
10
9
8
7
6
5
4
3
2
1
0
High Speed Test
High Speed Test
Warmed Up
10k
1k
Quad
100
Dual
10
1
Single
0.1
–75
–50
–25
0
25
50
75
100
125
–15
–10
–5
0
5
10
15
Ambient Temperature (°C)
Common-Mode Voltage (V)
Figure 5. Input Bias Current vs Temperature
Figure 6. Input Bias Current vs Input Common-Mode
Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.
130
4.3
4.2
4.1
4.0
3.9
3.8
60
50
40
30
20
120
110
100
90
Open-Loop
Gain
± ±SC
PSR
± ±Q
CMR
50
10
–75
–50
–25
0
25
75
100
125
–75
–50
–25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 7. AOL, CMR, PSR vs Temperature
Figure 8. Quiescent Current and Short-Circuit Current vs
Temperature
12
10
8
12
Typical production
Typical production distribution
distribution of packaged
units. Single, dual and
quad units included.
10
8
of packaged units. Single,
dual and quad units included.
6
6
4
4
2
2
0
0
Offset Voltage Drift (µV/°C)
Offset Voltage (µV)
Figure 10. Offset Voltage Drift Production Distribution
Figure 9. Offset Voltage Production Distribution
30
0.01
0.001
RL
Maximum output voltage
without slew-rate
VS = ±15V
2kΩ
600Ω
induced distortion
20
10
0
G = +10
0.0001
0.00001
G = +1
VS = ±5V
VO = 3.5Vrms
VS = ±2.5V
10k
100k
Frequency (Hz)
1M
10M
10
100
1k
10k
100k
Frequency (Hz)
Figure 11. Total Harmonic Distortion + Noise vs Frequency
Figure 12. Maximum Output Voltage vs Frequency
8
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.
200ns/div
1μs/div
G = 1
CL = 100pF
G = 1
CL = 100pF
Figure 13. Small-Signal Step Response
Figure 14. Large-Signal Step Response
100
10
1
60
50
40
30
20
10
0
G = +1
0.01%
G = –1
FPO
0.1%
G = 10
0.1
100pF
1nF
10nF
1
10
100
1000
Closed-Loop Gain (V/V)
Load Capacitance
Figure 15. Settling Time vs Closed-Loop Gain
Figure 16. Small-Signal Overshoot vs Load Capacitance
15
VIN = 15V
14
–55°C
25°C
13
12
11
10
125°C
85°C
–10
–11
–12
–13
–14
85°C
125°C
–55°C
25°C
VIN = –15V
10
–15
0
20
30
40
50
60
Output Current (mA)
Figure 17. Output Voltage Swing vs Output Current
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7 Detailed Description
7.1 Overview
The OPAx132 series of FET-input operational amplifiers provides highspeed and excellent dc performance. The
combination of high slew rate and wide bandwidth provide fast settling time. Single, dual, and quad versions
have identical specifications for maximum design flexibility. High performance grades are available in the single
and dual versions. All are ideal for general-purpose, audio, data acquisition and communications applications,
especially where high source impedance is encountered.
7.2 Functional Block Diagram
Input Offset
Adjust
(OPA132 only)
+IN
-IN
+
œ
Output
Input Offset
Adjust
Compensation
(OPA132 only)
7.3 Feature Description
The OPAx132 series of JFET operational amplifiers combine low noise and wide bandwidth with precision and
low input bias current to make them the ideal choice for applications with a high source impedance. The
OPAx132 is unity-gain stable and features high slew rate (±20 V/μs) and wide bandwidth (8 MHz).
7.4 Device Functional Modes
The OPAx132 has a single functional mode and is operational when the power-supply voltage is greater than 5 V
(±2.5 V). The maximum power supply voltage for the OPAx132 is 36 V (±18 V).
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx132 series operational amplifiers are unity-gain stable and suitable for a wide range of general-
purpose applications. Power supply pins should be bypassed with 10-nF ceramic capacitors or larger.
The OPAx132 series operational amplifiers are free from unexpected output phase reversal common with FET
operational amplifiers. Many FET-input operational amplifiers exhibit phase-reversal of the output when the input
common-mode voltage range is exceeded. This can occur in voltage-follower circuits, causing serious problems
in control loop applications. The OPAx132 series of operational amplifiers are free from this undesirable
behavior. All circuitry is completely independent in dual and quad versions, assuring normal behavior when one
amplifier in a package is overdriven or short-circuited.
8.1.1 Operating Voltage
The OPAx132 series of operation amplifiers operate with power supplies from ±2.5 V to ±18 V with excellent
performance. Although specifications are production tested with ±15 V supplies, most behavior remains
unchanged throughout the full operating voltage range. Parameters which vary significantly with operating
voltage are shown in the Typical Characteristics section.
8.1.2 Offset Voltage Trim
Offset voltage of the OPAx132 series of amplifiers is laser trimmed and usually requires no user adjustment. The
OPAx132 amplifier (single op amp version) provides offset voltage trim connections on pins 1 and 8. Offset
voltage can be adjusted by connecting a potentiometer as shown in Figure 18. This adjustment should be used
only to null the offset of the operational amplifier, not to adjust system offset or offset produced by the signal
source. Nulling offset could degrade the offset voltage drift behavior of the operational amplifier. While it is not
possible to predict the exact change in drift, the effect is usually small.
V+
Trim Range: 4mV typ
10nF
100kΩ
7
1
2
8
OPA132
6
3
OPA132 single op amp only.
4
10nF
Use offset adjust pins only to null
offset voltage of op amp—see text.
V–
Figure 18. OPAx132 Offset Voltage Trim Circuit
8.1.3 Input Bias Current
The FET-inputs of the OPAx132 series provide very low input bias current and cause negligible errors in most
applications. For applications where low input bias current is crucial, junction temperature rise should be
minimized. The input bias current of FET-input operational amplifiers increases with temperature as shown in
Figure 5.
The OPAx132 series may be operated at reduced power supply voltage to minimize power dissipation and
temperature rise. Using ±3 V supplies reduces power dissipation to one-fifth that at ±15 V.
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OPA132, OPA2132, OPA4132
SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
www.ti.com
Application Information (continued)
The dual and quad versions have higher total power dissipation than the single, leading to higher junction
temperature. Thus, a warmed-up quad will have higher input bias current than a warmed-up single. Furthermore,
an SOIC will generally have higher junction temperature than a DIP at the same ambient temperature because of
a larger θJA.
Printed-circuit-board layout can also help minimize junction temperature rise. Temperature rise can be minimized
by soldering the devices to the circuit board rather than using a socket. Wide copper traces will also help
dissipate the heat by acting as an additional heat sink.
Input stage cascode circuitry assures that the input bias current remains virtually unchanged throughout the full
input common-mode range of the OPAx132 series. See Figure 6.
8.2 Typical Application
The OPAx132 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer ultralow input bias current and input bias current noise, as well as 8-MHz bandwidth and
high capacitive load drive. These features make the OPAx132 a robust, high-performance operational amplifier
for high-voltage industrial applications with high source impedance.
2.94 kꢀ
1 nF
590 ꢀ
499 ꢀ
Input
œ
Output
39 nF
+
Figure 19. OPA132 2nd Order 30 kHz, Low Pass Filter Schematic
8.2.1 Design Requirements
Use the following parameters for this application:
•
•
•
•
Gain = 5 V/V
Low pass cutoff frequency = 30 kHz
-40 db/dec filter response
Maintain less than 3-dB gain peaking in the gain versus frequency response
8.2.2 Detailed Design Procedure
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
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Product Folder Links: OPA132 OPA2132 OPA4132
OPA132, OPA2132, OPA4132
www.ti.com
SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
Typical Application (continued)
8.2.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
100k
1M
Frequency (Hz)
Figure 20. OPA132 2nd Order 30-kHz, Low Pass Filter Response
Copyright © 1995–2015, Texas Instruments Incorporated
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SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
www.ti.com
9 Power Supply Recommendations
The OPAx132 is specified for operation from 5 V to 36 V (±2.5 V to ±18 V); many specifications apply from
–40°C to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 36 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 10-nF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 10 nF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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Product Folder Links: OPA132 OPA2132 OPA4132
OPA132, OPA2132, OPA4132
www.ti.com
SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
10.2 Layout Example
VIN
+
VOUT
RG
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
Offset trim
Offset trim
RG
GND
VIN
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
Use low-ESR, ceramic
bypass capacitor
GND
Use low-ESR,
ceramic bypass
capacitor
VOUT
VSœ
Ground (GND) plane on another layer
Figure 21. OPA132 Layout Example for the Noninverting Configuration
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Product Folder Links: OPA132 OPA2132 OPA4132
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www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 WEBENCH Filter Designer Tool
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
11.1.1.2 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.3 TI Precision Designs
The OPAx132 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
EMI Rejection Ratio of Operational Amplifiers, SBOA128
Circuit Board Layout Techniques, SLOA089
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
OPA132
OPA2132
OPA4132
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 Trademarks
TINA-TI is a trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
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Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: OPA132 OPA2132 OPA4132
OPA132, OPA2132, OPA4132
www.ti.com
SBOS054B –JANUARY 1995–REVISED SEPTEMBER 2015
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1995–2015, Texas Instruments Incorporated
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Product Folder Links: OPA132 OPA2132 OPA4132
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA132U
OPA132U/2K5
OPA132UA
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
OPA
132U
Samples
Samples
Samples
ACTIVE
ACTIVE
2500 RoHS & Green
75 RoHS & Green
Call TI
Call TI
OPA
132U
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA
132U
A
OPA132UA/2K5
OPA132UAE4
OPA132UAG4
OPA132UG4
ACTIVE
LIFEBUY
LIFEBUY
LIFEBUY
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500 RoHS & Green
Call TI
Call TI
Call TI
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
OPA
132U
A
Samples
75
75
75
RoHS & Green
RoHS & Green
RoHS & Green
OPA
132U
A
OPA
132U
A
OPA
132U
OPA2132P
ACTIVE
ACTIVE
PDIP
PDIP
P
P
8
8
50
50
RoHS & Green
RoHS & Green
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
OPA2132P
Samples
Samples
OPA2132PA
OPA2132P
A
OPA2132PAG4
OPA2132U
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
LIFEBUY
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
P
D
D
D
D
D
8
8
8
8
8
8
50
75
RoHS & Green
RoHS & Green
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
N / A for Pkg Type
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
OPA2132P
A
Samples
Samples
Samples
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA
2132U
OPA2132U/2K5
OPA2132U/2K5E4
OPA2132U/2K5G4
OPA2132UA
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
OPA
2132U
OPA
2132U
OPA
2132U
75
RoHS & Green
OPA
2132U
A
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2132UA/2K5
OPA2132UA/2K5E4
OPA2132UAE4
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
8
8
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
OPA
Samples
2132U
A
LIFEBUY
LIFEBUY
LIFEBUY
D
D
D
NIPDAU
Call TI
OPA
2132U
A
75
75
RoHS & Green
RoHS & Green
OPA
2132U
A
OPA2132UAG4
Call TI
OPA
2132U
A
OPA2132UE4
OPA2132UG4
LIFEBUY
LIFEBUY
SOIC
SOIC
D
D
8
8
75
75
50
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
OPA
2132U
OPA
2132U
OPA4132UA
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
NIPDAU-DCC
NIPDAU-DCC
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
OPA4132UA
Samples
Samples
OPA4132UA/2K5
2500 RoHS & Green
2500 RoHS & Green
OPA4132UA
OPA4132UA/2K5E4
OPA4132UAG4
LIFEBUY
LIFEBUY
SOIC
SOIC
D
D
14
14
NIPDAU-DCC
NIPDAU-DCC
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
OPA4132UA
OPA4132UA
50
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA132U/2K5
OPA132UA/2K5
OPA2132U/2K5
OPA2132UA/2K5
OPA4132UA/2K5
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
8
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
16.4
6.4
6.4
6.4
6.4
6.5
5.2
5.2
5.2
5.2
9.0
2.1
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
8
8
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA132U/2K5
OPA132UA/2K5
OPA2132U/2K5
OPA2132UA/2K5
OPA4132UA/2K5
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
8
2500
2500
2500
2500
2500
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
35.0
35.0
8
8
14
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA132U
OPA132UA
D
D
D
D
D
P
P
P
D
D
D
D
D
D
D
D
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
8
8
75
75
75
75
75
50
50
50
75
75
75
75
75
75
50
50
506.6
506.6
506.6
506.6
506.6
506
8
3940
3940
3940
3940
3940
11230
11230
11230
3940
3940
3940
3940
3940
3940
3940
3940
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
8
OPA132UAE4
OPA132UAG4
OPA132UG4
OPA2132P
8
8
8
8
8
8
8
13.97
OPA2132PA
OPA2132PAG4
OPA2132U
8
506
13.97
8
506
13.97
8
506.6
506.6
506.6
506.6
506.6
506.6
506.6
506.6
8
8
8
8
8
8
8
8
OPA2132UA
OPA2132UAE4
OPA2132UAG4
OPA2132UE4
OPA2132UG4
OPA4132UA
OPA4132UAG4
8
8
8
8
8
14
14
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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