OPA2171MDCUTEP [TI]
Enhanced product, dual, 36-V, 3-MHz, low-power operational amplifier | DCU | 8 | -55 to 125;
| 型号： | OPA2171MDCUTEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Enhanced product, dual, 36-V, 3-MHz, low-power operational amplifier | DCU | 8 | -55 to 125 放大器 光电二极管 |
| 文件： | 总27页 (文件大小：960K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
OPA2171-EP 36V 单电源 SOT553 通用运算放大器
1 特性
2 应用范围
1
•
•
•
•
•
•
•
•
•
•
•
•
•
电源电压范围：2.7V 至 36V，±1.35V 至 ±18V
•
•
•
•
•
•
•
•
•
电源模块内的跟踪放大器
商用电源
低噪声：14nV/√Hz
低偏移漂移：0.3µV/°C（典型值）
已过滤的射频干扰 (RFI) 输入
输入范围包括负电源
变频器放大器
桥式放大器
温度测量
输入范围运行至正电源
应力计放大器
精密积分器
轨至轨输出
增益带宽：3MHz
电池供电仪器
测试设备
低静态电流：每个放大器 475µA
高共模抑制：120dB（典型值）
低输入偏置电流：8pA
3 说明
OPA2171-EP 是一款 36V 单电源低噪声运算放大器，
能够在 2.7V (±1.35V) 至 36V (±18V) 的电源电压范围
内运行。 这个器件采用微型封装并且在保证低静态电
流的情况下提供低偏移、漂移和带宽。 单通道、双通
道和四通道版本均具有相同的技术规格，可最大程度地
提高设计灵活性。
微型封装：VSSOP-8 双列封装
支持国防、航天和医疗应用：
–
–
–
–
–
–
–
可控基线
一个组装/测试场所
一个制造场所
在扩展（-55°C 至 125°C）温度范围内可用
延长的产品生命周期
延长产品的变更通知周期
产品可追溯性
大多数运算放大器仅有一个指定的电源电
压，OPAx2171-EP 则有所不同，其可在 2.7V 至 36V
的电压范围内额定运行。超过电源轨的输入信号不会导
致相位反向。 OPA2171-EP 在电容负载高达 300pF
时可保持稳定。 输入可在负电源轨以下 100mV 以及
正电源轨 2V 之内正常运行。 请注意这些器件可在正
电源轨之上 100mV 的满轨到轨输入上运行，但是在正
电源轨 2V 之内运行时性能会受到影响。
具有 RISO 稳定性补偿的单位增益缓冲器
+VS
VOUT
RISO
+
OPA2171-EP 运算放大器额定工作温度范围为 –55°C
至 125°C。
CLOAD
+
VIN
器件信息(1)
-VS
œ
器件型号
封装
封装尺寸（标称值）
超薄小外形尺寸封装
(VSSOP)(8)
OPA2171-EP
2.30mm x 2.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS735
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 19
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
8
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................ 20
10.2 Layout Example .................................................... 20
11 器件和文档支持 ..................................................... 21
11.1 社区资源................................................................ 21
11.2 商标....................................................................... 21
11.3 静电放电警告......................................................... 21
11.4 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
日期
修订版本
注释
2015 年 9 月
*
最初发布版本。
2
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
5 Pin Configuration and Functions
DCU Package
8-Pin VSSOP
Top View
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
–IN A
–IN B
OUT A
OUT B
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
5
2
I
6
I
1
O
O
—
—
7
Output, channel B
7
Positive (highest) power supply
Negative (lowest) power supply
V–
4
Copyright © 2015, Texas Instruments Incorporated
3
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted(1)
MIN
±20
MAX
UNIT
V
Supply voltage
Voltage
Signal input pins
(V–) – 0.5
–10
(V+) + 0.5
10
V
Current
mA
Output short circuit(2)
Junction temperature
Storage temperature, Tstg
Continuous
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5 (±2.25)
–55
NOM
MAX
36 (±18)
125
UNIT
V
Supply voltage (V+ – V–)
Operating temperature, TJ
°C
6.4 Thermal Information
OPA2171-EP
DCU (VSSOP)
8 PINS
175.2
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
74.9
22.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
1.6
ψJB
22.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
6.5 Electrical Characteristics
at TJ = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input offset voltage
Over temperature
Drift
VOS
0.25
0.3
0.3
1
±1.8
±2
mV
mV
TJ = –55°C to 125°C
dVOS/dT TJ = –55°C to 125°C
µV/°C
vs power supply
Channel separation, dc
INPUT BIAS CURRENT
Input bias current
Over temperature
Input offset current
Over temperature
NOISE
PSRR
VS = 4 to 36 V, TA = –55°C to 125°C
±5 µV/V
µV/V
dc
5
IB
±8
±4
±15
pA
nA
pA
nA
TJ = –55°C to 125°C
TJ = –55°C to 125°C
±4
IOS
±4
Input voltage noise
ƒ = 0.1 to 10 Hz
ƒ = 100 Hz
3
25
14
µVPP
nV/√Hz
nV/√Hz
Input voltage noise density
en
ƒ = 1 kHz
INPUT VOLTAGE
Common-mode voltage
range(1)
VCM
(V–) – 0.1 V
(V+) – 2 V
V
VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TJ = –55°C to 125°C
87
104
120
dB
dB
Common-mode rejection
ratio
CMRR
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TJ = –55°C to 125°C
104
INPUT IMPEDANCE
MΩ ||
pF
1012Ω ||
pF
Differential
100 || 3
6 || 3
Common-mode
OPEN-LOOP GAIN
Open-loop voltage gain
VS = 4 to 36 V, (V–) + 0.35 V < VO < (V+) –
0.35 V, TJ = –55°C to 125°C
AOL
110
130
dB
FREQUENCY RESPONSE
Gain bandwidth product
Slew rate
GBP
SR
3.0
1.5
6
MHz
V/µs
µs
G = +1
To 0.1%, VS = ±18 V, G = +1, 10-V step
Settling time
tS
To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V
step
10
2
µs
µs
Overload recovery time
VIN × Gain > VS
Total harmonic distortion +
noise
THD+N
VO
G = +1, ƒ = 1kHz, VO = 3VRMS
0.0002%
OUTPUT
Voltage output swing from
rail
VS = 5 V, RL = 10 kΩ
30
mV
V
RL = 10 kΩ, AOL ≥ 110 dB,
TJ = –55°C to 125°C
Over temperature
(V–) + 0.35
(V+) – 0.35
Short-circuit current
Capacitive load drive
ISC
+25/–35
mA
pF
Ω
CLOAD
See Typical Characteristics
Open-loop output resistance RO
ƒ = 1 MHz, IO = 0 A
150
(1) The input range can be extended beyond (V+) – 2 V up to V+. See Typical Characteristics and Application and Implementation for
additional information.
Copyright © 2015, Texas Instruments Incorporated
5
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
Electrical Characteristics (continued)
at TJ = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX UNIT
Specified voltage range
VS
IQ
2.7
36
595
650
V
Quiescent current per
amplifier
IO = 0 A
IO = 0 A, TJ = –55°C to 125°C
475
µA
µA
Over temperature
TEMPERATURE
Operating temperature
TJ
–55
125
°C
6
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
6.6 Typical Characteristics
Table 1. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Figure 1
Offset Voltage Production Distribution
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Offset Voltage vs Power Supply
Figure 5
Figure 6
IB and IOS vs Common-Mode Voltage
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred-to Input)
CMRR vs Temperature
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23, Figure 24
Figure 25
Figure 26
Figure 27
Figure 28, Figure 29
Figure 30, Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
PSRR vs Temperature
0.1-Hz to 10-Hz Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Temperature
Quiescent Current vs Supply Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
No Phase Reversal
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (100 mV)
Large-Signal Step Response
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Channel Separation vs Frequency
Copyright © 2015, Texas Instruments Incorporated
7
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
16
14
12
10
8
25
20
15
10
5
Distribution Taken From 3500 Amplifiers
Distribution Taken From 110 Amplifiers
6
4
2
0
0
Offset Voltage (mV)
Offset Voltage Drift (mV/°C)
Figure 2. Offset Voltage Drift Distribution
Figure 1. Offset Voltage Production Distribution
1000
800
600
400
10 Typical Units Shown
5 Typical Units Shown
600
200
400
200
0
0
-200
-400
-600
-800
-200
-400
-600
-800
-1000
VCM = -18.1V
-20
-15
-10
-5
0
5
10
15
20
-75 -50 -25
0
25
50
75
100 125 150
VCM (V)
Temperature (°C)
Figure 3. Offset Voltage vs Temperature
Figure 4. Offset Voltage vs Common-Mode Voltage
10000
8000
350
10 Typical Units Shown
VSUPPLY = ±1.35V to ±18V
10 Typical Units Shown
250
150
6000
4000
2000
50
0
-50
-2000
-4000
-6000
-8000
-10000
Normal
Operation
-150
-250
-350
VCM = +18.1V
15.5
16
16.5
17
17.5
18
18.5
0
2
4
6
8
10
12
14
16
18
20
VCM (V)
VSUPPLY (V)
Figure 5. Offset Voltage vs Common-Mode Voltage (Upper
Stage)
Figure 6. Offset Voltage vs Power Supply
8
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
15
14
13
12
11
10
9
10000
1000
100
10
-IB
IB+
IB-
IOS
+IB
IB
-IOS
8
7
6
IOS
5
4
3
1
VCM = -18.1V
VCM = 16V
2
1
0
0
-20
-18
-12
-6
0
6
12
18
20
-75 -50 -25
0
25
50
75
100 125 150
VCM (V)
Temperature (°C)
Figure 7. IB and IOS vs Common-Mode Voltage
Figure 8. Input Bias Current vs Temperature
18
17
16
140
120
100
80
15
14.5
-14.5
-15
60
-40°C
+25°C
+85°C
+125°C
40
-16
-17
-18
+PSRR
-PSRR
CMRR
20
0
0
2
4
6
8
10
12
14
16
1
10
100
1k
10k
100k
1M
10M
Output Current (mA)
Frequency (Hz)
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
Figure 10. CMRR and PSRR vs Frequency (Referred-to
Input)
30
20
3
2
10
1
0
0
-10
-20
-30
-1
VS = 2.7V
VS = 4V
-2
-3
VS = 2.7V to 36V
VS = 4V to 36V
VS = 36V
-75 -50 -25
0
25
50
75
100 125 150
-75 -50 -25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
Figure 11. CMRR vs Temperature
Figure 12. PSRR vs Temperature
Copyright © 2015, Texas Instruments Incorporated
9
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
1000
100
10
1
Time (1s/div)
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 13. 0.1-Hz to 10-Hz Noise
Figure 14. Input Voltage Noise Spectral Density vs
Frequency
0.1
0.01
-80
0.01
0.001
-80
VOUT = 3VRMS
BW = 80kHz
BW = 80kHz
-100
-120
-140
-100
-120
-140
0.001
0.0001
0.00001
0.0001
0.00001
G = +1, RL = 10kW
G = -1, RL = 2kW
G = +1, RL = 10kW
G = -1, RL = 2kW
0.01
0.1
1
10 20
10
100
1k
Frequency (Hz)
10k 20k
Output Amplitude (VRMS
)
Figure 15. THD+N Ratio vs Frequency
Figure 16. THD+N vs Output Amplitude
0.65
0.6
0.6
0.55
0.5
0.55
0.5
0.45
0.4
0.45
0.4
0.35
0.3
Specified Supply-Voltage Range
0.35
0.25
-75 -50 -25
0
25
50
75
100 125 150
0
4
8
12
16
20
24
28
32
36
Temperature (°C)
Supply Voltage (V)
Figure 17. Quiescent Current vs Temperature
Figure 18. Quiescent Current vs Supply Voltage
10
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
180
135
90
180
135
90
25
20
15
10
5
Gain
Phase
0
45
45
-5
-10
-15
-20
G = 10
G = 1
0
0
G = -1
-45
-45
1
10
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 19. Open-Loop Gain and Phase vs Frequency
Figure 20. Closed-Loop Gain vs Frequency
3
1M
5 Typical Units Shown
VS = 2.7V
VS = 4V
100k
10k
1k
2.5
2
VS = 36V
1.5
1
100
10
0.5
0
1
1m
-75 -50 -25
0
25
50
75
100 125 150
1
10
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
Figure 21. Open-Loop Gain vs Temperature
Figure 22. Open-Loop Output Impedance vs Frequency
50
50
RL = 10kW
ROUT = 0W
45
40
35
30
25
20
15
10
5
45
ROUT = 25W
40
ROUT = 50W
35
30
25
20
G = +1
+18V
RF = 10kW
RI = 10kW
G = -1
ROUT = 0W
15
10
5
ROUT
+18V
OPA171
ROUT = 25W
ROUT
RL
CL
-18V
OPA171
CL
ROUT = 50W
-18V
0
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 23. Small-Signal Overshoot vs Capacitive Load (100-
mV Output Step)
Figure 24. Small-Signal Overshoot vs Capacitive Load (100-
mV Output Step)
Copyright © 2015, Texas Instruments Incorporated
11
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
+18V
VOUT
OPA171
Output
-18V
37VPP
Sine Wave
(±18.5V)
VIN
20kW
+18V
2kW
VOUT
OPA171
Output
VIN
-18V
G = -10
Time (5ms/div)
Time (100ms/div)
Figure 25. No Phase Reversal
Figure 26. Positive Overload Recovery
RL = 10kW
G = +1
+18V
OPA171
-18V
CL = 100pF
RL
CL
VIN
20kW
+18V
2kW
VOUT
OPA171
VIN
VOUT
-18V
G = -10
Time (5ms/div)
Time (1ms/div)
Figure 27. Negative Overload Recovery
Figure 28. Small-Signal Step Response (100 mV)
G = +1
RL = 10kW
CL = 100pF
CL = 100pF
RI = 2kW RF = 2kW
+18V
OPA171
CL
-18V
G = -1
Time (20ms/div)
Time (5ms/div)
Figure 29. Small-Signal Step Response (100 mV)
Figure 30. Large-Signal Step Response
12
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
10
G = -1
G = -1
8
RL = 10kW
CL = 100pF
6
4
12-Bit Settling
2
0
-2
-4
-6
-8
-10
(±1/2LSB = ±0.024%)
Time (4ms/div)
0
4
8
12
16
20
24
28
32
36
Time (ms)
Figure 31. Large-Signal Step Response
Figure 32. Large-Signal Settling Time (10-V Positive Step)
10
8
50
45
G = -1
ISC, Sink
6
40
35
30
25
20
15
10
5
4
12-Bit Settling
2
0
-2
-4
-6
-8
-10
ISC, Source
(±1/2LSB = ±0.024%)
0
0
4
8
12
16
20
24
28
32
36
-75 -50 -25
0
25
50
75
100 125 150
Time (ms)
Temperature (°C)
Figure 33. Large-Signal Settling Time (10-V Negative Step)
Figure 34. Short-Circuit Current vs Temperature
15
-60
-70
VS = ±15V
12.5
10
7.5
5
-80
Maximum output voltage without
slew-rate induced distortion.
-90
VS = ±5V
-100
-110
-120
2.5
0
VS = ±1.35V
10k
100k
Frequency (Hz)
1M
10M
10
100
1k
10k
100k
Frequency (Hz)
Figure 35. Maximum Output Voltage vs Frequency
Figure 36. Channel Separation vs Frequency
Copyright © 2015, Texas Instruments Incorporated
13
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
The OPA2171-EP operational amplifier provides high overall performance, making it ideal for many general-
purpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
7.2 Functional Block Diagram
+
PCH
FF Stage
œ
Ca
Cb
+
+IN
+
+
PCH
Input Stage
2nd Stage
OUT
Output
Stage
œ
œIN
œ
œ
+
NCH
Input Stage
œ
7.3 Feature Description
7.3.1 Operating Characteristics
The OPA2171-EP amplifier is specified for operation from 2.7 to 36 V (±1.35 to ±18 V). Many of the
specifications apply from –55°C to 125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Typical Characteristics.
7.3.2 Phase-Reversal Protection
The OPA2171-EP has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversal
when the input is driven beyond its linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The input of the OPA2171-EP prevents phase reversal with excessive
common-mode voltage. Instead, the output limits into the appropriate rail. Figure 37 shows this performance.
14
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
Feature Description (continued)
+18V
OPA171
-18V
Output
37VPP
Sine Wave
(±18.5V)
Output
Time (100ms/div)
Figure 37. No Phase Reversal
7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPA2171-EP extends 100 mV below the negative rail and within 2
V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. Table 2 summarizes the typical performance in this range.
Table 2. Typical Performance Range
PARAMETER
MIN
TYP
MAX
UNIT
V
Input Common-Mode Voltage
Offset voltage
(V+) – 2
(V+) + 0.1
7
12
mV
vs Temperature
Common-mode rejection
Open-loop gain
GBW
µV/°C
dB
65
60
dB
0.7
0.7
30
MHz
V/µs
nV/√Hz
Slew rate
Noise at ƒ = 1kHz
Copyright © 2015, Texas Instruments Incorporated
15
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Electrical Overstress
Designers often ask about the capability of an operational amplifier to withstand electrical overstress. These
questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin.
Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in Absolute Maximum Ratings. Figure 38 shows how a series input resistor may be added to the
driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its
value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10mA max
VOUT
OPA171
VIN
5kW
Figure 38. Input Current Protection
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that
some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is uncertainty about the ability of the supply to absorb this current, external Zener diodes may be added
to the supply pins. Select the Zener voltage such that the diode does not turn on during normal operation.
However, its Zener voltage should be low enough so that the Zener diode conducts if the supply pin begins to
rise above the safe operating supply voltage level.
16
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
8.2 Typical Application
Figure 39 shows a capacitive load drive solution using an isolation resistor. The OPA2171-EP device can be
used capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The circuit uses an
isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open loop gain of the system to
ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
CLOAD
+
VIN
-VS
œ
Figure 39. Unity-Gain Buffer with RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
•
•
•
Supply voltage: 30 V (±15 V)
Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
Figure 39 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 39. Not shown in Figure 39 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + R + R
× C
× s
o
ISO
LOAD
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade. Figure 40 depicts the concept. The 1/β curve for a unity-gain buffer is 0 dB.
120
AOL
100
1
fp
=
2 ì Œ ì
R
+ Ro ì C
(
)
ISO
LOAD
80
60
40
20
0
40 dB
1
fz
=
2 ì Œ ì RISO ì CLOAD
1 dec
1/ꢀ
20 dB
dec
ROC =
100M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 40. Unity-Gain Amplifier with RISO Compensation
Copyright © 2015, Texas Instruments Incorporated
17
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
Typical Application (continued)
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3
shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the OPA171, refer to the
Precision Design, Capacitive Load Drive Solution using an Isolation Resistor (TIPD128).
Table 3. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE MARGIN
OVERSHOOT
23.3%
AC GAIN PEAKING
2.35 dB
45°
60°
8.8%
0.28 dB
8.2.2.1 Capacitive Load and Stability
The dynamic characteristics of the OPA2171-EP have been optimized for commonly encountered operating
conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of
the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated
from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to
50 Ω) in series with the output. Figure 41 and Figure 42 illustrate graphs of small-signal overshoot versus
capacitive load for several values of ROUT. Also, refer to Applications Bulletin AB-028 (SBOA015), available for
download from www.ti.com for details of analysis techniques and application circuits.
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
RL = 10kW
ROUT = 0W
ROUT = 25W
ROUT = 50W
G = +1
+18V
OPA171
-18V
RF = 10kW
RI = 10kW
G = -1
ROUT = 0W
ROUT = 25W
ROUT = 50W
ROUT
+18V
ROUT
RL
CL
OPA171
CL
-18V
0
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 41. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 42. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
18
Copyright © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
8.2.3 Application Curve
The OPA2171-EP device meets the supply voltage requirements of 30 V. The OPA2171-EP device was tested
for various capacitive loads and RISO was adjusted to achieve an overshoot corresponding to Table 3. Figure 43
shows the test results.
10000
45è Phase Margin
60è Phase Margin
1000
100
10
1
0.01
0.1
1
10
100
1000
Capacitive Load (nF)
D001
Figure 43. RISO vs CLOAD
9 Power Supply Recommendations
The OPA2171-EP is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply
from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For detailed information on bypass capacitor placement, see the Layout section.
Copyright © 2015, Texas Instruments Incorporated
19
OPA2171-EP
ZHCSE93 –SEPTEMBER 2015
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, TI recommends good printed circuit board (PCB) layout
practices. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground, placed
as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
10.2 Layout Example
Place components close to
device and to each other to
reduce parasitic errors
VS+
Run the input traces as
far away from the supply
lines as possible
GND
OUT A
V+
GND
VIN
œIN A
OUT B
œIN B
+IN B
Use low-ESR, ceramic
bypass capacitor
+IN A
Vœ
VS ±
(or GND for single supply)
GND
Ground (GND) plane on
another layer
Only needed for dual-
supply operation
VOUT
Figure 44. Operational Amplifier Board Layout for Noninverting Configuration
20
版权 © 2015, Texas Instruments Incorporated
OPA2171-EP
www.ti.com.cn
ZHCSE93 –SEPTEMBER 2015
11 器件和文档支持
11.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏
版权 © 2015, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2171MDCUTEP
V62/15605-01XE
ACTIVE
ACTIVE
VSSOP
VSSOP
DCU
DCU
8
8
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
ZGAA
ZGAA
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DCU0008A
VSSOP - 0.9 mm max height
S
C
A
L
E
6
.
0
0
0
SMALL OUTLINE PACKAGE
3.2
3.0
TYP
C
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.5
8
1
2X
2.1
1.9
1.5
NOTE 3
4
5
0.25
0.17
8X
2.4
2.2
B
0.08
C A B
NOTE 3
SEE DETAIL A
0.9
0.6
0.12
GAGE PLANE
0.1
0.0
0.35
0.20
0 -6
(0.13) TYP
A
30
DETAIL A
TYPICAL
4225266/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.
www.ti.com
EXAMPLE BOARD LAYOUT
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
SEE SOLDER MASK
DETAILS
SYMM
8X (0.85)
(R0.05) TYP
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(3.1)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
OPENING
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225266/A 09/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
8X (0.85)
SYMM
(R0.05) TYP
8
1
8X (0.3)
SYMM
6X (0.5)
4
5
(3.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 25X
4225266/A 09/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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相关型号：
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