OPA2172IDR [TI]
双路、36V、10MHz、低功耗运算放大器 | D | 8 | -40 to 125;
| 型号： | OPA2172IDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、36V、10MHz、低功耗运算放大器 | D | 8 | -40 to 125 放大器 光电二极管 运算放大器 |
| 文件： | 总56页 (文件大小：3925K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA172, OPA2172, OPA4172
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
OPAx172 36V 单电源 10MHz 轨到轨输出运算放大器
1 特性
3 说明
1
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宽电源范围：
+4.5V 至 +36V，±2.25V 至 ±18V
低偏移电压：±0.2mV
OPA172、OPA2172 和 OPA4172 (OPAx172) 属于
36V、单电源、低噪声运算放大器系列，该系列放大器
能够在 +4.5V (±2.25V) 至 +36V
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低偏移漂移：±0.3µV/°C
增益带宽：10MHz
(±18V) 的电源范围内运行。这款最新补充的高压
CMOS 运算放大器与 OPAx171 和 OPAx170 搭配，
为用户提供了广泛的带宽、噪声和功率选择，可以满足
各种应用的 需要。OPAx172 采用微型封装并且提供低
偏移、漂移和静态电流。这些器件还提供宽带宽、快速
转换率和高输出电流驱动能力。单通道、双通道和四通
道版本均具有相同的技术规格，可最大程度地提高设计
灵活性。
低输入偏置电流 ：±8pA
低静态电流：每放大器 1.6mA
低噪声：7nV/√Hz
已过滤电磁干扰 (EMI) 和射频干扰 (RFI) 的输入
输入范围包括负电源
输入范围运行至正电源
轨到轨输出
与大多数只在一个电源电压下额定运行的运算放大器不
同，OPAx172 系列可在 +4.5 至 +36V 的电压范围内
额定运行。超过电源轨的输入信号不会导致相位反向。
输入可在负电源轨以下 100mV 以及正电源轨 2V 之内
正常运行。请注意这些器件可在正电源轨之上 100mV
的满轨到轨输入上运行，但是在正电源轨 2V 之内运行
时性能会受到影响。
高共模抑制：120dB
行业标准封装：
–
SOIC-8、VSSOP-8、SOIC-14、TSSOP-14
•
微型封装：单电源版本采用 SC70 和 SOT-23 封
装；
双电源版本采用 WSON-8 封装
2 应用
OPAx172 系列运算放大器额定运行温度范围为 -40°C
至 +125°C。
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电源模块内的跟踪放大器
商用电源
器件信息(1)
封装
传感器放大器
桥式放大器
温度测量
器件型号
封装尺寸（标称值）
2.00mm × 1.25mm
2.90mm × 1.60mm
4.90mm × 3.91mm
4.90mm × 3.91mm
3.00mm × 3.00mm
3.00mm × 3.00mm
8.65mm × 3.91mm
4.40mm × 5.00mm
SC70 (5)
OPA172
SOT-23 (5)
SOIC (8)
应力计放大器
精密积分器
测试设备
SOIC (8)
OPA2172
OPA4172
VSSOP (8)(2)
WSON (8)
SOIC (14)
TSSOP (14)
(1) 如需了解所有可用封装，请参见产品说明书末尾的封装选项附
录。
(2) VSSOP 封装与 MSOP 封装相同。
JFET 输入低噪声放大器
出色的总谐波失真 (THD) 性能
VCC
0.01
-80
G = +1 V/V, RL = 10 kꢀ
G = +1 V/V, RL = 2 kꢀ
G = +1 V/V, RL = 600 ꢀ
G = -1 V/V, RL = 10 kꢀ
G = -1 V/V, RL = 2 kꢀ
G = -1 V/V, RL = 600 ꢀ
VCC
VEE
R1
3.9 kΩ
R2
3.9 kΩ
VEE
V1
15
V2
15
V
V
OPA172
0.001
-100
-120
-140
VOUT
+
+
R3
LSK489
VCC
1.13 kΩ
0.0001
0.00001
Q1
Q2
VCC
R4
11.5
Ω
VOUT = 3.5 VRMS
BW = 80 kHz
R6
27.4 kΩ
Q3
MMBT4401
Q4
10
100
1k
10k
MMBT4401
Frequency (Hz)
C007
R5
300
Ω
VEE
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS618
OPA172, OPA2172, OPA4172
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 22
Applications and Implementation ...................... 25
9.1 Application Information............................................ 25
9.2 Typical Applications ................................................ 25
1
2
3
4
5
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison ............................................... 4
5.1 Device Comparison................................................... 4
5.2 Device Family Comparison ....................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ..................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information: OPA172 .................................. 8
7.5 Thermal Information: OPA2172 ................................ 8
7.6 Thermal Information: OPA4172 ................................ 8
7.7 Electrical Characteristics........................................... 9
7.8 Typical Characteristics: Table of Graphs................ 11
7.9 Typical Characteristics............................................ 12
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
9
10 Power-Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 30
12.1 器件支持................................................................ 30
12.2 文档支持................................................................ 30
12.3 相关链接................................................................ 30
12.4 社区资源................................................................ 30
12.5 商标....................................................................... 31
12.6 静电放电警告......................................................... 31
12.7 术语表 ................................................................... 31
13 机械、封装和可订购信息....................................... 31
6
7
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4 修订历史记录
Changes from Revision H (September 2015) to Revision I
Page
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Changed supply voltage values within Absolute Maximum Ratings table ............................................................................. 7
Changes from Revision G (June 2015) to Revision H
Page
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已添加 DRG 封装至 OPA2172 器件 ....................................................................................................................................... 1
已添加 WSON 至最后一个特性要点 ....................................................................................................................................... 1
已添加 OPA2172 WSON 行至器件信息表.............................................................................................................................. 1
Added WSON-8 to OPA2172 row of Device Comparison table ............................................................................................ 4
Added DRG pinout drawing ................................................................................................................................................... 6
Added DRG column to OPA2172 and OPA4172 Pin Functions table .................................................................................. 6
Added DRG column to OPA2172 Thermal Information table ................................................................................................ 8
Changes from Revision F (June 2015) to Revision G
Page
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Added input bias current (IB) values for DGK and PW packages. ......................................................................................... 9
Changes from Revision E (December 2014) to Revision F
Page
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已将器件状态从混合状态改为量产数据................................................................................................................................... 1
已将 OPA2172 DGK 和 OPA4172 PW 封装改为量产数据..................................................................................................... 1
已添加 OPA2172 VSSOP 和 OPA4172 TSSOP 行至器件信息表.......................................................................................... 1
Deleted footnote from Device Comparison table.................................................................................................................... 4
Deleted footnote from OPA2172 DGK and OPA4172 PW pin out drawings ........................................................................ 6
Added OPA2172 DGK thermal information ........................................................................................................................... 8
2
版权 © 2013–2018, Texas Instruments Incorporated
OPA172, OPA2172, OPA4172
www.ti.com.cn
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
Changes from Revision D (September 2014) to Revision E
Page
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已将 OPA2172 D 封装从产品预览改为量产数据 .................................................................................................................... 1
已更改器件信息表................................................................................................................................................................... 1
Changed Device Comparison table note (1) to show preview packages............................................................................... 4
Changed Handling Ratings table to ESD Ratings table ......................................................................................................... 7
Changes from Revision C (July 2014) to Revision D
Page
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已更改低噪声 特性 要点值，从 6nV/√Hz 改为 7..................................................................................................................... 1
已将 特性 要点中的 MSOP 改为 VSSOP ............................................................................................................................... 1
已添加封装和新的注释 2 至器件信息表 .................................................................................................................................. 1
Changed OPAx172 voltage noise density from 6 nV/√Hz to 7 in Device Family Comparison table ..................................... 4
Changed OPA4172 package from DGK to PW in Pin Functions table .................................................................................. 6
Added OPA2172 Thermal Information table........................................................................................................................... 8
Changed input voltage noise value in Electrical Characteristics from 1.2 µVPP to 2.5 µVPP .................................................. 9
Changed input voltage noise density value at 100 Hz in Electrical Characteristics from 8.6 nV/√Hz to 12 .......................... 9
Changed input voltage noise density value at 1 kHz in Electrical Characteristics from 6 nV/√Hz to 7.................................. 9
Changed voltage output swing values in the Electrical Characteristics ............................................................................... 10
Changed 图 13 .................................................................................................................................................................... 13
Changed 图 14 ..................................................................................................................................................................... 13
Added new note to Applications and Implementation section ............................................................................................. 25
Changes from Revision B (May 2014) to Revision C
Page
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已将 OPA4172 D 封装 (SOIC-14) 从产品预览改为量产数据.................................................................................................. 1
Added OPA4172-D Thermal information ............................................................................................................................... 8
Added Channel separation parameter to the Electrical Characteristics................................................................................. 9
Added Channel Separation vs Frequency plot .................................................................................................................... 17
Changes from Revision A (April 2014) to Revision B
Page
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已将 DCK (SC70) 封装从产品预览改为量产数据.................................................................................................................... 1
Changes from Original (December 2013) to Revision A
Page
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已更改文档格式以符合最新产品说明书标准；已添加处理额定值、建议运行条件以及器件和文档支持部分，并已移动
现有部分 ................................................................................................................................................................................. 1
Changed DCK package pin names from IN+ and IN– to +IN and –IN, respectively ............................................................. 5
Changed DBV package from product preview to production data ......................................................................................... 5
Changed 图 9 ....................................................................................................................................................................... 12
Added Functional Block Diagram section............................................................................................................................. 19
Added Capacitive Load Drive Solution Using an Isolation Resistor section ........................................................................ 25
Added Power-Supply Recommendations section ................................................................................................................ 28
Changed Layout Guidelines section..................................................................................................................................... 29
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Copyright © 2013–2018, Texas Instruments Incorporated
3
OPA172, OPA2172, OPA4172
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
www.ti.com.cn
5 Device Comparison
5.1 Device Comparison
DEVICE
PACKAGE
OPA172 (single)
OPA2172 (dual)
OPA4172 (quad)
SC70-5, SOT-23-5, SOIC-8
SOIC-8, VSSOP-8, WSON-8
SOIC-14, TSSOP-14
5.2 Device Family Comparison
QUIESCENT CURRENT
GAIN BANDWIDTH PRODUCT
(GBP)
VOLTAGE NOISE DENSITY
(en)
DEVICE
OPAx172
OPAx171
OPAx170
(IQ)
1600 µA
475 µA
110 µA
10 MHz
3.0 MHz
1.2 MHz
7 nV/√Hz
14 nV/√Hz
19 nV/√Hz
4
Copyright © 2013–2018, Texas Instruments Incorporated
OPA172, OPA2172, OPA4172
www.ti.com.cn
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
6 Pin Configuration and Functions
DCK Package: OPA172
SC70-5
D Package: OPA172
SOIC-8
Top View
Top View
+IN
V-
1
2
3
5
4
V+
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC(1)
V+
-IN
OUT
OUT
NC(1)
DBV Package: OPA172
SOT-23-5
(1) No internal connection.
Top View
V+
OUT
1
2
3
5
4
V-
-IN
+IN
Pin Functions: OPA172
PIN
OPA172
NAME
D (SOIC)
DBV (SOT)
DCK (SC70)
I/O
I
DESCRIPTION
+IN
–IN
NC
3
3
4
1
3
Noninverting input
Inverting input
No internal connection
Output
2
I
1, 5, 8
—
1
—
4
—
O
—
—
OUT
V+
6
7
4
5
5
Positive (highest) power supply
Negative (lowest) power supply
V–
2
2
Copyright © 2013–2018, Texas Instruments Incorporated
5
OPA172, OPA2172, OPA4172
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
www.ti.com.cn
D and DGK Packages: OPA2172
SOIC-8 and VSSOP-8
Top View
D and PW Packages: OPA4172
SO-14 and TSSOP-14
Top View
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
OUT A
1
2
3
4
5
6
7
14 OUT D
OUT B
-IN B
+IN B
-IN A
+IN A
V+
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
DRG Package: OPA2172
WSON-8
9
8
-IN C
OUT C
Top View
+IN A
V+
1
2
3
4
8
7
6
5
-IN A
A
B
OUT A
OUT B
-IN B
V-
+IN B
Pin Functions: OPA2172 and OPA4172
PIN
OPA2172
OPA4172
D (SOIC),
D (SOIC),
DGK
DRG
NAME
+IN A
(VSSOP)
(WSON)
PW (TSSOP)
I/O
I
DESCRIPTION
3
5
1
4
3
5
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input,,channel C
Inverting input, channel D
Output, channel A
+IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
I
—
—
2
—
—
8
10
12
2
I
I
I
6
5
6
I
—
—
1
—
—
7
9
I
13
1
I
O
O
O
O
—
—
7
6
7
Output, channel B
—
—
8
—
—
2
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
V–
4
3
11
6
Copyright © 2013–2018, Texas Instruments Incorporated
OPA172, OPA2172, OPA4172
www.ti.com.cn
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
40
UNIT
Supply voltage, [(V+) – (V-)]
Common-mode
V
(V–) – 0.5
(V+) + 0.5
±0.5
Signal input pins
Voltage(2)
Current
V
Differential(3)
Signal input pins
±10
mA
Output short circuit(4)
Operating temperature
Junction temperature, TJ
Storage temperature, Tstg
Continuous
–55
+150
+150
+150
°C
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transient conditions that exceed these voltage ratings must be current limited to 10 mA or less.
(3) Refer to the Electrical Overstress section for more information.
(4) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
Supply voltage (V+ – V–)
Specified temperature
4.5 (±2.25)
–40
36 (±18)
125
°C
Copyright © 2013–2018, Texas Instruments Incorporated
7
OPA172, OPA2172, OPA4172
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
www.ti.com.cn
7.4 Thermal Information: OPA172
OPA172
DBV (SOT-23)
5 PINS
227.9
THERMAL METRIC(1)
D (SOIC)
8 PINS
126.5
80.6
DCK (SC70)
5 PINS
285.2
60.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
115.7
67.1
65.9
78.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
31.0
10.7
0.8
ψJB
66.6
65.3
77.9
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package Thermal Metrics application
report.
7.5 Thermal Information: OPA2172
OPA2172
THERMAL METRIC(1)
D (SOIC)
8 PINS
116.1
69.8
DGK (VSSOP) DRG (WSON)
UNIT
8 PINS
158
8 PINS
63.2
63.5
36.5
1.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
48.6
78.7
3.9
56.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.5
ψJB
56.1
77.3
N/A
36.6
6.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package Thermal Metrics application
report.
7.6 Thermal Information: OPA4172
OPA4172
THERMAL METRIC(1)
D (SOIC)
14 PINS
82.7
PW (TSSOP)
14 PINS
111.1
40.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
42.3
37.3
54.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.9
3.8
ψJB
37
53.3
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package Thermal Metrics application
report.
8
Copyright © 2013–2018, Texas Instruments Incorporated
OPA172, OPA2172, OPA4172
www.ti.com.cn
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
7.7 Electrical Characteristics
At TA = +25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.2
±0.3
MAX
UNIT
OFFSET VOLTAGE
±1
±1.15
±1.5
±1.8
±3
VOS
Input offset voltage
Drift
mV
TA = –40°C to +125°C
TA = –40°C to +125°C
OPA172, OPA4172
dVOS/dT
PSRR
µV/°C
OPA2172
vs power supply
TA = –40°C to +125°C
At dc
±1
5
µV/V
µV/V
Channel separation, dc
INPUT BIAS CURRENT
±8
±15
±14
pA
nA
TA = –40°C to +125°C
TA = –40°C to +125°C
IB
Input bias current
OPA2172IDGK
OPA41721PW
±18
±2
±15
±1
pA
nA
IOS
Input offset current
OPA172, OPA4172
OPA2172
TA = –40°C to +125°C
±3
NOISE
En
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 100 Hz
2.5
12
7
µVPP
en
in
Input voltage noise density
Input current noise density
nV/√Hz
fA/√Hz
f = 1 kHz
f = 1 kHz
1.6
Copyright © 2013–2018, Texas Instruments Incorporated
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OPA172, OPA2172, OPA4172
ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
www.ti.com.cn
Electrical Characteristics (continued)
At TA = +25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE
VCM
Common-mode voltage range(1)
Common-mode rejection ratio
(V–) – 0.1 V
90
(V+) – 2 V
V
VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
104
120
CMRR
dB
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
110
INPUT IMPEDANCE
Differential
Common-mode
OPEN-LOOP GAIN
100 || 4
6 || 4
MΩ || pF
1013Ω || pF
OPA172, OPA4172
OPA2172
110
107
130
115
116
107
(V–) + 0.35 V < VO < (V+) – 0.35 V, RL
10 kΩ, TA = –40°C to +125°C
=
AOL
Open-loop voltage gain
dB
OPA172, OPA4172
OPA2172
(V–) + 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ, TA = –40°C to +125°C
FREQUENCY RESPONSE
GBP
SR
Gain bandwidth product
10
MHz
V/µs
Slew rate
G = +1
10
To 0.1%, VS = ±18 V, G = +1, 10-V step
2
3.2
tS
Settling time
µs
ns
To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V step
VIN × Gain > VS
Overload recovery time
200
THD+N
Total harmonic distortion + noise
VS = +36 V, G = +1, f = 1 kHz, VO = 3.5 VRMS
0.00005%
OUTPUT
RL = 10 kΩ
70
330
95
90
400
120
530
20
VS = +36 V
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
VS = +36 V,
TA = –40°C to +125°C
470
10
VO
Voltage output swing from rail
mV
VS = +4.5V
40
50
10
25
VS = +4.5 V,
TA = –40°C to +125°C
55
70
ISC
Short-circuit current
±75
mA
pF
Ω
CLOAD
ZO
Capacitive load drive
See Typical Characteristics
Open-loop output impedance
f = 1 MHz, IO = 0 A
60
POWER SUPPLY
VS
Specified voltage range
+4.5
+36
1.8
2
V
IO = 0 A
1.6
IQ
Quiescent current per amplifier
mA
IO = 0 A, TA = –40°C to +125°C
TEMPERATURE
Specified range
–40
+125
°C
(1) The input range can be extended beyond (V+) – 2 V up to (V+) + 0.1 V. For additional information, see the Typical Characteristics and
Application Information sections.
10
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7.8 Typical Characteristics: Table of Graphs
表 1. List of Typical Characteristics
DESCRIPTION
Offset Voltage Production Distribution
Offset Voltage Drift Distribution
FIGURE
图 1
图 2
Offset Voltage vs Temperature (VS = ±18 V)
Offset Voltage vs Common-Mode Voltage (VS = ±18 V)
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Offset Voltage vs Power Supply
图 3
图 4
图 5
图 6
IB vs Common-Mode Voltage
图 7
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred-to Input)
CMRR vs Temperature
图 8
图 9
图 10
图 11
PSRR vs Temperature
图 12
0.1-Hz to 10-Hz Noise
图 13
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
图 14
图 15
THD+N vs Output Amplitude
图 16
Quiescent Current vs Temperature
Quiescent Current vs Supply Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
图 17
图 18
图 19
图 20
Open-Loop Gain vs Temperature
图 21
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Positive Overload Recovery
图 22
图 23, 图 24
图 25, 图 26
图 27, 图 28
图 29, 图 30
图 31, 图 32
图 33, 图 34
图 35
Negative Overload Recovery
Small-Signal Step Response (10 mV)
Small-Signal Step Response (100 mV)
Large-Signal Step Response (1 V)
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
No Phase Reversal
图 36
图 37
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
图 38
图 39
图 40
Channel Separation vs Frequency
图 41
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7.9 Typical Characteristics
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
25
25
Distribution Taken From 5185 Amplifiers
Distribution Taken From 47 Amplifiers
Temperature = -40°C to 125°C
20
15
10
5
20
15
10
5
0
0
Offset Voltage Drift (µV/°C)
Offset Voltage (mV)
C013
C013
图 1. Offset Voltage Production Distribution
图 2. Offset Voltage Drift Production Distribution
250
200
150
100
50
225
150
75
5 Typical Units Shown
VS = ±18 V
5 Typical Units Shown
VS = ±18 V
VCM =16V
VCM = -18.1V
0
0
œ50
œ100
œ150
œ200
œ250
œ75
œ150
œ225
œ75 œ50 œ25
0
25
50
75
100 125 150
œ20
œ15
œ10
œ5
0
5
10
15
20
Temperature (°C)
C001
VCM (V)
C001
图 3. Offset Voltage vs Temperature
图 4. Offset Voltage vs Common-Mode Voltage
(VS = ±18 V)
(VS = ±18 V)
500
400
20
10
5 Typical Units Shown
VS = ±2.25V to ±18V
5 Typical Units Shown
VS = ±18 V
Vs = ±2.25V
300
0
200
100
-10
-20
-30
-40
-50
0
œ100
œ200
œ300
œ400
œ500
0.0
2.0
4.0
6.0 8.0 10.0 12.0 14.0 16.0 18.0
VSUPPLY (V)
14
15
16
17
18
VCM (V)
C001
C001
图 6. Offset Voltage vs Power Supply
图 5. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
12
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Typical Characteristics (接下页)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
12
10
8
8000
6000
4000
2000
0
IB+
IB -
Ios
IbP
6
IbN
4
2
0
œ2
œ4
Ios
TA = 25°C
œ2000
œ18.0 œ13.5 œ9.0 œ4.5
0.0
4.5
9.0
13.5 18.0
œ50
œ25
0
25
50
75
100
125
150
VCM (V)
Temperature (°C)
C001
C001
图 7. Input Bias Current vs Common-Mode Voltage
图 8. Input Bias Current vs Temperature
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
(V+) +1
(V+)
(V+) -1
(V+) -2
(V+) -3
(V+) -4
(V+) -5
(V-) +5
(V-) +4
(V-) +3
(V-) +2
(V-) +1
(V-)
25°C
œ40°C
125°C
85°C
85°C
125°C
+PSRR
-PSRR
CMRR
œ40°C
25°C
(V-) -1
0
10
20
30
40
50
60
70
80
90 100
1
10
100
1k
10k
100k
1M
C011
C012
Output Current (mA)
Frequency (Hz)
图 9. Output Voltage Swing vs Output Current (Maximum
图 10. CMRR and PSRR vs Frequency
Supply)
(Referred-To-Input)
30
10
8
20
VS = ±2.25V, -2.35V ≤ VCM ≤ 0.25V
6
10
4
2
0
0
VS = ±18 V, -18.1V ≤ VCM ≤ 16V
œ10
œ2
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C001
C001
图 11. CMRR vs Temperature
图 12. PSRR vs Temperature
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Typical Characteristics (接下页)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
100
10
1
Time (1 s/div)
1
10
100
1k
10k
100k
Frequency (Hz)
C002
C001
图 13. 0.1-Hz to 10-Hz Noise
图 14. Input Voltage Noise Spectral Density vs Frequency
0.01
0.001
-80
0.1
-60
G = +1 V/V, RL = 10 kꢀ
G = +1 V/V, RL = 2 kꢀ
G = +1 V/V, RL = 600 ꢀ
G = -1 V/V, RL = 10 kꢀ
G = -1 V/V, RL = 2 kꢀ
G = -1 V/V, RL = 600 ꢀ
G = +1 V/V, RL = 10 kꢀ
G = +1 V/V, RL = 2 kꢀ
G = +1 V/V, RL = 600 ꢀ
G = -1 V/V, RL = 10 kꢀ
G = -1 V/V, RL = 2 kꢀ
G = -1 V/V, RL = 600 ꢀ
0.01
-80
-100
-120
-140
0.001
-100
-120
-140
0.0001
0.00001
0.0001
VOUT = 3.5 VRMS
BW = 80 kHz
f = 1 kHz
BW = 80 kHz
0.00001
10
100
1k
10k
0.01
0.1
1
10
Frequency (Hz)
Output Amplitude (VRMS)
C007
C008
图 15. THD+N Ratio vs Frequency
图 16. THD+N vs Output Amplitude
2.0
1.8
1.6
1.4
1.2
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Vs = ±18V
Vs = ±2.25V
œ75 œ50 œ25
0
25
50
75
100 125 150
0
4
8
12
16
20
24
28
32
36
Temperature (°C)
Supply Voltage (V)
C001
C001
图 17. Quiescent Current vs Temperature
图 18. Quiescent Current vs Supply Voltage
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Typical Characteristics (接下页)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
140
120
100
80
180
135
90
25.0
20.0
15.0
10.0
5.0
CLOAD = 15 pF
Open-Loop Gain
Phase
60
0.0
40
œ5.0
œ10.0
œ15.0
œ20.0
20
45
G = +1
G = -10
G = -1
0
œ20
0
1
10
100
1k
10k
100k
1M
10M
1000
10k
100k
1M
10M
C003
Frequency (Hz)
Frequency (Hz)
C004
图 19. Open-Loop Gain and Phase vs Frequency
图 20. Closed-Loop Gain vs Frequency
2.0
1.5
1.0
0.5
0.0
1000
100
10
1
Vs = 4.5 V
Vs = 36 V
RL = 10kΩ
œ0.5
0
œ75 œ50 œ25
0
25
50
75
100 125 150
10
100
1k
10k
100k
1M
10M
100M
Temperature (°C)
Frequency (Hz)
C001
C016
图 21. Open-Loop Gain vs Temperature
图 22. Open-Loop Output Impedance vs Frequency
60
50
40
30
20
10
0
50
RI
=
1 kꢀ
RF
=
1 kꢀ
G = +1
G = -1
+
18 V
œ
ROUT
+
OPA172
40
30
20
10
0
VIN
= 100mV
+
CL
œ
œ 18 V
+
18
V
V
ROUT = 0 ꢀ
ROUT= 0 ꢀ
œ
ROUT
OPA172
+
+
RL
CL
R
= 25 ꢀ
RO = 25
RRO ==2255ꢀ
OUT
VIN = 100mV
OUT
œ
18
œ
RRO ==5500 ꢀ
RO = 50
ROUT= 50 ꢀ
OUT
0p
100p
200p
300p
400p
500p
0p
100p
200p
300p
400p
500p
Capacitive Load (F)
Capacitive Load (F)
C013
C013
图 23. Small-Signal Overshoot vs Capacitive Load
图 24. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
(100-mV Output Step)
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Typical Characteristics (接下页)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
RI = 1 kꢁ
RF = 10 kꢁ
+ 18 V
œ
+
OPA172
VOUT
VIN = 2V
+
VOUT
œ
œ 18 V
RI
=
1
kꢁ
RF = 10 kꢁ
+
18
V
VOUT
œ
+
OPA172
VOUT
VIN
= 2V
+
œ
œ
18
V
VIN
VIN
Time (1 ꢀs/div)
Time (1 ꢀs/div)
C009
C010
C006
C009
图 25. Positive Overload Recovery
图 26. Positive Overload Recovery (Zoomed In)
VIN
VIN
RI
=
1
kꢁ
RF = 10 kꢁ
+
18
V
œ
+
OPA172
VOUT
VIN
= 2V
+
œ
œ
18
V
VOUT
RI = 1 kꢁ
RF = 10 kꢁ
+ 18 V
VOUT
œ
+
OPA172
VOUT
VIN = 2V
+
œ
œ 18 V
Time (1 ꢀs/div)
Time (1 ꢀs/div)
C010
图 27. Negative Overload Recovery
图 28. Negative Overload Recovery (Zoomed In)
+ 18 V
RL = 1kΩ
CL = 10pF
CL = 10pF
œ
OPA172
+
+
CL
VIN = 10mV
œ 18 V
œ
RI
=
1
kꢀ
RF
=
+
1 kꢀ
18
V
œ
+
OPA172
VIN
= 10mV
+
RL
CL
œ
œ
18
V
Time (200 ns/div)
Time (200 ns/div)
C014
图 29. Small-Signal Step Response (10 mV, G = –1)
图 30. Small-Signal Step Response (10 mV, G = +1)
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Typical Characteristics (接下页)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
+ 18 V
CL = 10pF
RL = 1kΩ
CL = 10pF
œ
OPA172
+
+
CL
VIN = 100mV
œ 18 V
œ
RI
=
1
kꢀ
RF
=
+
1 kꢀ
18
V
œ
+
OPA172
VIN
= 100mV
+
RL
CL
œ
œ
18
V
Time (200 ns/div)
Time (200 ns/div)
C006
C014
图 31. Small-Signal Step Response (100 mV, G = –1)
图 32. Small-Signal Step Response (100 mV, G = +1)
+ 18 V
RL = 1kΩ
CL = 10 pF
CL = 10pF
œ
OPA172
+
+
CL
VIN = 10V
œ 18 V
œ
RI
=
1
kꢀ
RF
=
+
1 kꢀ
18
V
œ
+
OPA172
VIN
= 10V
+
RL
CL
œ
œ
18
V
Time (500 ns/div)
Time (500 ns/div)
C005
C014
图 33. Large-Signal Step Response (10 V, G = –1)
图 34. Large-Signal Step Response (10 V, G = +1)
20
20
G = +1
G = +1
CL = 10 pF
CL = 10 pF
15
10
5
15
10
5
0
0
-5
-5
0.1% Settling = ±10 mV
0.1% Settling = ±10 mV
-10
-15
-20
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (ꢀs)
Time (ꢀs)
C034
C034
图 35. Large-Signal Settling Time (10-V Positive Step)
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图 36. Large-Signal Settling Time (10-V Negative Step)
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Typical Characteristics (接下页)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
100
+ 18 V
œ
OPA172
VOUT
VOUT
+
+
75
50
25
0
œ 18 V
37 VPP
ISC, Sink ±18V
œ
Sine Wave
(±18.5V)
ISC, Source ±18V
VIN
Time (200 ꢀs/div)
œ75 œ50 œ25
0
25
50
75
100 125 150
C011
Temperature (°C)
C001
图 37. No Phase Reversal
图 38. Short-Circuit Current vs Temperature
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
30
25
20
15
10
5
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
VS = ±15 V
Maximum output voltage without
slew-rate induced distortion.
VS = ±5 V
VS = ±2.25 V
0
10k
100k
1M
Frequency (Hz)
10M
10M
100M
Frequency (Hz)
1G
10G
C017
C033
图 39. Maximum Output Voltage vs Frequency
图 40. EMIRR vs Frequency
0
œ20
œ40
œ60
œ80
œ100
œ120
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
C041
图 41. Channel Separation vs Frequency
18
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8 Detailed Description
8.1 Overview
The OPAx172 family of operational amplifiers provide high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1.5 µV/°C (max) provides excellent stability over
the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
The Functional Block Diagram section shows the simplified diagram of the OPA172 design. The design topology
is a highly-optimized, three-stage amplifier with an active-feedforward gain stage.
8.2 Functional Block Diagram
OPA172
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
OUT
Output
Stage
-IN
NCH
Input Stage
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8.3 Feature Description
8.3.1 EMI Rejection
The OPAx172 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx172 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. 图 42
shows the results of this testing on the OPAx172. 表 2 shows the EMIRR IN+ values for the OPAx172 at
particular frequencies commonly encountered in real-world applications. Applications listed in 表 2 can be
centered on or operated near the particular frequency shown. Detailed information can also be found in
Application Report SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download from
www.ti.com.
160.0
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
Frequency (Hz)
1G
10G
C017
图 42. EMIRR Testing
表 2. OPAx172 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh frequency (UHF)
applications
400 MHz
47.6 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5.0 GHz
58.5 dB
68 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
69.2 dB
82.9 dB
114 dB
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
20
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8.3.2 Phase-Reversal Protection
The OPAx172 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPAx172 prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in 图 43.
+ 18 V
œ
OPA172
VOUT
VOUT
+
+
œ 18 V
37 VPP
œ
Sine Wave
(±18.5V)
VIN
Time (200 ꢀs/div)
C011
图 43. No Phase Reversal
8.3.3 Capacitive Load and Stability
The dynamic characteristics of the OPAx172 are optimized for commonly-used operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
may lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT = 50 Ω) in series with the
output. 图 44 and 图 45 show graphs of small-signal overshoot versus capacitive load for several values of ROUT
.
Refer to Application Bulletin SBOA015 (AB-028), Feedback Plots Define Op Amp AC Performance, available for
download from www.ti.com, for details of analysis techniques and application circuits.
60
50
40
30
20
10
0
50
40
30
20
10
0
RI
=
1 kꢀ
RF
=
+
1 kꢀ
G = +1
G = -1
18 V
œ
ROUT
+
OPA172
VIN
= 100mV
+
CL
œ
œ 18 V
+
18
V
V
ROUT = 0 ꢀ
ROUT= 0 ꢀ
œ
ROUT
OPA172
+
+
RL
CL
R
= 25 ꢀ
RO = 25
RRO ==2255ꢀ
OUT
VIN = 100mV
OUT
œ
18
œ
RRO ==5500 ꢀ
RO = 50
ROUT= 50 ꢀ
OUT
0p
100p
200p
300p
400p
500p
0p
100p
200p
300p
400p
500p
Capacitive Load (F)
Capacitive Load (F)
C013
C013
图 44. Small-Signal Overshoot vs Capacitive Load (100-mV
图 45. Small-Signal Overshoot vs Capacitive Load (100-mV
Output Step)
Output Step)
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8.4 Device Functional Modes
8.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx172 series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in 表 3.
表 3. Typical Performance Range (VS = ±18 V)
PARAMETER
Input Common-Mode Voltage
MIN
TYP
MAX
UNIT
V
(V+) – 2
(V+) + 0.1
Offset voltage
5
10
70
60
4
mV
Offset voltage vs temperature (TA = –40°C to +125°C)
Common-mode rejection
Open-loop gain
µV/°C
dB
dB
Gain bandwidth product (GBP)
Slew rate
MHz
V/µs
nV/√Hz
4
Noise at f = 1 kHz
22
8.4.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage terminals or even the
output terminal. Each of these different terminal functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the terminal. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect
them from accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. 图
46 illustrates the ESD circuits contained in the OPAx172 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output terminals and
routed back to the internal power-supply lines, where the diodes meet at an absorption device internal to the
operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
22
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ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
TVS
R
F
+V
S
R
1
2.5 kΩ
INœ
2.5 kΩ
R
S
IN+
+
Power-Supply
ESD Cell
I
R
L
D
+
œ
V
IN
œV
S
TVS
图 46. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device terminals, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx172
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in 图 46), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given terminal. If
this condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current.
Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
图 46 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input-signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier will not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external zener diodes to the
supply terminals; see 图 46. Select the zener voltage so that the diode does not turn on during normal operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply terminal begins to
rise above the safe-operating, supply-voltage level.
The OPAx172 input terminals are protected from excessive differential voltage with back-to-back diodes; see 图
46. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits,
fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond
rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the
input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor
can be used to limit the input signal current. This input series resistor degrades the low-noise performance of the
OPAx172. 图 46 illustrates an example configuration that implements a current-limiting feedback resistor.
8.4.3 Overload Recovery
Overload recovery is defined as the time it takes for the op amp output to recover from the saturated state to the
linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices need time to return back to the normal state. After the
charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx172 is approximately 200 ns.
24
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9 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx172 family of amplifiers is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics.
9.2 Typical Applications
The following application examples highlight only a few of the circuits where the OPAx172 can be used.
9.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
The OPA172 can be used capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes.
The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open-loop gain
of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
CLOAD
+
VIN
-VS
œ
图 47. Unity-Gain Buffer with RISO Stability Compensation
9.2.1.1 Design Requirements
The design requirements are:
•
•
•
Supply voltage: 30 V (±15 V)
Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
Phase margin: 45° and 60°
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Typical Applications (接下页)
9.2.1.2 Detailed Design Procedure
图 47 depicts a unity-gain buffer driving a capacitive load. 公式 1 shows the transfer function for the circuit in 图
47. Not depicted in 图 47 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + R + R
× C
× s
o
ISO
LOAD
(1)
The transfer function in 公式 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO
)
and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is obtained by
selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1 / β is 20 dB per
decade. 图 48 shows the concept. Note that the 1 / β curve for a unity-gain buffer is 0 dB.
120
AOL
100
1
fp
=
2 ì Œ ì
R
+ Ro ì C
(
)
ISO
LOAD
80
60
40
20
0
40 dB
1
fz
=
2 ì Œ ì RISO ì CLOAD
1 dec
1/ꢀ
20 dB
dec
ROC =
100M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
图 48. Unity-Gain Amplifier with RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. 表 4
shows the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the OPA172, refer to the
precision design, Capacitive Load Drive Solution using an Isolation Resistor (TIPD128).
表 4. Phase Margin versus Overshoot and AC Gain Peaking
PHASE MARGIN
OVERSHOOT
23.3%
AC GAIN PEAKING
2.35 dB
45°
60°
8.8%
0.28 dB
26
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9.2.1.3 Application Curve
The OPA172 meets the supply voltage requirements of 30 V. The OPA172 is tested for various capacitive loads
and RISO is adjusted to get an overshoot corresponding to 表 4. The results of the these tests are summarized in
图 49.
1000
60°Phase Margin
45°Phase Margin
100
10
1
0.01
0.1
1
10
CLOAD (nF)
100
1000
C041
图 49. RISO vs CLOAD
9.2.2 Bidirectional Current Source
The improved Howland current-pump topology shown in 图 50 provides excellent performance because of the
extremely tight tolerances of the on-chip resistors of the INA132. By buffering the output using an OPA172, the
output current the circuit is able to deliver is greatly extended.
The circuit dc transfer function is shown in 公式 2:
IOUT = VIN / R1
(2)
The OPA172 can also be used as the feedback amplifier because the low bias current minimizes error voltages
produced across R1. However, for improved performance, select a FET-input device with extremely low offset,
such as the OPA192, OPA140, or OPA188 as the feedback amplifier.
INA132
40 kΩ
40 kΩ
SENSE
OUTPUT
REF
œIN
VCC
VIN
OPA172
+
+
+
40 kΩ
40 kΩ
+IN
VEE
VCC
R1
OPA172
+
+
IOUT
VEE
图 50. Bidirectional Current Source
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9.2.3 JFET-Input Low-Noise Amplifier
图 51 shows a low-noise composite amplifier built by adding a low noise JFET pair (Q1 and Q2) as an input
preamplifier for the OPA172. Transistors Q3 and Q4 form a 2-mA current sink that biases each JFET with 1 mA
of drain current. Using 3.9-kΩ drain resistors produces a gain of approximately 10 in the input amplifier, making
the extremely-low, broadband-noise spectral density of the JFET pair, Q1 and Q2, the dominant noise source of
the amplifier. The output impedance of the input differential amplifier is large enough that a FET-input amplifier
such as the OPA172 provides superior noise performance over bipolar-input amplifiers.
The gain of the composite amplifier is given by 公式 3:
AV = (1 + R3 / R4)
(3)
The resistances shown are standard 1% resistor values that produce a gain of approximately 100 (99.26) with
68° of phase margin. Gains less than 10 may require additional compensation methods to provide stability.
Select low resistor values to minimize the resistor thermal noise contribution to the total output noise.
VCC
VCC
VEE
R1
3.9 kΩ
R2
3.9 kΩ
VEE
V1
V2
15 V
15 V
OPA172
VOUT
+
+
R3
1.13 kΩ
LSK489
VCC
Q1
Q2
VCC
R4
11.5 Ω
R6
Q3
R5
27.4 kΩ
MMBT4401
Q4
MMBT4401
300 Ω
VEE
图 51. JFET-Input Low-Noise Amplifier
10 Power-Supply Recommendations
The OPA172 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply terminals to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
28
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ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information refer to SLOA089, Circuit Board Layout Techniques.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular as opposed
to in parallel with the noisy trace is preferable.
•
•
•
Place the external components as close to the device as possible. As shown in 图 52, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
图 52. Operational Amplifier Board Layout for Noninverting Configuration
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12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
12.2 文档支持
12.2.1 相关文档
SBOA015 (AB-028) — 《反馈曲线图定义运算放大器交流性能》。
SLOA089 — 《电路板布局布线技巧》。
SLOD006 — 《适用于所有人的运算放大器》。
SBOA128 — 《运算放大器的电磁干扰 (EMI) 抑制比》。
TIPD128 — 《使用隔离电阻器实现的电容负载驱动解决方案》。
12.3 相关链接
表 5 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 5. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
样片与购买
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
OPA172
OPA2172
OPA4172
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
30
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ZHCSBX8I –DECEMBER 2013–REVISED MAY 2018
12.5 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
版权 © 2013–2018, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA172ID
OPA172IDBVR
OPA172IDBVT
OPA172IDCKR
OPA172IDCKT
OPA172IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-23
SOT-23
SC70
D
DBV
DBV
DCK
DCK
D
8
5
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA172
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
OUWQ
OUWQ
SIU
5
5
NIPDAU
SC70
5
NIPDAU
SIU
SOIC
8
NIPDAU
OPA172
O2172A
OVJQ
OPA2172ID
SOIC
D
8
75
80
RoHS & Green
RoHS & Green
NIPDAU
OPA2172IDGK
OPA2172IDGKR
OPA2172IDR
OPA2172IDRGR
OPA2172IDRGT
OPA4172ID
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
NIPDAUAG
NIPDAUAG | SN
NIPDAU
8
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
OVJQ
8
O2172A
OP2172
OP2172
OPA4172
OPA4172
OPA4172
OPA4172
SON
DRG
DRG
D
8
NIPDAU
SON
8
250
50
RoHS & Green
RoHS & Green
NIPDAU
SOIC
14
14
14
14
NIPDAU
OPA4172IDR
OPA4172IPW
OPA4172IPWR
SOIC
D
2500 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
NIPDAU
TSSOP
TSSOP
PW
PW
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2023
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2172, OPA4172 :
Automotive : OPA2172-Q1, OPA4172-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA172IDBVR
OPA172IDBVT
OPA172IDCKR
OPA172IDCKT
OPA172IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
D
5
5
3000
250
180.0
180.0
178.0
178.0
330.0
330.0
330.0
330.0
330.0
180.0
330.0
330.0
8.4
8.4
3.23
3.23
2.4
2.4
6.4
5.3
5.3
6.4
3.3
3.3
6.5
6.9
3.17
3.17
2.5
2.5
5.2
3.4
3.4
5.2
3.3
3.3
9.0
5.6
1.37
1.37
1.2
1.2
2.1
1.4
1.4
2.1
1.1
1.1
2.1
1.6
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q1
Q1
Q1
Q1
Q2
Q2
Q1
Q1
5
3000
250
9.0
8.0
SC70
5
9.0
8.0
SOIC
8
2500
2500
2500
2500
3000
250
12.4
12.4
12.4
12.4
12.4
12.4
16.4
12.4
12.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
OPA2172IDGKR
OPA2172IDGKR
OPA2172IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
OPA2172IDRGR
OPA2172IDRGT
OPA4172IDR
SON
DRG
DRG
D
8
SON
8
SOIC
14
14
2500
2000
OPA4172IPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA172IDBVR
OPA172IDBVT
OPA172IDCKR
OPA172IDCKT
OPA172IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
D
5
5
3000
250
223.0
223.0
180.0
180.0
356.0
366.0
366.0
356.0
346.0
210.0
356.0
356.0
270.0
270.0
180.0
180.0
356.0
364.0
364.0
356.0
346.0
185.0
356.0
356.0
35.0
35.0
18.0
18.0
35.0
50.0
50.0
35.0
33.0
35.0
35.0
35.0
5
3000
250
SC70
5
SOIC
8
2500
2500
2500
2500
3000
250
OPA2172IDGKR
OPA2172IDGKR
OPA2172IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
OPA2172IDRGR
OPA2172IDRGT
OPA4172IDR
SON
DRG
DRG
D
8
SON
8
SOIC
14
14
2500
2000
OPA4172IPWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA172ID
OPA2172ID
D
D
SOIC
SOIC
8
8
75
75
80
50
90
506.6
506.6
330
8
8
3940
3940
500
4.32
4.32
2.88
4.32
3.5
OPA2172IDGK
OPA4172ID
DGK
D
VSSOP
SOIC
8
6.55
8
14
14
506.6
530
3940
3600
OPA4172IPW
PW
TSSOP
10.2
Pack Materials-Page 3
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRG0008A
WSON - 0.8 mm max height
SCALE 5.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
EXPOSED
THERMAL PAD
1.2 0.1
4
1
5
8
2X
1.5
2 0.1
6X 0.5
0.3
8X
0.2
0.1
0.08
0.6
0.4
PIN 1 ID
8X
C A B
C
4218885/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.2)
SYMM
8X (0.7)
1
8
8X (0.25)
SYMM
(2)
(0.75)
5
6X (0.5)
4
(R0.05) TYP
(
0.2) VIA
TYP
(0.35)
(2.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218885/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.7)
8
8X (0.25)
1
SYMM
(1.79)
6X (0.5)
4
5
(R0.05) TYP
(1.13)
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218885/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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