OPA2313-Q1 [TI]
汽车级、双路、5.5V、1MHz、低静态电流 (50μA)、RRIO 运算放大器;
| 型号： | OPA2313-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、双路、5.5V、1MHz、低静态电流 (50μA)、RRIO 运算放大器 放大器 运算放大器 |
| 文件： | 总33页 (文件大小：2717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
适用于成本敏感型系统的 OPA2313-Q1 低功耗、轨至轨输入/输出、
500µV 典型失调电压、1MHz 运算放大器
1 特性
3 说明
1
•
符合面向汽车应用的 AEC-Q100 标准
OPA2313-Q1 双通道运算放大器兼具低功耗和高性能
优势。因此，可将其用于广泛的 应用，例如信息娱乐
系统、发动机控制单元、汽车照明等。OPA2313-Q1
具有 轨至轨输入和输出 (RRIO) 摆幅、低静态电流
（典型值：50µA）、高带宽 (1MHz) 以及超低噪声
（1kHz 时为 25nV/√Hz）等特性，因此特别适合需要
在成本和性能之间取得良好平衡的各种 应用 。此外，
由于具有低输入偏置电流，该器件非常适合用于 源阻
抗高达兆欧级 的应用。
–
器件温度等级 1：
–40°C 至 +125°C TA
•
•
•
•
•
•
•
•
•
•
面向成本敏感型系统的精密放大器
低 IQ：50µA/ch
宽电源电压：1.8V 至 5.5V
低噪声：1kHz 下为 25nV/√Hz
增益带宽：1MHz
轨到轨输入/输出
低输入偏置电流：0.2pA
低失调电压：0.5mV
OPA2313-Q1 采用稳健耐用的设计，方便电路设计人
员使用。该器件在容性负载高达 150pF 的条件下具有
单位增益稳定性，集成了 RFI/EMI 抑制滤波器，在过
驱条件下无相位反转，并具有高静电放电 (ESD) 保护
(4kV HBM)。
单位增益稳定
内部射频干扰 (RFI)/电磁干扰 (EMI) 滤波器
2 应用
此器件经过优化，适合在低至 1.8V (±0.9V) 和高达
5.5V (±2.75V) 的电压下工作，且额定的扩展工作温度
范围为 –40°C 至 +125°C。
•
•
•
•
•
•
•
•
信息娱乐
引擎控制单元
汽车照明
低侧检测
器件信息(1)
电池管理系统
无源安全性
电容式检测
燃油泵
器件型号
封装
SOIC (8)
VSSOP (8)
封装尺寸（标称值）
4.90mm × 3.91mm
3.00mm × 3.00mm
OPA2313-Q1
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
EMIRR IN+ 与频率间的关系
120
100
80
60
40
20
0
10
100
1000
10000
Frequency (MHz)
C033
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS823
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
8.3 System Examples ................................................... 20
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: 5.5 V ................................ 5
6.6 Electrical Characteristics: 1.8 V ................................ 7
6.7 Typical Characteristics: Tables of Graphs ................ 9
6.8 Typical Characteristics............................................ 10
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 23
11.1 文档支持................................................................ 23
11.2 接收文档更新通知 ................................................. 23
11.3 社区资源................................................................ 23
11.4 商标....................................................................... 23
11.5 静电放电警告......................................................... 23
11.6 术语表 ................................................................... 23
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
日期
修订版本
说明
2018 年 12 月
*
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
5 Pin Configuration and Functions
OPA2313-Q1 D, DGK Packages
8-Pin SOIC, VSSOP
Top View
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
Pin Functions: OPA2313-Q1
PIN
I/O
DESCRIPTION
NAME
IN1–
NO.
2
I
I
Inverting input, channel 1
IN1+
IN2–
IN2+
OUT1
OUT2
V–
3
Noninverting input, channel 1
Inverting input, channel 2
6
I
5
I
Noninverting input, channel 2
Output, channel 1
1
O
O
—
—
7
Output, channel 2
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
8
Copyright © 2018, Texas Instruments Incorporated
3
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
MAX
UNIT
V
Supply voltage (V+) – (V–)
Signal input terminals(2)
Signal input terminals(2)
Output short circuit(3)
7
(V+) + 0.5
10
Voltage
(V–) – (0.5)
–10
mA
Current
Continuous
Operating, TA
–40
–65
150
150
150
Temperature
Junction, TJ
Storage, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
HBM ESD Classification Level 3A
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
CDM ESD Classification Level C6
±4000
V(ESD)
Electrostatic discharge
V
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
VS
TA
Supply voltage (V+) – (V–)
Specified temperature
1.8
V
–40
125
°C
6.4 Thermal Information
OPA2313-Q1
THERMAL METRIC(1)
D (SOIC)
8 Pins
138.4
89.5
DGK (VSSOP)
8 Pins
191.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
61.9
78.6
111.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
29.9
5.1
ψJB
78.1
110.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
6.5 Electrical Characteristics: 5.5 V(1)
For VS= (V+) – (V–) = 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, (unless otherwise
noted)(1)
PARAMETER
OFFSET VOLTAGE
VOS Input offset voltage
dVOS/dT Input offset voltage vs temperature
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
2
2.5
mV
µV/°C
dB
TA = –40°C to 125°C
TA = –40°C to 125°C
PSRR
Power-supply rejection ratio
Channel separation, dc
74
90
10
At dc
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
No phase reversal, rail-to-rail input
(V–) – 0.2
(V+) + 0.2
V
(V–) – 0.2 V < VCM < (V+) – 1.3 V TA = –40°C to 125°C
70
64
85
80
CMRR
Common-mode rejection ratio
dB
VCM = –0.2 V to 5.7 V
TA = –40°C to 125°C
INPUT BIAS CURRENT
±0.2
±0.2
±10
±50
IB
Input bias current
Input offset current
TA = –40°C to 85°C(2)
TA = –40°C to 125°C(2)
pA
pA
±600
±10
IOS
TA = –40°C to 85°C(2)
TA = –40°C to 125°C(2)
±50
±600
NOISE
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
f = 0.1 Hz to 10 Hz
f = 10 kHz
6
22
25
5
µVPP
nV/√Hz
fA/√Hz
en
in
f = 1 kHz
f = 1 kHz
INPUT CAPACITANCE
Differential
CIN
1
5
pF
Common-mode
OPEN-LOOP GAIN
0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ
0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ
90
100
104
104
110
116
65
AOL
Open-loop voltage gain
dB
°
0.1 V < VO < (V+) – 0.1 V
VS = 5 V, G = +1
TA = –40°C to 125°C
Phase margin
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
VS = 5 V, CL = 10 pF
1
MHz
V/µs
Slew rate
VS = 5 V, G = +1
0.5
To 0.1%, VS = 5 V, 2-V step, G = +1
To 0.01%, VS = 5 V, 2-V step, G = +1
VS = 5 V, VIN × Gain > VS
5
tS
Settling time
6
3
µs
Overload recovery time
THD+N
Total harmonic distortion + noise(3)
VS = 5 V, VO = 1 VRMS, G = +1, f = 1 kHz
0.0045%
OUTPUT
RL = 100 kΩ(2)
5
20
30
RL = 100 kΩ(2)
RL = 2 kΩ(2)
RL = 2 kΩ(2)
TA = –40°C to 125°C
VO
Voltage output swing from supply rails
mV
75
100
125
TA = –40°C to 125°C
TA = –40°C to 125°C
±15
±12
ISC
RO
Short-circuit current
mA
Open-loop output impedance
2300
Ω
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25°C, unless otherwise noted. Over-
temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization; not production tested.
(3) Third-order filter; bandwidth = 80 kHz at –3 dB.
Copyright © 2018, Texas Instruments Incorporated
5
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
Electrical Characteristics: 5.5 V(1) (continued)
For VS= (V+) – (V–) = 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, (unless otherwise
noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
Power-on time
1.8 (±0.9)
5.5 (±2.75)
V
VS = 5 V, IO = 0 mA
VS = 5 V, IO = 0 mA
50
10
60
85
µA
µs
TA = –40°C to 125°C
VS = 0 V to 5 V, to 90% IQ level
6
Copyright © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
6.6 Electrical Characteristics: 1.8 V(1)
For VS= (V+) – (V–) = 1.8 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS+ – 1.3 V, and VOUT = VS / 2, (unless
otherwise noted)(1)
PARAMETER
OFFSET VOLTAGE
VOS Input offset voltage
dVOS/dT Input offset voltage vs temperature
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
2
2.5
mV
µV/°C
dB
TA = –40°C to 125°C
TA = –40°C to 125°C
PSRR
Power-supply rejection ratio
Channel separation, dc
74
90
10
At dc
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
No phase reversal, rail-to-rail input
(V–) – 0.2
(V+) + 0.2
V
(V–) – 0.2 V < VCM < (V+) – 1.3 V TA = –40°C to 125°C
VS= 1.8 V, VCM = –0.2 V to 1.8 V
70
58
58
85
73
70
CMRR
Common-mode rejection ratio
dB
VCM = –0.2 V to 1.6 V
TA = –40°C to 125°C
INPUT BIAS CURRENT
±0.2
±0.2
±10
±50
IB
Input bias current
Input offset current
TA = –40°C to 85°C(2)
TA = –40°C to 125°C(2)
pA
pA
±600
±10
IOS
TA = –40°C to 85°C(2)
TA = –40°C to 125°C(2)
±50
±600
NOISE
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
f = 0.1 Hz to 10 Hz
f = 10 kHz
6
22
25
5
µVPP
nV/√Hz
fA/√Hz
en
in
f = 1 kHz
f = 1 kHz
INPUT CAPACITANCE
Differential
CIN
1
5
pF
dB
Common-mode
OPEN-LOOP GAIN
0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ
100
90
110
110
AOL
Open-loop voltage gain
0.1 V < VO < (V+) – 0.1 V
TA = –40°C to 125°C
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
CL = 10 pF
0.9
MHz
V/µs
Slew rate
G = +1
0.45
To 0.1%, VS = 5 V, 2-V step, G = +1
To 0.01%, VS = 5 V, 2-V step, G = +1
VS = 5 V, VIN × Gain > VS
VS = 5 V, VO = 1 VRMS, G = +1, f = 1kHz
5
tS
Settling time
6
3
µs
Overload recovery time
Total harmonic distortion + noise(3)
THD+N
0.0045%
OUTPUT
RL = 100 kΩ(2)
5
15
30
RL = 100 kΩ(2)
RL = 2 kΩ(2)
RL = 2 kΩ(2)
TA = –40°C to 125°C
VO
Voltage output swing from supply rails
mV
25
50
TA = –40°C to 125°C
125
ISC
RO
Short-circuit current
±6
mA
Open-loop output impedance
2300
Ω
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25°C, unless otherwise noted. Over-
temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization; not production tested.
(3) Third-order filter; bandwidth = 80 kHz at –3 dB.
Copyright © 2018, Texas Instruments Incorporated
7
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
Electrical Characteristics: 1.8 V(1) (continued)
For VS= (V+) – (V–) = 1.8 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS+ – 1.3 V, and VOUT = VS / 2, (unless
otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
Power-on time
1.8 (±0.9)
5.5 (±2.75)
60
V
VS = 5 V, IO = 0 mA
VS = 0 V to 5 V, to 90% IQ level
50
10
µA
µs
8
版权 © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
6.7 Typical Characteristics: Tables of Graphs
表 1. Characteristic Performance Measurements
TITLE
FIGURE
图 1
Open-Loop Gain and Phase vs Frequency
Open-Loop Gain vs Temperature
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Offset Voltage Production Distribution
Offset Voltage Drift Distribution
图 2
图 3
图 4
图 5
图 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
Offset Voltage vs Temperature
图 7
图 8
CMRR and PSRR vs Frequency (RTI)
图 9
CMRR and PSRR vs Temperature
图 10
图 11
图 12
图 13
图 14
图 15
图 16
图 17
图 18
图 19
图 20
图 21
图 22
图 23
图 24
图 25
图 26
图 27
图 28
图 29
图 30
图 31
图 32
图 33
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V)
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Input Voltage Noise vs Common-Mode Voltage (5.5 V)
Input Bias and Offset Current vs Temperature
Open-Loop Output Impedance vs Frequency
Maximum Output Voltage vs Frequency and Supply Voltage
Output Voltage Swing vs Output Current (over Temperature)
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V)
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V)
Small-Signal Overshoot vs Load Capacitance
Phase Margin vs Capacitive Load
Small-Signal Step Response, Noninverting (1.8 V)
Small-Signal Step Response, Noninverting ( 5.5 V)
Large-Signal Step Response, Noninverting (1.8 V)
Large-Signal Step Response, Noninverting ( 5.5 V)
Positive Overload Recovery
Negative Overload Recovery
No Phase Reversal
Channel Separation vs Frequency (Dual)
THD+N vs Amplitude (G = +1, 2 kΩ, 10 kΩ)
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ)
THD+N vs Frequency (0.5 VRMS, G = +1, 2 kΩ, 10 kΩ)
EMIRR IN+ vs Frequency
版权 © 2018, Texas Instruments Incorporated
9
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
6.8 Typical Characteristics
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
140
120
100
80
180
135
90
140
135
130
125
120
115
110
105
100
Gain
100 kꢀ, 5.5 V
Phase
CL = 10 pF
10 kꢀ, 5.5 V
60
2 kꢀ, 5.5 V
40
20
45
CL = 100 pF
0
10 kꢀ, 1.8 V
-25
-20
0
1
10
100
1k
10k 100k 1M
10M 100M
-50
0
25
50
75
100
125
C002
C001
Frequency (Hz)
Temperature (oC)
图 1. Open-Loop Gain and Phase vs Frequency
图 2. Open-Loop Gain vs Temperature
60
58
56
54
52
50
48
46
44
42
40
65
60
55
50
45
40
35
VS = 5.5 V
VS = 1.8 V
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-50
-25
0
25
50
75
100
125
Temperature (oC)
C003
C004
Supply Voltage (V)
图 3. Quiescent Current vs Supply
图 4. Quiescent Current vs Temperature
9
8
7
6
5
4
3
2
1
0
25
20
15
10
5
0
Offset Voltage Drift (µV/oC)
C006
Offset Voltage (mV)
C005
图 5. Offset Voltage Production Distribution
图 6. Offset Voltage Drift Distribution
10
版权 © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
1500
1200
900
1500
1200
900
600
600
300
300
0
0
-300
-600
-900
-1200
-1500
-300
-600
-900
-1200
-1500
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
25
50
75
100
125
Common-Mode Voltage (V)
Temperature (oC)
C007
C008
图 7. Offset Voltage vs Common-Mode Voltage
图 8. Offset Voltage vs Temperature
110
105
100
95
120
100
80
60
40
20
0
PSRR
90
+PSRR
CMRR
85
CMRR
80
75
70
65
-PSRR
60
-50
-25
0
25
50
75
100
125
C001
10
100
1k
10k
100k
1M
C009
Temperature (oC)
Frequency (Hz)
图 10. CMRR and PSRR vs Temperature
图 9. CMRR and PSRR vs Frequency
(Referred-to-Input)
1000
100
10
VS = 1.8 V
VS = 5.5 V
1
Time (1 s/div)
1
10
100
1k
10k
100k
C011
C012
Frequency (Hz)
图 11. 0.1-Hz to 10-Hz Input Voltage Noise
图 12. Input Voltage Noise Spectral Density vs Frequency
版权 © 2018, Texas Instruments Incorporated
11
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
40
35
30
25
20
15
10
200
150
100
50
IBN
IBP
0
IOS
-50
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
25
50
75
100
125
C014
Temperature (oC)
C013
Common-Mode Input Voltage (V)
图 13. Voltage Noise vs Common-Mode Voltage
图 14. Input Bias and Offset Current vs Temperature
100k
6
5
VS = 5.5 V
4
VS = 1.8 V
VS = 1.8 V
3
10k
2
1
0
VS = 5.5 V
1000
1000
10k
100k
1M
1
10
100
1k
10k
100k
Frequency (Hz)
C016
Frequency (Hz)
C015
图 15. Open-Loop Output Impedance vs Frequency
图 16. Maximum Output Voltage vs Frequency and Supply
Voltage
3
2
1
40
G = +10 V/V
20
G = +1 V/V
o
o
-40 o
C
+125C
+25
C
0
-1
-2
-3
0
G = -1 V/V
-20
10
100
1k
10k
100k
1M
10M
100M
0
5
10
Output Current (mA)
15
20
Frequency (Hz)
C018
C017
图 17. Output Voltage Swing vs Output Current (Over
图 18. Closed-Loop Gain vs Frequency (Minimum Supply)
Temperature)
12
版权 © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
42
50
45
40
35
30
25
20
15
10
5
VS = 1.8V, VCM = 0.5V
G = +12 V/V
±2
G = +1 V/V
VS = 5.5V
2
G = -1 V/V
±±2
0
12
122
1k
12k 122k
Frequency (Hz)
1M
12M
122M
C222
0
100
200
Capacitive Load (pF)
300
400
C002
图 19. Closed-Loop Gain vs Frequency
图 20. Small-Signal Overshoot vs
(Maximum Supply)
Load Capacitance
90
80
70
60
50
40
30
20
10
0
CL = 100 pF
VIN
CL = 10 pF
VS = 5.5V
VS = 1.8V, VCM = 0.5V
0
100
200
300
400
C003
C004
Time (1 µs/div)
Capacitive Load (pF)
图 22. Small-Signal Pulse Response
图 21. Phase Margin vs Capacitive Load
(Minimum Supply)
CL = 100 pF
VIN
VOUT
CL = 10 pF
VIN
Time (1 µs/div)
Time (2.5 µs/div)
C023
C024
图 23. Small-Signal Pulse Response
图 24. Large-Signal Pulse Response
(Maximum Supply)
(Minimum Supply)
版权 © 2018, Texas Instruments Incorporated
13
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
VOUT
VOUT
VIN
VIN
Time (2.5 µs/div)
Time (2 µs/div)
C025
C026
图 25. Large-Signal Pulse Response
图 26. Positive Overload Recovery
(Maximum Supply)
VIN
VOUT
VOUT
VIN
Time (125 µs/div)
Time (2 µs/div)
C028
C027
图 27. Negative Overload Recovery
图 28. No Phase Reversal
-60
-80
0.1
0.01
RL = 2 k
-100
-120
-140
-160
chB to chA
chA to chB
0.001
0.0001
RL = 10 k
100
1k
10k
100k
1M
10M
0.01
0.1 1
Output Amplitude (VRMS
10
C030
)
C029
Frequency (Hz)
图 30. THD+N vs Output Amplitude
图 29. Channel Separation vs Frequency
(Minimum Supply)
14
版权 © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
0.1
0.1
RL = 2 k
0.01
0.01
RL = 2 k
0.001
0.0001
0.001
0.0001
RL = 10 k
10k
R L = 10 k
10
100
1k
Frequency (Hz)
100k
0.01
0.1 1
Output Amplitude (VRMS
10
C032
)
C031
图 32. THD+N vs Frequency
图 31. THD+N vs Output Amplitude
(Maximum Supply)
120
100
80
60
40
20
0
10
100
1000
10000
Frequency (MHz)
C033
图 33. EMIRR IN+ vs Frequency
版权 © 2018, Texas Instruments Incorporated
15
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The OPA2313-Q1 is a low-power, rail-to-rail input and output operational amplifier designed for cost-constrained
applications. This device operates from 1.8 V to 5.5 V, is unity-gain stable, and suitable for a wide range of
general-purpose applications. The class AB output stage is capable of driving loads greater than 10-kΩ
connected to any point between V+ and ground. The input common-mode voltage range includes both rails, and
allows the OPA2313-Q1 to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes this device ideal for
driving sampling analog-to-digital converters (ADCs).
The OPA2313-Q1 features 1-MHz bandwidth and 0.5-V/µs slew rate with only 50-µA supply current per channel,
providing good ac performance at very low power consumption. Low frequency (dc) applications are also well
served with a low input noise voltage of 25 nV/√Hz at 1 kHz, low input bias current (0.2 pA), and an input offset
voltage of 0.5 mV (typical). The typical offset voltage drift is 2 µV/°C; over the full temperature range the input
offset voltage changes only 200 µV (0.5 mV to 0.7 mV).
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN-
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V-
(Ground)
16
版权 © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
7.3 Feature Description
7.3.1 Operating Voltage
The OPA2313-Q1 device is fully specified and tested from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Parameters that
vary with supply voltage are illustrated in the Typical Characteristics section.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPA2313-Q1 device extends 200 mV beyond the supply rails.
This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel
with a P-channel differential pair, as shown in the Functional Block Diagram section. The N-channel pair is active
for input voltages close to the positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the
P-channel pair is on for inputs from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a
small transition region, typically (V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition
region may vary up to 300 mV with process variation. Thus, the transition region (both stages on) may range
from (V+) – 1.7 V to (V+) – 1.5 V on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this
transition region, PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to device
operation outside this region.
7.3.3 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the OPA2313-Q1 delivers a robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing
capability. For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail
regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to
swing close to the rails, as shown in 图 17.
7.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the OPA2313-Q1 device is specified in several ways so the best match for a given application may be
used; see the Electrical Characteristics. First, the CMRR of the device in the common-mode range below the
transition region (VCM < (V+) – 1.3 V) is given. This specification is the best indicator of the capability of the
device when the application requires use of one of the differential input pairs. Second, the CMRR over the entire
common-mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through
the transition region, as shown in 图 7.
7.3.5 Capacitive Load and Stability
The OPA2313-Q1 device is designed to be used in applications where driving a capacitive load is required. As
with all op amps, there may be specific instances where the OPA2313-Q1 device may become unstable. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether or not an amplifier is stable in operation. An op amp in the unity-gain (+1-V/V) buffer
configuration that drives a capacitive load exhibits a greater tendency to be unstable than an amplifier operated
at a higher noise gain. The capacitive load, in conjunction with the op amp output resistance, creates a pole
within the feedback loop that degrades the phase margin. The degradation of the phase margin increases as the
capacitive loading increases. When operating in the unity-gain configuration, the OPA2313-Q1 device remains
stable with a pure capacitive load up to approximately 1 nF. The equivalent series resistance (ESR) of some
capacitors (CL greater than 1 µF) is sufficient to alter the phase characteristics in the feedback loop such that the
amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger
capacitance. This increased capability is evident when observing the overshoot response of the amplifier at
higher voltage gains. See the typical characteristic graph, 图 20.
版权 © 2018, Texas Instruments Incorporated
17
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
Feature Description (接下页)
One technique for increasing the capacitive load drive capability of the amplifier when it operates in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in 图 34. This
resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
图 34. Improving Capacitive Load Drive
7.3.6 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the op amp, the DC offset observed at the amplifier output may shift from the nominal
value while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. While all op amp pin functions may be affected by EMI, the signal input pins are likely to be the most
susceptible. The OPA2313-Q1 device incorporates an internal input low-pass filter that reduces the amplifiers
response to EMI. Both common-mode and differential mode filtering are provided by this filter. The filter is
designed for a common-mode cutoff frequency of approximately 35 MHz (–3 dB), with a rolloff of 20 dB per
decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. 图 33 illustrates the results of this testing on
the OPA2313-Q1 device. Detailed information may be found in EMI Rejection Ratio of Operational Amplifiers,
available for download from www.ti.com.
7.3.7 Input and ESD Protection
The OPA2313-Q1 device incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current-steering diodes connected between the
input and power-supply pins. The ESD protection diodes also provide in-circuit, input overdrive protection, as
long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings. 图 35 shows how a series
input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal
noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
VOUT
Device
VIN
5 kW
图 35. Input Current Protection
7.4 Device Functional Modes
The OPA2313-Q1 device has a single functional mode. The device is powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
18
版权 © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2313-Q1 device is a low-power, rail-to-rail input and output operational amplifier. The device operates
from 1.8 V to 5.5 V, is unity-gain stable, and is designed for a wide range of general-purpose applications. The
class AB output stage is capable of driving loads greater than 10 kΩ connected to any point between V+ and
ground. The input common-mode voltage range includes both rails, and allows the OPA2313-Q1 to be used in
virtually any single-supply application.
8.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier, as shown in 图 36. An inverting amplifier
takes a positive voltage on the input and outputs a signal inverted to the input, making a negative voltage of the
same magnitude. In the same manner, the amplifier also makes negative input voltages positive on the output. In
addition, amplification may be added by selecting the input resistor (RI) and the feedback resistor (RF.)
RF
VSUP+
RI
VOUT
+
VIN
VSUPœ
图 36. Inverting Amplifier Application
8.2.1 Design Requirements
The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must also be
considered. For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at
±2.5 V is sufficient to accommodate this application.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using 公式 1 and 公式 2:
VOUT
AV
=
V
IN
(1)
(2)
1.8
AV
=
= -3.6
-0.5
版权 © 2018, Texas Instruments Incorporated
19
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
Typical Application (接下页)
When the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures the device does not draw too much current. The trade-off is that very large
resistors (100s of kilohms) draw the smallest current but generate the highest noise. Small resistors (100s of
ohms) generate low noise but draw high current. This example uses 10 kΩ for RI, resulting in a 36-kΩ resistor
being used for RF. The values are determined by 公式 3:
RF
AV = -
RI
(3)
8.2.3 Application Curve
2
1.5
1
Input
Output
0.5
0
-0.5
-1
-1.5
-2
Time
图 37. Inverting Amplifier Input and Output
8.3 System Examples
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as shown in 图 38.
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
图 38. Single-Pole Low-Pass Filter
20
版权 © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
System Examples (接下页)
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter may be used for this
task, as shown in 图 39. For best results, the amplifier must have a bandwidth that is 8 to 10 times the filter
frequency bandwidth. Failure to follow this guideline may result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
R1
R2
Q = Peaking factor
(Butterworth Q = 0.707)
VIN
VOUT
C2
1
2pRC
f
=
-3 dB
RF
RF
RG
=
1
2 -
RG
(
(
Q
图 39. Two-Pole, Low-Pass, Sallen-Key Filter
9 Power Supply Recommendations
The OPA2313-Q1 device is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to +125°C. The Typical Characteristics section presents parameters that may exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings table).
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section.
版权 © 2018, Texas Instruments Incorporated
21
OPA2313-Q1
ZHCSJ37 –DECEMBER 2018
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise may propagate into analog circuitry through the power pins of the circuit and the operational
amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If the traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better
than crossing in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input to minimize parasitic capacitance, as shown in 图 40.
Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
图 40. Schematic Representation for 图 41
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
RG
RG
VIN 1
GND
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
图 41. Layout Example
22
版权 © 2018, Texas Instruments Incorporated
OPA2313-Q1
www.ti.com.cn
ZHCSJ37 –DECEMBER 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
《运算放大器的电磁干扰 (EMI) 抑制比》
《电路板布局布线技巧》
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2313QDGKRQ1
OPA2313QDRQ1
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
23131
O2313Q
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2313QDGKRQ1
OPA2313QDRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
6.4
3.4
5.2
1.4
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2313QDGKRQ1
OPA2313QDRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
366.0
340.5
364.0
336.1
50.0
25.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2021 德州仪器半导体技术（上海）有限公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明