OPA2340UA/2K5 [TI]
双路、单电源、轨到轨、低功耗运算放大器 | D | 8;
| 型号： | OPA2340UA/2K5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、单电源、轨到轨、低功耗运算放大器 | D | 8 放大器 光电二极管 运算放大器 |
| 文件： | 总44页 (文件大小：1640K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA340, OPA2340, OPA4340
SBOS073C –SEPTEMBER 1997–REVISED AUGUST 2016
OPAx340 Single-Supply, Rail-to-Rail Operational Amplifiers
MicroAmplifier™ Series
The OPA340 series operate on a single supply as low
1 Features
as 2.5 V with an input common-mode voltage range
that extends 500 mV below ground and 500 mV
above the positive supply. Output voltage swing is to
within 1 mV of the supply rails with a 100-kΩ load.
These devices offer excellent dynamic response
(BW = 5.5 MHz, SR = 6 V/µs), yet quiescent current
is only 750 A. Dual and quad designs feature
completely independent circuitry for lowest crosstalk
and freedom from interaction.
1
•
•
•
•
•
•
•
•
Rail-to-Rail Input
Rail-to-Rail Output (Within 1 mV)
MicroSize Packages
Wide Bandwidth: 5.5 MHz
High Slew Rate: 6 V/µs
Low THD + Noise: 0.0007% (f = 1 kHz)
Low Quiescent Current: 750 µA/Channel
Single, Dual, and Quad Versions
The single (OPA340) packages are the tiny 5-pin
SOT-23 surface mount, 8-pin SOIC surface mount,
and 8-pin DIP. The dual (OPA2340) comes in the
miniature 8-pin VSSOP surface mount, 8-pin SOIC
surface mount, and 8-pin PDIP packages. The quad
(OPA4340) packages are the space-saving 16-pin
SSOP surface mount and 14-pin SOIC surface
mount. All are specified from –40°C to 85°C and
operate from –55°C to 125°C. A SPICE macromodel
is available for design analysis.
2 Applications
•
•
•
•
•
•
•
•
Driving A/D Converters
PCMCIA Cards
Data Acquisition
Process Control
Audio Processing
Communications
Active Filters
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
3.00 mm × 3.00 mm
9.81 mm × 6.35 mm
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
4.90 mm × 3.90 mm
Test Equipment
OPA340
SOT-23 (5)
PDIP (8)
3 Description
OPA340, OPA2340
OPA2340
SOIC (8)
The OPA340 series rail-to-rail CMOS operational
amplifiers are optimized for low-voltage, single-supply
operation. Rail-to-rail input and output and high-
speed operation make them ideal for driving sampling
analog-to-digital (A/D) converters. They are also well-
suited for general purpose and audio applications as
well as providing I/V conversion at the output of
digital-to-analog (D/A) converters. Single, dual, and
quad versions have identical specifications for design
flexibility.
VSSOP (8)
SOIC (14)
SSOP (16)
OPA4340
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
OPA340 in Noninverting Configuration Driving ADS7816
+5V
0.1mF
0.1mF
1
VREF
8
V+
7
6
5
DCLOCK
DOUT
500W
+In
2
Serial
ADS7816
OPA340
Interface
12-Bit A/D
VIN
-In
CS/SHDN
3
3300pF
GND
4
VIN = 0V to 5V for
0V to 5V output.
NOTE: A/D Input = 0 to VREF
RC network filters high-frequency noise.
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA340, OPA2340, OPA4340
SBOS073C –SEPTEMBER 1997–REVISED AUGUST 2016
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
Power Supply Recommendations...................... 19
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information – OPA340 ................................ 5
6.5 Thermal Information – OPA2340 .............................. 6
6.6 Thermal Information – OPA4340 .............................. 6
6.7 Electrical Characteristics........................................... 6
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1 Device Support...................................................... 21
11.2 Documentation Support ........................................ 22
11.3 Related Links ........................................................ 22
11.4 Receiving Notification of Documentation Updates 22
11.5 Community Resources.......................................... 22
11.6 Trademarks........................................................... 22
11.7 Electrostatic Discharge Caution............................ 22
11.8 Glossary................................................................ 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision B (November 2007) to Revision C
Page
•
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Deleted Package/Ordering Information table, see POA at the end of the data sheet............................................................ 1
2
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Product Folder Links: OPA340 OPA2340 OPA4340
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SBOS073C –SEPTEMBER 1997–REVISED AUGUST 2016
5 Pin Configuration and Functions
OPA340: DBV Package
5-Pin SOT-23
OPA340: P and D Packages
8-Pin PDIP and SOIC
Top View
Top View
Pin Functions: OPA340
PIN
I/O
DESCRIPTION
NAME
–IN
SOT-23
SOIC, PDIP
4
3
2
I
Negative (inverting) input
+IN
NC
3
I
Positive (noninverting) input
—
1
1, 5, 8
—
O
—
—
No internal connection (can be left floating)
Output
OUT
V–
6
4
7
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
OPA2340: P, D, and DGK Packages
8-Pin PDIP, SOIC, and VSSOP
Top View
Pin Functions: OPA2340
PIN
I/O
DESCRIPTION
VSSOP, SOIC,
PDIP
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
2
3
6
5
1
7
4
8
I
I
Negative (inverting) input channel A
Positive (noninverting) input channel A
Negative (inverting) input channel B
Positive (noninverting) input channel B
Output channel A
I
I
O
O
—
—
Output channel B
Negative (lowest) power supply
Positive (highest) power supply
V+
Copyright © 1997–2016, Texas Instruments Incorporated
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OPA4340: D Package
14-Pin SOIC
OPA4340: DBQ Package
16-Pin SSOP
Top View
Top View
Pin Functions: OPA4340
PIN
I/O
DESCRIPTION
NAME
–IN A
–IN B
–IN C
–IN D
+IN A
+IN B
+IN C
+IN D
NC
SOIC
2
SSOP
2
I
I
Negative (inverting) input channel A
Negative (inverting) input channel B
Negative (inverting) input channel C
Negative (inverting) input channel D
Positive (noninverting) input channel A
Positive (noninverting) input channel B
Positive (noninverting) input channel C
Positive (noninverting) input channel D
No internal connection (can be left floating)
Output, channel A
6
6
9
11
15
3
I
13
3
I
I
5
5
I
10
12
—
1
12
14
8, 9
1
I
I
—
O
O
O
O
—
—
OUT A
OUT B
OUT C
OUT D
V–
7
7
Output, channel B
8
10
16
13
4
Output, channel C
14
11
4
Output, channel D
Negative (lowest) power supply
Positive (highest) power supply
V+
4
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Product Folder Links: OPA340 OPA2340 OPA4340
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SBOS073C –SEPTEMBER 1997–REVISED AUGUST 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.5
UNIT
V
Supply voltage
Voltage
Signal input terminals(2)
–0.5
0.5
Signal input terminals(2)
Output short circuit(3)
10
mA
Current
Continuous
Operating, TA
–55
125
150
125
Temperature
Junction, TJ
Storage, Tstg
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±600
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
Supply voltage
2.7
V
Specified temperature
–40
125
°C
6.4 Thermal Information – OPA340
OPA340
DBV
(SOT-23)
P
D
D
THERMAL METRIC(1)
UNIT
(PDIP)
(SOIC)
8 PINS
142
(SOIC)
5 PINS
207.9
71.2
36.0
2.0
8 PINS
53.1
42.5
30.3
19.7
30.2
—
14 PINS
83.8
70.7
59.5
11.6
37.7
—
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
90.2
82.5
39.4
82
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
35.2
—
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 1997–2016, Texas Instruments Incorporated
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6.5 Thermal Information – OPA2340
OPA2340
D
DGK
(VSSOP)
THERMAL METRIC(1)
UNIT
(SOIC)
8 PINS
138.4
89.5
78.6
29.9
78.1
—
8 PINS
169.2
62.8
89.8
7.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
88.2
—
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information – OPA4340
OPA4340
DBQ
(SSOP)
16 PINS
115.8
67
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
58.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19.9
ψJB
57.9
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Electrical Characteristics
At TA = 25°C, RL = 10 kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 5 V
±150
±2.5
30
±500
µV
dVOS/dt
Input offset voltage vs temperature
TA = –40°C to 85°C, VS = 5 V
VS = 2.7 V to 5.5 V, VCM = 0 V
µV/°C
µV/V
120
120
Input offset voltage vs
power supply
PSRR
VS = 2.7 V to 5.5 V, VCM = 0 V,
TA = –40°C to 85°C, VS = 5 V
Over temperature
µV/°C
µV/V
Channel separation, DC
INPUT BIAS CURRENT
0.2
±0.2
±0.2
±10
±60
±10
IS
Input bias current
Input offset current
pA
pA
Over temperature
TA = –40°C to 85°C, VS = 5 V
IOS
NOISE
Input voltage noise
f = 0.1 kHz to 50 kHz
f = 1 kHz
8
25
3
µVRMS
nV/√Hz
fA/√Hz
en
in
Input voltage noise density
Current noise density
f = 1 kHz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
–0.3
80
(V+) + 0.3
V
–0.3 V < VCM < (V+) – 1.8 V
VS = 5 V, –0.3 V < VCM < 5.3 V
VS = 2.7 V, –0.3 V < VCM < 3 V
92
84
80
CMRR
Common-mode rejection ratio
70
dB
66
(1) VS = 5 V.
6
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SBOS073C –SEPTEMBER 1997–REVISED AUGUST 2016
Electrical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
INPUT IMPEDANCE
1013 || 3
1013 || 6
Differential
Ω || pF
Ω || pF
Common-mode
OPEN-LOOP GAIN
RL = 100 kΩ,
5 mV < VO < (V+) – 5 mV
106
100
94
124
120
114
RL = 10 kΩ,
5 mV < VO < (V+) – 50 mV
RL = 2 kΩ,
200 mV < VO < (V+) – 200 mV
RL = 100 kΩ,
5 mV < VO < (V+) – 5 mV,
TA = –40°C to 85°C, VS = 5 V
AOL
Open-loop voltage gain
dB
106
100
94
RL = 10 kΩ,
5 mV < VO < (V+) – 50 mV,
TA = –40°C to 85°C, VS = 5 V
Over temperature
RL = 2 kΩ,
200 mV < VO < (V+) – 200 mV,
TA = –40°C to 85°C, VS = 5 V
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
G = 1
5.5
6
MHz
V/µs
µs
Slew rate
VS = 5 V, G = 1, CL = 100 pF
VS = 5 V, 2-V step, CL = 100 pF
VS = 5 V, 2-V step, CL = 100 pF
VIN × G = VS
Settling time, 0.1%
Settling time, 0.01%
Overload recovery time
1
1.6
0.2
µs
µs
VS = 5 V, VO = 3VPP(2), G = 1,
f = 1 kHz
THD+N
Total harmonic distortion + noise
0.0007%
OUTPUT
RL = 100 kΩ, AOL ≥ 106 dB
RL = 10 kΩ, AOL ≥ 106 dB
RL = 2 kΩ, AOL ≥ 106 dB
1
10
40
5
RL = 100 kΩ, AOL ≥ 106 dB,
TA = –40°C to 85°C, VS = 5 V
Voltage output swing from
rail(2)
5
50
mV
mA
RL = 10 kΩ, AOL ≥ 106 dB,
TA = –40°C to 85°C, VS = 5 V
Over temperature
RL = 2 kΩ, AOL ≥ 106 dB,
TA = –40°C to 85°C, VS = 5 V
200
ISC
Short-circuit current
Capacitive load drive
±50
CLOAD
See Typical Characteristics
POWER SUPPLY
VS Specified voltage range
2.7
2.5
5.5
750
5
V
V
Lower end
Operating voltage range
Higher end
IO = 0, VS = 5 V
950
100
Quiescent current
(per amplifier)
IQ
µA
Over temperature
IO = 0, VS = 5 V, TA = –40°C to 85°C
TEMPERATURE RANGE
Specified range
–40
–55
–55
85
125
125
°C
°C
°C
Operating range
Storage range
(2) Output voltage swings are measured between the output and power-supply rails.
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6.8 Typical Characteristics
At TA = 25°C, VS = 5 V, and RL = 10 kΩ connected to VS/2, unless otherwise noted.
160
140
120
100
80
0
100
80
60
40
20
0
PSRR
-45
-90
-135
-180
60
CMRR
40
20
0
-20
0.1
1
10
100
1k
10k 100k
1M
10M
1
10
100
1k
Frequency (Hz)
10k
100k
1M
Frequency (Hz)
Figure 1. Open-Loop Gain/Phase vs Frequency
Figure 2. Power-Supply and Common-Mode Rejection vs
Frequency
1k
140
130
120
10k
1k
Current Noise
100
10
1
Voltage Noise
100
10
1
110
G = 1, All Channels
0.1
100
1
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 4. Channel Separation vs Frequency
Figure 3. Input Voltage and Current Noise Spectral Density
vs Frequency
0.1
5k
4k
3k
2k
1k
0
G = 100
RL = 600
RL = 2kW
G = 10
0.01
G = 10
RL = 10kW
RL = 600
RL = 2kW
G = 1
0.001
G = 1
RL = 10kW
0.0001
10
100
1k
10k
100k
1M
10M
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Figure 6. Closed-Loop Output Impedance vs Frequency
Figure 5. Total Harmonic Distortion + Noise vs Frequency
8
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SBOS073C –SEPTEMBER 1997–REVISED AUGUST 2016
Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, and RL = 10 kΩ connected to VS/2, unless otherwise noted.
130
120
110
100
90
100
90
80
70
60
50
40
RL = 100kW
AOL
RL = 10kW
RL = 2kW
PSRR
VS = 2.7V to 5V, VCM = -0.3V to (V+) -1.8V
VS = 5V, VCM = -0.3V to 5.3V
VS = 2.7V, VCM = -0.3V to 3V
80
-75
-50 -25
0
25
50
75
100 125
-75
-50 -25
0
25
50
75
100 125
Temperature (°C)
Temperature (°C)
Figure 7. Open-Loop Gain and Power-Supply Rejection vs
Temperature
Figure 8. Common-Mode Rejection vs Temperature
1000
800
750
700
650
600
Per Amplifier
Per Amplifier
900
800
700
600
500
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-75
-50 -25
0
25
50
75
100 125
Supply Voltage (V)
Temperature (°C)
Figure 10. Quiescent Current vs Supply Voltage
Figure 9. Quiescent Current vs Temperature
100
90
80
70
60
50
40
30
20
10
0
60
50
40
30
-ISC
-ISC
+ISC
+ISC
-75
-50
-25
0
25
50
75
100
125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Temperature (°C)
Supply Voltage (V)
Figure 11. Short-Circuit Current vs Temperature
Figure 12. Short-Circuit Current vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, and RL = 10 kΩ connected to VS/2, unless otherwise noted.
1.0
1k
100
10
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
1
0.1
-75
-50
-25
0
25
50
75
100
125
-1
0
1
2
3
4
5
6
Temperature (°C)
Common-Mode Voltage (V)
Figure 13. Input Bias Current vs Temperature
Figure 14. Input Bias Current vs Input Common-Mode
Voltage
5
6
VS = 5.5V
Maximum output
voltage without
slew rate-induced
distortion.
+125°C
+25°C
-55°C
5
4
3
2
1
0
4
3
2
1
0
VS = 2.7V
-55°C
+125°C
+25°C
100k
1M
10M
0
±10 ±20 ±30 ±40 ±50 ±60 ±70 ±80 ±90 ±100
Frequency (Hz)
Output Current (mA)
Figure 16. Maximum Output Voltage vs Frequency
Figure 15. Output Voltage Swing vs Output Current
18
25
Typical production
distribution of
Typical production
distribution of
16
14
12
10
8
packaged units.
packaged units.
20
15
10
5
6
4
2
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 15
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 18. Offset Voltage Drift Magnitude Production
Distribution
Figure 17. Offset Voltage Production Distribution
10
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, and RL = 10 kΩ connected to VS/2, unless otherwise noted.
1ms/div
1ms/div
CL = 100 pF
CL = 100 pF
Figure 19. Small-Signal Step Response
Figure 20. Large-Signal Step Response
60
50
40
30
20
100
G = -1
0.01%
0.1%
G = +1
10
1
G = -5
See text for
G = +5
10
0
reducing overshoot.
0.1
1
100
1000
Load Capacitance (pF)
10k
10
100
1000
Closed-Loop Gain (V/V)
Figure 21. Small-Signal Overshoot vs Load Capacitance
Figure 22. Settling Time vs Closed-Loop Gain
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7 Detailed Description
7.1 Overview
The OPA340 series operational amplifiers are fabricated on a state-of-the-art, 0.6-micron CMOS process. These
devices are unity-gain stable and suitable for a wide range of general-purpose applications. Rail-to-rail input and
output make them ideal for driving sampling A/D converters. In addition, excellent AC performance makes them
well-suited for audio applications. The class AB output stage is capable of driving 600-Ω loads series and
extends 500 mV beyond the supply. Rail-to-rail input and output swing significantly increases dynamic range,
especially in low-supply applications. Figure 23 shows the input and output waveforms for the OPA340 in unity-
gain configuration. Operation is from a single 5-V supply with a 10-kΩ load connected to V/2. The input is a 5-
VPP sinusoid. Output voltage is approximately 4.98 VPP. Power-supply pins must be bypassed with 0.01-µF
ceramic capacitors.
VS = +5, G = +1, RL = 10kW
5
VIN
5
VOUT
0
Figure 23. Rail-to-Rail Input and Output
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN
-
VBIAS1
Class AB
Control
VO
Circuitry
VBIAS2
V-
(Ground)
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7.3 Feature Description
7.3.1 Operating Voltage
The OPA340 series operational amplifiers are fully specified from 2.7 V to 5 V. However, supply voltage may
range from 2.5 V to 5.5 V. Parameters are ensured over the specified supply range—a unique feature of the
OPA340 series. In addition, many specifications apply from –40°C to 85°C. Most behavior remains virtually
unchanged throughout the full operating voltage range. Parameters which vary significantly with operating
voltages or temperature are shown in the Typical Characteristics.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPA340 series extends 500 mV beyond the supply rails. This
extended range is achieved with a complementary input stage—an N-channel input differential pair in parallel
with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail, typically
(V+) – 1.3 V to 500 mV above the positive supply, while the P-channel pair is on for inputs from 500 mV below
the negative supply to approximately (V+) – 1.3 V. There is a small transition region, typically (V+) – 1.5 V to
(V+) – 1.1 V, in which both pairs are on. This 400-mV transition region can vary ±300 mV with process variation.
Thus, the transition region (both stages on) can range from (V+) – 1.8 V to (V+) – 1.4 V on the low end, up to
(V+) – 1.2 V to (V+) – 0.8 V on the high end.
OPA340 series operational amplifiers are laser-trimmed to the reduce offset voltage difference between the N-
channel and P-channel input stages, resulting in improved common-mode rejection and a smooth transition
between the N-channel pair and the P-channel pair. However, within the 400-mV transition region PSRR, CMRR,
offset voltage, offset drift, and THD may be degraded compared to operation outside this region.
A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class
AB output stage. Normally, input bias current is approximately 200 fA; however, input voltages exceeding the
power supplies by more than 500 mV can cause excessive current to flow in or out of the input pins. Momentary
voltages greater than 500 mV beyond the power supply can be tolerated if the current on the input pins is limited
to 10 mA. This current limiting is easily accomplished with an input resistor, as shown in Figure 24. Many input
signals are inherently current-limited to less than 10 mA; therefore, a limiting resistor is not required.
V+
IOVERLOAD
10mA max
VOUT
OPAx340
VIN
5kW
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Input Current Protection for Voltages Exceeding the Supply Voltage
7.3.3 Rail-to-Rail Output
A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For light resistive
loads (> 50 kΩ), the output voltage is typically a few millivolts from the supply rails. With moderate resistive loads
(2 kΩ to 50 kΩ), the output can swing to within a few tens of millivolts from the supply rails and maintain high
open-loop gain (see Figure 15).
7.3.4 Capacitive Load and Stability
OPA340 series operational amplifiers can drive a wide range of capacitive loads. However, all operational
amplifiers under certain conditions can become unstable. operational amplifier configuration, gain, and load value
are some of the factors to consider when determining stability. An operational amplifier in unity-gain configuration
is most susceptible to the effects of capacitive load. The capacitive load reacts with the output resistance of the
operational amplifier, along with any additional load resistance, to create a pole in the small-signal response that
degrades the phase margin. In unity-gain configuration, the OPA340 series operational amplifiers perform well,
with a pure capacitive load up to approximately 1000 pF. Increasing gain enhances the amplifier ability to drive
more capacitance (see Figure 21).
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Feature Description (continued)
One method of improving capacitive load drive in the unity-gain configuration is to insert a 10-Ω to 20-Ω resistor
in series with the output, as shown in Figure 25. This resistor significantly reduces ringing with large capacitive
loads. However, if there is a resistive load in parallel with the capacitive load, it creates a voltage divider
introducing a DC error at the output and slightly reduces output swing. This error can be insignificant. For
instance, with RL = 10 kΩ and RS = 20 Ω, there is only an approximate 0.2% error at the output.
When used with the miniature package options of the OPA340 series, the combination is ideal for space-limited
and low-power applications. For further information, consult the ADS7816 data sheet, 12-Bit High Speed Micro
Power Sampling Analog-To-Digital Converter (SBAS061). With the OPA340 in a noninverting configuration, an
RC network at the output of the amplifier can be used to filter high-frequency noise in the signal (see Figure 26).
In the inverting configuration, filtering may be accomplished with a capacitor across the feedback resistor (see
Figure 27).
V+
RS
VOUT
OPAx340
10W to
20W
VIN
CL
RL
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
7.3.5 Driving A/D Converters
The OPA340 series operational amplifiers are optimized for driving medium-speed (up to 100 kHz) sampling A/D
converters. However, they also offer excellent performance for higher speed converters. The OPA340 series
provides an effective means of buffering the converter input capacitance and resulting charge injection while
providing signal gain. Figure 26 and Figure 27 show the OPA340 driving an ADS7816. The ADS7816 is a 12-bit,
micro-power sampling converter in the tiny 8-pin VSSOP package.
+5V
0.1mF
0.1mF
1
VREF
8
V+
7
6
5
DCLOCK
DOUT
500W
+In
2
Serial
ADS7816
OPA340
Interface
12-Bit A/D
VIN
-In
CS/SHDN
3
3300pF
GND
4
VIN = 0V to 5V for
0V to 5V output.
NOTE: A/D Input = 0 to VREF
RC network filters high-frequency noise.
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Figure 26. OPA340 in Noninverting Configuration Driving ADS7816
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Feature Description (continued)
+5V
330pF
0.1mF
0.1mF
5kW
5kW
VIN
1
VREF
8
V+
7
6
5
DCLOCK
DOUT
+In
2
Serial
ADS7816
OPA340
Interface
12-Bit A/D
-In
CS/SHDN
3
GND
4
VIN = 0V to -5V for 0V to 5V output.
NOTE: A/D Input = 0 to VREF
Copyright © 2016, Texas Instruments Incorporated
Figure 27. OPA340 in Inverting Configuration Driving ADS7816
Filters 160Hz to 2.4kHz
+5V
10MW
10MW
VIN
243kW
1.74MW
1/2
OPA2340
200pF
1/2
47pF
OPA2340
RL
220pF
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Speech Bandpass Filter
7.4 Device Functional Modes
The OPAx340 has a single functional mode and is operational when the power-supply voltage is greater than
2.7 V (±1.35 V). The maximum power supply voltage for the OPAx340 is 5.5 V (±2.75 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx340 amplifier is a single-supply, CMOS operational amplifier with 5.5-MHz unity-gain bandwidth and
supply current of 950 µA. Its performance is optimized for low-voltage (2.7 V to 5.5 V), single-supply applications,
with its input common-mode voltage linear range extending 300 mV beyond the rails and the output voltage
swing within 5 mV of either rail. The OPAx340 series features wide bandwidth and unity-gain stability with rail-to-
rail input and output for increased dynamic range. Power-supply pins must be bypassed with 0.01-µF ceramic
capacitors.
8.2 Typical Applications
8.2.1 Single-Pole, Low-Pass Filter
Figure 29 shows the OPA340 in a typical noninverting application with the input signal bandwidth limited by the
input lowpass filter.
Figure 29. Single-Pole, Low-Pass Filter
Equation 1 through Equation 2 show calculations for corner frequency and gain:
(1)
(2)
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Typical Applications (continued)
8.2.1.1 Design Requirements
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as shown in Figure 29. If a steeper attenuation level is required, a two-pole or higher-order filter may be
used.
8.2.1.2 Detailed Design Procedure
The design goals for this circuit include these parameters:
•
•
•
A noninverting gain of 10 V/V (20 dB)
Design a single-pole response circuit with –3-dB rolloff at 15.9 kHz and 159 Hz
Modify the design to increase attenuation level to –40 dB/decade (Sallen-Key Filter)
Use these design values:
•
•
•
•
C1 = 0 nF, 10 nF, 1 µF
R1 = 1 kΩ
RG = 10 kΩ
RF = 90 kΩ
Figure 30 shows how the output voltage of OPA340 changes over frequency depending on the value of C1 with a
constant R1 of 1 kΩ. Without any filtering of the input signal (C1 = 0), the –3-dB effective bandwidth is a function
of the OPA340 unity-gain bandwidth and closed-loop gain, f(–3dB) = UGBW/ACL, where ACL is closed-loop gain
and UGBW denotes unity-gain bandwidth. Thus, for a closed-loop gain = 10, f(–3dB) = 1 MHz/10 =100 kHz; see
Figure 30.
To further limit the output bandwidth, an appropriate choice of C1 must be made: for C1 = 10 nF,
= 15.9 kHz.
To further limit the bandwidth, a larger C1 must be used: choosing C1 = 1 µF,
= 159 Hz (see Figure 30).
8.2.1.3 Application Curve
40
C1 = 0
20
C1 = 10 nF
0
C1 = 1 mF
-20
-40
1
10
100
1 k
10 k
100 k
1 M
Frequency (Hz)
Figure 30. OPA340 Single-Pole AC Gain vs Frequency Response
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Typical Applications (continued)
8.2.2 Two-Pole, Low-Pass Filter
If even more attenuation is required, a multiple pole filter is required. The Sallen-Key filter may be used for this
task, as shown in Figure 31. For best results, the amplifier must have effective bandwidth that is at least 10 times
higher than the filter cutoff frequency. Failure to follow this guideline results in a phase shift of the amplifier,
which in turn leads to lower precision of the filter bandwidth. Additionally, to minimize the loading effect between
multiple RC pairs on overall the filter cutoff frequency, choose R = 10 × R1 and C2 = C1/10; see Figure 32.
Figure 31. Two-Pole, Lowpass Filter
Equation 3 through Equation 5 show calculations for corner frequency and gain:
(3)
(4)
(5)
8.2.2.1 Detailed Design Procedure
Use these design values:
•
•
•
•
C1 = 10 nF and C2 = 1 nF
R1 = 1 kΩ and R2= 10 kΩ
RG = 10 kΩ
RF = 90 kΩ
Figure 32 shows the Sallen-Key filter second-order response for different RC values: for R and C values above,
= 15.9 kHz.
To further limit the bandwidth, a larger RC value must be used: increasing C values 100 times, such as
C1
=
1
µF and C2
=
0.1 µF, with unchanged resistors, results in the second-order rolloff at
= 159 Hz. See Figure 32.
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Typical Applications (continued)
8.2.2.2 Application Curve
Figure 32. OPA340 Two-Pole, Lowpass Sallen-Key AC Gain vs Frequency Response
9 Power Supply Recommendations
The OPAx340 is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V).
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings).
TI recommends placing 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in
from noisy or high-impedance power supplies.
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10 Layout
10.1 Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA340 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields can still cause varying offset levels.
10.2 Layout Example
Place components
close to device and
to eachother to
Run the input traces
reduce parasitic
as far away from
the supply lines
as possible
errors
VS+
RF
N/C
N/C
RG
GND
VIN
–IN
+IN
V–
V+
OUTPUT
N/C
GND
Use low-ESR, ceramic
bypass capacitor
GND
VS–
Use low-ESR,
ceramic bypass
capacitor
VOUT
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Layout Recommendation
+
VIN
VOUT
œ
RG
RF
Copyright © 2016,
Texas Instruments Incorporated
Figure 34. Schematic Representation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation
tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (MSOP-8), DBV (SOT23-6, SOT23-5 and
SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with
terminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of IC package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, MSOP, TSSOP and SOT23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends
requesting several operational amplifier device samples when ordering the Universal Op
Amp EVM.
11.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following application reports and publications (available for download from
www.ti.com):
•
•
•
•
•
•
•
12-Bit High Speed Micro Power Sampling Analog-To-Digital Converter (SBAS061)
A Dual-Polarity, Bidirectional Current-Shunt Monitor (SLYT311)
OPA340, OPA2340, OPA4340 EMI Immunity Performance (SBOZ010)
Getting the Full Potential from your ADC (SBAA069)
Feedback Plots Define Op Amp AC Performance (SBOA015)
Capacitive Load Drive Solution Using an Isolation Resistor (TIPD128)
Circuit Board Layout Techniques (SLOA089)
11.3 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
OPA340
OPA2340
OPA4340
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
MicroAmplifier, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2340EA/250
OPA2340EA/250G4
OPA2340EA/2K5
OPA2340EA/2K5G4
OPA2340UA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
8
250
250
RoHS & Green
RoHS & Green
NIPDAUAG | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
A40A
A40A
A40A
A40A
OPA
Samples
Samples
Samples
Samples
Samples
SN
NIPDAUAG | SN
SN
2500 RoHS & Green
2500 RoHS & Green
75
RoHS & Green
NIPDAU
-40 to 85
2340UA
OPA2340UA/2K5
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
OPA
2340UA
Samples
Samples
OPA2340UA/2K5G4
OPA
2340UA
OPA340NA/250
OPA340NA/250G4
OPA340NA/3K
OPA340NA/3KG4
OPA340PA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
PDIP
DBV
DBV
DBV
DBV
P
5
5
5
5
8
8
250
250
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
A40
Samples
Samples
Samples
Samples
Samples
Samples
A40
3000 RoHS & Green
3000 RoHS & Green
A40
A40
50
75
RoHS & Green
RoHS & Green
OPA340PA
OPA340UA
SOIC
D
Level-2-260C-1 YEAR
OPA
340UA
OPA340UA/2K5
OPA340UA/2K5G4
OPA4340EA/250
OPA4340EA/250G4
OPA4340EA/2K5
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SSOP
SSOP
SSOP
D
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
OPA
340UA
Samples
Samples
Samples
Samples
Samples
D
8
OPA
340UA
DBQ
DBQ
DBQ
16
16
16
250
250
RoHS & Green
RoHS & Green
OPA
4340EA
OPA
4340EA
2500 RoHS & Green
OPA
4340EA
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA4340UA
OPA4340UA/2K5
OPA4340UA/2K5G4
OPA4340UAG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
14
14
14
14
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
OPA4340UA
Samples
Samples
Samples
Samples
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
OPA4340UA
OPA4340UA
OPA4340UA
50
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA340 :
Enhanced Product : OPA340-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2340EA/250
OPA2340EA/250
OPA2340EA/2K5
OPA2340EA/2K5
OPA2340UA/2K5
OPA340NA/250
OPA340NA/250
OPA340NA/3K
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
250
250
330.0
330.0
330.0
330.0
330.0
179.0
178.0
178.0
179.0
330.0
180.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
8.4
5.3
5.3
5.3
5.3
6.4
3.2
3.3
3.3
3.2
6.4
6.4
6.4
6.5
3.4
3.4
3.4
3.4
5.2
3.2
3.2
3.2
3.2
5.2
5.2
5.2
9.0
1.4
1.4
1.4
1.4
2.1
1.4
1.4
1.4
1.4
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q3
Q3
Q3
Q3
Q1
Q1
Q1
Q1
8
2500
2500
2500
250
8
8
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
5
5
250
9.0
8.0
5
3000
3000
2500
250
9.0
8.0
OPA340NA/3K
5
8.4
8.0
OPA340UA/2K5
OPA4340EA/250
OPA4340EA/2K5
OPA4340UA/2K5
8
12.4
12.4
12.4
16.4
12.0
12.0
12.0
16.0
SSOP
DBQ
DBQ
D
16
16
14
SSOP
2500
2500
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2340EA/250
OPA2340EA/250
OPA2340EA/2K5
OPA2340EA/2K5
OPA2340UA/2K5
OPA340NA/250
OPA340NA/250
OPA340NA/3K
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
250
250
366.0
366.0
366.0
366.0
356.0
213.0
180.0
180.0
213.0
356.0
210.0
356.0
356.0
364.0
364.0
364.0
364.0
356.0
191.0
180.0
180.0
191.0
356.0
185.0
356.0
356.0
50.0
50.0
50.0
50.0
35.0
35.0
18.0
18.0
35.0
35.0
35.0
35.0
35.0
8
2500
2500
2500
250
8
8
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
5
5
250
5
3000
3000
2500
250
OPA340NA/3K
5
OPA340UA/2K5
OPA4340EA/250
OPA4340EA/2K5
OPA4340UA/2K5
8
SSOP
DBQ
DBQ
D
16
16
14
SSOP
2500
2500
SOIC
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA2340UA
OPA340PA
D
P
D
D
D
SOIC
PDIP
SOIC
SOIC
SOIC
8
8
75
50
75
50
50
506.6
506
8
3940
11230
3940
3940
3940
4.32
4.32
4.32
4.32
4.32
13.97
OPA340UA
8
506.6
506.6
506.6
8
8
8
OPA4340UA
OPA4340UAG4
14
14
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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