OPA2374AIDRG4 [TI]
Dual 6.5MHz, 585uA, Rail-to-Rail I/O CMOS Operational Amplifier 8-SOIC;
| 型号： | OPA2374AIDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 6.5MHz, 585uA, Rail-to-Rail I/O CMOS Operational Amplifier 8-SOIC 放大器 光电二极管 |
| 文件： | 总37页 (文件大小：1521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA373, OPA2373
OPA374
OPA2374, OPA4374
SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
6.5MHz, 585µA, Rail-to-Rail I/O
CMOS Operational Amplifier
FD EATURES
DESCRIPTION
LOW OFFSET: 5mV (max)
The OPA373 and OPA374 families of operational
amplifiers are low power and low cost with excellent
bandwidth (6.5MHz) and slew rate (5V/µs). The input
range extends 200mV beyond the rails and the output
range is within 25mV of the rails. The speed/power ratio
and small size make them ideal for portable and
battery-powered applications.
D
D
D
D
D
D
D
LOW I : 10pA (max)
B
HIGH BANDWIDTH: 6.5MHz
RAIL-TO-RAIL INPUT AND OUTPUT
SINGLE SUPPLY: +2.3V to +5.5V
SHUTDOWN: OPAx373
SPECIFIED UP TO +125°C
MicroSIZE PACKAGES: SOT23-5, SOT23-6,
The OPA373 family includes a shutdown mode. Under
logic control, the amplifiers can be switched from normal
operation to a standby current that is less than 1µA.
SOT23-8 and DFN-10
AD PPLICATIONS
PORTABLE EQUIPMENT
The OPA373 and OPA374 families of operational
amplifiers are specified for single or dual power supplies
of +2.7V to +5.5V, with operation from +2.3V to +5.5V. All
models are specified for −40°C to +125°C.
D
D
D
BATTERY-POWERED DEVICES
ACTIVE FILTERS
DRIVING A/D CONVERTERS
OPA374
OPA373
OPA2373
Out
1
2
3
5
4
V+
Out
1
2
3
6
5
4
V+
OUT A
1
2
3
4
5
10 V+
−
V
−
V
Enable
−
IN A
+IN A
9
8
7
6
OUT B
A
−
+IN
IN
−
+IN
IN
−
IN B
B
−
V
+IN B
SOT23−6(1)
SOT23−5
Enable A
Enable B
OPA2373
OPA373
MSOP−10
V+
OUT A
NC(2)
1
2
3
4
8
7
6
5
Enable
Exposed
thermal
die pad on
underside
(Must be
OUT B
IN A
−
OPA4374
V+
−
IN
IN B
−
+IN A
OUT
NC(2)
+IN
OUT A
1
2
3
4
5
6
7
14 OUT D
+IN B
V
−
connected to V )
−
−
V
−
−
IN D
IN A
13
Enable B
Enable A
D
C
A
B
+IN A
V+
12 +IN D
SO−8
DFN−10
−
V
11
OPA374
OPA2374
+IN B
10 +IN C
NC(2)
V+
NC(2)
1
8
OUT A
1
2
3
4
8
7
6
5
V+
−
−
IN B
9
8
IN C
A
−
−
IN A
OUT B
IN
2
3
4
7
6
5
OUT B
OUT C
B
OUT
NC(2)
−
+IN A
IN B
+IN B
+IN
SO−14, TSSOP−14
−
V
−
V
SO−8, SOT23−8
SO−8
(1)
(2)
Pin 1 of the SOT23-6 is determined by orienting the package marking as shown.
NC indicates no internal connection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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Copyright 2003-2008, Texas Instruments Incorporated
www.ti.com
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
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PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
Shutdown
OPA373
SOT23-6
DBV
−40°C to +125°C
A75
OPA373AIDBVT
Tape and Reel, 250
″
″
″
″
″
OPA373AIDBVR Tape and Reel, 3000
OPA373
SO-8
D
−40°C to +125°C
OPA373A
OPA373AID
Rails, 100
″
″
″
DGS
″
DRC
″
″
″
OPA373AIDR
Tape and Reel, 2500
OPA2373
MSOP-10
−40°C to +125°C
AYO
OPA2373AIDGST Tape and Reel, 250
OPA2373AIDGSR Tape and Reel, 2500
OPA2373AIDRCT Tape and Reel, 250
OPA2373AIDRCR Tape and Reel, 3000
″
″
DFN-10
″
″
″
OCEQ
″
OPA2373
−40°C to +125°C
″
″
Non-Shutdown
OPA374
SOT23-5
DBV
−40°C to +125°C
A76
OPA374AIDBVT
Tape and Reel, 250
″
″
″
″
″
OPA374AIDBVR Tape and Reel, 3000
OPA374
SO-8
D
−40°C to +125°C
OPA274A
OPA374AID
Rails, 100
″
″
″
″
″
OPA374AIDR
Tape and Reel, 2500
OPA2374
SOT23-8
DCN
−40°C to +125°C
ATP
″
OPA2374A
OPA2374AIDCNT Tape and Reel, 250
OPA2374AIDCNR Tape and Reel, 3000
″
″
″
D
″
″
OPA2374
SO-8
″
SO-14
−40°C to +125°C
OPA2374AID
OPA2374AIDR
OPA4374AID
Rails, 100
Tape and Reel, 2500
Rails, 58
″
″
″
OPA4374
D
−40°C to +125°C
OPA4374A
″
″
″
PW
″
″
″
OPA4374AIDR
OPA4374AIPWT
OPA4374AIPWR Tape and Reel, 2500
Tape and Reel, 2500
Tape and Reel, 250
OPA4374
TSSOP-14
−40°C to +125°C
OPA4374A
″
″
″
″
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet.
(1)
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
(2)
Signal Input Terminals, Voltage
. . . . . . . . . −0.5V to (V+) + 0.5V
. . . . . . . . . . . . . . . . . . . 10mA
proper handling and installation procedures can cause damage.
(2)
Current
(3)
Output Short-Circuit
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
. . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2)
(3)
Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails should be current-limited to 10mA or less.
Short-circuit to ground, one amplifier per package.
2
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: V = +2.7V to +5.5V
S
Boldface limits apply over the specified temperature range, T = −40°C to +125°C.
A
At T = +25°C, R = 10kΩ connected to V /2, and V
= V /2, unless otherwise noted.
A
L
S
OUT
S
OPA373, OPA2373, OPA374,
OPA2374, OPA4374
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
OFFSET VOLTAGE
Input Offset Voltage
over Temperature
Drift
V
V
= 5V
S
1
5
mV
mV
OS
6.5
dV /dT
OS
3
µV/°C
µV/V
µV/V
µV/V
dB
vs Power Supply
over Temperature
Channel Separation, DC
PSRR
V
= 2.7V to 5.5V, V
< (V+) − 2V
25
100
S
CM
V
= 2.7V to 5.5V, V
< (V+) − 2V
150
S
CM
0.4
f = 1kHz
128
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
over Temperature
V
(V−) − 0.2
(V+) + 0.2
V
CM
CMRR
(V−) − 0.2V < V
< (V+) − 2V
80
70
66
60
90
dB
dB
dB
dB
CM
(V−) − 0.2V < V
< (V+) − 2V
CM
V
= 5.5V, (V−) − 0.2V < V
< (V+) + 0.2V
S
CM
over Temperature
V
= 5.5V, (V−) − 0.2V < V
< (V+) + 0.2V
S
CM
INPUT BIAS CURRENT
Input Bias Current
I
0.5
0.5
10
10
pA
pA
B
Input Offset Current
I
OS
INPUT IMPEDANCE
Differential
13
10 3
Ω pF
Ω pF
13
Common-Mode
10 6
NOISE
V
< (V+) − 2V
CM
Input Voltage Noise, f = 0.1Hz to 10Hz
Input Voltage Noise Density, f = 10kHz
Input Current Noise Density, f = 10kHz
10
15
4
µV
nV/√Hz
fA/√Hz
PP
e
n
i
n
OPEN-LOOP GAIN
Open-Loop Voltage Gain
over Temperature
A
V
= 5V, R = 100kΩ, 0.025V < V < 4.975V
94
80
94
80
110
106
dB
dB
dB
dB
OL
S
L
O
V
= 5V, R = 100kΩ, 0.025V < V < 4.975V
S
L O
V
= 5V, R = 5kΩ, 0.125V < V < 4.875V
L O
S
over Temperature
V
= 5V, R = 5kΩ, 0.125V < V < 4.875V
S
L O
OUTPUT
Voltage Output Swing from Rail
over Temperature
R
= 100kΩ
= 100kΩ
= 5kΩ
18
25
25
mV
mV
mV
mV
L
R
L
R
100
125
125
L
over Temperature
Short-Circuit Current
R
= 5kΩ
L
I
See Typical Characteristics
See Typical Characteristics
220
SC
Capacitive Load Drive
Open-Loop Output Impedance
C
LOAD
f = 1MHz, I = 0
Ω
O
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
C = 100pF
L
GBW
SR
6.5
5
MHz
V/µs
µs
µs
µs
G = +1
Settling Time, 0.1%
0.01%
t
V
V
= 5V, 2V Step, G = +1
= 5V, 2V Step, G = +1
1
S
S
S
1.5
0.3
0.0013
Overload Recovery Time
Total Harmonic Distortion + Noise
V
• Gain > V
IN
S
THD+N
V
= 5V, V = 3V , G = +1, f = 1kHz
%
S
O
PP
ENABLE/SHUTDOWN
t
3
µs
µs
V
OFF
t
12
ON
V
V
(shutdown)
V−
(V−) + 0.8
L
(amplifier is active)
(V−) + 2
V+
V
H
Input Bias Current of Enable Pin
(per amplifier)
0.2
µA
µA
I
< 0.5
1
QSD
3
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
www.ti.com
ELECTRICAL CHARACTERISTICS: V = +2.7V to +5.5V (continued)
S
Boldface limits apply over the specified temperature range, T = −40°C to +125°C.
A
At T = +25°C, R = 10kΩ connected to V /2, and V
= V /2, unless otherwise noted.
A
L
S
OUT
S
OPA373, OPA2373, OPA374,
OPA2374, OPA4374
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
POWER SUPPLY
Specified Voltage Range
Operating Voltage Range
Quiescent Current (per amplifier)
over Temperature
V
I
2.7
5.5
V
V
S
2.3 to 5.5
585
I
= 0
O
750
µA
µA
Q
800
TEMPERATURE RANGE
Specified Range
−40
−55
−65
+125
+150
+150
°C
°C
°C
Operating Range
Storage Range
Thermal Resistance
SOT23-5, SOT23-6, SOT23-8
MSOP-10, SO-8
q
JA
°C/W
°C/W
°C/W
°C/W
°C/W
200
150
100
56
SO-14, TSSOP-14
DFN-10
JEDEC High-K Board
4
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
TYPICAL CHARACTERISTICS
At T = +25°C, R = 10kΩ connected to V /2, and V
OUT
= V /2, unless otherwise noted.
S
A
L
S
POWER−SUPPLY AND COMMON−MODE
REJECTION RATIO vs FREQUENCY
120
100
OPEN−LOOP GAIN AND PHASE vs FREQUENCY
Gain
120
30
0
100
80
60
40
20
0
CMRR
80
−30
PSRR
−60
60
−90
Phase
40
−120
20
−
150
0
−20
−180
10M
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
TOTAL HARMONIC DISTORTION+NOISE
vs FREQUENCY
INPUT VOLTAGE NOISE
SPECTRAL DENSITY vs FREQUENCY
0.100
1000
Ω
RL = 5k
G = 10V/V
0.010
0.001
100
G = 1V/V
10k
10
10
100
1k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
OPEN−LOOP GAIN AND POWER−SUPPLY
REJECTION RATIO vs TEMPERATURE
COMMON−MODE REJECTION RATIO vs TEMPERATURE
VS = 5.5V
120
110
100
90
130
120
110
100
90
Ω
RL = 100k
−
= 0.2V to 3.5V
VCM
Ω
RL = 5k
80
−
= 0.2V to 5.7V
VCM
70
PSRR
60
50
40
80
−
−
−
−
25
50
25
50
0
25
50
75
100
125
150
0
25
50
75
100
125
150
_
_
Temperature ( C)
Temperature ( C)
5
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C, R = 10kΩ connected to V /2, and V
OUT
= V /2, unless otherwise noted.
S
A
L
S
QUIESCENT CURRENT vs SUPPLY VOLTAGE
QUIESCENT CURRENT vs TEMPERATURE
800
700
600
500
400
300
800
−
−
VOUT = 1/2[(V+) (V )]
700
600
500
400
300
−
−
25
50
0
25
50
75
100
125
150
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
_
Temperature ( C)
Supply Voltage (V)
CONTINUOUS SHORT−CIRCUIT CURRENT vs
POWER−SUPPLY VOLTAGE
SHORT−CIRCUIT CURRENT vs TEMPERATURE
+ISC
12
10
8
16
14
12
10
8
+ISC
−
ISC
6
−
ISC
6
4
4
2
2
0
0
−
−
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
25
0
25
50
75
100
125
_
Power−Supply Voltage (V)
Temperature ( C)
INPUT BIAS CURRENT vs TEMPERATURE
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
3
2
1
0
10k
1k
100
10
−
−
−
1
1
−
_
55 C
2
3
_
25 C
_
150 C
0.1
−
−
25
50
0
25
50
75
100
125
0
2
4
6
8
10
12
14
16
18
20
_
Temperature ( C)
Output Current (mA)
6
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
TYPICAL CHARACTERISTICS (continued)
At T = +25°C, R = 10kΩ connected to V /2, and V
OUT
= V /2, unless otherwise noted.
S
A
L
S
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
VS = 5.5V
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
6
5
4
3
2
1
0
VS = 5V
VS = 2.5V
10k
100k
1M
10M
−
−
−
−
−
1
5
4
3
2
0
1
2
3
4
5 5.5
Frequency (Hz)
Offset Voltage (mV)
OFFSET VOLTAGE DRIFT MAGNITUDE
PRODUCTION DISTRIBUTION
SMALL−SIGNAL STEP RESPONSE
CL = 100pF
Typical production distribution
of packaged units.
200ns/div
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
µ
_
Offset Voltage Drift ( V/ C)
LARGE−SIGNAL STEP RESPONSE
CL = 100pF
SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE
60
50
40
30
20
10
0
Refer to the Capacitive Load
and Stability section for tips
on improving performance.
G = +1V/V
G = 10V/V
Ω
RFB = 10k
400ns/div
10
100
1k
10k
Load Capacitance (pF)
7
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At T = +25°C, R = 10kΩ connected to V /2, and V
OUT
= V /2, unless otherwise noted.
S
A
L
S
CHANNEL SEPARATION vs FREQUENCY
SETTLING TIME vs CLOSED−LOOP GAIN
100
10
1
140
120
100
80
G = +1V/V, All Channels
RL = 5kΩ
0.01%
0.1%
60
40
20
0.1
0
1
10
100
10
100
1K
10K
100K
1M
10M
100M
Frequency (Hz)
Closed−Loop Gain (V/V)
8
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
APPLICATIONS
2.0
1.5
1.0
0.5
0
The OPA373 and OPA374 series op amps are unity-gain
stable and suitable for a wide range of general-purpose
applications. Rail-to-rail input and output make them ideal
for driving sampling Analog-to-Digital Converters (ADCs).
Excellent ac performance makes them well-suited for
audio applications. The class AB output stage is capable
of driving 100kΩ loads connected to any point between V+
and ground.
−
−
−
−
0.5
1.0
1.5
2.0
−
The input common-mode voltage range includes both
rails, allowing the OPA373 and OPA374 series op amps to
be used in virtually any single-supply application up to a
supply voltage of +5.5V.
V
V+
−
0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common−Mode Voltage (V)
Figure 1. Behavior of Typical Transition Region at
Room Temperature
Rail-to-rail input and output swing significantly increases
dynamic range, especially in low-supply applications.
Power-supply pins should be bypassed with 0.01µF
ceramic capacitors.
RAIL-TO-RAIL INPUT
The input common-mode range extends from (V−) − 0.2V
to (V+) + 0.2V. For normal operation, inputs should be
limited to this range. The absolute maximum input voltage
is 500mV beyond the supplies. Inputs greater than the
input common-mode range but less than the maximum
input voltage, while not valid, will not cause any damage
to the op amp. Unlike some other op amps, if input current
is limited, the inputs may go beyond the supplies without
phase inversion, as shown in Figure 2.
OPERATING VOLTAGE
The OPA373 and OPA374 op amps are specified and
tested over a power-supply range of +2.7V to +5.5V
( 1.35V to 2.75V). However, the supply voltage may
range from +2.3V to +5.5V ( 1.15V to 2.75V). Supply
voltages higher than 7.0V (absolute maximum) can
permanently damage the amplifier. Parameters that vary
over supply voltage or temperature are shown in the
Typical Characteristics section of this data sheet.
G = +1V/V, VS = 5V
VIN
COMMON-MODE VOLTAGE RANGE
5V
VOUT
The input common-mode voltage range of the OPA373
and OPA374 series extends 200mV beyond the supply
rails. This is achieved with a complementary input
stage—an N-channel input differential pair in parallel with
a P-channel differential pair. The N-channel pair is active
for input voltages close to the positive rail, typically
(V+) − 1.65V to 200mV above the positive supply, while
the P-channel pair is on for inputs from 200mV below the
negative supply to approximately (V+) − 1.65V. There is a
500mV transition region, typically (V+) − 1.9V to
(V+) − 1.4V, in which both pairs are on. This 500mV
transition region, shown in Figure 1, can vary 300mV with
process variation. Thus, the transition region (both stages
on) can range from (V+) − 2.2V to (V+) − 1.7V on the low
end, up to (V+) − 1.6V to (V+) − 1.1V on the high end.
Within the 500mV transition region PSRR, CMRR, offset
voltage, offset drift, and THD may be degraded compared
to operation outside this region.
0V
µ
1 s/div
Figure 2. OPA373: No Phase Inversion with
Inputs Greater Than the Power-Supply Voltage
Normally, input bias current is approximately 500fA;
however, input voltages exceeding the power supplies by
more than 500mV can cause excessive current to flow in
or out of the input pins. Momentary voltages greater than
500mV beyond the power supply can be tolerated if the
current on the input pins is limited to 10mA. This is easily
accomplished with an input resistor; see Figure 3. (Many
input signals are inherently current-limited to less than
10mA, therefore, a limiting resistor is not required.)
9
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
www.ti.com
capacitor, CFB, can be inserted in the feedback, as shown
in Figure 5. This significantly reduces overshoot by
compensating the effect of capacitance, CIN, which
includes the amplifier input capacitance and printed circuit
board (PCP) parasitic capacitance.
V+
IOVERLOAD
10mA max
VOUT
OPA373
R
VIN
V+
RS
Ω
Ω
10 to 20
Figure 3. Input Current Protection for Voltages
Exceeding the Supply Voltage
OPA373
VOUT
VIN
RL
CL
RAIL-TO-RAIL OUTPUT
A class AB output stage with common-source transistors
is used to achieve rail-to-rail output. For light resistive
loads ( > 100kΩ), the output voltage can typically swing to
within 18mV from the supply rails. With moderate resistive
loads (5kΩ to 50kΩ), the output can typically swing to
within 100mV from the supply rails and maintain high
open-loop gain. See the Typical Characteristic curve,
Output Voltage Swing vs Output Current, for more
information.
Figure 4. Series Resistor in Unity-Gain
Configuration Improves Capacitive Load Drive
CFB
RF
CAPACITIVE LOAD AND STABILITY
V+
OPA373 series op amps can drive a wide range of
capacitive loads. However, under certain conditions, all op
amps may become unstable. Op amp configuration, gain,
and load value are just a few of the factors to consider
when determining stability. An op amp in unity-gain
configuration is the most susceptible to the effects of
capacitive load. The capacitive load reacts with the op amp
output resistance, along with any additional load
resistance, to create a pole in the small-signal response
that degrades the phase margin. The OPA373 series op
amps perform well in unity-gain configuration, with a pure
capacitive load up to approximately 250pF. Increased
gains allow the amplifier to drive more capacitance. See
the Typical Characteristics curve, Small-Signal Overshoot
vs Capacitive Load, for further details.
RI
VIN
VOUT
OPA373
CIN
CL
Figure 5. Improving Capacitive Load Drive
For example, when driving a 100pF load in unity-gain
inverter configuration, adding a 6pF capacitor in parallel
with the 10kΩ feedback resistor decreases overshoot from
57% to 12%, as shown in Figure 6.
60
One method of improving capacitive load drive in the
unity-gain configuration is to insert a small (10Ω to 20Ω)
resistor, RS, in series with the output, as shown in Figure 4.
This significantly reduces ringing while maintaining dc
performance for purely capacitive loads. When there is a
resistive load in parallel with the capacitive load, RS must
be placed within the feedback loop as shown to allow the
feedback loop to compensate for the voltage divider
created by RS and RL.
−
G = 1V/V
Ω
RFB = 10k
50
40
30
20
10
0
CFB = 6pF
In unity-gain inverter configuration, phase margin can be
reduced by the reaction between the capacitance at the op
amp input and the gain setting resistors, thus degrading
capacitive load drive. Best performance is achieved by
using small valued resistors. However, when large valued
resistors cannot be avoided, a small (4pF to 6pF)
10
100
1k
10k
Load Capacitance (pF)
Figure 6. Improving Capacitive Load Drive
10
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
Figure 8 shows the OPA373 driving the ADS7816 in a
speech band-pass filtered data acquisition system. This
small, low-cost solution provides the necessary
amplification and signal conditioning to interface directly
with an electret microphone. This circuit will operate with
VS = 2.7V to 5V.
DRIVING ADCs
The OPA373 and OPA374 series op amps are optimized
for driving medium-speed sampling ADCs. The OPA373
and OPA374 op amps buffer the ADC input capacitance
and resulting charge injection, while providing signal gain.
The OPA373 is shown driving the ADS7816 in a basic
noninverting configuration, as shown in Figure 7. The
ADS7816 is a 12-bit, MicroPower sampling converter in
the MSOP-8 package. When used with the low-power,
miniature packages of the OPA373, the combination is
ideal for space-limited, low-power applications. In this
configuration, an RC network at the ADC input can be used
to provide anti-aliasing filtering.
The OPA373 is shown in the inverting configuration
described in Figure 9. In this configuration, filtering may be
accomplished with the capacitor across the feedback
resistor.
ENABLE/SHUTDOWN
OPA373 and OPA374 series op amps typically require
585µA quiescent current. The enable/shutdown feature of
the OPA373 allows the op amp to be shut off in order to
reduce this current to less than 1µA.
+5V
µ
µ
0.1 F
0.1 F
1
VREF
8
V+
7
6
5
DCLOCK
DOUT
Ω
500
+In
2
Serial
Interface
ADS7816
12−Bit ADC
OPA373
VIN
−
In
CS/SHDN
3300pF
3
GND
4
VIN = 0V to 5V for
0V to 5V output.
fSAMPLE = 100kHz
NOTE: ADC Input = 0 to VREF
RC network filters high frequency noise.
Figure 7. The OPA373 in Noninverting Configuration Driving the ADS7816
V+ = +2.7V to +5V
Passband 300Hz to 3kHz
R9
Ω
510k
R1
R4
R2
Ω
Ω
1.5k
20k
Ω
Ω
1M
C3
C
33pF
1
1000pF
R7
R8
150k
V+
8
1
VREF
Ω
Ω
51k
1/2
7
6
DCLOCK
DOUT
OPA2373
+IN
2
R3
1/2
ADS7816
12−Bit ADC
Electret
Microphone(1)
Serial
Interface
C2
OPA2373
1M
R6
5
CS/SHDN
−
IN
1000pF
Ω
100k
3
4
GND
G = 100
NOTE: (1) Electret microphone
powered by R1.
R5
Ω
20k
Figure 8. The OPA2373 as a Speech Bypass Filtered Data Acquisition System
11
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
www.ti.com
+5V
330pF
µ
µ
0.1 F
0.1 F
Ω
Ω
5k
5k
VIN
1
VREF
8
V+
7
6
5
DCLOCK
DOUT
Ω
500k
+IN
2
ADS7816
12−Bit ADC
Serial
Interface
OPA373
VS
2
−
IN
3
CS/SHDN
3300pF
GND
4
NOTE: ADC Input = 0 to VREF
Figure 9. The OPA373 in Inverting Configuration Driving the ADS7816
C3
330pF
R2
R3
Ω
Ω
2.72k
21.4k
R1
1/2
Ω
11.7k
OPA373
1/2
OPA373
C1
680pF
C2
330pF
NOTE: FilterPro is a low-pass filter design program available for download at
no cost from TI’s web site (www.ti.com). The program can be used to determine
component values for other cutoff frequencies or filter types.
Figure 10. Three-Pole Sallen-Key Butterworth Low-Pass Filter
12
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SBOS279E − SEPTEMBER 2003 − REVISED MAY 2008
DFN PACKAGE
LAYOUT GUIDELINES
The OPA2373 is available in a DFN-10 package (also
known as SON), which is a QFN package with lead
contacts on only two sides of the bottom of the package.
This leadless, near-chip-scale package maximizes board
space and enhances thermal and electrical characteristics
through an exposed pad. DFN packages are physically
small, have a smaller routing area, improved thermal
performance, and improved electrical parasitics, with a
pinout scheme that is consistent with other
commonly-used packages, such as SO and MSOP.
Additionally, the absence of external leads eliminates
bent-lead issues.
The leadframe die pad should be soldered to a thermal pad
on the PCB. A mechanical data sheet showing an example
layout is attached at the end of this data sheet.
Refinements to this layout may be required based on
assembly process requirements.
Mechanical drawings located at the end of this data sheet
list the physical dimensions for the package and pad. The
five holes in the landing pattern are optional, and are
intended for use with thermal vias that connect the
leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests.
The DFN package can be easily mounted using standard
PCP assembly techniques. See Application Note,
QFN/SON PCB Attachment (SLUA271) and Application
Report, Quad Flatpack No-Lead Logic Packages
(SCBA017), both available for download at www.ti.com.
Even with applications that have low-power dissipation,
the exposed pad must be soldered to the PCB to provide
structural integrity and long-term reliability.
The exposed leadframe die pad on the bottom of the
package should be connected to V−.
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
OPA2373AIDGSR
OPA2373AIDGST
OPA2373AIDRCR
OPA2373AIDRCRG4
OPA2373AIDRCT
OPA2374AID
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSSOP
VSSOP
SON
DGS
10
10
10
10
10
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
AYO
AYO
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGS
DRC
DRC
DRC
D
250
3000
3000
250
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OCEQ
OCEQ
OCEQ
SON
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
SOIC
75
Green (RoHS
& no Sb/Br)
OPA
2374A
OPA2374AIDCNR
OPA2374AIDCNRG4
OPA2374AIDCNT
OPA2374AIDCNTG4
OPA2374AIDG4
OPA2374AIDR
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DCN
DCN
DCN
DCN
D
8
3000
3000
250
Green (RoHS
& no Sb/Br)
ATP
ATP
ATP
ATP
8
Green (RoHS
& no Sb/Br)
8
Green (RoHS
& no Sb/Br)
8
250
Green (RoHS
& no Sb/Br)
8
75
Green (RoHS
& no Sb/Br)
OPA
2374A
SOIC
D
8
2500
2500
75
Green (RoHS
& no Sb/Br)
OPA
2374A
OPA2374AIDRG4
OPA373AID
SOIC
D
8
Green (RoHS
& no Sb/Br)
OPA
2374A
SOIC
D
8
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA
373A
OPA373AIDBVR
OPA373AIDBVRG4
OPA373AIDBVT
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
6
3000
3000
250
Green (RoHS
& no Sb/Br)
A75
A75
A75
6
Green (RoHS
& no Sb/Br)
6
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OPA373AIDBVTG4
OPA373AIDG4
OPA373AIDR
ACTIVE
SOT-23
SOIC
DBV
6
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
A75
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
Green (RoHS
& no Sb/Br)
OPA
373A
SOIC
8
2500
2500
75
Green (RoHS
& no Sb/Br)
OPA
373A
OPA373AIDRG4
OPA374AID
SOIC
D
8
Green (RoHS
& no Sb/Br)
OPA
373A
SOIC
D
8
Green (RoHS
& no Sb/Br)
OPA
374A
OPA374AIDBVR
OPA374AIDBVRG4
OPA374AIDBVT
OPA374AIDBVTG4
OPA374AIDG4
OPA374AIDR
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
5
3000
3000
250
Green (RoHS
& no Sb/Br)
A76
A76
A76
A76
5
Green (RoHS
& no Sb/Br)
5
Green (RoHS
& no Sb/Br)
5
250
Green (RoHS
& no Sb/Br)
8
75
Green (RoHS
& no Sb/Br)
OPA
374A
SOIC
D
8
2500
2500
50
Green (RoHS
& no Sb/Br)
OPA
374A
OPA374AIDRG4
OPA4374AID
SOIC
D
8
Green (RoHS
& no Sb/Br)
OPA
374A
SOIC
D
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
OPA4374A
OPA4374A
OPA4374A
OPA4374A
OPA4374AIDG4
OPA4374AIDR
OPA4374AIDRG4
OPA4374AIPWR
OPA4374AIPWRG4
SOIC
D
50
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
PW
PW
Green (RoHS
& no Sb/Br)
OPA
4374A
Green (RoHS
& no Sb/Br)
OPA
4374A
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OPA4374AIPWT
ACTIVE
TSSOP
TSSOP
PW
14
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA
4374A
OPA4374AIPWTG4
ACTIVE
PW
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
4374A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2373AIDGSR
OPA2373AIDGST
OPA2373AIDRCR
OPA2373AIDRCT
OPA2374AIDCNR
OPA2374AIDCNT
OPA2374AIDR
VSSOP
VSSOP
SON
DGS
DGS
DRC
DRC
DCN
DCN
D
10
10
10
10
8
2500
250
330.0
180.0
330.0
180.0
180.0
180.0
330.0
330.0
178.0
178.0
330.0
330.0
330.0
180.0
12.4
12.4
12.4
12.4
8.4
5.3
5.3
3.3
3.3
3.2
3.2
6.4
6.4
3.3
3.3
6.4
6.5
6.9
6.9
3.4
3.4
3.3
3.3
3.1
3.1
5.2
5.2
3.2
3.2
5.2
9.0
5.6
5.6
1.4
1.4
1.1
1.1
1.39
1.39
2.1
2.1
1.4
1.4
2.1
2.1
1.6
1.6
8.0
8.0
8.0
8.0
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q2
Q2
Q3
Q3
Q1
Q1
Q3
Q3
Q1
Q1
Q1
Q1
3000
250
SON
SOT-23
SOT-23
SOIC
3000
250
8
8.4
8.0
8
2500
2500
3000
250
12.4
12.4
8.4
12.0
12.0
8.0
OPA373AIDR
SOIC
D
8
OPA374AIDBVR
OPA374AIDBVT
OPA374AIDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8.4
8.0
8
2500
2500
2500
250
12.4
16.4
12.4
12.4
12.0
16.0
12.0
12.0
OPA4374AIDR
SOIC
D
14
14
14
OPA4374AIPWR
OPA4374AIPWT
TSSOP
TSSOP
PW
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2373AIDGSR
OPA2373AIDGST
OPA2373AIDRCR
OPA2373AIDRCT
OPA2374AIDCNR
OPA2374AIDCNT
OPA2374AIDR
VSSOP
VSSOP
SON
DGS
DGS
DRC
DRC
DCN
DCN
D
10
10
10
10
8
2500
250
367.0
210.0
367.0
210.0
210.0
210.0
367.0
367.0
565.0
565.0
367.0
367.0
367.0
210.0
367.0
185.0
367.0
185.0
185.0
185.0
367.0
367.0
140.0
140.0
367.0
367.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
75.0
75.0
35.0
38.0
35.0
35.0
3000
250
SON
SOT-23
SOT-23
SOIC
3000
250
8
8
2500
2500
3000
250
OPA373AIDR
SOIC
D
8
OPA374AIDBVR
OPA374AIDBVT
OPA374AIDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
2500
2500
2500
250
OPA4374AIDR
SOIC
D
14
14
14
OPA4374AIPWR
OPA4374AIPWT
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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Applications
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www.dlp.com
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DLP® Products
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Copyright © 2014, Texas Instruments Incorporated
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