OPA2387DGKT [TI]

OPA2387 Ultra-High Precision, Zero-Drift, Low-Input-Bias-Current Op Amps;
OPA2387DGKT
型号: OPA2387DGKT
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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OPA2387 Ultra-High Precision, Zero-Drift, Low-Input-Bias-Current Op Amps

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OPA2387
SBOS984A – NOVEMBER 2020 – REVISED DECEMBER 2020  
OPA2387 Ultra-High Precision, Zero-Drift, Low-Input-Bias-Current Op Amps  
1 Features  
3 Description  
Ultra-low offset voltage: ±2 µV (maximum, tested)  
Zero drift: ±0.003 µV/°C  
The OPA387, OPA2387, and OPA4387 (OPAx387)  
family of precision amplifiers offers state-of-the-art  
performance. With zero-drift technology, the OPAx387  
offset voltage and offset drift provide unparalleled  
long-term stability. With a mere 570 µA of quiescent  
current, the OPAx387 are able to achieve 5.7 MHz of  
bandwidth, a broadband noise of 8.5 nV/√Hz, and a  
1/f noise at 177 nVPP. These specifications are crucial  
to achieve extremely-high precision and no  
degradation of linearity in 16-bit to 24-bit analog to  
digital converters (ADCs). The OPAx387 feature flat  
bias current over temperature; therefore, little to no  
calibration is needed in high input impedance  
applications over temperature.  
Low-input bias current: 135 pA (maximum, tested)  
Low noise: 8.5 nV√Hz at 1 kHz  
No 1/f noise: 177 nVPP (0.1 Hz to 10 Hz)  
Common-mode input range ±100 mV beyond  
supply rails  
Gain bandwidth: 5.7 MHz  
Quiescent current: 570 μA per amplifier  
Single supply: 1.7 V to 5.5 V  
Dual supply: ±0.85 V to ±2.75 V  
EMI/RFI filtered inputs  
2 Applications  
All versions are specified over the industrial  
temperature range of –40°C to +125°C.  
Electronic thermometer  
Weigh scale  
Temperature transmitter  
Ventilators  
Data acquisition (DAQ)  
Semiconductor test  
Lab and field instrumentation  
Merchant network and server PSU  
Analog input module  
Pressure transmitter  
Device Information  
PART NUMBER  
PACKAGE(1)  
BODY SIZE (NOM)  
2.90 mm × 1.60 mm  
1.50 mm × 1.50 mm  
4.90 mm × 3.90 mm  
3.00 mm × 3.00 mm  
2.00 mm × 2.00 mm  
5.00 mm × 4.40 mm  
SOT-23 (5)(3)  
OPA387(2)  
DFN (6)(3)  
SOIC (8)(3)  
VSSOP (8)  
DFN (8)(3)  
OPA2387  
OPA4387(2)  
TSSOP (14)(3)  
(1) For all available packages, see the package option  
addendum at the end of the data sheet.  
(2) Device is preview.  
(3) Package is preview.  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
ADC  
OPA387  
Radiation  
Detector  
OPA387 as an Ultra-Low Offset, Low-Noise ADC  
Driver  
0
-2  
-1.5  
-1  
-0.5  
0
0.5  
1
1.5  
2
Input Offset Voltage (mV)  
c110  
Ultra-Low Input Offset Voltage  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
 
OPA2387  
www.ti.com  
SBOS984A – NOVEMBER 2020 – REVISED DECEMBER 2020  
Table of Contents  
1 Features............................................................................1  
2 Applications.....................................................................1  
3 Description.......................................................................1  
4 Revision History.............................................................. 2  
5 Pin Configuration and Functions...................................3  
6 Specifications.................................................................. 4  
6.1 Absolute Maximum Ratings ....................................... 4  
6.2 ESD Ratings .............................................................. 4  
6.3 Recommended Operating Conditions ........................4  
6.4 Thermal Information ...................................................4  
6.5 Electrical Characteristics ............................................5  
6.6 Typical Characteristics................................................7  
7 Detailed Description......................................................12  
7.1 Overview...................................................................12  
7.2 Functional Block Diagram.........................................12  
7.3 Feature Description...................................................13  
7.4 Device Functional Modes..........................................13  
8 Application and Implementation..................................14  
8.1 Application Information............................................. 14  
8.2 Typical Applications.................................................. 14  
9 Power Supply Recommendations................................17  
10 Layout...........................................................................17  
10.1 Layout Guidelines................................................... 17  
10.2 Layout Example...................................................... 17  
11 Device and Documentation Support..........................18  
11.1 Device Support........................................................18  
11.2 Documentation Support.......................................... 18  
11.3 Receiving Notification of Documentation Updates..18  
11.4 Support Resources................................................. 18  
11.5 Trademarks............................................................. 18  
11.6 Electrostatic Discharge Caution..............................18  
11.7 Glossary..................................................................18  
12 Mechanical, Packaging, and Orderable  
Information.................................................................... 19  
4 Revision History  
Changes from Revision * (November 2020) to Revision A (December 2020)  
Page  
Changed OPA2387 from advanced information (preview) to production data (active).......................................1  
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SBOS984A – NOVEMBER 2020 – REVISED DECEMBER 2020  
5 Pin Configuration and Functions  
OUT A  
œIN A  
+IN A  
Vœ  
1
2
3
4
8
7
6
5
V+  
OUT B  
œIN B  
+IN B  
Not to scale  
Figure 5-1. DGK Package, 8-Pin VSSOP, Top View  
Table 5-1. Pin Functions  
PIN  
I/O  
DESCRIPTION  
NAME  
NO.  
2
–IN A  
–IN B  
+IN A  
+IN B  
I
I
Inverting input, channel A  
Inverting input, channel B  
Noninverting input, channel A  
Noninverting input, channel B  
Output, channel A  
6
3
I
5
I
OUT A  
OUT B  
V–  
1
O
O
7
Output, channel B  
4
Negative (lowest) power supply  
Positive (highest) power supply  
V+  
8
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SBOS984A – NOVEMBER 2020 – REVISED DECEMBER 2020  
6 Specifications  
6.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
MAX  
UNIT  
Single-supply  
6
VS  
Supply Voltage, VS = (V+) – (V–)  
Input voltage, all pins  
V
Dual-supply  
Common-mode  
Differential  
±3  
(V+) + 0.5  
(V+) – (V–) + 0.2  
±10  
(V–) – 0.5  
V
Input current, all pins  
Output short circuit(2)  
Operating temperature  
Junction temperature  
Storage temperature  
mA  
Continuous  
–55  
Continuous  
150  
TA  
°C  
°C  
°C  
TJ  
–55  
150  
Tstg  
–65  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under  
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device  
reliability.  
(2) Short-circuit to ground, one amplifier per package.  
6.2 ESD Ratings  
VALUE  
±3000  
±1000  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
6.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
1.7  
NOM  
MAX  
5.5  
UNIT  
V
Single-supply  
Dual-supply  
VS  
TA  
Supply voltage, VS = (V+) – (V–)  
Specified temperature  
±0.85  
–40  
±2.75  
125  
°C  
6.4 Thermal Information  
OPA2387  
THERMAL METRIC(1)  
DGK (VSSOP)  
UNIT  
8 PINS  
165  
53  
RθJA  
Junction-to-ambient thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
87  
ΨJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
4.9  
ΨJB  
85  
RθJC(bot)  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
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SBOS984A – NOVEMBER 2020 – REVISED DECEMBER 2020  
6.5 Electrical Characteristics  
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VS = 1.7 V to 5.5 V, VCM = VS / 2, VOUT = VS / 2, and min and max specification  
established from manufacturing final test (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OFFSET VOLTAGE  
VS = 5.5 V  
±1  
±1.5  
±2  
TA = –40°C to +125°C(1)  
VS = 5.5 V  
±0.25  
±0.35  
VOS  
Input offset voltage  
µV  
VS = 1.7 V  
±2.5  
±2  
VCM = (V–) – 0.1(1)  
VCM = (V+) + 0.1(1)  
±2  
dVOS/dT  
PSRR  
Input offset voltage drift TA = –40°C to +125°C(1)  
±0.003  
±0.05  
±0.012  
±0.35  
±1  
μV/°C  
μV/V  
Power supply rejection  
VS = 1.7 V to 5.5 V  
ratio  
TA = –40°C to +125°C(1)  
INPUT BIAS CURRENT  
±30  
±60  
±135  
±135  
±270  
±270  
IB  
Input bias current  
pA  
pA  
TA = –40°C to +125°C(1)  
TA = –40°C to +125°C(1)  
IOS  
Input offset current  
Input voltage noise  
NOISE  
177  
27  
nVPP  
f = 0.1 Hz to 10 Hz  
nVRMS  
f = 1 Hz  
8.5  
8.5  
8.5  
8.5  
70  
f = 10 Hz  
f = 100 Hz  
f = 1 kHz  
f = 1 kHz  
Input voltage noise  
density  
eN  
nV/√Hz  
fA/√Hz  
V
iN  
Input current noise  
INPUT VOLTAGE RANGE  
VS = 1.7 V  
VS = 5.5 V  
(V–) – 0.1  
(V–) – 0.2  
115  
(V+)  
Common-mode voltage  
range  
VCM  
(V+) + 0.1  
(V–) – 0.1 V < VCM < (V+), VS = 1.7 V  
138  
150  
132  
(V–) – 0.2 V < VCM < (V+) + 0.1 V, VS = 5.5 V  
(V–) – 0.1 V < VCM < (V+), TA = –40°C to +125°C(1)  
140  
Common-mode  
rejection ratio  
CMRR  
dB  
110  
(V–) – 0.2 V < VCM < (V+) + 0.1, VS = 5.5 V,  
TA = –40°C to +125°C(1)  
130  
INPUT CAPACITANCE  
ZID  
Differential  
100 || 3  
60 || 3  
MΩ || pF  
GΩ || pF  
ZICM  
Common-mode  
OPEN-LOOP GAIN  
(V–) + 100 mV < VOUT  
(V+) – 100 mV,  
RL = 10 kΩ  
<
<
132  
125  
132  
125  
145  
145  
TA = –40°C to +125°C(1)  
TA = –40°C to +125°C(1)  
AOL  
Open-loop voltage gain  
dB  
(V–) + 150 mV < VOUT  
(V+) – 150 mV,  
RL = 2 kΩ  
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SBOS984A – NOVEMBER 2020 – REVISED DECEMBER 2020  
6.5 Electrical Characteristics (continued)  
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VS = 1.7 V to 5.5 V, VCM = VS / 2, VOUT = VS / 2, and min and max specification  
established from manufacturing final test (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
FREQUENCY RESPONSE  
Gain-bandwidth  
product  
GBW  
5.7  
MHz  
V/μs  
SR  
tS  
Slew rate  
4-V step, G = +1  
2.8  
1.5  
2.5  
500  
To 0.1%, 1-V step , G = +1  
To 0.01%, 1-V step , G = +1  
Settling time  
μs  
Overload recovery time VIN × gain > VS  
ns  
Chopping clock  
frequency(1)  
100  
150  
kHz  
Total harmonic  
distortion + noise  
THD+N  
VOUT = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ  
0.002 %  
OUTPUT  
TA = 25°C, no load  
1
5
10  
30  
60  
30  
TA = 25°C, RL = 10 kΩ  
Voltage output swing  
from rail  
mV  
TA = 25°C, RL = 2 kΩ  
20  
RL = 10 kΩ, TA = –40°C to +125°C(1)  
(V–) +  
0.075  
(V+) –  
0.075  
AOL > 120 dB, RL = 10 kΩ  
AOL > 120 dB, RL = 2 kΩ  
V
V
High linearity output  
swing range(1)  
(V–) +  
0.075  
(V+) –  
0.075  
VS = 5.5 V  
±55  
±25  
40  
mA  
mA  
ISC  
Short-circuit current  
Phase margin  
VS = 1.7 V  
CL = 100 pF, gain = +1  
degrees  
POWER SUPPLY  
570  
25  
675  
700  
μA  
μA  
Quiescent current per  
amplifier  
IQ  
IO = 0 mA  
TA = –40°C to 125°C(1)  
At TA = 25°C, VS = 5.5 V,  
VS ramp rate > 0.3 V/µs, settle to 1%  
Turn-on time  
100  
μs  
(1) Specification established from device population bench system measurements across multiple lots.  
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6.6 Typical Characteristics  
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 50 pF (unless otherwise noted)  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
60  
55  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
0
-2  
0
-1.5  
-1  
-0.5  
0
0.5  
1
1.5  
2
-5  
-4  
-3  
-2  
-1  
0
1
2
3
4
5
Input Offset Voltage (mV)  
Input Offset Voltage (mV)  
c110  
c100  
VS = 5.5 V  
VS = 5.5 V  
Figure 6-1. Offset Voltage Distribution, 25°C  
Figure 6-2. Offset Voltage Distribution, –40°C  
40  
35  
30  
25  
20  
15  
10  
5
60  
50  
40  
30  
20  
10  
0
0
-5  
-4  
-3  
-2  
-1  
0
1
2
3
4
5
-0.02  
-0.01  
0
0.01  
0.02  
Input Offset Voltage (mV)  
Offset Voltage Drift (mV/èC)  
c101  
c103  
VS = 5.5 V  
VS = 5.5 V  
Figure 6-3. Offset Voltage Distribution, 125°C  
Figure 6-4. Offset Voltage Drift Distribution  
3
2
3
2
1
1
VCM = -2.95 V  
VCM = 2.85 V  
0
0
-1  
-2  
-3  
-1  
-2  
-3  
-40 -25 -10  
5
20 35 50 65 80 95 110 125  
Temperature (èC)  
-3  
-2  
-1  
0
Input Common Mode Voltage (V)  
1
2
3
c108  
c111  
Figure 6-5. Offset Voltage vs Temperature  
Figure 6-6. Offset Voltage vs Common-Mode Voltage  
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6.6 Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 50 pF (unless otherwise noted)  
1
0.75  
0.5  
160  
140  
120  
100  
80  
165  
150  
135  
120  
105  
90  
Gain  
Phase  
0.25  
0
60  
-0.25  
-0.5  
-0.75  
-1  
40  
75  
20  
60  
Vs = 1.7 V  
0
45  
-20  
30  
1.5  
2
3
Supply Voltage (V)  
4
5
5.5  
100m  
1
10  
100  
1k  
Frequency (Hz)  
10k  
100k  
1M  
10M  
c112  
c114  
Figure 6-7. Offset Voltage vs Supply Voltage  
Figure 6-8. Open-Loop Gain and Phase vs Frequency  
0.5  
0.25  
0
60  
VS = ê0.85 V  
VS = ê2.75 V  
40  
20  
0
-20  
-0.25  
G = -1  
G = +1  
-40  
-60  
G = +10  
G = +100  
-0.5  
-75  
-50  
-25  
0
25  
50  
75  
100 125 150  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
Temperature(èC)  
C129  
c113  
Figure 6-9. Open-Loop Gain vs Temperature  
Figure 6-10. Closed-Loop Gain and Phase vs Frequency  
0.1  
0.08  
0.06  
0.04  
0.02  
0
160  
CMRR  
PSRR-  
PSRR+  
140  
120  
100  
80  
VS = ê2.75 V, (V-) - 0.2 V Ç VCM Ç (V+) + 0.1 V  
-0.02  
-0.04  
-0.06  
-0.08  
-0.1  
60  
40  
VS = ê0.85 V, (V-) - 0.1 V Ç VCM Ç (V+)  
20  
0
10m 100m  
-75  
-50  
-25  
0
25  
50  
75  
100 125 150  
1
10  
100 1k  
Frequency (Hz)  
10k 100k 1M 10M  
Temperature (èC)  
C121  
C134  
Figure 6-11. CMRR vs Temperature  
Figure 6-12. PSRR and CMRR vs Frequency  
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6.6 Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 50 pF (unless otherwise noted)  
20  
10  
7
5
4
3
2
1
100m  
1
10  
100  
Frequency (Hz)  
1k  
10k  
100k  
Time (1 s/div)  
C130  
c115  
Figure 6-13. 0.1-Hz to 10-Hz Noise  
Figure 6-14. Input Voltage Noise Spectral Density vs Frequency  
0.1  
-60  
-40  
-60  
G = -1, RL = 10 kW  
G = -1, RL = 2 kW  
G = -1, RL = 600 W  
G = +1, RL = 10 kW  
G = +1, RL = 2 kW  
G = +1, RL = 600 W  
-80  
0.01  
-80  
-100  
-120  
-140  
-160  
-180  
-200  
0.001  
0.0001  
-100  
-120  
20k  
20  
200  
2k  
Frequency (Hz)  
C137  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
C122  
VS = 5.5 V, VOUT = 3 VRMS, BW = 80 kHz  
Figure 6-15. Channel-to-Channel Crosstalk  
Figure 6-16. THD+N Ratio vs Frequency  
1
-40  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
G = -1, RL = 10 kW  
G = -1, RL = 2 kW  
G = -1, RL = 600 W  
G = +1, RL = 10 kW  
G = +1, RL = 2 kW  
G = +1, RL = 600 W  
0.1  
0.01  
-60  
-80  
0.001  
-100  
-120  
0.0001  
10m  
100m  
Output Amplitude (VRMS  
1
)
C136  
1
2
3
Supply Voltage (V)  
4
5
6
c107  
VS = 5.5 V, f = 1 kHz, BW = 80 kHz  
Figure 6-17. THD+N vs Output Amplitude  
Figure 6-18. Quiescent Current vs Supply Voltage  
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SBOS984A – NOVEMBER 2020 – REVISED DECEMBER 2020  
6.6 Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 50 pF (unless otherwise noted)  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
1000  
100  
10  
1
0.1  
-40 -25 -10  
5
20 35 50 65 80 95 110 125  
Temperature (èC)  
1
10  
100  
1k 10k  
Frequency (Hz)  
100k  
1M  
10M  
c102  
C138  
Figure 6-19. Quiescent Current vs Temperature  
Figure 6-20. Open-Loop Output Impedance vs Frequency  
80  
60  
40  
20  
0
80  
RISO = 0 W  
RISO = 25 W  
RISO = 50 W  
RISO = 0 W  
RISO = 25 W  
RISO = 50 W  
60  
40  
20  
0
100  
Load Capacitance (pF)  
1k  
100  
Load Capacitance (pF)  
1k  
C124  
C127  
G = –1, 10 mV step  
G = +1, 10 mV step  
Figure 6-21. Small-Signal Overshoot vs Capacitive Load  
Figure 6-22. Small-Signal Overshoot vs Capacitive Load  
60  
VIN  
VOUT  
45  
30  
15  
0
100  
Load Capacitance (pF)  
1k  
Time (100 µs/div)  
C125  
C132  
Figure 6-24. No Phase Reversal  
Figure 6-23. Phase Margin vs Capacitive Load  
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6.6 Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 50 pF (unless otherwise noted)  
VIN  
VOUT  
VIN  
VOUT  
Time (500 ns/div)  
Time (1 µs/div)  
C133  
C128  
G = –1  
G = +1  
Figure 6-25. Overload Recovery  
Figure 6-26. Small-Signal Step Response  
VIN  
VOUT  
Rising Edge  
Falling Edge  
Time (1 µs/div)  
Time (10 µs/div)  
c105  
C135  
0.01% settling = ±100 µV  
Figure 6-27. Large-Signal Step Response (4-V Step)  
Figure 6-28. Settling Time  
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7 Detailed Description  
7.1 Overview  
The OPAx387 family of zero-drift amplifiers is engineered with state-of-the-art, proprietary, precision zero-drift  
technology. These amplifiers offer ultra-low input offset voltage and drift, and achieve excellent input and output  
dynamic linearity. The OPAx387 operate from 1.7 V to 5.5 V, are unity-gain stable, and are designed for a wide  
range of general-purpose and precision applications. The OPAx387 strengths also include a 5.7-MHz bandwidth,  
8.5-nV/√Hz noise spectral density, and no 1/f noise, making the OPAx387 an excellent choice for interfacing with  
sensor modules, and buffering high-fidelity, digital-to-analog converters (DACs).  
7.2 Functional Block Diagram  
GM_FF  
CCOMP  
CLK  
CLK  
+IN  
OUT  
œIN  
GM1  
GM2  
GM3  
CCOMP  
Ripple Reduction  
Technology  
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7.3 Feature Description  
7.3.1 Input Bias Current  
During normal operation, the typical input bias current of the OPAx387 is 30 pA. The device exhibits low drift  
over the full temperature range of –40°C to +125°C. There are no antiparallel diodes between the input pins (+IN  
and –IN); therefore, the differential input maximum voltage is limited only by diodes connected to the supply  
voltage pins. However, use caution in cases where the input differential voltage exceeds the nominal operating  
input differential voltage. When inputs are separated, the switching offset-cancellation path internal to the  
amplifier exceeds normal operating conditions, and can potentially create long settling behavior upon return to  
normal operation. The equivalent input circuit of OPAx387 is shown in Figure 7-1.  
V+  
450  
+IN  
œ
CORE  
450 ꢀ  
œIN  
+
Vœ  
Figure 7-1. Equivalent Input Circuit  
7.3.2 EMI Susceptibility and Input Filtering  
Operational amplifiers can exhibit sensitivity to electromagnetic interference (EMI). Typically, conducted EMI  
(that is, EMI that enters the device through conduction) is more commonly observed than radiated EMI (that is,  
EMI that enters the device through radiation). When conducted EMI enters the operational amplifier, the dc offset  
at the amplifier output can shift from the nominal value. This shift is a result of signal rectification associated with  
the internal semiconductor junctions. Although all operational amplifier pin functions can be affected by EMI, the  
input pins are likely to be the most susceptible. The OPAx387 operational amplifier family incorporates an  
internal input low-pass filter that reduces the amplifier response to EMI. Both common-mode and differential-  
mode filtering are provided by the input filter. The conducted EMI rejection of the OPAx387 is seen in Figure 7-2.  
140  
130  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10M  
100M  
Frequency (Hz)  
1G  
5G  
c104  
Figure 7-2. EMI Rejection Ratio  
7.4 Device Functional Modes  
The OPAx387 has a single functional mode and is operational when the power-supply voltage is greater than  
1.7 V (±0.85 V). The maximum specified power-supply voltage for the OPAx387 is 5.5 V (±2.75 V).  
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8 Application and Implementation  
Note  
Information in the following applications sections is not part of the TI component specification, and TI  
does not warrant its accuracy or completeness. TI’s customers are responsible for determining  
suitability of components for their purposes, as well as validating and testing their design  
implementation to confirm system functionality.  
8.1 Application Information  
The OPAx387 are unity-gain stable, precision, operational amplifiers featuring state-of-the-art, zero-drift  
technology. The use of proprietary zero-drift circuitry gives the benefit of low input offset voltage over time and  
temperature, as well as lower 1/f noise component. As a result of the high PSRR, the devices work well in  
applications that run directly from battery power without regulation. The OPAx387 family is optimized for full rail-  
to-rail input, allowing for low-voltage, single-supply operation or split-supply use. These miniature, high-precision,  
low-noise amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the supplies  
without input crossover distortion, and a rail-to-rail output that swings within 5 mV of the supplies under normal  
test conditions. The OPAx387 precision amplifiers are designed for upstream analog signal-chain applications in  
low or high gains, as well as downstream signal-chain functions, such as DAC buffering.  
8.1.1 Zero-Drift Clocking  
The OPAx387 use an advanced zero-drift architecture to achieve ultra-low offset and offset drift. This  
architecture uses a clock and switches internally to create a dc error-correction path. The clocking is filtered  
internally, and typically not observable for most configurations. Take the following precautions to minimize clock  
noise in the signal chain. The clocking creates a small charge-injection pulse at the input of the amplifier;  
therefore, do not use high-value resistors (> 100 kΩ) in series with the inputs to avoid higher clock voltage noise  
at the output. The charge injection pulses are minimized when the impedance to the input pins is matched. If  
higher value resistors are used, then use matching impedances on both amplifier input pins.  
8.2 Typical Applications  
8.2.1 Bidirectional Current Sensing  
This single-supply, low-side, bidirectional current-sensing design example detects load currents from –1 A to +1  
A. The single-ended output spans from 110 mV to 3.19 V. This design uses the OPAx387 because of the device  
low offset voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier  
and the other amplifier provides the reference voltage. Figure 8-1 shows the design example schematic.  
VCC  
VREF  
VCC  
R5  
+
U1B  
ILOAD  
R6  
R2  
+
R1  
+
VBUS  
+
œ
VSHUNT  
RSHUNT  
VOUT  
U1A  
VCC  
R4  
R3  
œ
RL  
Figure 8-1. Bidirectional Current-Sensing Schematic  
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8.2.1.1 Design Requirements  
This solution has the following requirements:  
Supply voltage: 3.3 V  
Input: –1 A to +1 A  
Output: 1.65 V ±1.54 V (110 mV to 3.19 V)  
8.2.1.2 Detailed Design Procedure  
The load current, ILOAD, flows through the shunt resistor, RSHUNT, to develop the shunt voltage, VSHUNT. The  
shunt voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the  
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference  
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by Equation 1.  
VOUT = VSHUNT ´ GainDiff_Amp + VREF  
(1)  
where  
VSHUNT = ILOAD ´ RSHUNT  
R4  
GainDiff_Amp  
=
R3  
R6  
R5 + R6  
VREF = VCC  
´
There are two types of errors in this design: gain and offset. Gain errors are introduced by the tolerance of the  
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage  
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of  
the difference amplifier, ultimately translating to an offset error.  
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.  
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set to  
100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of  
100 mV and maximum load current of 1 A.  
VSHUNT(Max)  
100 mV  
= 100 mW  
RSHUNT(Max)  
=
=
ILOAD(Max)  
1 A  
(2)  
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%  
was selected. If greater accuracy is required, select a 0.1% resistor or better.  
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to +100 mV. This voltage is  
divided down by R1 and R2 before reaching the operational amplifier, U1A. Make sure that the voltage present at  
the noninverting node of U1A is within the common-mode range of the device. Use an operational amplifier, such  
as the OPAx387, that has a common-mode range that extends below the negative supply voltage. The offset  
error is minimal because the OPAx387 has a typical offset voltage of merely ±0.25 µV (±5 µV, maximum).  
Given a symmetric load current of –1 A to +1 A, the voltage divider resistors, R5 and R6, must be equal. To be  
consistent with the shunt resistor, a tolerance of 0.5% is selected. To minimize power consumption, 10kΩ  
resistors are used.  
To set the gain of the difference amplifier, the common-mode range and output swing of the OPAx387 must be  
considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,  
respectively, of the OPAx387 given a 3.3V supply.  
–100 mV < VCM < 3.4 V  
100 mV < VOUT < 3.2 V  
(3)  
(4)  
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The gain of the difference amplifier can now be calculated as shown in Equation 5.  
V
OUT_Max - VOUT_Min  
3.2 V - 100 mV  
100 mW ´ [1 A - (- 1A)]  
V
V
= 15.5  
=
GainDiff_Amp  
=
R
SHUNT ´ (IMAX - IMIN  
)
(5)  
The resistor value selected for R1 and R3 was 1 kΩ. 15.4 kΩ was selected for R2 and R4 because this number is  
the nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.  
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors  
were selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple  
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.  
8.2.1.3 Application Curve  
3.30  
1.65  
0
-1.0  
-0.5  
0
0.5  
1.0  
Input Current (A)  
Figure 8-2. Bidirectional Current-Sensing Circuit Performance: Output Voltage vs Input Current  
8.2.2 Load Cell Measurement  
Figure 8-3 shows the OPAx387 in a high-CMRR dual-op amp instrumentation amplifier with a trim resistor and 6-  
wire load cell for precision measurement.  
R3  
25 k  
R4  
100 kꢀ  
5 V  
REF5025  
RG  
R4  
R2  
100 kꢀ  
25 kꢀ  
5 V  
5 V  
5 V  
+SENSE  
œ
OPAx387  
œ
OPAx387  
VOUT  
+
+
R2  
GND  
GND  
10 kꢀ  
œSENSE  
200 kΩ  
Load Cell  
G = 5 +  
GND  
RG  
GND  
Figure 8-3. Load Cell Measurement Schematic  
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9 Power Supply Recommendations  
The OPAx387 family of devices is specified for operation from 1.7 V to 5.5 V for single supplies, and ±0.85 V to  
±2.75 V for dual supplies. Key parameters that can exhibit significant variance with regard to operating voltage  
are presented in Section 6.6.  
CAUTION  
Supply voltages greater than 6 V can permanently damage the device (see Section 6.1).  
10 Layout  
10.1 Layout Guidelines  
Pay attention to good layout practice. Keep traces short and, when possible, use a printed-circuit board (PCB)  
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-µF  
capacitor close to the supply pins. These guidelines must be applied throughout the analog circuit to improve  
performance, and provide benefits such as reducing the electromagnetic interference (EMI) susceptibility.  
For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid  
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from  
connecting dissimilar conductors. Cancel these thermally-generated potentials by making sure that the potentials  
are equal on both input terminals. Other layout and design considerations include:  
Use low thermoelectric-coefficient conditions (avoid dissimilar metals).  
Thermally isolate components from power supplies or other heat sources.  
Shield operational amplifier and input circuitry from air currents, such as cooling fans.  
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which can cause  
thermoelectric voltage drift of 0.1 µV/°C or higher depending on materials used.  
10.2 Layout Example  
RIN  
VIN  
+
VOUT  
RG  
RF  
Figure 10-1. Schematic Representation  
GND  
VS+  
VOUT  
Place components close  
to device and to each  
other to reduce parasitic  
errors  
Use a low-ESR,  
ceramic bypass  
capacitor  
RF  
OUT A  
V+  
VOUT  
RG  
GND  
œIN A  
+IN A  
Vœ  
OUT B  
œIN B  
+IN B  
RF  
Place components  
RIN  
close to device  
and to each other  
to reduce parasitic  
errors  
VIN  
Run the input traces  
as far away from  
the supply lines  
as possible  
RG  
Use low-ESR,  
ceramic bypass  
capacitor  
RIN  
GND  
Run the input traces  
as far away from  
the supply lines  
as possible  
GND  
VSœ  
VIN  
Ground (GND) plane on another layer  
Figure 10-2. OPA387 Layout Example  
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11 Device and Documentation Support  
11.1 Device Support  
11.1.1 Development Support  
11.1.1.1 TINA-TI Simulation Software (Free Download)  
TINA-TIsoftware is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine.  
TINA-TI simulation software is a free, fully-functional version of the TINAsoftware, preloaded with a library of  
macromodels, in addition to a range of both passive and active models. TINA-TI simulation software provides all  
the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design  
capabilities.  
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive  
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the  
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-  
start tool.  
Note  
These files require that either the TINA software or TINA-TI software be installed. Download the free  
TINA-TI simulation software from the TINA-TI software folder.  
11.2 Documentation Support  
11.2.1 Related Documentation  
For related documentation see the following: Texas Instruments, Circuit board layout techniques  
11.3 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on  
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For  
change details, review the revision history included in any revised document.  
11.4 Support Resources  
TI E2Esupport forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
11.5 Trademarks  
TINA-TIis a trademark of TI.  
TINAis a trademark of DesignSoft, Inc.  
TI E2Eis a trademark of Texas Instruments.  
All trademarks are the property of their respective owners.  
11.6 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
11.7 Glossary  
TI Glossary  
This glossary lists and explains terms, acronyms, and definitions.  
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12 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical packaging and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
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29-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
OPA2387DGKR  
OPA2387DGKT  
ACTIVE  
ACTIVE  
VSSOP  
VSSOP  
DGK  
DGK  
8
8
2500 RoHS & Green  
250 RoHS & Green  
SN  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 125  
-40 to 125  
2B2T  
2B2T  
SN  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
29-Dec-2020  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
24-Dec-2020  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
OPA2387DGKR  
OPA2387DGKT  
VSSOP  
VSSOP  
DGK  
DGK  
8
8
2500  
250  
330.0  
330.0  
12.4  
12.4  
5.3  
5.3  
3.4  
3.4  
1.4  
1.4  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
24-Dec-2020  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
OPA2387DGKR  
OPA2387DGKT  
VSSOP  
VSSOP  
DGK  
DGK  
8
8
2500  
250  
366.0  
366.0  
364.0  
364.0  
50.0  
50.0  
Pack Materials-Page 2  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
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SI9130_11

Pin-Programmable Dual Controller - Portable PCs

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SI9137

Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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