OPA2625 [TI]
具有关断功能的高带宽、高精密、低 THD+N、16 位和 18 位 ADC 驱动器;
| 型号： | OPA2625 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有关断功能的高带宽、高精密、低 THD+N、16 位和 18 位 ADC 驱动器 驱动 驱动器 |
| 文件： | 总48页 (文件大小：2997K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA625, OPA2625
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
OPAx625 高带宽、高精度、低 THD+N、
16 位和 18 位模数转换器 (ADC) 驱动器
1 特性
3 说明
1
•
高驱动模式：
OPAx625 系列运算放大器是出色的 16 位和 18 位
SAR ADC 驱动器，具备高精度、低总谐波失真 (THD)
及低噪声等诸多优势，可提供一套独特的电源可扩展解
决方案。该器件系列在额定工作条件下的 16 位稳定时
间为 280ns，可提供真正的 16 位有效位数 (ENOB)。
该系列器件具备高直流精度（偏移电压仅为
–
–
–
–
–
–
–
–
增益带宽 (GBW) (G = 100)：120MHz
转换率：115V/μs
4V 输出时的 16 位稳定时间： 280ns
低电压噪声：10kHz 时为 2.5nV/√Hz
低输出阻抗：1MHz 时为 1Ω
100µV）、120MHz 的宽增益带宽积以及 2.5nV/√Hz
的低宽带噪声，并且经优化可驱动高吞吐量、高分辨率
的 SAR ADC，例如 ADS88xx 系列 SAR ADC。
偏移电压：±100µV（最大值）
偏移电压漂移：±3µV/ºC（最大值）
低静态电流：2mA（典型值）
•
低功耗模式：
此 OPAx625 具有 两种工作模式：高驱动模式和低功
耗模式。在创新型低功耗模式下，OPAx625 会跟踪输
入信号，从而能够在 170ns 内以 16 位 ENOB 从低功
耗模式切换至高驱动模式。
–
–
GBW：1MHz
低静态电流：270µA（典型值）
•
•
功率可扩展性 特性：
–
可超快速地从低功耗模式切换至高驱动模
式：170ns
OPAx625 系列采用 6 引脚小外形尺寸晶体管 (SOT)
封装和 10 引脚超薄小外形尺寸 (VSSOP) 封装，额定
工作温度范围为 –40°C 至 +125℃。
高交流和直流精度：
–
低失真：100kHz 时，HD2 为 –122dBc，HD3
为 –140dBc
器件信息(1)
–
–
–
输入共模范围包括负电源轨
轨到轨输出
器件型号
OPA625
OPA2625
封装
SOT (6)
VSSOP (10)
封装尺寸（标称值）
2.90mm x 1.60mm
3.00mm × 3.00mm
宽额定温度范围：-40℃ 至 +125℃
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
2 应用
•
•
•
•
•
精密逐次逼近寄存器 (SAR) ADC 驱动器
精密电压基准缓冲器
可编程逻辑控制器
测试和测量设备
16 位 SAR ADC，fIN = 10kHz，1MSPS FFT
0
功耗敏感型数据采集系统
THD = -110.8 dBc
SNR = 91.88 dB
SINAD = 91.86 dB
ENOB = 14.97
-25
-50
SAR ADC 驱动器
1 kꢀ
1 kꢀ
Mode
Control
-75
Input
Voltage
-115.91 dBc (Third Harmonic)
5 V
VREF
3.3 V
-100
-125
-150
-175
œ
4.7 ꢀ
4.7 ꢀ
OPA625
REF AVDD
ADS8860
GND
10 nF
+
VREF / 4
0
50 100 150 200 250 300 350 400 450 500
Frequency (kHz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS688
OPA625, OPA2625
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics High-Drive Mode............... 5
6.6 Electrical Characteristics Low-Power Mode.............. 7
6.7 Electrical Characteristics High-Drive Mode............... 8
6.8 Electrical Characteristics Low-Power Mode............ 10
6.9 Switching Characteristics........................................ 11
6.10 Typical Characteristics.......................................... 12
Parameter Measurement Information ................ 23
7.1 DC Parameter Measurements ................................ 23
7.2 Transient Parameter Measurements ...................... 24
7.3 AC Parameter Measurements ................................ 24
7.4 Noise Parameter Measurements ............................ 25
8
9
Detailed Description ............................................ 26
8.1 Overview ................................................................. 26
8.2 Functional Block Diagram ....................................... 26
8.3 Feature Description................................................. 27
8.4 Device Functional Modes........................................ 28
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Applications ................................................ 30
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 35
12 器件和文档支持 ..................................................... 36
12.1 器件支持................................................................ 36
12.2 文档支持................................................................ 36
12.3 相关链接................................................................ 36
12.4 Community Resources.......................................... 36
12.5 商标....................................................................... 37
12.6 静电放电警告......................................................... 37
12.7 Glossary................................................................ 37
13 机械、封装和可订购信息....................................... 37
7
4 修订历史记录
Changes from Original (April 2015) to Revision A
Page
•
•
•
•
•
•
•
•
•
已将 OPA2625 从“产品预览”改为“量产数据”；已添加 OPA2625 规范至数据表 .................................................................... 1
Changed MODE B pin description options for V+ and V– ..................................................................................................... 3
Added crosstalk parameter to Electrical Characteristics table .............................................................................................. 5
Added crosstalk parameter to Electrical Characteristics table .............................................................................................. 8
Changed short-circuit current value from 150 mA to 80 mA in Electrical Characteristics table............................................. 9
Changed short-circuit current value from 100 mA to 50 mA in Electrical Characteristics table........................................... 10
Added OPA2625 data to 图 12 ............................................................................................................................................ 13
Added 图 24.......................................................................................................................................................................... 15
Deleted "18" from several typical characteristic figure titles (typo) ..................................................................................... 19
2
Copyright © 2015, Texas Instruments Incorporated
OPA625, OPA2625
www.ti.com.cn
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
5 Pin Configuration and Functions
OPA625: DBV Package
6-Pin SOT
OPA2625: DGS Package
10-Pin VSSOP
Top View
Top View
OUT A
œIN A
V+
OUT
Vœ
1
2
3
6
5
4
V+
1
2
3
4
5
10
9
OUT B
œIN B
MODE
œIN
+IN A
8
Vœ
+IN B
7
+IN
MODE B
MODE A
6
Pin Functions: OPA625
PIN
I/O
DESCRIPTION
NAME
NO
3
+IN
–IN
I
I
Noninverting input
4
Inverting input
Controls OPA625 mode:
V+ = low-power mode
V– = high-drive mode
MODE
5
I
NOTE: Do not float this pin.
OUT
V+
1
6
2
O
—
—
Output terminal
Positive supply voltage
Negative supply voltage
V–
Pin Functions: OPA2625
PIN
I/O
DESCRIPTION
NAME
NO.
3
+IN A
–IN A
+IN B
–IN B
I
I
I
I
Noninverting input for channel A
Inverting input for channel A
Noninverting input for channel B
Inverting input for channel B
2
7
8
Controls OPA2625 mode for channel A:
V+ = low-power mode
V– = high-drive mode
MODE A
MODE B
5
6
I
I
NOTE: Do not float this pin.
Controls OPA2625 mode for channel B:
V+ = low-power mode
V– = high-drive mode
NOTE: Do not float this pin.
OUT A
OUT B
V+
1
9
O
O
Output terminal for channel A
Output terminal for channel B
Positive supply voltage
10
4
—
—
V–
Negative supply voltage
Copyright © 2015, Texas Instruments Incorporated
3
OPA625, OPA2625
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6
UNIT
Supply voltage, VS
Input voltage(2)
Output voltage
(V+) – (V–)
+IN
V
(V–) – 0.3
(V–) – 0.3
(V–) – 0.3
(V–)
(V+) + 0.3
(V+) + 0.3
(V+) + 0.3
(V+)
10
–IN
V
V
MODE
OUT
+IN
–IN
10
Sink current
mA
MODE
OUT
10
150
+IN
10
–IN
10
Source current
Temperature
mA
°C
MODE
OUT(2)
Operating junction
Storage, Tstg
10
150
–40
–65
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For input voltages beyond the power-supply rails, voltage or current must be limited.
6.2 ESD Ratings
VALUE
±3000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
5.5
UNIT
VS
VI
Supply input voltage, (V+) – (V–)
Input voltage
V
+IN
(V–)
(V–)
(V–)
(V–)
–120
–40
(V+) – 1.15
(V+) – 1.15
(V+)
–IN
V
MODE
VO
IO
Output voltage
(V+)
V
Output current
120
mA
°C
°C
TA
TJ
Operating free-air temperature
Operating junction temperature
125
–40
125
4
Copyright © 2015, Texas Instruments Incorporated
OPA625, OPA2625
www.ti.com.cn
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
6.4 Thermal Information
OPA625
DBV (SOT)
6 PINS
184.9
OPA2625
DGS (VSSOP)
10 PINS
171.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
123.6
68.4
30.7
91.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.1
9.4
ψJB
30.2
90.5
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics High-Drive Mode
at TA = 25°C, V+ = 5 V, V– = 0 V, MODE pin connected to V– pin, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF,
CLOAD = 20 pF, and RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Unity gain frequency
Phase margin
VO = 10 mVPP
80
50
MHz
Degrees
MHz
φm
GBW
Gain-bandwidth product G = 100, VO = 10 mVPP
120
45
VO = 1-V step, G = 1
Slew rate
SR
V/µs
VO = 4-V step, G = 2
115
Settling time to 0.1%
(10-bit accuracy)
80
110
280
to 0.005%
(14-bit accuracy)
tsettle
Settling time
VO = 4-V step, G = 2
ns
to 0.00153%
(16-bit accuracy)
Overshoot
VO = 4-V step, G = 2
VO = 4-V step, G = 2
2.5%
3%
144
122
80
Undershoot
f = 10 kHz
f = 100 kHz
f = 1 MHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
Second-order harmonic
Distortion
HD2
HD3
VO = 2 VPP, G = 2
VO = 2 VPP, G = 2
dBc
dBc
155
140
80
Third-order harmonic
Distortion
Second-order
intermodulation distortion
VO = 2 VPP, f = 1 MHz, 200-kHz tone spacing
VO = 2 VPP, f = 1 MHz, 200-kHz tone spacing
90
dBc
dBc
Third-order
intermodulation distortion
100
f = 0.1 Hz to 10 Hz, peak-to-peak
f = 0.1 Hz to 10 Hz, rms
f = 1 kHz
0.8
120
3.2
2.5
4.1
2.8
50
µVPP
VN
Vn
In
Input noise voltage
nVRMS
Input voltage noise
density
nV/√Hz
pA/√Hz
f = 10 kHz
f = 1 kHz
Input current noise
density
f = 10 kHz
tOR
Zo
Overload recovery time
G = 5
ns
Open-loop output
impedance
f = 1 MHz
1
Ω
DC
150
127
Crosstalk
dB
µV
f = 1 MHz
DC PERFORMANCE
VOS Input offset voltage
15
±100
±300
TA = –40°C to +125°C
Copyright © 2015, Texas Instruments Incorporated
5
OPA625, OPA2625
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
www.ti.com.cn
Electrical Characteristics High-Drive Mode (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, MODE pin connected to V– pin, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF,
CLOAD = 20 pF, and RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = –40°C to +125°C
0.5
±3
µV/°C
dVOS/dT
PSRR
Input offset voltage drift
OPA2625 only, TA = –40°C to +125°C
0.6
±4
100
90
Power-supply rejection
ratio
2.7 V ≤ (V+) ≤ 5 V
dB
TA = –40°C to +125°C
120
2
4
5.7
6.5
IB
Input bias current
TA = –40°C to +125°C
µA
nA/°C
nA
OPA2625 only, TA = –40°C to +125°C
TA = –40°C to +125°C
dIB/dT
IOS
Input bias current drift
Input offset current
Input offset current drift
15
20
120
150
200
TA = –40°C to +125°C
OPA2625 only, TA = –40°C to +125°C
TA = –40°C to +125°C
dIOS/dT
0.6
nA/°C
OPEN LOOP GAIN
(V–) + 0.2 V < VO < (V+) – 0.2 V, RLOAD = 600 Ω
(V–) + 0.15 V < VO < (V+) – 0.15 V, RLOAD = 10 kΩ
110
114
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
AOL
Open-loop gain
dB
106
110
128
132
TA = –40°C to +125°C
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
INPUT VOLTAGE
Common-mode voltage
range
(V+) –
1.15
VCM
TA = –40°C to +125°C
(V–)
V
100
90
117
115
Common-mode rejection
ratio
CMRR
(V–) < VCOM < (V+) – 1.15 V
dB
TA = –40°C to +125°C
INPUT IMPEDANCE
Differential input
impedance
ZID
27 || 1.2
47 || 1.5
KΩ || pF
MΩ || pF
Common-mode input
impedance
ZIC
OUTPUT
60
20
80
100
35
RLOAD = 600 Ω
RLOAD = 10 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
Output voltage swing to
the rail
mV
mA
40
Isc
Short-circuit current
Capacitive load drive
150
CLOAD
MODE
See Typical Characteristics
High-drive (HD) mode
threshold
VIL
TA = –40°C to +125°C
TA = –40°C to +125°C
(V–)
(V–) + 0.5
V
Low-power (LP) mode
threshold
VIH
IIL
(V–) + 1.2
(V+)
V
Low-level input current
TA = –40°C to +125°C, VMODE ≤ (V–) + 0.5 V
0.01
20
1
30
1
µA
TA = –40°C to +125°C, VMODE ≥ (V–) + 1.2 V
IIH
High-level input current
µA
OPA2625 only, TA = –40°C to +125°C, VMODE ≥ (V–) + 1.2 V
POWER SUPPLY
Quiescent current per
2
2.2
3.1
IO = 0 mA,
MODE connected to ground
IQ
mA
amplifier
TA = –40°C to +125°C
6
Copyright © 2015, Texas Instruments Incorporated
OPA625, OPA2625
www.ti.com.cn
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
6.6 Electrical Characteristics Low-Power Mode
at TA = 25°C, V+ = 5 V, V– = 0 V, VMODE = 5 V, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
GBW
Gain-bandwidth product G = 100, VO = 10 mVPP
Phase margin
1
72
MHz
φm
Degrees
VO = 1-V step
Slew rate
4.3
4.1
SR
Zo
V/µs
VO = 4-V step, G = 2
Open-loop output
f = 1 MHz
12
Ω
impedance
DC PERFORMANCE
0.6
0.7
3
VOS
Input offset voltage
mV
dB
TA = –40°C to +125°C
3.7
74
70
Power-supply rejection
ratio
PSRR
2.7 V ≤ (V+) ≤ 5 V
TA = –40°C to +125°C
100
140
150
200
250
20
IB
Input bias current
TA = –40°C to +125°C
nA
nA
OPA2625 only, TA = –40°C to +125°C
IOS
Input offset current
TA = –40°C to +125°C
25
OPEN LOOP GAIN
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
70
90
100
100
AOL
Open-loop gain
TA = –40°C to +125°C
dB
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
INPUT VOLTAGE
Common-mode voltage
range
(V+) –
1.15
VCM
TA = –40°C to +125°C
(V–)
V
66
60
114
114
Common-mode rejection
ratio
CMRR
(V–) < VCOM < (V+) – 1.15 V
dB
TA = –40°C to +125°C
OUTPUT
RLOAD = 600 Ω
RLOAD = 10 kΩ
110
40
Output voltage swing to
the rail
TA = –40°C to +125°C
mV
mA
Isc
Short-circuit current
100
270
POWER SUPPLY
320
450
Quiescent current per
amplifier
IO = 0 mA,
MODE connected to V+
IQ
µA
TA = –40°C to +125°C
Copyright © 2015, Texas Instruments Incorporated
7
OPA625, OPA2625
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
www.ti.com.cn
6.7 Electrical Characteristics High-Drive Mode
at TA = +25°C, V+ = 2.7 V, V– = 0 V, VMODE = 0 V, VCOM = VO = 1.35 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF,
and RLOAD = 1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Unity gain frequency
Phase margin
VO = 10 mVPP
76
45
MHz
Degrees
MHz
φm
GBW
SR
Gain-bandwidth product G = 100, VO = 10 mVPP
120
45
Slew rate
VO = 1-V step, G = 2
V/µs
to 0.1%
80
tsettle
Settling time
VO = 1-V step, G = 2
to 0.01%
170
250
6%
5%
136
118
80
ns
to 0.000763% (17-bit accuracy)
Overshoot
VO = 1-V step, G = 2
VO = 1-V step, G = 2
Undershoot
f = 10 kHz
(V+) = 3.3 V, (V–) = 0 V,
VCOM = 1.1 V,
VO = 2 VPP
Second order harmonic
Distortion
HD2
HD3
f = 100 kHz
dBc
dBc
f = 1 MHz
f = 10 kHz
143
143
130
125
85
OPA2625 only, f = 10 kHz
f = 100 kHz
(V+) = 3.3 V, (V–) = 0 V,
VCOM = 1.1 V,
VO = 2 VPP
Third order harmonic
Distortion
OPA2625 only, f = 100 kHz
f = 1 MHz
OPA2625 only, f = 1 MHz
74
Second order inter-
modulation distortion
(V+) = 3.3 V, (V–) = 0 V, VCOM = 1.1 V, VO = 2 VPP
f = 1 MHz, 200-kHz tone spacing
,
95
dBc
dBc
Third order inter-
modulation distortion
(V+) = 3.3 V, (V–) = 0 V, VCOM = 1.1V, VO = 1 VPP
,
104
f = 1 MHz, 200-kHz tone spacing
f = 0.1 Hz to 10 Hz peak to peak
f = 0.1 Hz to 10 Hz rms
0.8
µVPP
VN
Vn
Input noise voltage
120
nVRMS
Input voltage noise
density
f = 10 kHz
2.5
nV/√Hz
Input current noise
density
In
f = 10 kHz
G = 5
2.8
35
pA/√Hz
tOR
Zo
Overload recovery time
ns
Open-loop output
impedance
f = 1 MHz
1.3
Ω
DC
150
127
Crosstalk
dB
f = 1 MHz
DC PERFORMANCE
15
±100
±300
±3.1
±4
VOS
Input offset voltage
µV
TA = –40°C to +125°C
TA = –40°C to +125°C
0.5
0.6
2
dVOS/dT
Input offset voltage drift
µV/°C
OPA2625 only, TA = –40°C to +125°C
4
IB
Input bias current
TA = –40°C to +125°C
5.7
µA
nA/°C
nA
OPA2625 only, TA = –40°C to +125°
TA = –40°C to +125°C
6.5
dIB/dT
IOS
Input bias current drift
Input offset current
Input offset current drift
15
20
120
150
200
TA = –40°C to +125°C
OPA2625 only, TA = –40°C to +125°
TA = –40°C to +125°C
dIOS/dT
80
pA/°C
OPEN-LOOP GAIN
8
Copyright © 2015, Texas Instruments Incorporated
OPA625, OPA2625
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ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
Electrical Characteristics High-Drive Mode (continued)
at TA = +25°C, V+ = 2.7 V, V– = 0 V, VMODE = 0 V, VCOM = VO = 1.35 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF,
and RLOAD = 1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
110
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
114
106
110
AOL
Open-loop gain
dB
(V–) + 0.2 V < VO < (V+) – 0.2 V,
128
132
RLOAD = 600 Ω
TA = –40°C to +125°C
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
INPUT VOLTAGE
Common-mode voltage
range
(V+) –
1.15
VCM
TA = –40°C to +125°C
(V–)
V
100
90
117
115
Common-mode rejection
ratio
CMRR
(V–) < VCOM < (V+) – 1.15 V
dB
TA = –40°C to +125°C
INPUT IMPEDANCE
Differential input
impedance
ZID
27 || 0.8
47 || 1.2
KΩ || pF
MΩ || pF
Common-mode input
impedance
ZIC
OUTPUT
60
20
80
80
100
35
R LOAD = 600 Ω
R LOAD = 10 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
Output voltage swing to
the rail
mV
mA
40
ISC
Short-circuit current
Capacitive load drive
CLOAD
MODE
See Typical Characteristics
High-drive (HD) mode
threshold
VIL
VIH
TA = –40°C to +125°C
TA = –40°C to +125°C
(V–)
(V–) + 0.5
V
V
Low-power (LP) mode
threshold
(V–) + 1.2
(V+)
POWER SUPPLY
2
2.1
2.8
Quiescent current per
amplifier
IO = 0 mA
MODE connected to ground
IQ
mA
TA = –40°C to +125°C
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6.8 Electrical Characteristics Low-Power Mode
at TA = +25°C, V+ = 2.7 V, V– = 0 V, VMODE = 2.7 V, VCOM = VO = 1.35V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF,
and RLOAD = 1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
GBW
φm
Gain-bandwidth product G = 100, VIN = 10 mVPP
Phase margin
0.8
72
MHz
Degrees
V/µs
SR
Slew rate
VO = 1 V-step, G = 2
f = 1 MHz
3.7
Open-loop output
impedance
Zo
13
Ω
DC PERFORMANCE
VOS Input offset voltage
0.6
0.7
3
±3.6
150
220
250
20
mV
nA
nA
TA = –40°C to +125°C
TA = –40°C to +125°C
IB
Input bias current
140
OPA2625 only, TA = –40°C to +125°
IOS
Input offset current
TA = –40°C to +125°C
25
OPEN LOOP GAIN
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
74
84
100
100
AOL
Open-loop gain
TA = –40°C to +125°C
dB
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
INPUT VOLTAGE
Common-mode voltage
range
(V+) –
1.15
VCM
TA = –40°C to +125°C
(V–)
V
66
60
114
114
Common-mode rejection
ratio
CMRR
(V–) < VCOM < (V+) – 1.15 V
dB
TA = –40°C to +125°C
OUTPUT
RLOAD = 600 Ω
RLOAD = 10 kΩ
110
40
Output voltage swing to
rail
TA = –40°C to +125°C
mV
mA
Isc
Short-circuit current
50
POWER SUPPLY
250
270
400
Quiescent current per
amplifier
IO = 0 mA,
MODE connected to V+
IQ
µA
TA = –40°C to +125°C
10
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OPA625, OPA2625
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ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
6.9 Switching Characteristics
at TA = 25°C, V+ = 5 V, V– = 0 V, MODE pin connected to V– pin, gain (G) = 1 , VCOM = VO = 2.5 V, CLOAD = 20 pF, and RLOAD
= 1 kΩ connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Settling time to within 50 µV of final value,
MODE pin = high to low (LP to HD), VO = 3.8 V
180
ns
Delay time, MODE pin falling
(low-power mode to high-drive mode)
tLP-HD is defined as the time taken for the
quiescent current to increase from 110% of its
value in LP mode to 90% of its value in HD
mode.
tLP-HD
170
300
ns
ns
tHD-LP is defined as the time taken for the
quiescent current to decrease from 90% of its
value in HD mode to 110% of its value in LP
mode.
Delay time, MODE pin rising
(high-drive mode to low-power mode)
tHD-LP
tHD-LP
MODE
tLP-HD
OPAx625
STATE
Low-Power mode
High-Drive mode
图 1. Switching Characteristics Timing Diagram
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6.10 Typical Characteristics
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
25
20
25
20
15
15
10
10
5
5
0
0
Gain = 1
Gain = -1
Gain = 2
Gain = 5
Gain = 10
œ5
œ5
Gain = 1
Gain = -1
Gain = 2
Gain = 5
Gain = 10
œ10
œ15
œ20
œ25
œ10
œ15
œ20
œ25
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
C004
C005
VO = 10 mVPP
VO = 2 VPP
图 2. Small-Signal Frequency Response for Various Gains
图 3. Large-Signal Frequency Response for Various Gains
2.5
10
8
5.5 V
2.0
2.7 V
6
1.5
1.0
4
2
0
0.5
œ2
œ4
0 pF
8.2 pF
22 pF
33 pF
47 pF
0.0
œ6
-0.5
œ8
-1.0
œ10
100k
1M
10M
100M
1M
10M
100M
Frequency (Hz)
1G
Frequency (Hz)
C006
C007
VO = 10 mVPP, G = 1
VO = 10 mVPP , G = 1
图 4. Small-Signal Frequency Response for Various Power
图 5. Small-Signal Frequency Response for Various
Supply Voltages
Capacitive Loads
2
1
2.5
2 kꢀ
1 kꢀ
600 ꢀ
2.0
1.5
1.0
0.5
0.0
-0.5
0
œ1
œ2
œ3
œ4
œ5
œ6
œ7
œ8
0 pF
8.2 pF
22 pF
33 pF
47 pF
10k
100k
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
C007
C007
VO = 2 VPP, G = 1
VO = 10 mVPP , G = 1
图 6. Large-Signal Frequency Response for Various
图 7. Small-Signal Frequency Response for Various
Capacitive Loads
Resistive Loads
12
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ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
160
120
80
40
0
225
180
135
90
1000
100
10
45
Gain
Phase
0
-40
0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M
1
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
C024
Frequency (Hz)
VO = 10 mVPP
图 8. High-Drive Mode Open-Loop Gain and Phase vs
图 9. High-Drive Mode Open-Loop Output Impedance vs
Frequency
Frequency
1000
120
100
80
60
40
20
0
210
180
150
120
90
100
10
1
60
Gain
30
Phase
0
-20
10M
1M
10k 100k
0.01 0.1
1
10
100
1k
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
C024
Frequency (Hz)
VO = 10 mVPP , VMODE = 5 V
图 10. Low-Power Mode Open-Loop Gain and Phase vs
图 11. Low-Power Mode Open-Loop Output Impedance vs
Frequency
Frequency
140
120
140
120
100
80
OPA625
OPA2625
100
80
60
40
20
0
60
40
PSRR+
20
PSRR-
0
1
10
100
1k
10k 100k 1M
10M 100M
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
C025
Frequency (Hz)
图 13. Power-Supply Rejection Ratio vs Frequency
图 12. Common-Mode Rejection Ratio vs Frequency
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Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
5
60
55
50
45
40
35
30
25
20
15
10
Riso = 0 ꢀ, 5.5 V
Riso = 25 ꢀ, 5.5 V
Riso = 0 ꢀ, 2.7 V
Riso = 25 ꢀ, 2.7 V
Riso = 10 ꢀ, 5.5 V
Riso = 50 ꢀ, 5.5 V
Riso = 10 ꢀ, 2.7 V
Riso = 50 ꢀ, 2.7 V
0
œ5
Riso = 10 ꢀ
Riso = 25 ꢀ
Riso = 50 ꢀ
œ10
œ15
100k
1M
10M
100M
10
100
1000
10000
Frequency (Hz)
Load Capacitance (pF)
C024
C027
G = 1, CLOAD = 1.2 nF
G = 1, VO = 10 mVPP
图 14. Series Resistance for Capacitive Load Stability
图 15. Overshoot vs Capacitive Load, G = 1
50
0
œ20
Riso = 0 ꢀ, 5.5 V
Riso = 25 ꢀ, 5.5 V
Riso = 0 ꢀ, 2.7 V
Riso = 25 ꢀ, 2.7 V
Riso = 10 ꢀ, 5.5 V
Riso = 50 ꢀ, 5.5 V
Riso = 10 ꢀ, 2.7 V
Riso = 50 ꢀ, 2.7 V
HD2, Gain = 1
HD3, Gain = 1
HD2, Gain = 2
HD3, Gain = 2
45
40
35
30
25
20
15
10
5
œ40
œ60
œ80
œ100
œ120
œ140
œ160
œ180
0
10
100
1000
10000
1k
10k
100k
1M
Load Capacitance (pF)
Input Frequency (Hz)
C027
C010
G = –1, VO = 10 mVPP
VS = 5.5 V, VO = 2 VPP, RLOAD = 600 Ω
图 16. Overshoot vs Capacitive Load, G = –1
图 17. Distortion vs Frequency for Various Gains
0
œ20
0
œ20
HD2, Vs = 5.5 V
HD3, Vs = 5.5 V
HD2, Vs = 3.3 V
HD3, Vs = 3.3 V
HD2, Vs = 5.5 V
HD3, Vs = 5.5 V
HD2, Vs = 3.3 V
HD3, Vs = 3.3 V
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ180
œ100
œ120
œ140
œ160
1k
10k
100k
1M
1k
10k
100k
1M
Input Frequency (Hz)
Input Frequency (Hz)
C010
C010
G = 1, VO = 2 VPP, RLOAD = 600 Ω
G = 2, VO = 2 VPP, RLOAD = 600 Ω
图 18. Distortion vs Frequency for Various Power Supplies
图 19. Distortion vs Frequency for Various Power Supplies
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ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
0
0
f = 1 kHz
2 kꢀ
1 kꢀ
600 ꢀ
œ20
œ20
f = 10 kHz
f = 100 kHz
f = 1 MHz
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ100
œ120
œ140
œ160
1
2
3
4
1k
10k
100k
1M
Output Voltage (VPP
)
Input Frequency (Hz)
C013
C010
G = 1, RLOAD = 600 Ω
G = 1, VO = 2 VPP , RLOAD = 600 Ω
图 20. Total Harmonic Distortion vs Output Voltage for
图 21. Total Harmonic Distortion vs Frequency for Various
Various Frequencies
Loads
1000
1000
100
10
100
10
1
1
0.1
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C015
C015
图 22. Voltage Noise Density vs Frequency
图 23. Current Noise Density vs Frequency
-80
-100
-120
-140
-160
-180
Time (1 s/div)
10
100
1k
10k
100k
1M
10M
C020
Frequency (Hz)
图 25. 0.1-Hz to 10-Hz Voltage Noise
图 24. Crosstalk vs Frequency
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Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
180
160
140
120
100
80
6
5
4
3
2
1
0
VS = 5 V
VS = 3.3 V
Rising, Gain = 1
Falling, Gain = 1
Rising, Gain = 2
Falling, Gain = 2
60
40
20
0
0
1
2
3
4
1k
10k
100k
1M
10M
100M
1G
Output Voltage Step (V)
C018
Frequency (Hz)
图 26. Slew Rate vs Output Step Size
图 27. Maximum Output Voltage vs Frequency
Time (200 ns/div)
Time (200 ns/div)
C020
C019
G = 1, VO = 4-V step
G = –1, VO = 4-V step
图 28. Large-Signal Pulse Response
图 29. Large-Signal Pulse Response
Time (200 ns/div)
Time (200 ns/div)
C029
C029
G = 1, VO = 10-mV step
G = –1, VO = 10-mV step
图 30. Small-Signal Pulse Response
图 31. Small-Signal Pulse Response
16
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ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
200
150
100
50
200
150
100
50
16-bit settling
16-bit settling
0
0
œ50
œ100
œ150
œ200
œ50
œ100
œ150
œ200
16-bit settling
800
16-bit settling
800
0
200
400
600
1000
0
200
400
600
1000
Time (ns)
Time (ns)
C032
C032
VO = 3.6-V step at t = 0 s
VO = 3.6-V step at t = 0 s
图 32. 16-Bit Negative Settling Time
图 33. 16-Bit Positive Settling Time
4
3
0.8
4
3
2
1
0
0.6
0.4
0.2
0.0
-0.2
2
1
0
œ1
œ2
œ3
œ4
Input
Input
Output
Output
-1
Time (200 µs/div)
Time (100 ns/div)
C031
C021
VS = ±2.75 V, G = 1
VS = ±2.75 V, G = 5
图 34. No Phase Reversal
图 35. Positive Overload Recovery
20
15
10
5
0.2
1
Input
Output
0.0
-0.2
-0.4
-0.6
-0.8
0
-1
-2
-3
0
-4
Time (100 ns/div)
C021
Offset Voltage (µV)
C013
VS = ±2.75 V, G = 5
Distribution taken from 3139 amplifiers
图 37. Input Offset Voltage Distribution
图 36. Negative Overload Recovery
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Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
20
15
10
5
20
15
10
5
0
0
Offset Voltage (µV)
Offset Voltage (µV)
C013
C013
Distribution taken from 80 amplifiers, TA = 125°C
Distribution taken from 80 amplifiers, TA = 85°C
图 38. Input Offset Voltage Distribution
图 39. Input Offset Voltage Distribution
400
20
300
200
15
10
5
100
0
œ100
œ200
œ300
œ400
0
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C001
Offset Voltage (µV)
C013
7 typical units shown
Distribution taken from 80 amplifiers, TA = –40°C
图 40. Input Offset Voltage Distribution
图 41. Input Offset Voltage vs Temperature
30
35
30
25
20
15
10
5
25
20
15
10
5
0
0
Input Bias Current (µA)
Offset Voltage Drift (µV/°C)
C013
C013
Distribution taken from 83 amplifiers, TA = –40°C to +125°C
Distribution taken from 3139 amplifiers
图 42. Input Offset Voltage Drift Distribution
图 43. Input Bias Current Distribution
18
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ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
5
4
3
2
1
0
30
25
20
15
10
5
IB -
IB+
0
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C001
Input Offset Current (nA)
C013
Distribution taken from 3139 amplifiers
图 45. Input Offset Current Distribution
图 44. Input Bias Current vs Temperature
1000
100
10
30
20
VS = ±2.75 V, (Vœ) ≤ VCM ≤ (V+) œ 1.15
VS = ±1.35 V, (Vœ) ≤ VCM ≤ (V+) œ 1.15 V
10
0
œ10
œ20
œ30
1
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C001
C001
图 46. Input Offset Current vs Temperature
图 47. Common-Mode Rejection Ratio vs Temperature
30
20
10
0
3.0
2.0
VS = ±1.35 V
VS = ±2.5 V
1.0
0.0
-10
-20
-30
œ1.0
œ2.0
œ3.0
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C001
C001
2.7 V ≤ VS ≤ 5.5 V
RLOAD = 10 kΩ
图 48. Power-Supply Rejection Ratio vs Temperature
图 49. Open-Loop Gain vs Temperature with 10-kΩ Load
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Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
5.0
1
4.0
0
3.0
2.0
œ1
œ2
œ3
œ4
œ5
VS = ±1.35 V
1.0
0.0
œ1.0
œ2.0
œ3.0
œ4.0
œ5.0
VS = ±2.5 V
œ75 œ50 œ25
0
25
50
75
100 125 150
œ4
œ2
0
2
4
Temperature (°C)
VCM (V)
C001
C001
RLOAD = 600 Ω
High-drive mode, VS = ±2.5 V
图 50. Open-Loop Gain vs Temperature with 600-Ω Load
图 51. Input Bias Current vs Input Common-Mode Voltage
50
40
50
30
25
20
10
VCM = œ2.5 V
0
0
VCM = 1.35 V
œ10
œ20
œ25
œ30
œ40
œ50
VS = ±2.75 V
VS = ±1.35 V
œ50
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
œ3
œ2
œ1
0
1
2
VSUPPLY (V)
VCM (V)
C001
C001
6 typical units shown, VS = ±1.35 V to ±2.75 V
6 typical units shown, VS = ±2.5 V
图 52. Input Offset Voltage vs Power-Supply Voltage
图 53. Input Offset Voltage vs Common-Mode Voltage
3
200
180
25°C
2
œ40°C
ISC, Sink
160
1
125°C
140
0
ISC, Source
120
-1
125°C
100
80
-2
œ40°C
25°C
60
-3
œ75 œ50 œ25
0
25
50
75
100 125 150
0
20
40
60
80 100 120 140 160 180 200
Temperature (°C)
IO (mA)
C001
C001
图 55. Short-Circuit Current vs Temperature
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图 54. Output Voltage vs Output Current
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Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
3
2.5
2
3
2.5
2
VS = ±2.5 V
VS = ±1.35 V
1.5
1
1.5
1
0.5
0
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
œ75 œ50 œ25
0
25
50
75
100 125 150
Supply Voltage (V)
Temperature (°C)
C001
C001
High-drive mode
图 56. High-Drive Mode Quiescent Current vs Power-Supply
图 57. High-Drive Mode Quiescent Current vs Temperature
Voltage
450
400
400
350
300
250
200
150
100
50
350
VS = ±2.5 V
300
VS = ±1.35 V
250
200
150
100
50
0
0
œ75 œ50 œ25
0
25
50
75
100 125 150
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Temperature (°C)
Supply Voltage (V)
C001
C001
MODE pin connected to V+
图 58. Low-Power Mode Quiescent Current vs Temperature
Low-drive mode, MODE pin connected to V+
图 59. Low-Power Mode Quiescent Current vs Power-Supply
Voltage
4
2
4
3
2
1
0
4
2
4
3
2
1
0
MODE Pin Voltage
IQ
MODE Pin Voltage
0
0
IQ
œ2
œ4
œ2
œ4
Time (200 ns/div)
Time (200 ns/div)
C035
C035
VS = ±2.75 V
VS = ±2.75 V
图 60. Quiescent Current When MODE transitions From High
图 61. Quiescent Current When MODE Transitions From Low
To Low
To High
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Typical Characteristics (接下页)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
3
200
150
100
50
4
2.5
2
MODE Pin
3
16-bit settling
2
1.5
1
1
0.5
0
0
0
-0.5
-1
œ50
œ100
œ150
œ200
-1
-2
-3
-4
16-bit settling
800
-1.5
-2
-2.5
-3
œ200
0
200
400
600
1000
0
0.2
0.4
0.6
Time (s)
0.8
1
1.2
C032
Time (ns)
D001
VO = 3.8 VDC
OPA625 powered on in high-drive mode at t = 0 s, PCB
dimensions: 4 in2, 2 layer, FR4
图 62. Output Voltage When MODE Transitions From High
图 63. Warm-Up Time
To Low
22
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7 Parameter Measurement Information
7.1 DC Parameter Measurements
The circuit shown in 图 64 is used to measure the dc input offset related parameters of the OPAx625. Input offset
voltage, power supply rejection ratio, common mode rejection ratio and open loop gain can be measured with
this circuit. The basic test procedure requires setting the inputs (the power-supply voltage, VS, and the common-
mode voltage, VCM), to the desired values. VO is set to the desired value by adjusting the loop-drive voltage while
measuring VO. After all inputs are configured, measure the input offset at the VX measurement point. Calculate
the input offset voltage by dividing the measured result by 101. Changing the voltages on the various inputs
changes the input offset voltage. The input parameters can be measured according to the relationships illustrated
in 公式 1 through 公式 5.
RCOMP = 1 kꢀ
CCOMP = 0.1 mF
RB = 1.26 kꢀ
+
Loop
Drive
30 V
œ
V+
OPA551
+
VX
VOS
OPA625
+
RA = 12.6 ꢀ
RIN = 12.6 ꢀ
-30 V
VO
RLOAD
V-
+
VCM
œ
图 64. DC-Parameters Measurement Circuit
VX
VOS
=
101
(1)
(2)
(3)
(4)
(5)
DVOS
DTemperature
DVOS
DVSUPPLY
DVOS
DVCM
VOSDrift
=
PSRR =
CMRR =
DVO
DVOS
AOL =
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7.2 Transient Parameter Measurements
The circuit shown in 图 65 is used to measure the transient response of the OPAx625. Configure V+, V–, RISO
,
RLOAD, and CLOAD as desired. Monitor the input and output voltages on an oscilloscope or other signal analyzer.
Use this circuit to measure large-signal and small-signal transient response, slew rate, overshoot, and capacitive-
load stability.
V+
RISO
OPA625
+
O-Scope
CLOAD
V-
RLOAD
+
Input
œ
图 65. Pulse-Response Measurement Circuit
7.3 AC Parameter Measurements
The circuit shown in 图 66 is used to measure the ac parameters of the OPAx625. Configure V+, V–, and CLOAD
as desired. The THS4271 are used to buffer the input and output of the OPAx625 to prevent loading by the gain
phase analyzer. Monitor the input and output voltages on a gain phase analyzer. Use this circuit to measure the
gain bandwidth product, and open-loop gain versus frequency versus capacitive load.
249 ꢀ
249 ꢀ
50 ꢀ
+
Gain/Phase
Analyzer
THS4271
249 ꢀ
249 ꢀ
50 ꢀ
1 kꢀ
1 kꢀ
+
THS4271
OPA625
+
CLOAD
图 66. AC-Parameters Measurement Circuit
24
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7.4 Noise Parameter Measurements
The circuit shown in 图 67 is used to measure the voltage noise of the OPAx625. Configure V+, V–, and CLOAD
as desired.
10 ꢀ
1 kꢀ
Spectrum
Analyzer
OPA625
+
CLOAD
图 67. Voltage Noise Measurement Circuit
The circuit shown in 图 68 is used to measure the current noise of the OPAx625. Configure V+, V– and CLOAD as
desired.
Spectrum
Analyzer
OPA625
+
CLOAD
100 kꢀ
图 68. Current Noise Measurement Circuit
The circuit shown in 图 69 is used to measure the OPAx625 0.1-Hz to 10-Hz voltage noise. Configure V+, V–,
and CLOAD as desired.
0.1 Hz to 10 Hz
Active Bandpass Filter
10 ꢀ
1 kꢀ
O-Scope
OPA625
+
40 db/dec
-80 db/dec
CLOAD
图 69. 0.1-Hz to 10-Hz Voltage-Noise Measurement Circuit
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8 Detailed Description
8.1 Overview
The OPAx625 is a fast-settling, high slew rate, high-bandwidth, voltage-feedback operational amplifier. Low
offset and low offset drift combine with the superior dynamic performance and very low output impedance,
resulting in an amplifier suited for driving 16-bit SAR ADCs, and buffering precision voltage references in
industrial applications. The OPAx625 is comprised of a low-noise input stage, a slew boost stage, and a rail-to-
rail output stage. A mode bias select feature allows the OPAx625 to be configured in a high-drive mode and a
low-power mode. High-drive mode is used when driving SAR ADCs during the ADC signal acquisition period.
The OPAx625 is also configurable in low-power mode while the SAR ADC is converting the acquired signal, thus
saving overall system power. To facilitate a fast transition from low-power mode to high-drive mode, the
OPAx625 does not completely shut down while in low-power mode; rather, the device remains as an active
amplifier with a lower bandwidth (1 MHz) and relaxed dc specifications.
8.2 Functional Block Diagram
MODE
V+
Mode Select / Bias
+IN
-IN
Common
Mode
Feedback
Low Noise Input
Stage
Slew
Boost
Rail-to-Rail
Output Stage
OUT
Frequency
Compensation
Network
V-
26
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8.3 Feature Description
8.3.1 SAR ADC Driver
The OPAx625 is designed to drive precision (16-bit and 18-bit) SAR ADCs at sample rates up to 1 MSPS. The
combination of low output impedance, low THD, low noise, and fast settling time make the OPAx625 the ideal
choice for driving both the SAR ADC inputs, as well as the reference input to the ADC. Internal slew boost
circuitry increases the slew rate as a function of the input signal magnitude, resulting in settling from a 4-V step
input to 16-bit levels within 280 ns. Low output impedance (1 Ω at 1 MHz) ensures capacitive load stability with
minimal overshoot.
8.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD
circuitry and its relevance to an electrical overstress event is helpful. See 图 70 for an illustration of the ESD
circuits contained in the OPAx625. The ESD protection circuitry involves several current-steering diodes
connected from the input and output pins and routed back to the internal power-supply lines, where the diodes
meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
V+
Power Supply
ESD Cell
MODE
30 ꢀ
+IN
+
30 ꢀ
œ
OUT
œ IN
Vœ
图 70. Simplified ESD Circuit
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8.4 Device Functional Modes
The OPAx625 has two functional modes: high-drive and low-power. In low-power mode, the quiescent current of
the OPAx625 is reduced to 270 µA (typ), and results in significantly lower bandwidth, higher noise, and lower
output current drive. The OPAx625 transitions from low-power mode to high-drive mode in 170 ns.
tCONV-MAX
tCONV-MIN
tCONV-MAX
tCONV-MIN
ADC State
MODE
Acquisition
Conversion
Conversion
tsettle + tLP-HD
tmargin
tHD-LP
tLP-HD
tHD-LP
OPAx625
State
Low-Power Mode
High-Drive Mode
图 71. Simplified Timing Diagram: Power-Scaling Precision Signal Chain
8.4.1 High-Drive Mode
Place the OPAx625 into high-drive mode by applying a logic level low to the MODE pin. The MODE pin can be
driven by a general-purpose input/output (GPIO) from the system controller, from discrete logic gates, or can be
connected directly to the V– pin. Do not leave the MODE pin floating. When driving the MODE pin from a
microcontroller GPIO, make sure that the GPIO is not placed into a high-impedance state. Placing the GPIO into
a high impedance state results in the MODE pin essentially floating, and is not recommended. Do not drive the
MODE pin voltage below the voltage at the V– pin; see the Absolute Maximum Ratings for the allowable voltage
to drive the MODE pin. Use the MODE pin to force the OPAx625 in either the high-drive mode or the low-power
mode. The OPAx625 has 120-MHz gain bandwidth, 2.5-nV/√Hz input-referred noise, and consumes just 2 mA of
quiescent current in high-drive mode. In addition, the OPAx625 also has an offset voltage of 100 µV (max) and
offset voltage drift of 1 µV/°C (typ). This combination of high precision, high speed, and low noise makes this
device suitable for use as an input driver for high-precision, high-throughput SAR ADCs such as ADS88xx family
of SAR ADC, as shown in 图 73.
In high-drive mode, the OPAx625 is fully specified as a wideband, low-noise, low-distortion precision amplifier.
High-drive mode is the primary mode of operation of the OPAx625 when driving the inputs of a SAR ADC during
the signal acquisition period just before the start of the conversion period. Placing the OPAx625 into the high-
drive mode before the acquisition period is complete, and before the start of the conversion period, allows the
OPAx625 to settle to the final value just prior to the conversion. When the ADC is converting the input signal,
and therefore no longer acquiring the signal, place the OPAx625 into the low-power mode to reduce system
power. Using low-power mode allows the OPAx625 power consumption to scale directly with the sample rate.
The OPAx625 is unique in that the switching between the modes occurs in 170 ns (typ). This fast switching is
achieved by the architecture of the OPAx625 during low-power mode; see the Low-Power Mode section for more
information.
28
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Device Functional Modes (接下页)
8.4.2 Low-Power Mode
Place the OPAx625 low-power mode by applying a logic level high to the MODE pin. The MODE pin can be
driven by a GPIO from the system controller, from discrete logic gates, or can be connected to directly to the V+
pin. Do not leave the MODE pin floating. When driving the MODE pin from a microcontroller GPIO, make sure
that the GPIO is not placed into a high-impedance state. Placing the GPIO into a high-impedance state results in
the MODE pin essentially floating, and is not recommended. Do not allow the MODE pin voltage to exceed the
voltage at the V+ pin; see the Absolute Maximum Ratings for the allowable voltage to drive the MODE pin.
In low-power mode, the OPAx625 is fully specified as a general-purpose operational amplifier. The MODE signal
can be controlled so that the OPAx625 is placed in high-drive mode just before the ADC enters the acquisition
phase. This configuration makes sure that the voltage on the antialiasing filter capacitor settles to the required
precision before the acquisition period is complete. The power consumed by the OPAx625 scales with the
throughput of the system when operated in this manner. This feature is extremely useful in power-critical
applications and variable-throughput data acquisition systems.
The OPAx625 is unique in that the switching between the modes occurs in 170 ns (typ). This fast switching is
achieved by the architecture of the OPAx625 during low-power mode. Most amplifiers in power-down or shut-
down mode consume very minimal power, but are also not operating in a linear fashion. For example, the output
of a typical amplifier, when disabled, can be placed into a high-impedance state, and thus unable to drive any
load whatsoever. Switching from a shut-down state to a linear state requires charging internal capacitances and
bias points to a level within the linear operating range. Typically, this switch can take several microseconds or
longer. This problem is solved with the OPAx625. The OPAx625 operates as a linear operational amplifier in low-
power mode, and the output tracks the input signal, but with a lower bandwidth and slightly higher offset and
noise. Switching from low-power mode to high-drive mode and settling to 16-bit levels occurs in 170 ns (typ) as a
result of maintaining operation in a linear fashion throughout the duration of each mode. This configuration allows
for dynamic power scaling, while still maintaining high throughput rates.
200
150
100
50
4
MODE Pin
3
16-bit settling
2
1
0
0
œ50
œ100
œ150
œ200
-1
-2
-3
-4
16-bit settling
800
œ200
0
200
400
600
1000
C032
Time (ns)
图 72. Output Voltage when Mode Pin Changes High to Low
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx625 is a precision, high-speed, voltage-feedback operational amplifier. Fast settling to 16-bit levels, low
THD, and low noise make the OPAx625 suitable for driving SAR ADC inputs and buffering precision voltage
references. With a wide power-supply voltage range from 2.7 V to 5.5 V, and operating from –40°C to +125°C,
the OPAx625 is suitable for a variety of high-speed, industrial applications. The following sections show
application information for the OPAx625. For simplicity, power-supply decoupling capacitors are not shown in
these diagrams.
9.2 Typical Applications
9.2.1 Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
1 kꢀ
1 kꢀ
Mode
Control
5 V
Input
Voltage
RFLT
4.7 ꢀ
VREF
REF
3.3 V
OPA625
+
VREF / 4
AVDD
10 nF
CFLT
ADS8860
GND
4.7 ꢀ
RFLT
图 73. Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
9.2.1.1 Design Requirements
SAR ADCs, such as the ADS8860, use sampling capacitors on the data converter input. During the signal
acquisition phase, these sampling capacitors are connected to the ADC analog input terminals, AINP and AINN,
through a set of switches. After the acquisition period has elapsed, the internal sampling capacitors are
disconnected from the input terminals and connected to the input of the ADC through a second set of switches,
during this period the ADC is performing the analog-to-digital conversion. 图 74 illustrates this architecture.
SAR ADC
RSW
!Lbt
CS/H
RSW
CS/H
!Lbb
图 74. Simplified SAR ADC Input
30
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Typical Applications (接下页)
The SAR ADC inputs and sampling capacitors must be driven by the OPA625 to 16-bit levels within the
acquisition time of the ADC. For the example illustrated in 图 73, the OPA625 is used to drive the ADS8860 at a
sample rate of 1 MSPS.
9.2.1.2 Detailed Design Procedure
The circuit illustrated in 图 73 consists of the SAR ADC driver, a low-pass filter and the SAR ADC. The SAR ADC
driver circuit consists of an OPA625 configured in an inverting gain of 1. The filter consists of RFLT and CFLT
,
connected between the output of the OPA625 and input of the ADS8860. Selecting the proper values for each of
these passive components is critical to obtain the best performance from the ADC. Capacitor CFLT serves as a
charge reservoir, providing the necessary charge to the ADC sampling capacitors. The dynamic load presented
by the ADC creates a glitch on the filter capacitor, CFLT. To minimize the magnitude of this glitch, choose a value
for CFLT large enough to maintain a glitch amplitude of less than 100 mV. Maintaining such a low glitch amplitude
at the amplifier output makes sure that the amplifier remains in the linear operating region, and results in a
minimum settling time. Using 公式 6, a 10-nF capacitor is selected for CFLT
.
CFLT í 15ìCSH
(6)
Connecting a 10-nF capacitor directly to the output of the OPA625 degrades the OPA625 phase margin and
results in stability and settling-time problems. To properly drive the 10-nF capacitor, use a series resistor (RFLT
)
to isolate the capacitor, CFLT, from the OPA625. RFLT must be sized based upon several constraints. To
determination a suitable value for RFLT, consider the impact upon the THD due to the voltage divider effect from
RFLT reacting with the switch resistance (RSW) of the ADC input circuit, as well as the impact of the output
impedance upon amplifier stability. In this example, 4.7-Ω resistors are selected. In this design example, 图 16
can be used to estimate a suitable value for RISO. RISO represents the total resistance in series with CFLT, and in
this example is equivalent to 2 × RFLT
.
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design, TIDU014, "Power-optimized 16-bit 1MSPS
Data Acquisition Block for Lowest Distortion and Noise Reference Design".
9.2.1.3 Application Curves
图 75 illustrates the performance of the circuit shown in 图 73.
0
THD = -110.8 dBc
SNR = 91.88 dB
SINAD = 91.86 dB
ENOB = 14.97
-25
-50
-75
-115.91 dBc (Third Harmonic)
-100
-125
-150
-175
0
50 100 150 200 250 300 350 400 450 500
Frequency (kHz)
4096-point FFT at 1 MSPS, fIN = 10 kHz , VIN = 1.5 VRMS
图 75. ADC Output FFT for 图 73
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9.2.2 Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
In order to operate a high-resolution, 16-bit ADC at its maximum throughput, the full-scale voltage step must
settle to better than 16-bit accuracy at the ADC inputs within the minimum specified acquisition time (tACQ). This
settling imposes very stringent requirements on the driver amplifier in terms of large-signal bandwidth, slew rate,
and settling time. 图 76 illustrates a typical multiplexed ADC driver application using the OPA625.
1.5 pF
8 kꢀ
2 kꢀ
Mode
Control
5 V
VREF
4.5 V
5 V
RFLT
12.4 ꢀ
3.3 V
Mux
10 ꢀ
10 ꢀ
OPA625
+
OPA320
+
REF
AVDD
1 nF
CFLT
TS5A3159
ADS8860
GND
100 pF
22 µF
Input
Voltage
12.4 ꢀ
RFLT
图 76. Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
9.2.2.1 Design Requirements
To optimize this circuit for performance, this design does not allow any large signal input transients at the inputs
of the driver circuit for a small quiet-time period (tQT) towards the end of the previous conversion. The input step
voltage can appear anytime from the beginning of conversion (CONVST rising edge) until the elapse of a half
cycle time (0.5 × tCYC). This timing constraint on the input step allows a minimum settling time of (tQT + tACQ) for
the ADC input to settle within the required accuracy, in the worst-case scenario. This provides more time for the
amplifier's output to slew and settle within the required accuracy before the next conversion starts. 图 77
illustrates this timing sequence.
Transients Allowed
No Transients Allowed
CONVST
0.5 x tCYC_MIN = 500 ns
tQT
tACQ
Slewing
Settling
VIN
tCYC_MIN = 1 µs
Conversion
Sampling
图 77. Timing Diagram for Input Signals
32
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9.2.2.2 Detailed Design Procedure
An ADC input driver circuit mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier
is used for signal conditioning of the input voltage and its low output impedance provides a buffer between the
signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switched-
capacitor input stage of the ADC as well as acts as an anti-aliasing filter to band-limit the wideband noise
contributed by the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the
circuit, driven primarily by the following requirements:
•
The RFLTCFLT filter bandwidth should be low to band-limit the noise fed into the input of the ADC thereby
increasing the signal-to-noise ratio (SNR) of the system.
•
The overall system bandwidth should be large enough to accommodate optimal settling of the input signal at
the ADC input before the start of conversion.
CFLT is chosen based upon 公式 7 . CFLT is chosen to be 1 nF.
CFLT í 15ìCSH
(7)
Connecting a 1-nF capacitor directly to the output of the OPA625 would degrade the OPA625 phase margin and
result in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, RFLT, is used
to isolate the capacitor, CFLT, from the OPA625. RFLT must be sized based upon several constraints. To
determination a suitable value for RFLT, the system designer must consider the impact upon the THD due to the
voltage divider effect from RFLT reacting with the switch resistance, RSW, of the ADC input circuit as well as the
impact of the output impedance upon amplifier stability. In this example 12.4-Ω resistors are selected. In this
design example, 图 15 can be used to estimate a suitable value for RISO. RISO represents the total resistance in
series with CFLT, which in this example is equivalent to 2 × RFLT
.
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design, TIDU012, "Power-optimized 16-bit 1MSPS
Data Acquisition Block for Lowest Distortion and Noise Reference Design".
9.2.2.3 Application Curves
图 78 illustrates the performance of the circuit shown in 图 76.
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
500
1000
1500
2000
0
500
1000
1500
2000
Time (ns)
Time (ns)
图 78. Positive Transient Response for 图 76
图 79. Negative Transient Response for 图 76
版权 © 2015, Texas Instruments Incorporated
33
OPA625, OPA2625
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
www.ti.com.cn
10 Power Supply Recommendations
The OPAx625 is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics. Place bypass capacitors close to the power-supply pins
to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on
bypass capacitor placement, see the Layout section.
CAUTION
Supply voltages larger than 6 V can cause permanent damage to the device. See to
the Absolute Maximum Ratings section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Use bypass capacitors to reduce the noise coupled from the power supply. Connect low ESR, ceramic,
bypass capacitors between the power supply pins (V+ and V–) and the ground plane. Place the bypass
capacitors as close to the device as possible with the 100-nF capacitor closest to the device, as indicated in
图 80. For single-supply applications, bypass capacitors on the V– pin are not required.
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
SLOA089, Circuit Board Layout Techniques.
•
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
•
•
Minimize parasitic coupling between +IN and OUT for best ac performance.
Place the external components as close to the device as possible. As shown in 图 80, keeping RF, CF, and
RG close to the inverting input will minimize parasitic capacitance.
•
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
34
版权 © 2015, Texas Instruments Incorporated
OPA625, OPA2625
www.ti.com.cn
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
11.2 Layout Example
Power Supply
100 nF
1 µF
RIN
RG
+
Input
Output
RF
CF
(Schematic Representation)
Positive Power Supply
1 µF
Ground
Use Low-ESR, ceramic bypass
capacitors.
Place 100 nF capacitor close to the
device
100 nF
1
2
3
OUT
V-
V+
MODE
-IN
6
5
4
Output
Ground
Input
Ground
MODE pin can be connected to a GPIO on the system
controller for applications requiring the lowest power or
it can be connected to ground for active mode only
+IN
Ground
RG
RIN
Place close to the device to
reduce parasitic capacitance
RF
CF
Place close to the device to
reduce parasitic capacitance
图 80. PCB Layout Example
版权 © 2015, Texas Instruments Incorporated
35
OPA625, OPA2625
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
12.1.1.2 TI 高精度设计
欲获取 TI 高精度设计，请访问 http://www.ti.com.cn/ww/analog/precision-designs/。TI 高精度设计是由 TI 公司高
精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选择、仿真、完整印刷电路板
(PCB) 电路原理图和布局布线、物料清单以及性能测量结果。
12.2 文档支持
12.2.1 相关文档
《16 位、1MSPS 多路复用数据采集参考设计指南》，TIDUAD9
12.3 相关链接
表 1
接。
列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买链
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
OPA625
OPA2625
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided AS IS by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
36
版权 © 2015, Texas Instruments Incorporated
OPA625, OPA2625
www.ti.com.cn
ZHCSDL0A –APRIL 2015–REVISED OCTOBER 2015
12.5 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA is a trademark of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2625IDGSR
OPA2625IDGST
OPA625IDBVR
OPA625IDBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOT-23
SOT-23
DGS
DGS
DBV
DBV
10
10
6
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2625
2625
O625
O625
NIPDAUAG
NIPDAU
6
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2625IDGSR
OPA2625IDGST
OPA625IDBVR
OPA625IDBVT
VSSOP
VSSOP
SOT-23
SOT-23
DGS
DGS
DBV
DBV
10
10
6
2500
250
330.0
330.0
178.0
178.0
12.4
12.4
9.0
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
4.0
4.0
12.0
12.0
8.0
Q1
Q1
Q3
Q3
3000
250
3.23
3.23
3.17
3.17
1.37
1.37
6
9.0
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2625IDGSR
OPA2625IDGST
OPA625IDBVR
OPA625IDBVT
VSSOP
VSSOP
SOT-23
SOT-23
DGS
DGS
DBV
DBV
10
10
6
2500
250
366.0
366.0
180.0
180.0
364.0
364.0
180.0
180.0
50.0
50.0
18.0
18.0
3000
250
6
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
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Copyright © 2021 德州仪器半导体技术（上海）有限公司
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