OPA2834 [TI]
超低功耗、50MHz 轨到轨输出、负电源轨输入、电压反馈运算放大器;
| 型号： | OPA2834 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 超低功耗、50MHz 轨到轨输出、负电源轨输入、电压反馈运算放大器 放大器 运算放大器 |
| 文件： | 总34页 (文件大小：1949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA2834
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
OPA2834 50MHz、170µA、负电源轨输入、轨至轨输出、电压反馈放大器
1 特性
3 说明
1
•
超低功耗：
OPA2834 是一款双通道超低功耗、轨至轨输出、负电
源轨输入、电压反馈 (VFB) 运算放大器，设计的工作
电源电压范围为 2.7V 至 5.4V（单电源）或 ±1.35V 至
±2.7V（双电源）。这款放大器每通道仅消耗 170µA
的电流，单位增益带宽为 50MHz，性能/功耗比处于轨
至轨放大器的行业领先水平。
–
–
电源电压：2.7V 至 5.4V
静态电流 (IQ)：170µA/ch（典型值）
•
•
•
•
带宽：50MHz (G = 1V/V)
压摆率：26V/µs
稳定时间 (0.1%)：88ns (2VSTEP
)
HD2、HD3：10kHz (2VPP) 时分别为 –131dBc 和
–146dBc
对于 要求 低功耗的电池供电和便携式应用，OPA2834
可提供出色的带宽 IQ 比。OPA2834 可提供极低的失
真，非常适用于数据采集系统和麦克风前置放大器。
•
•
•
输入电压噪声：12nV/√Hz (f = 10kHz)
输入失调电压：350µV（最大值为 ±1.9mV）
负电源轨输入，轨至轨输出 (RRO)
请参见器件比较表，了解如何选择德州仪器 (TI) 提供
的低功耗、低噪声 5V 放大器，以及 20MHz 至
300MHz 的增益带宽产品。
–
输入电压范围：–0.2V 至 3.9V
（5V 电源）
•
工作温度范围：
–40°C 至 +125°C
器件信息(1)
器件型号
OPA2834
封装
VSSOP (8)
封装尺寸（标称值）
3.00mm × 3.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
•
•
•
•
电源电流检测
低功耗信号调节
电池供电 应用
便携式录音机
低功耗 SAR 和 Δ-Σ ADC 驱动器
便携式器件
1kHz FFT 图
低侧电流分流监控
（VOUT = 1VRMS，RL = 100kΩ，G = 1）
40
LOAD
RF‘
VS
20
0
VS
œ
RG
‘
‘
REXT
-20
-40
-60
-80
-100
-120
-140
-160
œ
+
RG
RSH
OPA2834-2
CEXT
+
OPA2834-1
RF‘
Short-
Circuit Fault
Detection
VTH
+
TLV3201
œ
Interrupt
VREF
VS
0
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k
Frequency (Hz)
µC
FFT_
ADS7056
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS973
OPA2834
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
8.2 Functional Block Diagrams ..................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 20
9.1 Application Information............................................ 21
9.2 Typical Applications ................................................ 21
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics: 3V to 5V........................... 5
7.6 Typical Characteristics: Vs = 5 V .............................. 6
7.7 Typical Characteristics: VS = 3.0 V........................... 9
9
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Examples................................................... 26
12 器件和文档支持 ..................................................... 27
12.1 文档支持................................................................ 27
12.2 接收文档更新通知 ................................................. 27
12.3 社区资源................................................................ 27
12.4 商标....................................................................... 27
12.5 静电放电警告......................................................... 27
12.6 Glossary................................................................ 27
13 机械、封装和可订购信息....................................... 27
7.8 Typical Characteristics: ±2.5-V to ±1.5-V Split
Supply ...................................................................... 12
8
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2019) to Revision A
Page
•
已更改 将文档状态从 APL 更改为生产数据 ............................................................................................................................ 1
2
Copyright © 2019, Texas Instruments Incorporated
OPA2834
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ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
5 Device Comparison Table
INPUT NOISE
VOLTAGE
(nV/√Hz)
Av = +1 BANDWIDTH
5-V IQ
(mA, Typ 25°C)
2-VPP THD
(dBc, 100 kHz) INPUT/OUTPUT
RAIL-TO-RAIL
PART NUMBER CHANNELS
Single Channel
(MHz)
OPA2834
OPA2835
OPA2836
OPA2837
OPA838
2
2
2
2
1
50
56
0.17
0.25
1.0
12
9.4
4.6
4.7
1.9
VS–, output
—
–104
–118
–118
–110
VS–, output
VS–, output
VS–, output
VS–, output
OPA835
OPA836
OPA837
—
205
105
—
0.6
0.96
6 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
VOUT1
VIN1-
VIN1+
VS-
VS+
1
2
3
4
8
7
6
5
VOUT2
A
VIN2-
VIN2+
B
Pin Functions
PIN
FUNCTION(1)
DESCRIPTION
NO.
1
NAME
VOUT1
VIN1–
VIN1+
VS–
O
I
Amplifier 1 output pin
2
Amplifier 1 inverting input pin
Amplifier 1 noninverting input pin
Negative power-supply pin
Amplifier 2 noninverting input pin
Amplifier 2 inverting input pin
Amplifier 2 output pin
3
I
4
P
I
5
VIN2+
VIN2–
VOUT2
VS+
6
I
7
O
P
8
Positive power-supply input
(1) I = input, O = output, and P = power.
Copyright © 2019, Texas Instruments Incorporated
3
OPA2834
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.5
UNIT
V
Supply voltage (total bipolar supplies)(2)
VS– to VS+
Supply turnon/off maximum dV/dT(3)
1
V/µs
V
VI
VID
II
Input voltage
VS– – 0.5
VS+ + 0.5
±1
Differential input voltage
Continuous input current(4)
Continuous output current(5)
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature
Storage temperature
V
±10
mA
mA
IO
±20
See Thermal Information
TJ
150
°C
°C
°C
TA
–40
–65
125
150
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VS is the total supply voltage given by VS = VS+ – VS–
.
(3) Staying below this ± supply turnon edge rate prevents the edge-triggered ESD absorption device across the supply pins from turning on.
(4) Continuous input current limit for both the ESD diodes to supply pins and amplifier differential input clamp diodes. The differential input
clamp diodes limit the voltage across them to 1 V with this continuous input current flowing through them.
(5) Long-term continuous current for electromigration limits.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification
JESD22(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
5
MAX
5.4
UNIT
V
VS+
TA
Single-supply positive voltage
Ambient temperature
–40
25
125
°C
7.4 Thermal Information
OPA2834
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
192.6
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
79.3
114.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
15.7
YJB
112.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
OPA2834
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ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
7.5 Electrical Characteristics: 3V to 5V
VS = 3 V to 5 V, RF = 0 Ω, CL = 4 pF, RL = 5 kΩ referenced to mid-supply, G = 1 V/V, input and output VCM = mid-supply, and
TA ≈ 25°C (unless otherwise noted)
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO = 20 mVPP, G = 1, < 1 dB peaking
50
20
SSBW
GBWP
LSBW
Small-signal bandwidth
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
MHz
MHz
MHz
MHz
V/µs
ns
VO = 20 mVPP, G = 2, RF = 3.65 kΩ
20
VO = 2 VPP,VS = 5 V
6
VO = 1 VPP, VS = 3 V
9
VO = 200 mVPP, G = 2, RF = 3.65 kΩ
VS= 5V, VO = 2–V step, 20% to 80%
VS= 3V, VO = 1–V step, 20% to 80%
VO = 200–mV step, input tR = 1 ns
VO = 2–V step, input tR = 50 ns
VO = 2–V step, input tR = 50 ns
VO = 2–V step, input tR = 50 ns
G = 2, 2x output overdrive
9
26
SR
17
tR, tF
Rise, fall time
16
Settling time to 0.1%
Settling time to 0.01%
Over/Under Shoot
Overdrive recovery time
88
ns
110
0.6
240
–131
–143
12
%
ns
HD2
HD3
eN
Second-order harmonic distortion f = 10 kHz, VO = 2 VPP
dBc
Third-order harmonic distortion
Input voltage noise
f = 10 kHz, VO = 2 VPP
f > 10 kHz , 1/f corner at 150 Hz
f > 10 kHz , 1/f corner at 900 Hz
f = 100 kHz, VO = 2 VPP
nV/√Hz
pA/√Hz
dBc
iN
Input current noise
0.2
–130
Channel-to-channel crosstalk
DC PERFORMANCE
AOL
Open-loop voltage gain
VO = ±1 V
102
124
0.35
0.5
1.2
50
dB
mV
1.9
2.1
5
VOS
Input-referred offset voltage
Input offset voltage drift
Input bias current
TA = –40°C to +125°C(1)
TA = –40°C to +125°C(1)
µV/°C
nA
90
TA = –40°C to +125°C(1)
70
115
30
Input offset current
5
nA
INPUT
VICR
VS–– 0.2
VS–– 0.1
86
VS+–1.1
VS+–1.1
Common-mode input range
V
dB
TA = –40°C to +125°C(1)
CMRR
Common-mode rejection ratio
Common-mode input impedance
Differential input impedance
VCM = VS- – 0.2V to VS+ – 1.1 V
104
1050 || 1.1
1 || 0.2
MΩ||pF
OUTPUT
VOL
Output voltage, low
Output voltage, high
Vs–+0.02
Vs––0.05
28
Vs–+0.05
V
VOH
Vs+– 0.1
16
VO = ±1 V, ΔVOS < 1 mV , VS = 5 V
VO = ±1 V, ΔVOS < 1 mV , VS = 3 V
G = 1, IOUT = ±5 mA DC
Linear output drive
(sourcing/sinking)
mA
11
13.5
ZO
Closed-loop output impedance
1.1
mΩ
POWER SUPPLY
VS
Specified operating voltage
2.7
86
5.4
210
290
V
170
220
103
IQ
Quiescent current per amplifier
Power-supply rejection ratio
µA
dB
TA = –40°C to +125°C(1)
PSRR
ΔVS = 0.3 V
(1) Based on electrical characterization of 32 devices. Minimum and maximum values are not specified by final automated test equipment
(ATE) nor by QA sample testing. Typical specifications are ±1 sigma.
Copyright © 2019, Texas Instruments Incorporated
5
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ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
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7.6 Typical Characteristics: Vs = 5 V
VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
3
0
3
0
-3
-6
-9
-3
-6
-9
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D101
D102
VO = 20 mVPP
VO = 20 mVPP
图 1. Noninverting Small-Signal Frequency Response
图 2. Inverting Small-Signal Frequency Response
9
6
3
0
3
0
-3
-6
-9
-3
-6
-9
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 2 VPP
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D103
D104
Gain = 2 V/V
Gain = –1 V/V
图 3. Noninverting Large-Signal Frequency Response
图 4. Inverting Large-Signal Frequency Response
0.5
0.5
0.4
0.3
0.2
0.1
0
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
0.4
0.3
0.2
0.1
0
VO = 2 VPP
VO = 2 VPP
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D206
D205
Gain = 2 V/V
Gain = –1 V/V
图 5. Noninverting Large-Signal Response Flatness
图 6. Inverting Large-Signal Response Flatness
6
版权 © 2019, Texas Instruments Incorporated
OPA2834
www.ti.com.cn
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
Typical Characteristics: Vs = 5 V (接下页)
VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
1.2
1.2
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
VO = ê 0.125 V
VO = ê 0.25 V
VO = ê 0.5 V
VO = ê 1 V
VO = ê 0.125 V
VO = ê 0.25 V
VO = ê 0.5 V
VO = ê 1 V
-1.2
-1.2
Time (100 ns/div)
Time (100 ns/div)
D303
D304
Gain = 2 V/V
Gain = –1 V/V
图 7. Noninverting Step Response
图 8. Inverting Step Response
5
4
5
4
VIN ì 2 Gain
VOUT (AV = 2)
VIN ì -2 Gain
VOUT (Av = -2)
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Time (500 ns/div)
Time (500 ns/div)
D305
D306
Gain = 2 V/V
Gain = –2 V/V
图 9. Noninverting Overdrive Recovery
图 10. Inverting Overdrive Recovery
-40
-50
-60
-70
HD2 Gain = 1 V/V
HD3 Gain = 1 V/V
HD2 Gain = -1 V/V
HD3 Gain = -1 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
-60
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
100
1k
10k
Frequency (Hz)
100k
1M
100
1k
RLOAD (W)
10k
D110
D307
VO = 2 VPP
VO = 2 VPP, f = 100 kHz
图 11. Harmonic Distortion vs Frequency
图 12. Harmonic Distortion vs RLOAD
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www.ti.com.cn
Typical Characteristics: Vs = 5 V (接下页)
VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
-90
-80
-85
-95
-90
-100
-105
-110
-115
-120
-125
-130
-95
-100
-105
-110
-115
-120
-125
HD2, Gain = 2V/V
HD3, Gain = 2V/V
HD2, Gain = -1V/V
HD3, Gain = -1V/V
HD2, +Gain
HD3, +Gain
HD2, -Gain
HD3, -Gain
0.4
0.8
1.2
1.6
2
Output Voltage (Vpp)
2.4
2.8
3.2
3.6
4
1
2
3
4
5
Gain (V/V)
6
7
8
9
10
D111
D201
f = 100 kHz
VO = 2 VPP, f = 100 kHz
图 13. Harmonic Distortion vs Output Voltage
图 14. Harmonic Distortion vs Gain Magnitude
8
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OPA2834
www.ti.com.cn
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
7.7 Typical Characteristics: VS = 3.0 V
VS+ = 3 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
3
0
3
0
-3
-6
-9
-3
-6
-9
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
0.1
1
10
100
Frequency (MHz)
0.1
1
10
100
D115
Frequency (MHz)
D114
VO = 20 mVPP
VO = 20 mVPP
图 16. Inverting Small-Signal Frequency Response
图 15. Noninverting Small-Signal Frequency Response
3
3
0
0
-3
-6
-3
-6
-9
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
-9
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D116
D117
Gain = 2 V/V
Gain = –1 V/V
图 18. Inverting Large-Signal Bandwidth
图 17. Noninverting Large-Signal Bandwidth
0.5
0.4
0.3
0.2
0.1
0
0.5
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D207
D208
Gain = 2 V/V
Gain = –1 V/V
图 19. Noninverting Large-Signal Frequency Response
图 20. Inverting Large-Signal Frequency Response Flatness
Flatness
版权 © 2019, Texas Instruments Incorporated
9
OPA2834
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
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Typical Characteristics: VS = 3.0 V (接下页)
VS+ = 3 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
1.2
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
VO = ê 0.125 V
VO = ê 0.25 V
VO = ê 0.5 V
VO = ê 0.125 V
VO = ê 0.25 V
VO = ê 0.5 V
-1.2
Time (100 ns/div)
Time (100 ns/div)
D308
D309
Gain = 2 V/V
Gain = –1 V/V
图 21. Noninverting Step Response
图 22. Inverting Step Response
3
2
3
2
VIN ì 2 Gain
VOUT (Av = 2)
VIN ì -1 Gain
VOUT (Av = -1)
1
1
0
0
-1
-2
-3
-1
-2
-3
Time (500 ns/div)
Time (500 ns/div)
D310
D311
Gain = –1 V/V
Gain = 2 V/V
图 24. Inverting Overdrive Recovery
图 23. Noninverting Overdrive Recovery
-60
-70
-60
-70
HD2 Gain1= 1 V/V
HD3 Gain1= 1 V/V
HD2 Gain1= -1 V/V
HD3 Gain1= -1 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
-80
-80
-90
-100
-110
-120
-130
-140
-150
-160
-90
-100
-110
-120
-130
100
1k
10k
Frequency (Hz)
100k
1M
100
1k
RLOAD(W)
10k
D122
D312
VO = 1 VPP
VO = 1 VPP, f = 100 kHz
图 25. Harmonic Distortion vs Frequency
图 26. Harmonic Distortion vs RLOAD
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Typical Characteristics: VS = 3.0 V (接下页)
VS+ = 3 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
-90
-80
-90
-95
-100
-105
-110
-115
-120
-125
-130
-100
-110
-120
-130
-140
HD2, Gain = 2V/V
HD3, Gain = 2V/V
HD2, Gain = -1V/V
HD3, Gain = -1V/V
HD2, +Gain
HD3, +Gain
HD2, -Gain
HD3, -Gain
1
2
3
4
5 6
Gain (V/V)
7
8
9
10
0.4
0.6
0.8
Output Voltage (Vpp)
1
1.2
D204
D123
f = 100 kHz, VO = 1 VPP
f = 100 kHz
图 28. Harmonic Distortion vs Gain Magnitude
图 27. Harmonic Distortion vs Output Voltage
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7.8 Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
with PD = VCC and TA ≈ 25°C , gain mentioned in V/V (unless otherwise noted)
100
10
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
60
45
30
15
Gain = 1V/V
Gain = 2V/V
Gain = 5V/V
Gain (dB)
Phase (è)
0
-15
-30
-45
-60
-75
-90
-105
-120
-135
-150
-165
-180
1
0.1
10m
1m
0.1m
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
100
1k
10k 100k
Frequency (Hz)
1M
10M
D313
D314
图 29. Open-Loop Gain and Phase vs Frequency
图 30. Closed-Loop Output Impedance vs Frequency
100
10
1
120
Voltage Noise
Current Noise
CMRR 5V
CMRR 3V
PSRR 5V
PSRR 3V
110
100
90
80
70
60
50
40
30
20
10
0
0.1
10
100
1k 10k
Frequency (Hz)
100k
1M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D100
D315
Measured then fit to ideal 1/f model
图 31. Input Noise Density vs Frequency
图 32. CMRR and PSRR vs Frequency
14k
300
200
100
0
5V
3V
12k
10k
8k
6k
-100
-200
-300
4k
2k
-50
-25
0
25
50
75
100
125
Ambient Temperature (èC)
D151
D141
Input Offset Voltage (mV)
32 units at 5-V and 3-V supply, Input offset voltage calibrated to
0V at 25°C
54000 units at each supply voltage
图 33. Input Offset Voltage Distribution
图 34. Input Offset Voltage vs Ambient Temperature
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (接下页)
with PD = VCC and TA ≈ 25°C , gain mentioned in V/V (unless otherwise noted)
20
10
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-10
-20
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (èC)
Ambient Temperature (èC)
D154
D153
32 units at 5-V and 3-V supply
32 units at 5-V and 3-V supply
图 36. Input Bias Current vs Ambient Temperature
图 35. Input Offset Current vs Ambient Temperature
240
220
200
180
160
140
120
40
35
30
25
20
15
10
5
0
-50
-25
0
25
50
75
100
125
Ambient Temperature (èC)
D150
Input Offset Voltage Drift mV/èC
D142
32 units at 5-V and 3-V supply
136 units, –40°C to +125°C
图 38. Supply Current vs Ambient Temperature
图 37. Input Offset Voltage Drift Distribution
200
180
160
140
120
100
80
9
6
Gain=1V/V
Gain=2V/V
Gain=5V/V
Gain=10V/V
3
0
-3
-6
G=1 CL=1nF RO=70W
G=1 CL=0.1nF RO=170W
G=2 CL=1nF RO=55W
G=2 CL=0.1nF RO=110W
G=5 CL=1nF RO=25W
G=5 CL=0.1nF RO=0W
G=10 CL=1nF RO=0W
G=10 CL=0.1nF RO=0W
-9
60
-12
-15
-18
-21
40
20
0
1
10
100
CL (pF)
1000
10000
0.01
0.1
1
Frequency (MHz)
10
100
D301
D302
See 图 49,
See 图 49
Recommended value of RO for targeting 30° phase margin
图 39. Output Resistor (RO) vs CL
图 40. Small-Signal Frequency Response vs CL
With Recommended RO
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (接下页)
with PD = VCC and TA ≈ 25°C , gain mentioned in V/V (unless otherwise noted)
3
2.5
1.5
2
1
0.5
0
1.5
1
0.5
0
ê 2.5 VOH
ê 2.5 VOL
ê 1.5 VOH
ê 1.5 VOL
-0.5
-1
-0.5
-1
-1.5
-2
-2.5
-3
-1.5
-2
100
1k
RLOAD (W)
10k
-3 -2.4 -1.8 -1.2 -0.6
0
Input Common-mode Voltage (V)
0.6 1.2 1.8 2.4
3
D316
D317
32 units at 5-V and 3-V supplies
图 41. Output Voltage Swing vs Load Resistor
图 42. Input Offset Voltage vs Input Common-Mode Voltage
5k
-40
Ch A to Ch B
Ch B to Ch A
-50
-60
4k
3k
2k
1k
-70
-80
-90
-100
-110
-120
-130
-140
0.1
1
10
100
D300
Frequency (MHz)
D107
Input offset mismatch between channels (mV)
图 43. Crosstalk vs Frequency
图 44. Input Offset Mismatch (Between Channel A and
Channel B) Distribution
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8 Detailed Description
8.1 Overview
The OPA2834 bipolar input operational amplifier offers an unity-gain bandwidth of 50 MHz with ultra-low HD2
and HD3 as shown in the Electrical Characteristics: 3V to 5V. The device can swing to within 100 mV of the
supply rails while driving a 5-kΩ load. The input common-mode voltage of the amplifier can swing to 200 mV
below the negative supply rail. This level of performance is achieved at 170 µA of quiescent current per amplifier
channel.
8.2 Functional Block Diagrams
VSIG
VREF
VS+
½ OPA2834
VOUT
VIN
+
RG
œ
VS-
RF
Gain × VSIG
VREF
VREF
图 45. Noninverting Amplifier
VS+
VREF
VREF
VIN
-
Gain ×
VSIG
VS-
RF
VREF
图 46. Inverting Amplifier
8.3 Feature Description
8.3.1 Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier circuit with high CMRR, it is important to not violate the input
common-mode voltage range (VICR) of the op amp. The typical specifications for this device are 0.2 V below the
negative rail and 1.1 V below the positive rail.
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally 0 V);
and the input common-mode voltage is analyzed at either input pin with the other input pin assumed to be at the
same potential. The voltage at VIN+ is simple to evaluate. In a noninverting configuration, as shown in 图 45, the
input signal, VIN, must not violate the VICR for this operation. In an inverting configuration, as shown in 图 46, the
reference voltage, VREF, must be within the VICR. Assuming VREF is within VICR, the amplifier is always in the
linear operation range irrespective of the amplitude of the input signal VIN.
The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For a 5-V
supply, the linear input voltage ranges from –0.2 V to 3.9 V and –0.2 V to 1.6 V for a 2.7-V supply. The delta
headroom from each power-supply rail is the same in either case: –0.2 V and 1.1 V.
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Feature Description (接下页)
8.3.2 Output Voltage Range
The OPA2834 is a rail-to-rail output (RRO) op amp. Rail-to-rail output typically means that the output voltage
swings within a couple hundred millivolts of the supply rails. There are different ways to specify this parameter,
one is with the output still in linear operation and another is with the output saturated. Saturated output voltages
are closer to the power-supply rails than linear outputs, but the signal is not a linear representation of the input.
Linear output is a better representation of how well a device performs when used as a linear amplifier. Saturation
and linear operation limits are affected by the output current, where higher currents lead to lower headroom from
either of the output rails.
The Electrical Characteristics: 3V to 5V list the saturated output voltage specifications with a 5-kΩ load. Given a
light load, the output voltage limits have nearly constant headroom to the power rails and track the power-supply
voltages. For example, with a 5-kΩ load and a single 5-V supply, the saturation output voltage ranges from 0.1 V
to 4.95 V and ranges from 0.1 V to 2.65 V for a 2.7-V supply.图 41 illustrates the saturated voltage-swing limits
versus output load resistance.
With a device such as the OPA2834, where the input range is lower than the output range, typically the input
limits the available signal swing only in a noninverting gain of 1. Signal swing in noninverting configurations in
gains greater than +1 and inverting configurations in any gain is typically limited by the output voltage limits of
the op amp.
8.3.3 Low-Power Applications and the Effects of Resistor Values on Bandwidth
Choosing the right value of feedback resistor (RF) gives the lowest operating current, maximum bandwidth,
lowest DC error, and the best pulse response. In this section for simplicity, the main focus of the signal chain
design is assumed to be the total operating current. The feedback resistor used to set the gain value invariably
loads the amplifier. For example, in a gain of 2 with RF = RG = 3.6 kΩ (see 图 48) and VOUT = 4 V (assumed),
555 µA of current flows through the feedback path to ground. However, using a 3.6-kΩ resistor may not be
practical in low-power applications.
In low-power applications, there is a tendency to reduce the current consumed by the amplifier by increasing the
gain-setting resistor values in the feedback path. Using larger value gain resistors has two primary side effects
(other than lower power), because of the interaction of the resistors with parasitic circuit capacitance. These
large-value resistors:
•
•
Lower the bandwidth as a result of the interaction with the parasitic capacitor
Lower the phase margin by causing
–
–
Peaking in the frequency response
Overshoot and ringing in the pulse response
图 47 shows the small-signal frequency response for a noninverting gain of 2 with RF and RG equal to 2 kΩ, 5
kΩ, 10 kΩ, and 100 kΩ. The test was done with RL = 5 kΩ. Peaking reduces with lower values of RL.
15
12
9
6
3
0
-3
-6
-9
RF = 2 kW
-12
RF = 5 kW
RF = 10 kW
RF = 100 kW
-15
-18
100k
1M
10M
Frequency (Hz)
100M
D401
图 47. Frequency Response With Various Gain-Setting Resistor Values
As expected, larger value gain resistors result in gain peaking in the frequency response plots (peaking in the
frequency response is synonymous with the reduced phase margin).
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Feature Description (接下页)
However, there is a simple way to get the best of both worlds. An ideal application requires a high value of RF for
a particular gain to reduce the operating current but be limited by the reduced phase margin from the interaction
of RF and CIN. The trick is simple: adding a capacitor in parallel with RF helps compensate the phase margin and
restores the flat frequency response (avoids gain peaking). The value of C chosen must be such that RF × CF =
CIN × RG. CIN for the OPA2834 is 1.1 pF. This value of CIN is listed in the Electrical Characteristics: 3V to 5V
table as common-mode input impedance. For the case discussed here with a Gain = 2, RF = RG = 3.6 kΩ, , CIN
=
1.1 pF, using a CF equal to 1 pF is sufficient to reduce the gain peaking. Using a CF equal to 1 pF enables users
to increase the values of RF and RG to much higher values beyond 3.6 kΩ to reduce the operational current
consumed by the amplifier.
图 48 shows the test circuit.
½ OPA2834
VIN
RG
+
VOUT
5 kꢀ
œ
RF
CF
图 48. G = 2 Test Circuit for Various Gain-Setting Resistor Values
8.3.4 Driving Capacitive Loads
The OPA2834 drives up to a nominal capacitive load of 10 pF on the output with no special consideration and
without the need of RO. When driving capacitive loads greater than 10 pF, TI recommends using a small resistor
(RO) in series with the output as close to the device as possible. Without RO, output capacitance interacts with
the output impedance (ZO) of the amplifier causing phase shift in the feedback loop of the amplifier reducing the
phase margin. This reduction in the phase margin causes peaking in the frequency response and overshoot and
ringing in the pulse response. Interaction with other parasitic elements can lead to further instability or ringing.
Inserting RO isolates the phase shift from the loop gain path and restores the phase margin; however RO can
limit the bandwidth slightly. 图 49 shows a diagram of driving capacitive loads.
图 39 shows the test circuit and shows the recommended values of RO versus capacitive loads, CL. See 图 40 for
the frequency responses with various optimized values of RO with CL.
½ OPA2834
RO
VIN
+
VOUT
5 kꢀ
œ
CL
图 49. Driving Capacitive Loads With the OPA2834
8.4 Device Functional Modes
8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
To facilitate testing with common lab equipment, the OPA2834EVM (see the OPA2837DGK Evaluation Module
user guide) is built to allow split-supply operation. This configuration eases lab testing because the mid-point
between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum
analyzers, and other lab equipment have inputs and outputs with a ground reference.
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Device Functional Modes (接下页)
图 50 shows a simple noninverting configuration analogous to 图 45 with a ±2.5-V supply and the reference
voltage (VREF) equal to ground. The input and output swing symmetrically around ground. For ease of use, split
supplies are preferred in systems where signals swing around ground.
+2.5 V
½ OPA2834
+
RG
VOUT
œ
VSIG
Load
-2.5 V
RF
图 50. Split-Supply Operation
8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
Often, newer systems use a single power supply to improve efficiency and reduce the cost of the power supply.
The OPA2834 is designed for use with single-supply power operation and can be used with single-supply power
with no change in performance from split supply, as long as the input and output are biased within the linear
operation of the device.
To change the circuit from split-supply to single-supply, level shift all voltages by half the difference between the
power-supply rails. For example, 图 51 shows changing from a ±2.5-V split supply to a 5-V single supply.
5 V
½ OPA2834
+
RG
VOUT
œ
VSIG
Load
RF
+
2.5 V
图 51. Single-Supply Concept
A practical circuit has an amplifier or some other circuit providing the bias voltage for the input, and the output of
this amplifier stage provides the bias for the next stage.
图 52 shows a typical noninverting amplifier circuit. With a 5-V single-supply, a mid-supply reference generator is
needed to bias the negative side through RG. To cancel the voltage offset that is otherwise caused by the input
bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of 2 is required and RF =
3.6 kΩ, select RG = 3.6 kΩ to set the gain, and R1 = 1.8 kΩ for bias current cancellation. The value for C is
dependent on the reference, and TI recommends a value of at least 0.1 µF to limit noise.
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Device Functional Modes (接下页)
Signal and bias from
previous stage
VSIG
2.5 V
5 V
½ OPA2834
R1
RO
+
VOUT
œ
RG
Gain × VSIG
2.5 V
REF
5 V
2.5 V
C
Signal and bias to
next stage
RF
图 52. Noninverting Single-Supply Operation With Reference
图 53 illustrates a similar noninverting single-supply scenario with the reference generator replaced by the
Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5-V
supply and are used to bias the negative side with the parallel sum equal to the equivalent RG to set the gain. To
cancel the voltage offset that is otherwise caused by the input bias currents, R1 is selected to be equal to RF in
parallel with RG’ in parallel with RG” (R1= RF || RG’ || RG”). For example, if a gain of 2 is required and RF = 3.6 kΩ,
selecting RG’ = RG” = 7.2 kΩ gives an equivalent parallel sum of 3.6 kΩ, sets the gain to 2, and references the
input to mid supply (2.5 V). R1 is set to 1.8 kΩ for bias current cancellation. The resistor divider costs less than
the 2.5-V reference in 图 53 but can increase the current from the 5-V supply.
Signal and bias from
previous stage
VSIG
2.5 V
5 V
½ OPA2834
R1
RO
+
RG‘
VOUT
Gain × VSIG
œ
5 V
RG“
2.5 V
Signal and bias to
next stage
RF
图 53. Noninverting Single-Supply Operation With Resistors
图 54 shows a typical inverting-amplifier circuit. With a 5-V single-supply, a mid-supply reference generator is
needed to bias the positive side through R1. To cancel the voltage offset that is otherwise caused by the input
bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of –2 is required and RF
= 3.6 kΩ, select RG = 1.8 kΩ to set the gain and R1 = 1.2 kΩ for bias current cancellation. The value for C is
dependent on the reference, but TI recommends a value of at least 0.1 µF to limit noise into the op amp.
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Device Functional Modes (接下页)
5 V
½ OPA2834
R1
C
2.5 V
REF
RO
+
5 V
VOUT
œ
Gain × VSIG
2.5 V
RG
VSIG
RF
Signal and bias to
next stage
2.5 V
Signal and bias from
previous stage
图 54. Inverting Single-Supply Operation With Reference
图 55 illustrates a similar inverting single-supply scenario with the reference generator replaced by the Thevenin
equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply and are
used to bias the positive side. To cancel the voltage offset that is otherwise caused by the input bias currents,
set the parallel sum of R1 and R2 equal to the parallel sum of RF and RG. C must be added to limit the coupling of
noise into the positive input. For example, if a gain of –2 is required and RF = 3.6 kΩ, select RG = 1.8 kΩ to set
the gain. R1 = R2 = 2.4 kΩ for the mid-supply voltage bias and for op-amp input-bias current cancellation. A good
value for C is 0.1 µF. The resistor divider costs less than the 2.5-V reference in 图 55 but can increase the
current from the 5-V supply.
5 V
5 V
½ OPA2834
R1
RO
+
VOUT
C
R2
œ
Gain × VSIG
2.5 V
RG
RF
Signal and bias to
next stage
VSIG
2.5 V
Signal and bias from
previous stage
图 55. Inverting Single-Supply Operation With Resistors
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
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9.1 Application Information
9.1.1 Noninverting Amplifier
The OPA2834 can be used as a noninverting amplifier with a signal input to the noninverting input, VIN+. 图 45
illustrates a basic block diagram of the circuit.
The amplifier output can be calculated according to 公式 1 if VIN = VREF + VSIG
.
æ
ö
÷
ø
RF
V
OUT
= VSIG 1 +
+ VREF
ç
RG
è
(1)
RF
G = 1 +
RG
The signal gain of the circuit is set by
, and VREF provides a reference around which the input and
output signals swing. Output signals are in-phase with the input signals.
The OPA2834 is designed for the nominal value of RF to be 3.6 kΩ in gains other than +1. This value gives
excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. RF = 3.6 kΩ must
be used as a default unless other design goals require changing to other values. All test circuits used to collect
data for this document have RF = 3.6 kΩ for all gains other than +1. A gain of +1 is a special case where RF is
shorted and RG is left open.
9.1.2 Inverting Amplifier
The OPA2834 can be used as an inverting amplifier with a signal input to the inverting input, VIN–, through the
gain-setting resistor RG. 图 46 illustrates a basic block diagram of the circuit.
The output of the amplifier can be calculated according to 公式 2 if VIN = VREF + VSIG
.
æ
SIG ç
è
ö
÷
ø
-RF
V
= V
+ V
REF
OUT
RG
(2)
-RF
G =
RG
The signal gain of the circuit is given by
and VREF provides a reference point around which the input
and output signals swing. Output signals are 180˚ out-of-phase with the input signals. The nominal value of RF
must be 3.6 kΩ for inverting gains.
9.2 Typical Applications
9.2.1 Low-Side Current Sensing
Power stages use current feedback for phase current control and regulation. One of the commonly used methods
for this current measurement is low-side current shunt monitoring. 图 56 shows a representative schematic of
such a system. The use of the OPA2834 is described in this section for a low-side, current-shunt monitoring
application.
Short-
Circuit Fault
Detection
+
VTH
LOAD
œ
10 kΩ
3.3V
5 V
œ
5 V
500 Ω
500 Ω
OPA2834-2
œ
ADS7056
15 APP
470 pF
OPA2834-1
+
+
90 Ω
10 mΩ
10 kΩ
VREF =1.24V
图 56. Low-Side Current Sensing
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Typical Applications (接下页)
9.2.1.1 Design Requirements
The OPA2834 is used in a gain of 20 V/V followed by an OPA2834 used in a gain of 1 V/V for driving the input of
the ADS7056 which is sampling at 1 MSPS. A comparator is connected to the ADC input for short-circuit fault
detection. This design example is illustrated for the following specifications:
•
•
•
•
•
•
•
Switching frequency: 50 kHz
Shunt resistance: 10 mΩ
Load current: 15 APP
Output voltage: 3.0 VPP
Amplifier supply voltage: 5 V
Data Acquisition: 1 MSPS with 0.1% accuracy
Input spikes due to inductive kickbacks from the power plane: 10 V
9.2.1.2 Detailed Design Procedure
One of the channels of the OPA2834 is connected to the shunt resistor in 图 56 in a 20-V/V difference amplifier
configuration. 公式 3 gives the gain of this circuit. A well-known way to start the design of this signal chain is to
start from fixating the value of RG.
≈
∆
«
’
÷
◊
RF
RG
VOUT
=
V -V
(
)
2
1
where
•
RF and RG are the feedback and gain resistors for channel A of the OPA2834
(3)
The values of RF and RG depend on multiple factors. Using small resistors in the feedback network helps reduce
output noise and improves measurement accuracy. Small feedback resistors result in larger power dissipation in
the amplifier output stage. In order to reduce this power dissipation, large-value resistors reduce the phase
margin and cause gain peaking; see 图 47. Select the values of RF and RG from the recommended range of
values for this device. As given in 公式 4, care must be taken to use a gain-resistor value large enough to limit
the current through the input ESD diodes to within 10 mA for a 10-V input transient (as per the design targets)
with the amplifier powered off a 5-V supply.
VIN -VD -VS
ID,Max
RG =
where
•
•
•
VIN is the input transient voltage
VD is the ESD diode forward voltage drop
ID is the current resulting from this input transient flowing through the ESD diode
(4)
A total gain of 20 V/V is required from the amplifier signal chain. We have chosen RG = 500 Ω in this design, thus
RF = 10 kΩ. A SAR ADC features a sampling capacitor at the input pin. At the end of every conversion cycle, the
circuit driving this SAR ADC needs to replenish this capacitor. Using the analog calculator, the required
bandwidth for the amplifier to drive the ADS7056 ( sampling rate of 1MSPS and a clock frequency of 40 MHz )
comes out to be at least 5 MHz. Because of this requirement, the two amplifier channels are configured in gains
of 20 V/V and 1 V/V, respectively. The effective bandwidth of the amplifier set in a gain on 20 V/V comes out to
be 20MHz/20 = 1MHz. The bandwidth of the second amplifier set in a gain of 1V/V , equals 50MHz. Thus the
rise time and the settling time of the entire signal chain is decided by the first amplifier. Using an amplifier in the
first stage of any lower bandwidth will result in a penalty in the settling time on the ADC. The 1.24-V reference
voltage to the noninverting input of channel 1 sets the output common-mode voltage to 1.24 V. The two channels
of the OPA2834 together provide a signal gain of 20 V/V. The first Amplifier's bandwidth is dedicated to gaining
up the signal with a very low rise time whereas the function of the second amplifier is to utilize its bandwidth to
drive the SAR ADC to achieve the required settling.
22
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OPA2834
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ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
Typical Applications (接下页)
The ADS7056 samples at 1 MSPS with a 40-MHz clock which translates to an acquisition time of 550 nsec. This
provides the dual amplifier 550 nsec to settle to the required accuracy. In this application, we target an accuracy
of 0.1%. As the ADC is powered from a 3.3 V supply we have assumed the full scale to be 3 V.
An accuracy of 0.1% of 3 V = 3 mV. Thus the second OPA2834 should settle to ±3 mV of its final intended value
within 550 nsec. 图 57 shows the TINA simulation plots for the OPA2834 driving the ADS7056. Input voltage
(red) is the signal swing across the shunt resistance, the error signal is the % error in the voltage across the
sampling capacitor from its steady-state value (instantaneous value - final value). The input signal sharply
transits from its lowermost point to the uppermost point at 600 nsec instant. This can be considered as a short
circuit event or step increase due to a mosfet switching in real-world circuits. This acquisition window of the ADC
as discussed earlier is 550 nsec. The details on how this time is decided by the ADC can be found from the
ADS7056 datasheet. Thus the % error signal (blue) must settle down to less than 0.1 % before the end of this
550 nsec window. The output signal (black) is divided by 20 V/V so as to be shown beside its corresponding
input signal. As per 图 57 the error signal comfortably settles to the final value with an error % of -0.05% which is
well within the 0.1% accuracy. Hence the dual OPA2834 settles to 0.1% accuracy within 550 ns with a worst-
case, 0 to 3-V full-scale transient output that too in a gain configuration of 20 V/V as shown in the 图 57.
OPA2834 enables single sample settling for ADS7056 running at 40 MHz clock with 1 MSPS.
0.1
0.08
0.06
0.04
0.02
0
0.5
0.4
0.3
0.2
0.1
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.1
-0.2
-0.3
-0.4
-0.5
Input
% error
Output/20
Time ( 600 nsec/div)
sett
图 57. OPA2834 Settling Performance With the ADS7056
Another way to look at the signal chain is using the SNR and THD numbers. A 2 kHz tone is input to the first
OPA2834 shown in 图 56. This signal is gained up by 20 V/V and fed to the ADS7056. The results are compared
to the specifications given in the ADS7056 datasheet.
表 1. OPA2834 based signal-chain comparison
Parameter
ENOB
OPA2834 + ADS7056
Ideal Opamp + ADS7056
11.2
69.3
12.16
75.15
-90.13
SNR (dB)
THD (dB)
-87.89
版权 © 2019, Texas Instruments Incorporated
23
OPA2834
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
Using a slower clock with the ADC and the same sampling rate causes the ENOB to reduce as the amplifier has
reduced time available to settle. This reduction in ENOB is restored with a lower sampling frequency or use of
wider bandwidth amplifiers from the OPA83x family of products.
9.2.2 Field Transmitter Sensor Interface
XTR117
VREG
5V
Regulator
OPA2834-1
Sensor
µ C
OPA2834-2
IRET
图 58. Field Transmitter Sensor Interface Block Diagram
9.2.3 Ultrasonic Flow Meters
图 59. Ultrasonic Flow Meters Gain Stage
9.2.4 Microphone Pre-Amplifier
5 V
3.3V
0.1 ꢁF
Electret
Microphone
C1
R3
OPA2834
0.1 ꢁF
100 ꢀ
+
Output
Microphone
Cable
œ
R1
5.9 kꢀ
R2
100 kꢀ
C2
10 nF
0.1 ꢁF
-1.8 V
R4 100 kꢀ
R5 1.1 kꢀ
C3
1 ꢁF
R6 100 ꢀ
C4 6.8 nF
图 60. Low-Power Microphone Pre-Amplifier
24
版权 © 2019, Texas Instruments Incorporated
OPA2834
www.ti.com.cn
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
图 60 shows an example circuit of the audio pre-amplifier application using OPA2834. The excellent distortion
performance and the ultra-low quiescent current, make OPA2834 a very attractive solution for the portable and
handheld audio instruments. 图 60 circuit is a bandpass filter with frequency cutoff at 5 Hz and 180 kHz. The
OPA2834 is connected to a positive 3.3 V and a negative 1.8 V supply. the primary reason for the skew in the
power supply is to enable the maximum dynamic range possible to the user. The VICR of OPA2834 mentioned in
Electrical Characteristics: 3V to 5V is 1.1 V from the positive rail. Thus having a skewed power supply like in 图
60 gives a common-mode input range from -2 V up to 2.2 V.
40
30
20
10
0
180
120
60
Gain
Phase
0
-60
-120
-180
-10
-20
100m
1
10
100
1k
Frequency (Hz)
10k 100k 1M 10M 100M
freq
图 61. Frequency Response of Microphone Pre-Amplifier
10 Power Supply Recommendations
The OPA2834 is intended to work in a nominal supply range of 3.0 V to 5.0 V. Supply-voltage tolerances are
supported with the specified operating range of 2.7 V (–10% on a 3-V supply) and 5.4 V (8% on a 5-V supply).
Good power-supply bypassing is required. Minimize the distance (< 0.1 inch) from the power-supply pins to high-
frequency, 0.1-µF decoupling capacitors. A larger capacitor (2.2 µF is typical) is used along with a high-
frequency, 0.1-µF, supply-decoupling capacitor at the device supply pins. For single-supply operation, only the
positive supply has these capacitors. When a split supply is used, use these capacitors for each supply to
ground. If necessary, place the larger capacitors further from the device and share these capacitors among
several devices in the same area of the printed circuit board (PCB). Avoid narrow power and ground traces to
minimize inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor
across the two power supplies (for bipolar operation) reduces second-order harmonic distortion.
版权 © 2019, Texas Instruments Incorporated
25
OPA2834
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The OPA2837EVM can be used as a reference when designing the circuit board. TI recommends following the
EVM layout of the external components near to the amplifier, ground plane construction, and power routing as
closely as possible. Follow these general guidelines:
1. Signal routing must be direct and as short as possible into and out of the op amp.
2. The feedback path must be short and direct avoiding vias if possible, especially with G = 1 V/V.
3. Ground or power planes must be removed from directly under the negative input and output pins of the
amplifier.
4. TI recommends placing a series output resistor as close to the output pin as possible.
5. See 图 40 for recommended values for the expected capacitive load. These values are derived targeting a
30° phase margin to the output of the op amp.
6. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be
shared with other op amps. For split supply, a capacitor is required for both supplies.
7. A 0.1-µF power-supply decoupling capacitor must be placed as close to the supply pins as possible,
preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
11.2 Layout Examples
C6 and C8 bypass capacitors
placed close to the device
supply pins.
图 62. EVM Layout Top Layer
GND and power planes removed
under the device pins in order to
minimize parasitic capacitance on
the sensitive input and output nodes.
图 63. EVM Layout Bottom Layer
26
版权 © 2019, Texas Instruments Incorporated
OPA2834
www.ti.com.cn
ZHCSJY2A –JUNE 2019–REVISED SEPTEMBER 2019
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
德州仪器 (TI)，《OPA2837DGK 评估模块》 用户指南
德州仪器 (TI)，《ADS7046 12 位、3MSPS、单端输入、小尺寸、低功耗 SAR ADC》 数据表
德州仪器 (TI)，《单电源运算放大器设计技术》应用报告
德州仪器 (TI)，《高速运算放大器噪声分析》应用报告
德州仪器 (TI)，《TIDA-01565 有线 OR 多路复用器以及 PGA 参考设计》设计指南
德州仪器 (TI)，TINA 模型与仿真工具
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2834IDGKR
OPA2834IDGKT
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
2834
2834
Samples
Samples
NIPDAUAG | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2834IDGKR
OPA2834IDGKR
OPA2834IDGKT
OPA2834IDGKT
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
8
8
8
8
2500
2500
250
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2834IDGKR
OPA2834IDGKR
OPA2834IDGKT
OPA2834IDGKT
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
8
8
8
8
2500
2500
250
366.0
366.0
366.0
366.0
364.0
364.0
364.0
364.0
50.0
50.0
50.0
50.0
250
Pack Materials-Page 2
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