OPA2837 [TI]
双路、低功耗、精密、轨到轨输出、105MHz 电压反馈放大器;
| 型号： | OPA2837 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、低功耗、精密、轨到轨输出、105MHz 电压反馈放大器 放大器 |
| 文件： | 总63页 (文件大小：2884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
OPAx837 低功耗 105MHz 电压反馈精密运算放大器
1 特性
3 说明
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带宽：105MHz (AV = 1V/V)
OPA837 和 OPA2837 是单通道和双通道单位增益稳
定电压反馈放大器，与其他精密运算放大器相比能够提
供较高的 MHz/mW 带宽。这两款 3.0mW 器件每通道
仅消耗 600µA（通过单个 5V 电源），能够以 1V/V 的
增益提供 105MHz 带宽。±130µV（最大值）的极低修
整失调电压可提供典型值 (±1σ) 为 ±0.4µV/°C 的温
漂。
极低（修整后）的电源电流：600µA
增益带宽积：50MHz
压摆率：105V/µs
负轨输入，轨至轨输出
单电源工作电压范围：2.7V 至 5.4V
25°C 下的输入偏移电压：±130µV（最大值）
输入偏移电压漂移（DCK 封装）：
< ±1.6µV/°C（最大值）
OPAx837 理论上非常适合单端逐次逼近型寄存器
(SAR) 模数转换器 (ADC) 驱动 应用，能够针对 3mW
静态功率提供一种较低的输入点噪声级别 (4.7nV/√
Hz)。极高的 50MHz 增益带宽积可针对高频率提供低
输出阻抗，这是在 SAR ADC 驱动器应用中提供快速
充电电流 所必需的。该低动态输出阻抗还适用于采用
精密 ADC 的 基准 缓冲器应用。单通道 OPA837 采用
6 引脚 SOT-23 封装（包括电源关断特性）和 5 引脚
SC70 封装，而双通道 OPA2837 则采用 8 引脚
VSSOP 封装和 10 引脚 WQFN 封装。
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输入电压噪声：4.7nV/√Hz (> 100Hz)
HD2：-120dBc（2VPP、100kHz 时）
HD3：-145dBc（2VPP、100kHz 时）
稳定时间：35ns，0.5V 阶跃到 0.1%
5-µA 关断电流，并且能够从关断快速恢复
（针对功率调节 应用）
2 应用
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12 位至 16 位低功耗 SAR 驱动器
精密 ADC 基准缓冲器
极低功耗有源滤波器
低功耗跨阻放大器
传感器信号调节
可穿戴设备
OPAx837 具有 –40°C 至 +125°C 的宽额定运行温度范
围。
器件信息(1)
器件型号
OPA837
封装
SOT-23 (6)
封装尺寸（标称值）
2.90mm × 1.60mm
2.00mm × 1.25mm
3.00mm × 3.00mm
2.00mm × 2.00mm
低侧电流检测
SC70 (5)
VSSOP (8)
WQFN (10)
具有真正接地输入和输出范围的低功耗、低噪声、精密
单端 SAR ADC 驱动器
OPA2837
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
+ 5.0 V
4.096 V
REF5040
GND
4.0 V
3.3 V
+VCC
0 V
0 V
3.8 V
PD
OPA837
+
22 Ω
Gain = 1.05
V/V
œ
ADS8860
16-Bit SAR
1 MSPS
œVCC
2.2 nF
499 Ω
22 Ω
10.0 kΩ
GND
GND
GND
œ 0.23 V
LM7705
+ 3.3 V
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS673
OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
目录
7.2 Functional Block Diagrams ..................................... 22
7.3 Feature Description................................................. 23
7.4 Device Functional Modes........................................ 26
Application and Implementation ........................ 30
8.1 Application Information............................................ 30
8.2 Typical Applications ................................................ 39
Power Supply Recommendations...................... 43
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information: OPA837 .................................. 6
6.5 Thermal Information: OPA2837 ................................ 6
6.6 Electrical Characteristics: VS = 5 V........................... 7
6.7 Electrical Characteristics: VS = 3 V........................... 9
6.8 Typical Characteristics: VS = 5.0 V......................... 11
6.9 Typical Characteristics: VS = 3.0 V......................... 14
8
9
10 Layout................................................................... 43
10.1 Layout Guidelines ................................................. 43
10.2 Layout Example .................................................... 44
11 器件和文档支持 ..................................................... 45
11.1 文档支持................................................................ 45
11.2 相关链接................................................................ 45
11.3 接收文档更新通知 ................................................. 45
11.4 社区资源................................................................ 45
11.5 商标....................................................................... 45
11.6 静电放电警告......................................................... 45
11.7 术语表 ................................................................... 45
12 机械、封装和可订购信息....................................... 46
6.10 Typical Characteristics: ±2.5-V to ±1.5-V Split
Supply ...................................................................... 17
7
Detailed Description ............................................ 22
7.1 Overview ................................................................. 22
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (August 2018) to Revision D
Page
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已添加 在说明 部分添加了 WQFN (RUN) 封装 ...................................................................................................................... 1
Added OPA2837 RUN package thermal information to document. ....................................................................................... 6
Changed values of maximum and minimum input-referred offset voltage at 25℃ and across temperature in 5 V and
3 V Electrical Characteristics tables. ...................................................................................................................................... 7
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Changed value of maximum input offset current drift for OPA2837 in 5 V and 3 V Electrical Characteristics tables. ......... 8
Changed minimum value of CMRR in 5 V Electrical Characteristics table ............................................................................ 8
已添加 reference to TIDA-01565 reference design in Power-Down Operation section ....................................................... 24
已添加 reference to TIDA-01565 reference design in1-Bit PGA Operation section............................................................. 42
Changes from Revision B (July 2018) to Revision C
Page
•
已添加 向文档添加了 OPA2837 RUN 封装............................................................................................................................. 1
Changes from Revision A (April 2018) to Revision B
Page
•
Changed input common-mode impedance in 5V and 3V electrical characteristics tables..................................................... 8
Changes from Original (September 2017) to Revision A
Page
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已添加 文档中添加了 OPA2837.............................................................................................................................................. 1
已添加 单电源工作电压范围 特性 要点................................................................................................................................... 1
已更改 将首页框图中的 1 SPS 更改为 1 MSPS ..................................................................................................................... 1
Added footnote to Pin Functions table .................................................................................................................................. 4
Changed footnote describing method of computation of slew rate in Electrical Characteristics: VS = 5 V table ................... 7
Changed default test condition in Electrical Characteristics: VS = 3 V table ......................................................................... 9
2
版权 © 2017–2018, Texas Instruments Incorporated
OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
•
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•
Changed footnote describing method of computation of slew rate in Electrical Characteristics: VS = 3 V table .................. 9
Changed values for common-mode input range, high in Electrical Characteristics: VS = 3 V table .................................... 10
Changed values for VOH in Electrical Characteristics: VS = 3 V table .................................................................................. 10
已更改 VO = 20 mVPP to VOUT = 200 mVPP in conditions of Noninverting Response Flatness vs Gain and Inverting
Response Flatness vs Gain figures...................................................................................................................................... 11
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已更改 gain –1 V/V to gain –2 V/V, swapped legend colors in Inverting Overdrive Recovery figure .................................. 12
已更改 VOUT = 2 VPP to VOUT = 1 VPP in conditions of Typical Characteristics: VS = 3.0 V section....................................... 14
已更改 VO = 20 mVPP to VOUT = 200 mVPP in Noninverting Response Flatness vs Gain and Inverting Response
Flatness vs Gain figure conditions........................................................................................................................................ 14
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已更改 VIN to VIN × –1 gain, swapped legend colors in Inverting Overdrive Recovery figure .............................................. 15
已更改 VO = 2 VPP to VOUT = 1 VPP in Harmonic Distortion vs RLOAD figure conditions ........................................................ 16
已更改 VOUT = 2 VPP to VOUT = 1 VPP in Harmonic Distortion vs Gain Magnitude figure conditions..................................... 16
已更改 y-axis caption in Turn-On Time to Sinusoidal Input and Turn-Off Time to Sinusoidal Input figures ........................ 19
已添加 OPA838 row to Device Family Comparison table .................................................................................................... 23
已更改 EVM link in Split-Supply Operation section from OPA837DBV to OPA835DBV...................................................... 26
已更改 V2 value from 2.5 to –2.5 V in Characterization Test Circuit for Network, Spectrum Analyzer figure ..................... 30
已更改 VEE value from 2.5 V to –2.5 V in Inverting Characterization Circuit for Network Analyzer figure ........................... 32
已更改 1 SPS to 1 MSPS in OPA837 and ADS8860 Example Circuit figure....................................................................... 38
Copyright © 2017–2018, Texas Instruments Incorporated
3
OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
5 Pin Configuration and Functions
OPA837 DBV Package
6-Pin SOT-23
OPA837 DCK Package
5-Pin SC70
Top View
Top View
VOUT
VS-
VS+
VOUT
VS-
1
2
3
6
5
4
VS+
PD
VIN-
1
2
3
5
4
VIN+
VIN-
+IN
OPA2837 DGK Package
8-Pin VSSOP
OPA2837 RUN Package
10-Pin WQFN
Top View
Top View
VS+
10
VOUT1
VIN1-
VIN1+
VS-
VS+
1
2
3
4
8
7
6
5
VOUT1
1
9
VOUT2
VIN2-
VIN2+
PD2
VOUT2
A
VIN1-
2
3
4
8
VIN2-
VIN2+
B
A
B
VIN1+
7
6
PD1
5
VS-
Pin Functions
PIN
OPA837
OPA2837
FUNCTION(1)
DESCRIPTION
NAME
SOT-23
SC-70
VSSOP
WQFN
Amplifier power down.
PD
5
—
—
—
I
I
I
Low = disabled, high = normal operation (pin must be
driven).
Amplifier 1 power down.
Low = disabled, high = normal operation (pin must be
driven).
PD1
PD2
—
—
—
—
—
—
4
6
Amplifier 2 power down.
Low = disabled, high = normal operation (pin must be
driven).
VIN–
4
3
4
3
—
—
2
—
—
2
I
I
Inverting input pin
VIN+
Noninverting input pin
VIN1–
VIN1+
VIN2–
VIN2+
VOUT
VOUT1
VOUT2
VS–
—
—
—
—
1
—
—
—
—
1
I
Amplifier 1 inverting input pin
Amplifier 1 noninverting input pin
Amplifier 2 inverting input pin
Amplifier 2 noninverting input pin
Output pin
3
3
I
6
8
I
5
7
I
—
1
—
1
O
O
O
P
P
—
—
2
—
—
2
Amplifier 1 output pin
7
9
Amplifier 2 output pin
4
5
Negative power-supply pin
Positive power-supply input
VS+
6
5
8
10
(1) I = input, O = output, and P = power.
4
Copyright © 2017–2018, Texas Instruments Incorporated
OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.5
UNIT
V
Supply voltage
VS– to VS+
Supply turn-on/off maximum dV/dT(2)
1
V/µs
V
VI
VID
II
Input voltage
VS– – 0.5
VS+ + 0.5
±1
Differential input voltage
Continuous input current
Continuous output current(3)
V
±10
mA
mA
IO
±20
See Thermal Information:
Continuous power dissipation
OPA837
TJ
Maximum junction temperature
Operating free-air temperature
Storage temperature
150
°C
°C
°C
TA
–40
–65
125
150
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Staying below this ± supply turn-on edge rate prevents the edge-triggered ESD absorption device across the supply pins from turning
on.
(3) Long-term continuous output current for electromigration limits.
6.2 ESD Ratings
VALUE
±1500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
5
MAX
5.4
UNIT
VS+
TA
Single-supply voltage
Ambient temperature
V
–40
25
125
°C
Copyright © 2017–2018, Texas Instruments Incorporated
5
OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
6.4 Thermal Information: OPA837
OPA837
DBV
(SOT23-6)
DCK
(SC70)
THERMAL METRIC(1)
UNIT
6 PINS
194
129
39
5 PINS
203
152
76
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
26
58
ψJB
39
76
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2837
OPA2837
RUN
(WQFN-10)
DGK
(VSSOP-8)
THERMAL METRIC(1)
UNIT
10 PINS
124.9
72.0
8 PINS
182
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
63.5
63.2
103.6
7.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.3
ψJB
63.0
101.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2017–2018, Texas Instruments Incorporated
OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
6.6 Electrical Characteristics: VS = 5 V
at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
VOUT = 20 mVPP, G = 1
90
105
45
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SSBW
Small-signal bandwidth
VOUT = 20 mVPP, G = 2
MHz
VOUT = 20 mVPP, G = 10
5
GBP
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
VOUT = 20 mVPP, G = 10
45
50
MHz
MHz
MHz
V/µs
ns
LSBW
VOUT = 2 VPP, G = 2
26
VOUT = 200 mVPP, G = 2
From LSBW(2)
6
SR
105
10
tR, tF
Rise, fall time
VOUT = 0.5-V step, G = 2, input tR = 10 ns
VOUT = 2-V step, G = 2, input tR = 40 ns
VOUT = 2.0-V step, G = 1, input tR = 4 ns
VOUT = 2.0-V step, G = 1, input tR = 4 ns
11
Overshoot
7.0%
25
Settling time to 0.1%
Settling time to 0.01%
ns
ns
40
HD2
HD3
Second-order harmonic distortion f = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73)
–120
–145
4.7
35
dBc
dBc
nV/√Hz
Hz
Third-order harmonic distortion
Input voltage noise
f = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73)
f = 500 Hz
Voltage noise 1/f corner frequency See Figure 39
Input current noise f = 20 kHz
Current noise 1/f corner frequency See Figure 39
0.4
5
pA/√Hz
kHz
ns
Overdrive recovery time
G = 2, 2x output overdrive (see Figure 30)
75
Closed-loop output impedance
f = 1 MHz, G = 1 (see Figure 38)
f = 10 kHz
0.14
Ω
Channel-to-channel crosstalk
(OPA2837)
-126
dBc
dB
C
DC PERFORMANCE
AOL Open-loop voltage gain
VO = ±2 V, RL = 2 kΩ
120
–165
–205
–269
–269
–1.6
135
±30
±30
±30
±30
±0.4
±0.4
±0.67
340
340
340
340
1.5
A
A
B
B
B
B
B
B
A
B
B
B
B
A
B
B
B
A
TA ≈ 25°C
165
235
261
325
1.6
TA = 0°C to +70°C (DCK package)
Input-referred offset voltage
Input offset voltage drift(3)
µV
TA = –40°C to +85°C (DCK package)
TA = –40°C to +125°C (DCK package)
DCK package, TA = –40°C to +125°C
DBV, RUN package, TA = –40°C to +125°C
DGK package, TA = –40°C to +125°C
–2.0
2.0
µV/°C
TA ≈ 25°C
150
50
520
664
718
850
3.3
40
TA = 0°C to +70°C
Input bias current(4)
nA
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +125°C
50
50
Input bias current drift(3)
0.8
–40
–46
–56
–56
-60
nA/°C
TA ≈ 25°C (OPA837)
±6
TA = 0°C to +70°C
±6
52
Input offset current
TA = –40°C to +85°C
TA = –40°C to +125°C
±6
55
nA
±6
65
TA ≈ 25°C (OPA2837)
±8
60
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB
where this f–3dB is the typical measured 2-VPP bandwidth at gains of 1 V/V.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range. Typical drift specifications are ±1sigma. Maximum drift
specifications are set by min/max sample packaged test data using a wafer-level screened drift. Min/Max drift is not specified by final
automated test equipment (ATE) nor by QA sample testing.
(4) Current is considered positive out of the pin.
Copyright © 2017–2018, Texas Instruments Incorporated
7
OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
Electrical Characteristics: VS = 5 V (continued)
at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
pA/°C
µV
LEVEL(1)
TA = –40°C to +125°C
TA = –40°C to +125°C (OPA2837)
–250
–270
±40
±80
250
330
B
B
Input offset current drift(3)
Input-referred offset voltage
mismatch
T
A ≈ 25°C (OPA2837)
-220
50
220
A
INPUT
T
A ≈ 25°C, < 3-dB degradation in CMRR limit
–0.2
–0.2
3.8
0
0
A
B
A
B
Common-mode input range, low
Common-mode input range, high
V
V
TA = –40°C to +125°C, < 3-dB degradation in
CMRR limit
TA ≈ 25°C, < 3-dB degradation in CMRR limit
3.7
3.7
91
TA = –40°C to +125°C, < 3-dB degradation in
CMRR limit
3.8
CMRR
Common-mode rejection ratio
Input impedance common-mode
Input impedance differential mode
110
175 || 1.5
180 || 0.5
dB
A
C
C
MΩ || pF
kΩ || pF
OUTPUT
T
A ≈ 25°C, G = 2
TA = –40°C to +125°C, G = 5
A ≈ 25°C, G = 2
TA = –40°C to +125°C, G = 5
0.05
0.05
4.95
4.9
0.1
0.1
A
B
A
B
VOL
Output voltage, low
Output voltage, high
V
V
T
4.9
4.8
VOH
Maximum current into a resistive
load
T
A ≈ 25°C, ±1.6 V into 27 Ω, VIO < 2 mV
A ≈ 25°C, ±1.7 V into 37.4 Ω, AOL > 80 dB
±58
±45
±35
±70
±50
±45
0.6
mA
mA
mA
mΩ
A
A
C
C
Linear current into a resistive load
T
Linear current into a resistive load TA = –40°C to +125°C, ±1.31 V into 37.4 Ω,
overtemperature
AOL > 80 dB
Closed-loop output impedance
Gain of 1 V/V, ±30-mA DC
POWER SUPPLY
Specified operating voltage
2.7
564
408
5.4
625
865
V
B
A
B
T
A ≈ 25°C(5)
592
592
Quiescent operating current per
amplifier (5-V supply)
µA
TA = –40°C to +125°C
Supply current temperature
coefficient per amplifier
TA = –40°C to +125°C (see Figure 57)
1.1
95
92
1.9
110
108
2.4
µA/°C
dB
B
A
A
Positive power-supply rejection
ratio
+PSRR
–PSRR
Negative power-supply rejection
ratio
dB
POWER DOWN (Pin Must be Driven)
Enable voltage threshold
Specified on above VS– + 1.5 V
Specified off below VS– + 0.55 V
PD = 0 V to VS+
1.5
V
V
A
A
A
A
Disable voltage threshold
0.55
–50
4
Power-down pin bias current
Power-down quiescent current
50
10
nA
µA
PD ≤ 0.55 V
5
Power-down quiescent current
over temperature
PD ≤ 0.55 V, TA = –40°C to +125°C
10
µA
ns
ns
B
C
C
Time from PD = high to VOUT = 90% of final
value
Turnon time delay
Turnoff time delay
300
100
Time from PD = low to VOUT = 10% of original
value
(5) The typical specification is at 25°C TJ. The min, max limits are expanded for the automated test equipment (ATE) to account for an
ambient range from 22°C to 32°C with a 2-µA/°C temperature coefficient on the supply current.
8
Copyright © 2017–2018, Texas Instruments Incorporated
OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
6.7 Electrical Characteristics: VS = 3 V
at VS+ = 3 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
VOUT = 20 mVPP, G = 1
85
105
45
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SSBW
Small-signal bandwidth
VOUT = 20 mVPP, G = 2
MHz
VOUT = 20 mVPP, G = 10
5
GBP
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
VOUT = 20 mVPP, G = 10
40
50
MHz
MHz
MHz
V/µs
ns
LSBW
VOUT = 1 VPP, G = 2
30
VOUT = 200 mVPP, G = 2
From LSBW(2)
6
SR
65
tR, tF
Rise, fall time
VOUT = 0.5-V step, G = 2, input tR = 10 ns
VOUT = 2-V step, G = 2, input tR = 40 ns
VOUT = 0.5-V step, G = 1, input tR = 4 ns
VOUT = 0.5-V step, G = 1, input tR = 4 ns
10
11
Overshoot
7%
35
Settling time to 0.1%
Settling time to 0.01%
ns
ns
50
HD2
HD3
Second-order harmonic distortion f = 100 kHz, VO = 1 VPP, G = 1 (see Figure 73)
–125
–138
4.9
35
dBc
dBc
nV/√Hz
Hz
Third-order harmonic distortion
Input voltage noise
f = 100 kHz, VO = 1 VPP, G = 1 (see Figure 73)
f = 500 Hz
Voltage noise 1/f corner frequency See Figure 39
Input current noise f = 10 kHz
Current noise 1/f corner frequency See Figure 39
0.4
5
pA/√Hz
kHz
ns
Overdrive recovery time
G = 2, 2x output overdrive (see Figure 29)
65
Closed-loop output impedance
f = 1 MHz, G = 1 (see Figure 38)
f = 10 kHz
0.14
Ω
Channel-to-channel crosstalk
(OPA2837)
-126
dBc
dB
C
DC PERFORMANCE
VO = ±1 V, RL = 2 kΩ
120
110
133
133
±30
±30
±30
±30
±0.4
±0.4
±0.67
320
320
320
320
1.5
A
A
A
B
B
B
B
B
B
A
B
B
B
B
A
B
B
B
A
AOL Open-loop voltage gain
VO = ±1 V, RL = 2 kΩ (OPA2837)
TA ≈ 25°C
–165
–205
–269
–269
–1.6
–2.0
165
235
261
325
1.6
TA = 0°C to +70°C
Input-referred offset voltage
Input offset voltage drift(3)
µV
TA = –40°C to +85°C
TA = –40°C to +125°C
DCK package, TA = –40°C to +125°C
DBV, RUN package, TA = –40°C to +125°C
DGK package, TA = –40°C to +125°C
2.0
µV/°C
TA ≈ 25°C
145
50
510
659
708
840
3.3
40
TA = 0°C to +70°C
Input bias current(4)
nA
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +125°C
50
50
Input bias current drift(3)
0.8
–40
–46
–56
–56
–60
nA/°C
TA ≈ 25°C (OPA837)
±6
TA = 0°C to +70°C
±6
52
Input offset current
TA = –40°C to +85°C
TA = –40°C to +125°C
±6
55
nA
±6
65
TA ≈ 25°C (OPA2837)
±8
60
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 x VPEAK / √2) × 2π × f–3dB
where this f-3dB is the typical measured 2-Vpp bandwidth at gains of 1V/V.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range. Typical drift specifications are ±1sigma. Maximum drift
specifications are set by min/max sample packaged test data using a wafer-level screened drift. Min/Max drift is not specified by final
automated test equipment (ATE) nor by QA sample testing.
(4) Current is considered positive out of the pin.
Copyright © 2017–2018, Texas Instruments Incorporated
9
OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
Electrical Characteristics: VS = 3 V (continued)
at VS+ = 3 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
pA/°C
µV
LEVEL(1)
TA = –40°C to +125°C
TA = –40°C to +125°C (OPA2837)
–250
–250
±40
±80
250
330
B
B
Input offset current drift(3)
Input-referred offset voltage
mismatch
T
A ≈ 25°C (OPA2837)
-220
50
220
A
INPUT
T
A ≈ 25°C, < 3-dB degradation in CMRR limit
–0.2
–0.2
1.8
0
0
A
B
A
B
Common-mode input range, low
Common-mode input range, high
V
V
TA = –40°C to +125°C, < 3-dB degradation in
CMRR limit
TA ≈ 25°C, < 3-dB degradation in CMRR limit
1.7
1.7
90
TA = –40°C to +125°C, < 3-dB degradation in
CMRR limit
1.8
CMRR
Common-mode rejection ratio
Input impedance common-mode
Input impedance differential mode
105
300 || 1.5
180 || 0.5
dB
A
C
C
MΩ || pF
kΩ || pF
OUTPUT
T
A ≈ 25°C, G = 2
TA = –40°C to +125°C, G = 2
A ≈ 25°C, G = 2
TA = –40°C to +125°C, G = 2
0.05
0.10
2.95
2.9
0.1
0.2
A
B
A
B
VOL
Output voltage, low
Output voltage, high
V
V
T
2.9
2.8
VOH
Maximum current into a resistive
load
T
A ≈ 25°C, ±0.8 V into 17.5 Ω, VIO < 2 mV
A ≈ 25°C, ±0.9 V into 21.5 Ω, AOL > 80 dB
±45
±40
±32
±55
±45
±40
mA
mA
mA
A
A
C
Linear current into a resistive load
T
Linear current into a resistive load TA = –40°C to 125°C, ±0.7 V into 21.5 Ω, AOL
overtemperature > 80 dB
POWER SUPPLY
Specified operating voltage
2.7
547
404
5.4
607
817
V
B
A
B
T
A ≈ 25°C(5)
TA = –40°C to +125°C
A ≈ 25°C(5)
570
570
Quiescent operating current per
amplifier (OPA837, 3-V supply)
µA
Quiescent operating current per
amplifier (OPA2837, 3-V supply)
T
540
0.8
90
570
1.7
607
2.2
µA
µA/°C
dB
A
B
A
A
Supply current temperature
coefficient per amplifier
TA = –40°C to +125°C (see Figure 57)
Positive power-supply rejection
ratio
+PSRR
–PSRR
110
105
Negative power-supply rejection
ratio
88
dB
POWER DOWN (Pin Must be Driven)
Enable voltage threshold
Specified on above VS– + 1.5 V
Specified off below VS– + 0.55 V
PD = 0 V to VS+
1.5
V
V
A
A
A
A
Disable voltage threshold
0.55
–50
1
Power-down pin bias current
Power-down quiescent current
50
8
nA
µA
PD ≤ 0.55 V
3
Power-down quiescent current
over temperature
PD ≤ 0.55 V, TA = –40°C to +125°C
8
µA
ns
ns
B
C
C
Time from PD = high to VOUT = 90% of final
value
Turnon time delay
Turnoff time delay
300
100
Time from PD = low to VOUT = 10% of original
value
(5) The typical spec is at 25oC Tj. The min, max limits are expanded for ATE to account for ambient range from 22oC to 32oC with a +4-
uA/oC temperature coefficient on the supply current.
10
Copyright © 2017–2018, Texas Instruments Incorporated
OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
6.8 Typical Characteristics: VS = 5.0 V
at VS+ = 5.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
3
0
3
0
-3
-3
-6
-6
-9
-9
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-12
-12
-15
0.1
-15
0.1
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
D002
D001
See 图 75 and 表 3, VOUT = 20 mVPP, RLOAD = 2 kΩ
See 图 74 and 表 2, VOUT = 20 mVPP, RLOAD = 2 kΩ
图 2. Inverting Small-Signal Frequency Response
图 1. Noninverting Small-Signal Frequency Response
vs Gain
vs Gain
9
6
3
0
3
-3
0
-6
-3
-6
-9
-9
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
-12
-15
VO 2 VPP
VO = 2 VPP
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D003
D004
Gain = 2 V/V, RLOAD = 2 kΩ
Gain = –1 V/V, RLOAD = 2 kΩ
图 3. Noninverting Large-Signal Bandwidth vs VOPP
图 4. Inverting Large-Signal Bandwidth vs VOPP
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D005
D006
See 图 74 and 表 2, VOUT = 200 mVPP, RLOAD = 2 kΩ
图 5. Noninverting Response Flatness vs Gain
See 图 75 and 表 3, VOUT = 200 mVPP, RLOAD = 2 kΩ
图 6. Inverting Response Flatness vs Gain
版权 © 2017–2018, Texas Instruments Incorporated
11
OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
Typical Characteristics: VS = 5.0 V (接下页)
at VS+ = 5.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
1.2
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
VO = ±0.125 V
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
VO = ±0.125 V
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
-1.2
-1.2
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
Time (ns)
D007
D008
See 图 74, gain = 2 V/V,
See 图 75, gain = –1 V/V,
input edge rate set to stay below slew limiting
input edge rate set to stay below slew limiting
图 7. Noninverting Step Response vs Time and VOPP
图 8. Inverting Step Response vs Time and VOPP
0.1
0.08
0.06
0.04
0.02
0
0.1
0.08
0.06
0.04
0.02
0
AV = -1 , 500-mV Step, TR = 10 ns
AV = -1 , 2-V Step, TR = 40 ns
AV = -2 , 500-mV Step, TR = 10 ns
AV = -2, 2-V Step, TR = 40 ns
-0.02
-0.04
-0.06
-0.08
-0.1
-0.02
-0.04
-0.06
-0.08
-0.1
AV = 1, 500-mV Step, TR = 10 ns
AV = 1, 2-V Step, TR = 40 ns
AV = 2, 500-mV Step, TR = 10 ns
AV = 2, 2-V Step, TR = 40 ns
0
25
50
75 100 125 150 175 200 225 250
Time (ns)
0
25
50
75 100 125 150 175 200 225 250
Time (ns)
D009
D010
See 图 74 and 表 2
See 图 75 and 表 3
图 9. Simulated Noninverting Settling Time
图 10. Simulated Inverting Settling Time
5
4
5
4
VIN x 2 gain
VOUT (AV = 2)
VIN x -2 gain
VOUT (AV = -2)
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
50
250
450
650
850
1050
1250
1450
50
250
450
650
850
1050
1250
1450
Time (ns)
Time (ns)
D011
D012
See 图 74 and 表 2, gain = 2 V/V
图 11. Noninverting Overdrive Recovery
See 图 75 and 表 3, gain –2 V/V
图 12. Inverting Overdrive Recovery
12
版权 © 2017–2018, Texas Instruments Incorporated
OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
Typical Characteristics: VS = 5.0 V (接下页)
at VS+ = 5.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
-80
-90
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
-100
-110
-120
-130
-140
-150
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
10k
100k
Frequency (Hz)
1M
100
1k
RLOAD (W)
D013
D014
See 图 74, 图 75, 表 2, and 表 3, VOUT = 2 VPP
See 图 74, 图 75, 表 2, and 表 3, VOUT = 2 VPP,
f = 100 kHz
图 14. Harmonic Distortion vs RLOAD
图 13. Harmonic Distortion vs Frequency
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-110
-115
-120
-125
-130
-135
-140
HD2, Gain = 2 V/V
HD3, Gain = 2 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
HD2, +Gain
HD3, +Gain
HD2, -Gain
HD3, -Gain
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
1
10
Output Voltage (V)
Gain Magnitude (V/V)
D015
D016
See 图 74, 图 75, 表 2, and 表 3, VOUT = 2 VPP
,
See 图 74, 图 75, 表 2, and 表 3, VOUT = 2 VPP
,
f = 100 kHz
f = 100 kHz
图 15. Harmonic Distortion vs Output Voltage
图 16. Harmonic Distortion vs Gain Magnitude
-80
-85
-80
-85
HD2 (PGA 1)
HD3 (PGA 1)
HD2 (PGA 2)
HD3 (PGA 2)
-90
-90
-95
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
HD2
HD3
10k
100k
1M
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
D017
D018
See 图 87, VOUT = 2 VPP, f = 100 kHz
See 图 87, gain of 1 V/V or 2 V/V, VOUT = 2 VPP,
f = 100 kHz
图 18. Harmonic Distortion as 1-Bit PGA
图 17. Harmonic Distortion as Active Mux
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13
OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
6.9 Typical Characteristics: VS = 3.0 V
at VS+ = 3.0 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
3
0
3
0
-3
-3
-6
-6
-9
-9
-12
-15
-18
-21
-12
-15
-18
-21
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D019
D020
See 图 74 and 表 2, VOUT = 20 mVPP, RLOAD = 2 kΩ
See 图 75 and 表 3, VOUT = 20 mVPP, RLOAD = 2 kΩ
图 20. Inverting Small-Signal Response vs Gain
图 19. Noninverting Small-Signal Response vs Gain
3
0
3
0
-3
-3
-6
-6
-9
-9
-12
-15
-18
-21
-12
-15
-18
-21
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D021
D022
See 图 74, gain = 2 V/V
See 图 75, gain = –1 V/V
图 21. Noninverting Large-Signal Bandwidth vs VOPP
图 22. Inverting Large-Signal Bandwidth vs VOPP
1.2
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-1.2
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D024
D023
See 图 75 and 表 3, VOUT = 200 mVPP, RLOAD = 2 kΩ
图 24. Inverting Response Flatness vs Gain
See 图 74 and 表 2, VOUT = 200 mVPP, RLOAD = 2 kΩ
图 23. Noninverting Response Flatness vs Gain
14
版权 © 2017–2018, Texas Instruments Incorporated
OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
Typical Characteristics: VS = 3.0 V (接下页)
at VS+ = 3.0 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
0.6
0.4
0.2
0
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
VO = ±0.125 V
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
VO = ±0.125 V
VO = ±0.25 V
VO = ±0.5 V
-1.2
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
Time (ns)
D025
D026
See 图 74 and 表 2, gain = 2 V/V,
See 图 75 and 表 3, gain = –1 V/V,
input edge rate set to stay below slew limiting
input edge rate set to stay below slew limiting
图 25. Noninverting Step Response vs VOPP
图 26. Inverting Step Response vs VOPP
0.1
0.08
0.06
0.04
0.02
0
0.1
0.08
0.06
0.04
0.02
0
AV = -1, 500-mV Step, TR = 10 ns
AV = -1 , 2-V Step, TR = 40 ns
AV = -2 , 500-mV Step, TR = 10 ns
AV = -2 , 1-V Step, TR = 40 ns
-0.02
-0.04
-0.06
-0.08
-0.1
-0.02
-0.04
-0.06
-0.08
-0.1
AV = 1, 500-mV Step, TR = 10 ns
AV = 2 , 1-V Step, TR = 20 ns
AV = 2 , 500-mV Step, TR = 10 ns
0
25
50
75
100
125
150
175
200
0
25 50 75 100 125 150 175 200 225 250 275
Time (ns)
Time (ns)
D027
D028
See 图 74 and 表 2
See 图 75 and 表 3
图 27. Simulated Noninverting Settling Time
图 28. Simulated Inverting Settling Time
3
2
3
2
VIN x 2 gain
VOUT (AV = 2)
VIN x -1 gain
VOUT (AV = -1)
1
1
0
0
-1
-2
-3
-1
-2
-3
50
250
450
650
850
1050
1250
1450
50
250
450
650
850
1050
1250
1450
Time (ns)
Time (ns)
D029
D030
See 图 74 and 表 2, gain = 2 V/V
图 29. Noninverting Overdrive Recovery
See 图 75 and 表 3, gain = –1 V/V
图 30. Inverting Overdrive Recovery
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OPA837, OPA2837
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Typical Characteristics: VS = 3.0 V (接下页)
at VS+ = 3.0 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
-80
-90
-100
-105
-110
-115
-120
-125
-130
-135
-140
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
-100
-110
-120
-130
-140
-150
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
10k
100k
Frequency (Hz)
1M
100
1k
Load (W)
D031
D032
See 图 74, 图 75, 表 2, and 表 3, VOUT = 1 VPP, RLOAD = 2 kΩ
See 图 74, 图 75, 表 2, and 表 3, VOUT = 1 VPP
,
f = 100 kHz, RLOAD = 2 kΩ
图 31. Harmonic Distortion vs Frequency
图 32. Harmonic Distortion vs RLOAD
-100
-105
-110
-115
-120
-125
-130
-135
-140
-116
-118
-120
HD2, +Gain
HD3, +Gain
HD2, -Gain
HD3, -Gain
HD2, Gain = 2 V/V
-122
HD3, Gain = 2 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
-124
-126
-128
-130
-132
-134
-136
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1
10
VOPP (V)
Gain Magnitude (V/V)
D033
D034
See 图 74, 图 75, 表 2, and 表 3, RLOAD = 2 kΩ,
See 图 74, 图 75, 表 2, and 表 3, RLOAD = 2 kΩ,
f = 100 kHz
f = 100 kHz, VOUT = 1 VPP
图 33. Harmonic Distortion vs Output Swing
图 34. Harmonic Distortion vs Gain Magnitude
-90
-95
-80
-90
HD2
HD3
HD2 (PGA 1)
HD3 (PGA 1)
HD2 (PGA 2)
HD3 (PGA 2)
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-100
-110
-120
-130
-140
-150
10k
100k
1M
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
D035
D036
See 图 87, gain = 1 V/V, VOUT = 1 VPP, RLOAD = 2 kΩ
图 35. Harmonic Distortion as Active Mux
See 图 88, gain of 1 V/V and 2 V/V, VOUT = 1 VPP
,
RLOAD = 2 kΩ
图 36. Harmonic Distortion as 1-Bit PGA
16
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OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
6.10 Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
20
10
150
130
110
90
0
G = 1, 3-V supply
G = 1, 5-V supply
G = 2, 3-V supply
G = 2, 5-V supply
G = 5, 3-V supply
G = 5, 5-V supply
5-V AOL (dB)
3-V AOL (dB)
5-V AOL phase (è)
3-V AOL phase (è)
-30
-60
1
0.1
-90
70
-120
-150
-180
-210
-240
50
30
0.01
0.001
10
-10
1
10
100
1k
10k 100k 1M 10M 100M
Frequency (Hz)
10k
100k
1M
10M
Frequency (Hz)
D037
D038
No load simulation
图 74 and 表 2 (simulation)
图 37. Open-Loop Gain and Phase vs Frequency
图 38. Closed-Loop Output Impedance vs Frequency
10
250
200
150
100
50
5-V supply
3-V supply
+5-V En
+5-V In
+3-V En
+3-V In
1
0
-50
-100
-150
-200
0.1
10
100
1k
10k
100k
1M
10M
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Time (s)
D039
D040
Measured then fit to ideal 1/f model
Input-referred voltage noise RS = 0 Ω
图 40. Low-Frequency Voltage Noise vs Time
图 39. Input Spot Noise Density vs Frequency
-70
-75
120
110
100
90
80
70
60
50
40
30
20
-80
-85
-90
-95
-100
-105
-110
-115
-120
CMRR 5 V
CMRR 3 V
PSRR VCC 5 V
PSRR VEE 5 V
PSRR VCC 3 V
PSRR VEE 3 V
5-V 200-mVPP (Output)
5-V 2-VPP (Output)
3-V 200-mVPP (Output)
3-V 2-VPP (Output)
100k
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D042
D041
Simulated curves
图 42. Disabled Isolation Noninverting Input to Output vs
图 41. CMRR and PSRR vs Frequency
Frequency
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (接下页)
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
250
225
200
175
150
125
100
75
500
450
400
350
300
250
200
150
100
50
5-V Supply
3-V Supply
5-V Supply
3-V Supply
50
25
0
0
-130-110 -90 -70 -50 -30 -10 10 30 50 70 90 110 130
-40-35-30-25-20-15-10 -5
0
5 10 15 20 25 30 35 40
Input Offset Voltage (mV)
Input Offset Current (nA)
D043
D044
830 units at each supply voltage
830 units at each supply voltage
图 43. Input Offset Voltage Distribution
图 44. Input Offset Current Distribution
200
150
100
50
30
25
20
15
10
5
0
0
-5
-50
-10
-15
-20
-25
-30
-100
-150
-200
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (èC)
Ambient Temperature (èC)
D045
D046
50 units at 5-V and 3-V supply
50 units at 5-V and 3-V supply
图 45. Input Offset Voltage vs Ambient Temperature
图 46. Input Offset Current vs Ambient Temperature
16
15
14
13
12
11
10
9
8
7
6
5
60
55
50
45
40
35
30
25
20
15
10
5
5-V Supply
3-V Supply
5-V Supply
3-V Supply
4
3
2
1
0
0
2
1
-
0
2
4
6
8
1
2
4
6
8
2
0
5
0
5
0
5
0
5
0
5
0
5
0
5
7
-
5
2
0
7
5
2
0
7
5 2
-
2
5
0. 0. 0. 0.
1. 1. 1. 1.
-
-
2
2
2
1
1
1 1
100125 150175200225250
-1.8-1.6-1.4-1.2
-0.8-0.6-0.4-0.2
-
-
-
-
-
-
-
D047
D048
Input Offset Voltage Drift (mV/èC)
–40°C to +125°C fit, 82 units, DBV package
Input Offset Current Drift (pA/èC)
–40°C to +125°C fit, 82 units, DBV package
图 47. Input Offset Voltage Drift Distribution
图 48. Input Offset Current Drift Distribution
18
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ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (接下页)
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
140
130
120
110
100
90
21
18
15
12
9
AV = 1 V/V
AV = 2 V/V
AV = 5 V/V
AV = 10 V/V
Gain 1, 100 pF
Gain 1, 1000 pF
Gain 2, 100 pF
Gain 2, 1000 pF
Gain 5, 100 pF
Gain 5, 1000 pF
Gain 10, 100 pF
Gain 10, 1000 pF
80
70
6
60
50
3
40
0
30
20
-3
-6
10
0
1M
10M
Frequency (Hz)
100M
1G
1
10
100
CLOAD (pF)
1k
10k
D050
D049
See 图 66 and 表 2, small signal,
targeting 30° phase margin
图 50. Small-Signal Frequency Response vs CLOAD
图 49. Output Resistor vs CLOAD
With Recommended ROUT
3
2
3
2
1
0
Power-Down Voltage (5 V)
Output Voltage (5 V)
Power-Down Voltage (3 V)
Output Voltage (3 V)
1
0
-1
-2
-3
-1
Power-Down Voltage (5 V)
Output Voltage (5 V)
Power-Down Voltage (3 V)
Output Voltage (3 V)
-2
-3
1
1.1
1.2
Time (ms}
1.3
1.4
1.5
0.8
0.9
1
1.1
Time (ms)
1.2
1.3
D051
D052
图 51. Turn-On Time to Sinusoidal Input
图 52. Turn-Off Time to Sinusoidal Input
5.5
0.006
5.5
0.006
0.005
0.004
0.003
0.002
0.001
0
5-V Disable
5-V VOUT
5-V %Err
3-V Disable
3-V VOUT
3-V %Err
5-V Disable
5-V VOUT
5-V %Err
3-V Disable
3-V VOUT
3-V %Err
5
4.5
4
0.005
0.004
0.003
0.002
0.001
0
5
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
-0.001
-0.002
-0.003
-0.004
-0.005
-0.001
-0.002
-0.003
-0.004
-0.005
1.5
1
1.5
1
0.5
0
0.5
0
0
0.1
0.2
0.3
0.4
0
0.1
0.2
0.3
0.4
0.5
Time From Turn-On (ms)
Time from Turn-On (ms)
D053
D054
图 53. Gain of 1 Turn-On Time to Final DC Value at Midscale
图 54. Gain of 2 Turn-On Time to Final DC Value at Midscale
(Simulated)
(Simulated)
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (接下页)
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
3
2
3
2.5
2
1.5
1
1
VOUT +5 V
VOUT +3 V
VOUT -5 V
VOUT -3 V
VOUT +5 V
VOUT +3 V
VOUT -5 V
VOUT -3 V
0.5
0
0
-0.5
-1
-1
-2
-1.5
-2
-2.5
-3
-3
100
1k
100.1m
1
10
RLOAD (W)
IOUT (mA)
D055
D056
图 55. Output Voltage Swing vs Load Resistor
图 56. Output Saturation Voltage vs Load Current
800
700
600
500
400
300
200
100
0
840
800
760
720
680
640
600
560
520
480
440
IQ 5 V
IQ 3 V
0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
PD-VS- (V)
-40
-20
0
20
40
60
80
100
120
D058
Ambient Temperature (èC)
D057
50 units at 5-V and 3-V supply
图 57. Supply Current vs Ambient Temperature
图 58. Supply Current vs Power-Down Voltage
(Turn-On Higher Than Turn-Off)
150
120
90
800
20
15
10
5
5-V IB-
5-V IB+
5-V IOS
3-V IB-
3-V IB+
3-V IOS
700
600
500
400
300
200
100
0
60
30
0
0
-30
-60
-90
-120
-150
-5
-10
-15
-20
-0.4 0.1
0.6
1.1
1.6
2.1
2.6
3.1
3.6
4.1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Input Common-Mode Voltage (Single Supply, V)
Input Common-Mode Voltage (V)
D059
D060
12 units, 5-V and 3-V supplies
Measured single device, 5-V and 3-V supplies
图 60. Input Bias and Offset Current vs VICM
图 59. Input Offset Voltage vs
Input Common-Mode Voltage
20
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ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (接下页)
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
Ch-A to Ch-B
Ch-B to Ch-A
-130
-135
10k
100k
1M
10M 100M
Frequency (Hz)
D061
Crosstalk for the OPA2837 only
图 61. Crosstalk vs Frequency
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7 Detailed Description
7.1 Overview
The OPA837 and OPA2837 are single- and dual-channel, power efficient, unity-gain stable, voltage-feedback
amplifiers (VFAs). Combining a negative rail input stage and a rail-to-rail output (RRO) stage, the OPAx837
provides a flexible solution where exceptional precision and wide bandwidth at low power are required. This
50-MHz gain bandwidth product (GBP) amplifier requires less than 0.65 mA of supply current per channel over a
2.7-V to 5.4-V total supply operating range. A shutdown feature on the OPA837 6-pin package version provides
power savings where the system requires less than 10 µA when shut down. Offering a unity-gain bandwidth
greater than 100 MHz, the OPAx837 provides less than –118-dBc THD at 100 kHz and a 2-VPP output.
7.2 Functional Block Diagrams
The OPAx837 is a standard voltage-feedback op amp with two high-impedance inputs and a low-impedance
output. 图 62 and 图 63 show the supported standard applications circuits. These application circuits are shown
with a DC VREF on the inputs that set the DC operating points for single-supply designs. The VREF is often
ground, especially for split-supply applications.
VSIG
VS+
VREF
VIN
VOUT
OPA837
RG
GVSIG
VREF
VREF
VS-
RF
图 62. Noninverting Amplifier
VS+
VREF
VSIG
VREF
VOUT
OPA837
RG
GVSIG
V
IN
VREF
VS-
RF
图 63. Inverting Amplifier
22
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www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
7.3 Feature Description
7.3.1 OPA837 Comparison
表 1 lists several members of the device family that includes the OPA837.
表 1. Device Family Comparison(1)
INPUT NOISE
VOLTAGE
(nV/√Hz)
Av = +1
BANDWIDTH (MHz)
5-V IQ
(mA, Max 25°C)
2-VPP THD
(dBc, 100 kHz)
RAIL-TO-RAIL
INPUT/OUTPUT
PART NUMBER
DUALS
OPA837
OPA838
LMV118
LMH6647
OPA835
OPA625
OPA836
105
—
0.63
0.99
0.9
4.7
1.9
40
–118
–110
—
VS–, output
VS–, output
VS–, output
Input, output
VS–, output
VS–, output
VS–, output
OPA2837
—
45
—
55
1.6
17
–75
LMH6646
OPA2835
OPA2625
OPA2836
56
0.35
2.2
9.4
2.5
4.6
–104
–120
–118
120
205
1.0
(1) For a complete selection of TI high speed amplifiers, visit www.ti.com.
7.3.2 Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier with high CMRR, the design must remain within the input
common-mode voltage range (VICR) of an op amp. These ranges are referenced off of each supply as an input
headroom requirement. Ensured operation at 25°C is maintained to the negative supply voltage and to within
1.3 V of the positive supply voltage. The common-mode input range specifications in the Electrical
Characteristics table use CMRR to set the limit. The limits are selected to ensure CMRR does not degrade more
than 3 dB below the minimum CMRR value if the input voltage is within the specified range.
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally 0 V);
and the input common-mode voltage is analyzed at either input pin with the other input pin assumed to be at the
same potential. The voltage at VIN+ is simple to evaluate. In the noninverting configuration of 图 62, the input
signal, VIN, must not violate the VICR. In the inverting configuration of 图 63, the reference voltage, VREF, must be
within the VICR
.
The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For one 5-V
supply, the typical linear input voltage ranges from –0.2 V to 3.8 V and –0.2 V to 1.5 V for a 2.7-V supply. The
delta headroom from each power-supply rail is the same in either case: –0.2 V and 1.2 V, respectively.
7.3.3 Output Voltage Range
The OPAx837 is a rail-to-rail output op amp. Rail-to-rail output typically means that the output voltage swings to
within 100 mV of the supply rails. There are two different ways to specify this feature: one is with the output still
in linear operation and another is with the output saturated. Saturated output voltages are closer to the power-
supply rails than the linear outputs, but the signal is not a linear representation of the input. Saturation and linear
operation limits are affected by the output current, where higher currents lead to more voltage loss in the output
transistors; see 图 55.
The Electrical Characteristics tables list saturated output voltage specifications with a 2-kΩ load. 图 55 illustrates
the saturated voltage-swing limits versus output load resistance, and 图 56 illustrates the output saturation
voltage versus load current. Given a light load, the output voltage limits have nearly constant headroom to the
power rails and track the power-supply voltages. For example, with
a 2-kΩ load and a single
5-V supply, the linear output voltage ranges from 0.10 V to 4.9 V and ranges from 0.1 V to 2.6 V for a 2.7-V
supply. The delta from each power-supply rail is the same in either case: 0.1 V.
With devices like the OPA837 and OPA2837 where the input range is lower than the output range, typically the
input limits the available signal swing only in a noninverting gain of 1 V/V. Signal swing in noninverting
configurations in gains greater than +1 V/V and inverting configurations in any gain are typically limited by the
output voltage limits of the op amp.
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7.3.4 Power-Down Operation
The OPA837 includes a power-down mode in the 6-pin SOT23-6 package. Under logic control, the amplifier can
switch from normal operation to a standby current of less than 10 µA. When the PD pin is connected high, the
amplifier is active. Connecting the PD pin low disables the amplifier and places the output in a high-impedance
state. When the amplifier is configured as a unity-gain buffer, the output stage is in a high DC-impedance state.
A new feature in the OPA837 is a switch from the external inverting input pin to the internal active transistors.
This switch operates with the disable pin function to open up the connection to the internal devices when
powered down. Operating in unity gain provides a high-impedance voltage into both the output and inverting
input pins. This feature allows direct active multiplexer operation to be implemented; see 图 87. The TIDA-01565
Wired OR MUX and PGA Reference Design demonstrates the use of the OPAx837 in wired-OR multiplexer and
programmable gain amplifier applications. When disabled, the internal input devices on the inverting input
approximately follow the noninverting input on the other side of the open switch through the back-to-back
protection diodes across the inputs. When powered up, these diodes (two in each direction) act to limit overdrive
currents into the active transistors.
The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used,
PD must be tied to the positive supply rail.
PD logic states are referenced relatively low to the negative supply rail, VS–. When the op amp is powered from a
single-supply and ground, and the disable line is driven from logic devices with similar VDD voltages to the op
amp, the disable operation does not require any special consideration. The OPA837 is specified to be off with PD
driven to within 0.55 V of the negative supply and specified to be on when driven more than 1.5 V above the
negative supply. Slight hysteresis is provided around a nominal 1-V switch point; see 图 58. When the op amp is
powered from a split supply with VS– below ground, a level shift logic swing below ground is required to operate
the disable function.
7.3.5 Low-Power Applications and the Effects of Resistor Values on Bandwidth
The OPAx837 can use a direct short in the feedback for a gain of 1 V/V. 表 2 gives a list of recommended values
over gain for an increasing noninverting gain target. This table was produced by increasing the R values until
they added 50% of the total output noise power. Higher values can be used to reduce power at the cost of higher
noise. Lower values can be used to reduce the total output noise at the cost of more load power in the feedback
network. Stability is also impaired going to very high values because of the pole introduced into the feedback
path with the inverting input capacitance (1.5-pF common-mode). In low-power applications, reducing the current
in the feedback path is preferable by increasing the resistor values. Using larger value resistors has two primary
side effects (other than lower power) because of the interactions with the inverting input parasitic capacitance.
Using large value resistors lowers the bandwidth and lowers the phase margin. When the phase margin is
lowered, peaking in the frequency response and overshoot and ringing in the pulse response results.
图 64 shows the gain = 2 V/V (6 dB) small-signal frequency response with RF and RG equal to 1 kΩ, 2 kΩ, 5 kΩ,
10 kΩ, and 20 kΩ. This test was done with RL = 2 kΩ. Lower RL values can reduce the peaking because of RL
loading effects, but higher values do not have a significant effect.
18
Rf = 1 kOhm
Rf = 2 kOhm
Rf = 5 kOhm
Rf = 10 kOhm
Rf = 20 kOhm
15
12
9
Rf = 20 kOhm || 1.5 pF
6
3
0
10k
100k
1M
Frequency (Hz)
10M
100M
D063
图 64. Frequency Response With Various RF = RG Resistor Values
24
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As expected, larger value resistors cause lower bandwidth and peaking in the response (peaking in frequency
response is synonymous with overshoot and ringing in pulse response). Adding a 1.5-pF capacitor in parallel with
RF (equal to the input common-mode capacitance) helps compensate the phase margin loss and restores flat
frequency response. 图 65 shows the test circuit.
VIN
VOUT
RG
OPA837
2 kW
RF
Optional CF
图 65. G = 2 Test Circuit for Various Gain-Setting Resistor Values
7.3.6 Driving Capacitive Loads
The OPAx837 can drive a parasitic load capacitance up through 4 pF on the output with no special
considerations. When driving capacitive loads greater than 4 pF, TI recommends using a small resistor (RO) in
series with the output as close to the device as possible. Without RO, output capacitance interacts with the output
impedance of the amplifier causing phase shift in the loop gain of the amplifier that reduces the phase margin.
This reduction causes peaking in the frequency response and overshoot and ringing in the pulse response.
Inserting RO isolates the phase shift from the loop-gain path and restores the phase margin; however RO can
also limit bandwidth to the capacitive load.
图 66 shows the test and 图 49 illustrates the recommended values of RO versus capacitive loads, CL using a 30°
phase margin target for the op amp. See 图 50 for the frequency responses with various values of CL and ROUT
parametric on gain.
RO
VIN
VOUT
OPA837
2 kΩ
CL
图 66. ROUT versus CL Test Circuit
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7.4 Device Functional Modes
7.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
To facilitate testing with common lab equipment, the OPA837EVM (see the OPA835DBV and OPA836DBV EVM
User's Guide) allows split-supply operation. This configuration eases lab testing because the mid-point between
the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers, and
other lab equipment have inputs and outputs that prefer a ground reference for DC-coupled testing.
图 67 shows a simple noninverting configuration analogous to 图 62 with a ±2.5-V supply and VREF equal to
ground. The input and output swing symmetrically around ground. For ease of use, split supplies are preferred in
systems where signals swing around ground. In this example, an optional bias current cancellation resistor is
used in series with the noninverting input. For DC-coupled applications, set this resistor to be equal to the
parallel combination of RF and RG. This resistor increases the noise contribution at the input because of that
resistor noise (see the Output Noise Calculations section).
+2.5 V
RF // RG
VOUT
RG
OPA837
VSIG
Load
-2.5 V
RF
图 67. Split-Supply Operation
图 68 shows the step response for this gain of 2-V/V circuit with a ±1-V input to a ±2-V output. For a 4-V output
step, the input edge rate is set to 40 ns to avoid slew limiting.
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
Input
-2
Output
-2.5
0
200
400
600
800
1000
1200
Time (ns)
D064
图 68. VIN and VOUT vs Time
26
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Device Functional Modes (接下页)
7.4.2 Single-Supply Operation (2.7 V to 5.4 V)
Most newer systems use a single power supply to improve efficiency and to simplify power-supply design. The
OPAx837 can be used with single-supply power (ground for the negative supply) with no change in performance
from split supply, as long as the input and output pins are biased within the linear operating region of the device.
The outputs nominally swing rail-to-rail with approximately a 100-mV headroom required for linear operation. The
inputs can typically swing 0.2 V below the negative rail (typically ground) and to within 1.2 V of the positive
supply. For DC-coupled single-supply operation, the input swing is below the available output swing range for
noninverting gains greater than 1.30 V/V. Typically, the 1.2-V input headroom required to the positive supply only
limits output swing range for a unity-gain buffer.
To change the circuit from split supply to single-supply, level shift all voltages by half the difference between the
power-supply rails. For example, 图 69 depicts changing from a ±2.5-V split supply to a 5-V single-supply. The
load is shown as mid-supply referenced but can be grounded as well.
5 V
VOUT
RG
OPA837
VSIG
Load
RF
2.5 V
图 69. Single-Supply Concept
A practical circuit has an amplifier or other circuit providing the bias voltage for the input, and the output of this
amplifier stage provides the bias for the next stage.
图 70 shows a typical noninverting amplifier circuit. With 5-V single-supply, a mid-supply reference generator is
needed to bias the negative side through RG. To cancel the voltage offset that is otherwise caused by the input
bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of 2 V/V is required and
RF = 2 kΩ, select RG = 2 kΩ to set the gain, and R1 = 1 kΩ for bias current cancellation which reduces the output
DC error to IOS × RF. The value for C is dependent on the reference, and TI recommends a value of at least
0.1 µF to limit noise. The frequency response flatness is impacted by the AC impedance, including the reference
and capacitor added to the RG element.
Signal and bias
from previous stage
VSIG
2.5 V
5 V
R1
RO
VOUT
OPA837
GVSIG
RG
2.5 V
REF
2.5 V
5 V
C
Signal and bias to
next stage
RF
图 70. Noninverting Single-Supply Operation With Reference
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Device Functional Modes (接下页)
图 71 shows a similar noninverting single-supply scenario with the reference generator replaced by the Thevenin
equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5-V supply and
are used to bias the negative side with the parallel sum equal to the equivalent RG to set the gain. To cancel the
voltage offset that is otherwise caused by the input bias currents, R1 is selected to be equal to RF in parallel with
RG’ in parallel with RG” (R1= RF || RG’ || RG”). For example, if a gain of 2 V/V is required and RF = 2 kΩ, selecting
RG’ = RG” = 4 kΩ gives an quivalent parallel sum of 2 kΩ, sets the gain to 2, and references the input to mid-
supply (2.5 V). R1 is set to 1 kΩ for bias current cancellation. The resistor divider costs less than the 2.5-V
reference in 图 70 but increases the current from the 5-V supply. Any noise or variation on the 5-V supply now
also comes into the circuit as an input through the biasing path.
Signal and bias
from previous stage
VSIG
2.5 V
5 V
R1
RO
VOUT
RG’
OPA837
GVSIG
5 V
2.5 V
RG”
Signal and bias to
next stage
RF
图 71. Noninverting Single-Supply Operation With Resistor Mid-Supply Biasing
图 72 shows a typical inverting amplifier circuit. With a 5-V single supply, a mid-supply reference generator is
needed to bias the positive side through R1. To cancel the voltage offset that is otherwise caused by the input
bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of –2 V/V is required and
RF = 2 kΩ, select RG = 1 kΩ to set the gain and R1 = 667 Ω for bias current cancellation. The value for C is
dependent on the reference, but TI recommends a value of at least 0.1 µF to limit noise into the op amp.
5 V
R1
2.5 V
REF
RO
5 V
V
OPA837
OUT
C
GVSIG
2.5 V
RG
VSIG
Signal and bias to
next stage
RF
2.5 V
Signal and bias
from previous stage
图 72. Inverting Single-Supply Operation With Reference
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Device Functional Modes (接下页)
图 73 shows a similar inverting single-supply scenario with the reference generator replaced by the Thevenin
equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply and are
used to bias the positive side. To cancel the voltage offset that is otherwise caused by the input bias currents,
set the parallel value of R1 and R2 equal to the parallel value of RF and RG. C must be added to limit coupling of
noise into the positive input. For example, if gain of –2 V/V is required and RF = 2 kΩ, select RG = 1 kΩ to set the
gain. R1 = R2 = 2 × 667 Ω = 1.33 kΩ for the mid-supply voltage bias and for op-amp input-bias current
cancellation. A good value for C is 0.1 µF. The resistor divider costs less than the 2.5-V reference in 图 72 but
increases the current from the 5-V supply. Any noise or variation in the 5-V supply also comes into the circuit
through this bias setup but be band-limited by the pole formed with R1 || R2 and C.
5 V
5 V
R1
RO
VOUT
OPA837
R2
C
GVSIG
2.5 V
RG
RF
Signal and bias to
next stage
VSIG
2.5 V
Signal and bias
from previous stage
图 73. Inverting Single-Supply Operation With Resistor Midsupply Biasing
These examples are only a few of the ways to implement a single-supply design. Many other designs exist that
can often be simpler if AC-coupled inputs are allowed. A good compilation of options can be found in the Single-
Supply Op Amp Design Techniques application report.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Noninverting Amplifier
The OPAx837 can be used as a noninverting amplifier with a signal input to the noninverting input, VIN+. A basic
block diagram of the circuit is illustrated in 图 62. VREF is often ground when split supplies are used.
Calculate the amplifier output according to 公式 1 if VIN = VREF + VSIG
.
æ
ö
÷
ø
RF
V
OUT
= VSIG 1 +
+ VREF
ç
RG
è
(1)
The signal gain of the circuit is set by 公式 2, and VREF provides a reference around which the input and output
signals swing. Output signals are in-phase with the input signals within the flat portion of the frequency response.
For a high-speed, low-noise device such as the OPAx837, the values selected for RF (and RG for the desired
gain) can strongly influence the operation of the circuit. For the characteristic curves, the noninverting circuit of 图
74 shows the test configuration set for a gain of 2 V/V. 表 2 lists the recommended resistor values over gain.
RF
G = 1 +
RG
(2)
RG 2 kΩ
RF 2 kΩ
50-Ω
source
VEE
Network
Analyzer
50-Ω
Cable
U1 OPA837
œ
R3 1.96 kΩ
2-kΩ load
50-Ω
Cable
RS 50 Ω
+
+
PD
VM1
V
Network
Analyzer
VCC
VCC
VEE
+
+
V1 2.5
V2 -2.5 V
图 74. Characterization Test Circuit for Network, Spectrum Analyzer
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Application Information (接下页)
表 2 lists the recommended resistor values from target gains of 1 V/V to 10 V/V where standard E96 values are
shown. This table controls the RF and RG values to set the resistor noise contribution at approximately 50% of
the total output noise power. These values increase the spot noise at the output over what the op amp voltage
noise produces by 41%. Lower values reduce the output noise of any design at the cost of more power in the
feedback circuit. Using the TINA model and simulation tool shows the impact of different resistor value choices
on response shape and noise.
表 2. Noninverting Recommended Resistor Values
TARGET GAIN (V/V)
RF (Ω)
0
RG (Ω)
Open
2370
2000
1130
787
ACTUAL GAIN (V/V)
GAIN (dB)
0.00
1
1.5
2
1.00
1.50
2.00
3.00
4.01
5.02
5.99
7.04
7.97
9.04
10.08
1190
2000
2260
2370
2490
2550
2610
2670
2670
2670
3.53
6.02
3
9.54
4
12.07
14.02
15.55
16.95
18.03
19.13
20.07
5
619
6
511
7
432
8
383
9
332
10
294
8.1.2 Inverting Amplifier
The OPAx837 can be used as an inverting amplifier with a signal input to the inverting input, VIN–, through the
gain-setting resistor RG. A basic block diagram of the circuit is illustrated in 图 63.
The output of the amplifier can be calculated according to 公式 3 if VIN = VREF + VSIG and the noninverting input
is biased to VREF
.
æ
ö
÷
ø
-RF
V
= V
SIG ç
+ V
REF
OUT
RG
è
(3)
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The signal gain of the circuit is set by 公式 4 and VREF provides a reference point around which the input and
output signals swing. For bipolar-supply operation, VREF is often ground. The output signal is 180˚ out-of-phase
with the input signal in the pass band of the application. 图 75 shows the 50-Ω input matched configuration used
for the inverting characterization plots set up for a gain of –1 V/V. In this case, an added termination resistor, RT,
is placed in parallel with the input RG resistor to provide an impedance match to 50-Ω test equipment. The output
network appears as a 2-kΩ load but with a 50-Ω source to the network analyzer. This output interface network
does add a 37.9-dB insertion loss that is normalized out in the characterization curves. 表 3 lists the suggested
values for RF, RG, and RT for inverting gains from –0.5 V/V to –10 V/V. If a 50-Ω input match is not required,
eliminate the RT element.
-RF
G =
RG
(4)
Network
Analyzer
Gain of -1 V/V
50-Ω
RS 50 Ω
RG 2 kΩ
RF 2 kΩ
Cable
+
„ 50-Ω source
VEE
Network
Analyzer
50-Ω
Cable
œ
R1 1.96 kΩ
+
+
PD
2-kΩ load ‰
VCC
+
VEE
V
+
VCC
-2.5 V
2.5 V
图 75. Inverting Characterization Circuit for Network Analyzer
表 3. Inverting Recommended Resistor Values
INVERTING GAIN
(V/V)
STANDARD RT
RF (Ω)
RG (Ω)
INPUT ZI (Ω)
ACTUAL (V/V)
GAIN (dB)
(Ω)
51.1
51.1
52.3
53.6
54.9
54.9
56.2
57.6
59
–0.5
–1
1190
2000
2260
2370
2490
2550
2610
2670
2670
2670
2670
2370
2000
1130
787
619
511
432
383
332
294
267
50.02
49.83
49.99
50.18
50.43
49.57
49.73
50.07
50.10
50.11
50.25
–0.50
–1.00
–2.00
–3.01
–4.02
–4.99
–6.04
–6.97
–8.04
–9.08
–10.00
–5.98
0.00
–2
6.02
–3
9.58
–4
12.09
13.96
15.62
16.87
18.11
19.16
20.00
–5
–6
–7
–8
–9
60.4
61.9
–10
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8.1.3 Output DC Error Calculations
The OPAx837 can provide excellent DC signal accuracy because of its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full
advantage of this low input offset voltage, pay careful attention to input bias current cancellation. The low-noise
input stage for the OPAx837 has a relatively high input bias current (0.34 µA typical out the pins) but with a close
match between the two input currents. The OPAx837 is a negative rail input device using PNP input devices
where the base current flows out of the device pins. A large resistor to ground on the V+ input shifts the pin
voltage positively because of the input bias current. The mismatch between the two input bias currents is very
low, typically only ±10 nA of input offset current. Match the DC source impedances out of the two inputs to
reduce the total output offset voltage. 图 67 illustrates an example of resistor matching for bias current
cancellation. Analyzing the simple circuit of 图 67 (using a gain of 2-V/V target with RF = RG = 2 kΩ) illustrates
that the noise gain for the input offset voltage drift is 1 + 2 kΩ / 2 kΩ = 2 V/V. This value results in an output drift
term of ±1.6 µV/°C × 2 = ±3.2 µV/°C (DCK package). Because the two impedances out of the inputs are
matched, the residual error from the maximum ±250 pA/°C offset current drift is this maximum IOS drift times the
2-kΩ feedback resistor value, or ±50 µV/°C. The total output DC error drift band is ±53.2 µV/°C. If the output DC
drift is more important than reduced feedback currents, lower the resistor values to reduce the dominant drift
term resulting from the IOS term.
8.1.4 Output Noise Calculations
The unity-gain stable, voltage-feedback OPAx837 op amp offers among the lowest input voltage and current
noise terms for any device with a supply current less than 0.7 mA. 图 76 shows the op amp noise analysis model
that includes all noise terms. In this model, all noise terms are shown as noise voltage or current density terms in
nV/√Hz or pA/√Hz.
E
NI
+
OPA837
E
O
R
S
I
BN
E
RS
R
F
4kTRS
4kTRF
R
G
I
BI
4kT
RG
4kT = 1.6E œ 20J
at 290°K
图 76. Op Amp Noise Analysis Model
The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation is adding all the contributing noise powers at the output by superposition,
then taking the square root to return to a spot noise voltage. The last term includes the noise for both the RG and
RF resistors. 公式 5 shows the general form for this output noise voltage using the terms presented in 图 76.
ENI + I R + 4kTR NG + I R 2 + 4kTRFNG
» ÿ
BN S S BI F
2
2
EO
=
(
)
(
)
⁄
(5)
Dividing this expression by the noise gain (NG = 1 + RF / RG), as shown in 公式 6, gives the equivalent input
referred spot noise voltage at the noninverting input.
2
I R
4kTRF
NG
≈
’
2
EN = EN2I + IBNRS + 4kTRS +
+
BI
F
(
)
∆
«
÷
◊
NG
(6)
33
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Using the resistor values listed in 表 2 with RS = 0 Ω results in a constant input-referred voltage noise of
< 7 nV/√Hz. Reducing the resistor values can reduce this noise value towards the 4.7 nV/√Hz intrinsic to the
OPA837. As shown in 公式 5, adding the RS for bias current cancellation in noninverting mode adds the noise
from the RS to the total output noise. In inverting mode, bypass the RS bias current cancellation resistor with a
capacitor for the best noise performance. For more details on op amp noise analysis, see the Noise Analysis for
High-Speed Op Amps application report.
8.1.5 Instrumentation Amplifier
图 77 is an instrumentation amplifier that combines the high input impedance of the differential-to-differential
amplifier circuit and the common-mode rejection of the differential-to-single-ended amplifier circuit. This circuit is
often used in applications where high input impedance is required (such as taps from a differential line) or in
cases where the signal source is a high impedance.
VIN-
½OPA837
VSIG-
RF2
VCM
RG2
RG2
RF1
RG1
VOUT
OPA837
RF1
G[(VSIG+)-(VSIG-)]
VSIG+
RF2
VREF
VCM
½OPA837
VREF
VIN+
图 77. Instrumentation Amplifier (INA)
The output of the amplifier can be calculated according to 公式 7 if VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG–
.
æ
ö æ
ö
÷
ø
2R
RF2
RG2
F1 ÷ ç
V
=
V
IN+ - V
´ 1 +
+ V
REF
(
)
ç
IN-
OUT
RG1
è
ø è
(7)
公式 8 shows the signal gain of the circuit. The input VCM is rejected, and VREF provides a reference voltage or
level shift around which the output signal swings. The single-ended output signal is in-phase to the lower input
signal polarity.
æ
ö æ
ö
÷
ø
2R
RF2
F1 ÷ ç
RG1
G = 1 +
ç
RG2
è
ø è
(8)
Integrated INA solutions are available, but the OPAx837 device provides a high-frequency solution at relatively
low power (< 1.8 mA for the three op-amp solution). For best CMRR performance, resistors must be matched. A
good rule of thumb is CMRR ≈ the resistor tolerance; so a 0.1% tolerance provides approximately 60-dB CMRR.
For higher gain INA implementations with higher bandwidths, apply the OPA838 to the circuit of 图 77.
8.1.6 Attenuators
The noninverting circuit of 图 62 has a minimum gain of 1. To implement attenuation, a resistor divider can be
placed in series with the positive input, and the amplifier set for a gain of 1 V/V by shorting VOUT to VIN– and
removing RG. Because the op amp input is high impedance, the resistor divider sets the attenuation.
The inverting circuit of 图 63 is used as an attenuator by making RG larger than RF. The attenuation is the
resistor ratio. For example, a 10:1 attenuator can be implemented with RF = 2 kΩ and RG = 20 kΩ.
34
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8.1.7 Differential to Single-Ended Amplifier
图 78 shows a differential amplifier that converts differential signals to single-ended in a single stage and
provides gain (or attenuation) and level shifting. This circuit can be used in applications such as a line receiver
for converting a differential signal from a Cat5 cable to a single-ended output signal.
VSIG-
RF
VCM
RG
VIN-
VOUT
RG
OPA837
VIN+
VSIG+
G[(VSIG+)-(VSIG-)]
VREF
RF
VCM
VREF
图 78. Differential to Single-Ended Amplifier
The output of the amplifier can be calculated according to 公式 9 if VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG–
.
æ
ç
è
ö
÷
ø
RF
VOUT
=
V
- V
´
+ VREF
(
)
IN+
IN-
RG
(9)
The signal gain of the circuit is shown in 公式 10, VCM is rejected, and VREF provides a level shift or reference
voltage around which the output signal swings. The single-ended output signal is in-phase with the noninverting
input signal. VREF is often ground when split supplies are used on the op amp.
RF
G =
RG
(10)
Line termination can be accomplished by adding a shunt resistor across the VIN+ and VIN– inputs. The differential
impedance is the shunt resistance in parallel with the input impedance of the amplifier circuit, which is usually
much higher. For low gain and low line impedance, the resistor value to add is approximately the impedance of
the line. For example, if a 100-Ω Cat5 cable is used with a gain of 1 V/V amplifier and RF = RG = 2 kΩ, adding a
100-Ω shunt across the input gives a differential impedance of 99 Ω, which is an adequate match for most
applications.
For best CMRR performance, resistors must be matched. Assuming CMRR ≈ the resistor tolerance, a 0.1%
tolerance provides approximately 60-dB CMRR.
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8.1.8 Differential-to-Differential Amplifier
图 79 shows a differential amplifier that is used to amplify differential signals to a differential output. This circuit
has high input impedance and is used in differential line driver applications where the signal source is a high-
impedance driver (for example, a differential DAC) that must drive a line.
VIN-
VOUT-
GVSIG-
½
OPA837
VSIG-
VCM
VCM
RF
RF
RG
GVSIG+
VSIG+
VCM
VCM
VOUT+
½
OPA837
VIN+
图 79. Differential-to-Differential Amplifier
The output of the amplifier can be calculated according to 公式 11 if VIN± is set to VCM + VSIG±
.
æ
ö
÷
ø
2RF
RG
V
= V
´ 1 +
+ VCM
ç
IN±
OUT ±
è
(11)
The signal gain of the circuit is shown in 公式 12, and VCM passes with unity gain. The amplifier combines two
noninverting amplifiers into one differential amplifier that shares the RG resistor, which makes RG effectively half
its value when calculating the gain. The output signals are in-phase with the input signals.
2RF
G = 1 +
RG
(12)
36
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OPA837, OPA2837
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ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
8.1.9 Pulse Application With Single-Supply Circuit
For pulsed applications where the signal is at ground and pulses to a positive or negative voltage, the circuit
bias-voltage considerations differ from those in an application with a signal that swings symmetrically around a
reference point. 图 80 shows a circuit where the signal is at ground (0 V) and pulses to a positive value. The
waveforms are shown slightly above ground because the output stage requires approximately 100 mV headroom
to the supplies. To operate with the I/O swing truly to ground on a single-supply setup, consider using the fixed
–0.23-V output LM7705.
Signal and bias
from previous stage
VSIG
0 V
5 V
R1
RO
VOUT
OPA837
GVSIG
0 V
RG
Signal and bias to
next stage
R
F
图 80. Noninverting Single-Supply Circuit With Pulse
As shown in 图 81, an inverting amplifier is more appropriate if the input signal pulses negative from ground. A
key consideration in noninverting and inverting cases is that the input and output voltages are kept within the
limits of the amplifier. Because the VICR of the OPA837 includes the negative supply rail, the OPA837 op amp is
well-suited for this application.
5 V
R1
RO
VOUT
OPA837
GVSIG
RG
0 V
Signal and bias
from previous stage
Signal and bias to
0 V
RF
next stage
VSIG
图 81. Inverting Single-Supply Circuit With Pulse
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37
OPA837, OPA2837
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8.1.10 ADC Driver Performance
The OPAx837 provides excellent performance when driving high-performance delta-sigma (ΔΣ) or successive-
approximation-register (SAR) ADCs in low-power audio and industrial applications.
图 82 repeats the front page diagram. Many designs prefer to work with a true 0-V input range to 0-V output at
the ADC. The 100-mV output headroom requirement for the OPAx837 then requires a small negative supply to
hold the output linearity to ground. This supply is provided in this example using the low-cost LM7705 fixed
negative, –0.23-V output regulator. On a 5-V supply, the input headroom requires at least a 1.2-V headroom to
that supply. As shown in 图 82, this requirement limits the maximum input to 3.8 V. The SAR operates with a
precision 4.096-V reference provided by the REF5040, where the gain of 1.05 V/V takes the 3.8-V maximum
input to a 4.0-V maximum output. The RC values have been set to limit the overshoot at the OPAx837 output pin
to reduce clipping on fast (50 ns) transitions.
+ 5.0 V
4.096 V
REF5040
GND
4.0 V
3.3 V
+VCC
0 V
0 V
3.8 V
PD
OPA837
+
22 Ω
Gain = 1.05
V/V
œ
ADS8860
16-Bit SAR
1 MSPS
œVCC
2.2 nF
499 Ω
22 Ω
10.0 kΩ
GND
GND
GND
œ 0.23 V
LM7705
+ 3.3 V
图 82. OPA837 and ADS8860 Example Circuit
38
版权 © 2017–2018, Texas Instruments Incorporated
OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
8.2 Typical Applications
8.2.1 Active Filters
The OPAx837 is a good choice for active filters. 图 83 and 图 84 show MFB and Sallen-Key circuits designed
implementing second-order, low-pass Butterworth filter circuits. 图 85 illustrates the frequency response.
The main difference is that the MFB active filter provides an inverting amplifier in the pass band and the Sallen-
Key active filter is noninverting. The primary advantage for each active filter is that the Sallen-Key filter in unity
gain has no resistor gain error term or feedback resistor noise contribution. The MFB active filter has better
attenuation properties beyond the bandwidth of the op amp. The example circuits are assuming a split-supply
operation but single-supply operation is possible with midscale biasing.
1.4 kW
430 pF
1.4 kW
1.91 kW
OPA837
2.2 nF
图 83. MFB Active Filter, 100-kHz, Second-Order, Low-Pass Butterworth Filter Circuit
12 nF
255 W
147 W
OPA837
5.6 nF
图 84. Sallen-Key Active Filter, 100-kHz, Second-Order, Low-Pass Butterworth Filter Circuit
8.2.1.1 Design Requirements
For both designs, target the following filter shape characteristic:
•
•
•
Gain of 1 V/V
100-kHz Butterworth response
Q = 0.707 gives a flat Butterworth design
Scale the resistors down to reduce their noise contribution. In the MFB design, the input resistor is the in-band
load to the prior stage. Use values slightly below the gain of –1 V/V in 表 3. The Sallen-Key filter shows a high
impedance input in-band, so scale those resistors down further to improve noise.
The output DC error and drift can be improved by adding bias current cancellation resistors. For the MFB filter
that is a resistor (and a noise filter capacitor) on the noninverting input to ground equal to the resistor inside the
loop times the noise gain. For the Sallen-Key design, add a feedback resistor equal to the sum of the two input
resistors.
8.2.1.2 Detailed Design Procedure
The filter designs shown in this section used an improved design flow that reduces the resistor noise and noise
gain peaking. For the MFB filter, the design was based on the information in the Design Methodology for MFB
Filters in ADC Interface Applications application note.
For the Sallen-Key design, the solution is based on the information in the Component Pre-Distortion for Sallen
Key Filters application note.
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Typical Applications (接下页)
8.2.1.3 Application Curves
图 85 shows the comparative response curves for each of the filter design examples. Both filters hit the desired
response shape exactly. However, notice the loss of stop-band rejection in the Sallen-Key design. This loss
results from the op amp output impedance increasing at higher frequencies and allowing the signal to feed
through the feedback capacitor to the output.
图 86 shows a comparison of the output spot noise for the two designs. The Sallen-Key is much lower because
of the lower resistor values used. Also, the MFB shows a noise gain of 2 V/V versus the Sallen-Key gain of 1
V/V. This difference immediately increases the MFB output noise by at least twice the input voltage noise from
the op amp. The higher resistor values also increase the total output noise for the MFB.
3
-3
20
18
16
14
12
10
8
MFB
SKF
MFB
SKF
-9
-15
-21
-27
-33
-39
-45
-51
6
4
2
0
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
D083
D084
图 85. MFB and Sallen-Key Active Filters, Second-Order,
图 86. Output Spot Noise Comparison
Low-Pass Butterworth Filter Response
8.2.2 Implementing a 2:1 Active Multiplexer
The OPA837 includes a unique feature that enables a much improved wired-or mux operation. When disabled,
an internal switch opens from the inverting input to the active transistors isolating those nonlinear loads from the
signal being driven back into the inverting input through the active channel. 图 87 illustrates a simple example of
this multiplexer. In this figure, one of two signals are selected to be passed on to a shared output. The logic
control turns both amplifiers off (logic low) prior to turning one of them on. This control eliminates both outputs
being active at the same time. If both amplifiers must be on, as in the simple switch illustrated in 图 87, adding
100-Ω isolating resistors inside the loop at the outputs limits the current flow when both amplifiers are turned on.
This solution offers a very high input impedance to both inputs, very low buffered output drive, and nearly perfect
channel-to-channel isolation. The example of 图 87 also includes a –0.23-V supply generator to allow true swing
to ground on the output pins. This negative supply generator is optional if the outputs are more than 0.1 V above
ground or intended to be AC-coupled. Testing with a single channel active and an off channel attached to the
output showed no degradation in harmonic distortion; see 图 17 and 图 35. This approach can be expanded to
more than two channels or to operate with gain in the channels. Adding more than two select channels in parallel
should add 100-Ω feedback resistors to isolate the inverting input capacitance from the active output channel.
40
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OPA837, OPA2837
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ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
Typical Applications (接下页)
PD
R6 100 kꢀ
+VS
Å
+
This line is
actually
a logic
line
U1 OPA837
+
+
VIN
1
2X1 Active
Mux
VOUT
ÅVS
+VS
+
+
LM7705 œ 230 mV
VS1
5
PD
+VS
R7 100 kꢀ
Å
+
U2 OPA837
+
+
VIN
2
图 87. 2:1 Active Multiplexer
8.2.2.1 Design Requirements
To implement a 2:1 active mux, connect the outputs of two OPA837 devices together with separate input signals.
If termination is required for the input signals, add this termination as a resistor to ground on the noninverting
inputs. The inputs accept an input range from 0 V to 3.8 V by using a negative 0.23-V supply generator, such as
the LM7705.
8.2.2.2 Detailed Design Procedure
Aside from simply connecting the two outputs together as shown in 图 87, there are several other considerations
as well:
•
•
If the source impedance is not 0 Ω, consider adding a resistor in the feedback networks equal to that source
impedance to reduce the output DC error resulting from bias currents
If the logic control can place both channels on at the same time, place 100-Ω resistors inside the feedback
loop to limit supply currents when both outputs are active
•
•
If a matched gain is desired for the two inputs, configure the op amps for that gain instead of gain of 1 V/V
If the load is capacitive, add the required ROUT before the summing point on each op amp output
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Typical Applications (接下页)
8.2.3 1-Bit PGA Operation
Using the internal inverting input switch that operates along with the power disable function can also allow a
simple gain selection on a single input signal. 图 88 shows an example gain select of either 1 V/V or 2 V/V from
a single input to a single output. The logic disables both channels before turning one of them on to avoid high
currents in both outputs to be active at the same time. If this approach is not possible, as in the simple switch
shown in 图 88, insert 100-Ω resistors inside the loop of each op amp output. A bipolar supply is shown in 图 88,
but any of the single-supply options are also possible. Any combination of gains can be implemented, but wide
gain ranges show a larger change in signal bandwidth. This approach can be expanded to more than two gain
settings. Testing with the circuit of 图 88 showed no change in harmonic distortion; see 图 18 and 图 36.
R5 2 kꢀ
R4 2 kꢀ
Gain of 2 or
Gain of 1
ÅVS
1-Bit PGA
OPA837
+
VOUT
PD
R1 100 kꢀ
+VS
+
VIN
+VS
ÅVS
ÅVS
This line is
actually
a logic
line
+VS
ÅVS
+
+
+
+
PD
R2 100 kꢀ
VS1 2.5
VS1 Å2.5
OPA837
+VS
+VS
图 88. 1-Bit PGA
8.2.3.1 Design Requirements
Configure two OPA837 device outputs in different gains when driving the noninverting input with the same input
signal. Select one the two channels using the disable control. Set one channel to a gain of 1 V/V and the second
channel to a gain of 2 V/V using the recommended 2-kΩ values from 表 2.
8.2.3.2 Detailed Design Procedure
The simple design of 图 88 has several options and details to consider, which include:
•
For split-supply operation, the disable control line must operate to within 0.55 V of the negative supply to
disable a channel. A logic level shift is required.
•
Any combination of gains can be implemented. However, the signal bandwidths may vary widely through the
gain bandwidth product effect between the two channels if the gains are widely separated. If a more constant
bandwidth between gains is desired, consider adding a fixed RC filter after the combined outputs at a lower
cutoff frequency than the slowest gain setting.
The TIDA-01565 Wired OR MUX and PGA Reference Design demonstrates the use of the OPAx837 in wired-OR
multiplexer and programmable gain amplifier applications.
42
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www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
9 Power Supply Recommendations
The OPAx837 is intended to work in a nominal supply range of 3.0 V to 5 V. Supply-voltage tolerances are
supported with the specified operating range of 2.7 V (–10% on a 3-V supply) and 5.4 V (+8% on a 5-V supply).
Good power-supply bypassing is required. Minimize the distance (< 0.1 inch) from the power-supply pins to high-
frequency, 0.1-µF decoupling capacitors. A larger capacitor (2.2 µF is typical) is used along with a high-
frequency, 0.1-µF supply-decoupling capacitor at the device supply pins. For single-supply operation, only the
positive supply has these capacitors. When a split supply is used, use these capacitors for each supply to
ground. If necessary, place the larger capacitors further from the device and share these capacitors among
several devices in the same area of the printed circuit board (PCB). Avoid narrow power and ground traces to
minimize inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor
across the two power supplies (for bipolar operation) reduces second harmonic distortion.
The OPA837 has a positive supply current temperature coefficient; see 图 57. This coefficient helps improve the
input offset voltage drift. Supply current requirements in the system design must account for this effect using the
maximum intended ambient and 图 57 to size the supply required. The very low power dissipation for the
OPA837 typically does not require any special thermal design considerations. For the extreme case of 125°C
operating ambient, use the approximate maximum 200°C/W for the two packages, and a maximum internal
power of 5.4-V supply × 0.8-mA 125°C supply current from 图 57 gives a maximum internal power of 4.3 mW.
This power only gives a 0.86°C rise from ambient to junction temperature, which is well below the maximum
150°C junction temperature. Load power adds to this value, but also increases the junction temperature only
slightly over ambient temperature.
10 Layout
10.1 Layout Guidelines
The OPA837EVM can be used as a reference when designing the circuit board. TI recommends following the
EVM layout of the external components near to the amplifier, ground plane construction, and power routing as
closely as possible. General guidelines are listed below:
1. Signal routing must be direct and as short as possible into and out of the op amp.
2. The feedback path must be short and direct avoiding vias if possible, especially with G = 1 V/V.
3. Ground or power planes must be removed from directly under the negative input and output pins of the
amplifier.
4. TI recommends placing a series output resistor as close to the output pin as possible. See 图 49 for
recommended values for the expected capacitive load. These values are derived targeting a 30° phase
margin to the output of the op amp.
5. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be
shared with other op amps. For split supply, a capacitor is required for both supplies.
6. A 0.1-µF power-supply decoupling capacitor must be placed as close to the supply pins as possible,
preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
7. The PD pin uses low logic swing levels. If the pin is not used, PD must be tied to the positive supply to
enable the amplifier. If the pin is used, PD must be actively driven. A bypass capacitor is not necessary, but
can be used for robustness in noisy environments.
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OPA837, OPA2837
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
10.2 Layout Example
Ground and power plane exist on
inner layers
Ground and power plane removed
from inner layers
Place output resistors close
to output pins to minimize
parasitic capacitance
1
2
3
6
5
4
Place bypass capacitors
close to power pins
Place bypass capacitors
close to power pins
Power control (disable) pin
Must be driven
Place input resistor close to pin 4
to minimize stray capacitance
Non-inverting input
terminated in 50 Ω
Place feedback resistor on the bottom
of PCB between pins 4 and 6
Remove GND and Power plane
under pins 1 and 4 to minimize
stray PCB capacitance
图 89. EVM Layout Example
44
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OPA837, OPA2837
www.ti.com.cn
ZHCSGP3D –SEPTEMBER 2017–REVISED DECEMBER 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《ADS8860 16 位、1 MSPS、串行接口、微功耗、微型、单端输入、SAR 模数转换器》数据表
德州仪器 (TI)，《LM7705 低噪声负偏置发生器》数据表
德州仪器 (TI)，《OPA838 1mA、300MHz 增益带宽、电压反馈运算放大器》数据表
德州仪器 (TI)，《REF50xx 低噪声、极低漂移、精密电压基准》数据表
德州仪器 (TI)，《OPA837DBV、OPA836DBV EVM》用户指南
德州仪器 (TI)，《单电源运算放大器设计技术》应用报告
德州仪器 (TI)，《高速运算放大器噪声分析》应用报告
德州仪器 (TI)，《ADC 接口应用中 MFB 滤波器的 设计方法》应用手册
德州仪器 (TI)，《Sallen Key 滤波器组件预失真》应用手册
德州仪器 (TI)，《TIDA-01565 有线 OR 多路复用器以及 PGA 参考设计》设计指南
德州仪器 (TI)，TINA 模型与仿真工具
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
OPA837
OPA2837
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
46
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2837IDGKR
OPA2837IDGKT
OPA2837IRUNR
OPA2837IRUNT
OPA837IDBVR
OPA837IDBVR2
OPA837IDBVT
OPA837IDCKR
OPA837IDCKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
QFN
DGK
DGK
RUN
RUN
DBV
DBV
DBV
DCK
DCK
8
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2837
2837
2837
2837
19FF
19FF
19FF
16K
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAUAG
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
10
10
6
QFN
SOT-23
SOT-23
SOT-23
SC70
3000 RoHS & Green
3000 RoHS & Green
6
6
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
5
SC70
5
16K
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2837IDGKR
OPA2837IDGKT
OPA2837IRUNR
OPA2837IRUNT
OPA837IDBVR
OPA837IDBVR2
OPA837IDBVT
OPA837IDCKR
OPA837IDCKT
VSSOP
VSSOP
QFN
DGK
DGK
RUN
RUN
DBV
DBV
DBV
DCK
DCK
8
8
2500
250
330.0
330.0
180.0
180.0
178.0
178.0
178.0
178.0
178.0
12.4
12.4
8.4
8.4
9.0
9.0
9.0
9.0
9.0
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q2
Q2
Q3
Q2
Q3
Q3
Q3
10
10
6
3000
250
2.3
2.3
1.15
1.15
1.37
1.37
1.37
1.2
QFN
2.3
2.3
SOT-23
SOT-23
SOT-23
SC70
3000
3000
250
3.23
3.23
3.23
2.4
3.17
3.17
3.17
2.5
6
6
5
3000
250
SC70
5
2.4
2.5
1.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2837IDGKR
OPA2837IDGKT
OPA2837IRUNR
OPA2837IRUNT
OPA837IDBVR
OPA837IDBVR2
OPA837IDBVT
OPA837IDCKR
OPA837IDCKT
VSSOP
VSSOP
QFN
DGK
DGK
RUN
RUN
DBV
DBV
DBV
DCK
DCK
8
8
2500
250
366.0
366.0
210.0
210.0
180.0
180.0
180.0
180.0
180.0
364.0
364.0
185.0
185.0
180.0
180.0
180.0
180.0
180.0
50.0
50.0
35.0
35.0
18.0
18.0
18.0
18.0
18.0
10
10
6
3000
250
QFN
SOT-23
SOT-23
SOT-23
SC70
3000
3000
250
6
6
5
3000
250
SC70
5
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RUN 10
2 X 2, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228249/A
www.ti.com
PACKAGE OUTLINE
RUN0010A
WQFN - 0.8 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
SYMM
5
(0.2) TYP
4
6
SYMM
2X 1.5
6X 0.5
9
1
0.3
0.2
10X
10
PIN 1 ID
0.1
C A B
0.6
10X
0.05
0.4
4220470/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
SEE SOLDER MASK
DETAIL
10X (0.7)
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220470/A 05/2020
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
10X (0.7)
10
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
4220470/A 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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