OPA320SAIDBVR [TI]
高精度、零交叉 20MHz、0.9pA Ib、RRIO、CMOS 运算放大器 | DBV | 6 | -40 to 125;
| 型号： | OPA320SAIDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高精度、零交叉 20MHz、0.9pA Ib、RRIO、CMOS 运算放大器 | DBV | 6 | -40 to 125 放大器 运算放大器 放大器电路 |
| 文件： | 总31页 (文件大小：1217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA320, OPA2320
OPA320S, OPA2320S
www.ti.com
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
Precision, 20MHz, 0.9pA, Low-Noise, RRIO,
CMOS Operational Amplifier with Shutdown
Check for Samples: OPA320, OPA2320, OPA320S, OPA2320S
1
FEATURES
DESCRIPTION
The OPA320 (single) and OPA2320 (dual) are a new
generation of precision, low-voltage CMOS
operational amplifiers optimized for very low noise
and wide bandwidth while operating on a low
quiescent current of only 1.45mA.
23
•
Precision with Zero-Crossover Distortion:
–
–
–
Low Offset Voltage: 150μV (max)
High CMRR: 114dB
Rail-to-Rail I/O
•
Low Input Bias Current: 0.9pA (max)
Low Noise: 7nV/√Hz at 10kHz
Wide Bandwidth: 20MHz
The OPA320 series is ideal for low-power,
single-supply applications. Low-noise (7nV/√Hz) and
high-speed operation also make them well-suited for
driving sampling analog-to-digital converters (ADCs).
Other applications include signal conditioning and
sensor amplification.
•
•
•
•
•
•
Slew Rate: 10V/μs
Quiescent Current: 1.45mA/ch
Single-Supply Voltage Range: 1.8V to 5.5V
OPA320S, OPA2320S:
The OPA320 features a linear input stage with
zero-crossover distortion that delivers excellent
common-mode rejection ratio (CMRR) of typically
114dB over the full input range. The input
common-mode range extends 100mV beyond the
negative and positive supply rails. The output voltage
typically swings within 10mV of the rails.
–
IQ in Shutdown Mode: 0.1μA
•
•
Unity-Gain Stable
Small Packages:
–
SOT23, MSOP, DFN
In addition, the OPAx320 have a wide supply voltage
range from 1.8V to 5.5V with excellent PSRR (106dB)
over the entire supply range, making them suitable
for precision, low-power applications that run directly
from batteries without regulation.
APPLICATIONS
•
•
•
•
•
•
•
•
High-Z Sensor Signal Conditioning
Transimpedance Amplifiers
Test and Measurement Equipment
Programmable Logic Controllers (PLCs)
Motor Control Loops
The OPA320 (single version) is available in a
SOT23-5 package; the OPA320S shut-down single
version is available in an SOT23-6 package. The dual
OPA2320 is offered in SO-8, MSOP-8, and DFN-8
packages, and the OPA2320S (dual with shut-down)
in an MSOP-10 package.
Communications
Input/Output ADC/DAC Buffers
Active Filters
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
OPA320, OPA2320
OPA320S, OPA2320S
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE
DESIGNATOR
PACKAGE MARKING,
QUANTITY
PRODUCT
OPA320
OPA320S(2)
PACKAGE-LEAD
SOT23-5
SOT23-6
MSOP-8
DBV
DBV
DGK
DRG
D
RAC
RAE
OCLQ
OCMQ
O2320A
TBD
OPA2320
DFN-8
SO-8
OPA2320S(2)
MSOP-10
DGS
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or visit
the device product folder at www.ti.com.
(2) Product preview device.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
OPA320, OPA320S, OPA2320, OPA2320S
UNIT
V
Supply voltage, VS = (V+) – (V–)
6
(V–) – 0.5 to (V+) + 0.5
±10
Voltage(2)
Current(2)
V
Signal input pins
mA
mA
°C
°C
°C
V
Output short-circuit current(3)
Operating temperature, TA
Storage temperature, TSTG
Junction temperature, TJ
Continuous
–40 to +150
–65 to +150
+150
Human body model (HBM)
4000
ESD ratings
Charged device model (CDM)
Machine model (MM)
1000
V
200
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10mA or less.
(3) Short-circuit to ground, one amplifier per package.
2
Copyright © 2010–2011, Texas Instruments Incorporated
OPA320, OPA2320
OPA320S, OPA2320S
www.ti.com
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
ELECTRICAL CHARACTERISTICS: VS = +1.8V to +5.5V or ±0.9V to ±2.75V
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN x = VS+, unless otherwise noted.
OPA320, OPA320S, OPA2320, OPA2320S
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input offset voltage
vs Temperature
VOS
dVOS/dT
PSR
40
1.5
5
150
5
μV
μV/°C
μV/V
μV/V
dB
VS = +5.5V
VS = +1.8V to +5.5V
VS = +1.8V to +5.5V
At 1kHz
vs Power supply
20
Over temperature
15
130
Channel separation
INPUT VOLTAGE
Common-mode voltage range
Common-mode rejection ratio
Over temperature
VCM
(V–) – 0.1
100
(V+) + 0.1
V
CMRR
VS = 5.5V, (V–) – 0.1V < VCM < (V+) + 0.1V
114
dB
dB
96
INPUT BIAS CURRENT
Input bias current
IB
±0.2
±0.9
±50
pA
pA
pA
pA
pA
pA
pA
TA = –40°C to +85°C
Over temperature
OPA2320, OPA2320S, TA = –40°C to +125°C
OPA320, OPA320S, TA = –40°C to +125°C
±400
±600
±0.9
±50
Input offset current
IOS
±0.2
TA = –40°C to +85°C
TA = –40°C to +125°C
Over temperature
±400
NOISE
Input voltage noise
f = 0.1Hz to 10Hz
f = 1kHz
2.8
8.5
7
μVPP
nV/√Hz
nV/√Hz
fA/√Hz
Input voltage noise density
en
in
f = 10kHz
Input current noise density
INPUT CAPACITANCE
Differential
f = 1kHz
0.6
5
4
pF
pF
Common-mode
OPEN-LOOP GAIN
0.1V < VO < (V+) – 0.1V, RL = 10kΩ
0.1V < VO < (V+) – 0.1V, RL = 10kΩ
0.2V < VO < (V+) – 0.2V, RL = 2kΩ
0.2V < VO < (V+) – 0.2V, RL = 2kΩ
VS = 5V, CL = 50pF
114
100
108
96
132
130
123
130
47
dB
dB
Open-loop voltage gain
AOL
PM
dB
dB
Phase margin
Degrees
FREQUENCY RESPONSE
Gain bandwidth product
Slew rate
VS = 5.0V, CL = 50pF
GBP
SR
Unity gain
20
10
MHz
V/μs
μs
G = +1
To 0.1%, 2V step, G = +1
To 0.01%, 2V step, G = +1
To 0.0015%, 2V step, G = +1(1)
0.25
0.32
0.5
Settling time
tS
μs
μs
Overload recovery time
VIN × G > VS
100
ns
VO = 4VPP, G = +1, f = 10kHz, RL = 10kΩ
VO = 2VPP, G = +1, f = 10kHz, RL = 600Ω
0.0005
0.0011
%
Total harmonic distortion +
noise(2)
THD+N
%
(1) Based on simulation.
(2) Third-order filter; bandwidth = 80kHz at –3dB.
Copyright © 2010–2011, Texas Instruments Incorporated
3
OPA320, OPA2320
OPA320S, OPA2320S
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +1.8V to +5.5V or ±0.9V to ±2.75V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN x = VS+, unless otherwise noted.
OPA320, OPA320S, OPA2320, OPA2320S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
RL = 10kΩ
RL = 2kΩ
RL = 10kΩ
RL = 2kΩ
VS = 5.5V
10
25
20
35
30
45
mV
mV
mV
mV
mA
Voltage output swing from
both rails
VO
Over temperature
Short-circuit current
Capacitive load drive
Open-loop output resistance
SHUTDOWN(3)
ISC
CL
RO
±65
See Typical Characteristics
90
IO = 0mA, f = 1MHz
Ω
All amplifiers disabled, SHDN = V–
0.1
1.6
1.6
0.5
μA
mA
mA
V
Quiescent current per amplifier
IQSD OPA2320S only, SHDN A = VS–, SHDN B = VS+
OPA2320S only, SHDN A = VS+, SHDN B = VS–
High-level input voltage
Low-level input voltage
VIH
VIL
Amplifier enabled
0.7 × VS+
5.5
Amplifier disabled
0.3 × VS+
V
G = 1, VOUT = 0.1 × VS/2, full shutdown(5)
OPA2320S only, partial shutdown(5)
G = 1, VOUT = 0.1 × VS/2
VIH = 5V
20
6
μs
Amplifier enable time(4)
tON
Amplifier disable time(4)
tOFF
3
μs
μA
μA
0.13
0.04
SHDN pin input bias current (per pin)
VIL = 0V
POWER SUPPLY
Specified voltage range
Quiescent current per amplifier
OPA320, OPA320S
Over temperature
OPA2320, OPA2320S
Over temperature
Power-on time
VS
IQ
1.8
5.5
V
IO = 0mA, VS = +5.5V
IO = 0mA, VS = +5.5V
1.5
1.45
28
1.75
1.85
1.6
mA
mA
mA
mA
μs
IO = 0mA, VS = +5.5V
IO = 0mA, VS = +5.5V
1.7
V+ = 0V to 5V, to 90% IQ level
TEMPERATURE
Specified range
–40
–40
+125
+150
°C
°C
Operating range
(3) Specified by design and characterization; not production tested.
(4) Disable time (tOFF) and enable time (tON) are defined as the time between the 50% point of the signal applied to the SHDN pin and the
point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(5) Full shutdown refers to the dual OPA2320S having both A and B channels disabled (SHDN A = SHDN B = VS–). For partial shutdown,
only one SHDN pin is exercised; in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
4
Copyright © 2010–2011, Texas Instruments Incorporated
OPA320, OPA2320
OPA320S, OPA2320S
www.ti.com
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
THERMAL INFORMATION: OPA320, OPA320S
OPA320
DBV (SOT23)
5 PINS
219.3
OPA320S
DBV (SOT23)
6 PINS
177.5
THERMAL METRIC(1)
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
θJC(top)
θJB
107.5
108.9
57.5
27.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
7.4
13.3
ψJB
56.9
26.9
θJC(bottom)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA2320, OPA2320S
OPA2320
DGK (MSOP)
8 PINS
174.8
OPA2320S
DGS (MSOP)
10 PINS
171.5
THERMAL METRIC(1)
D (SO)
8 PINS
122.6
67.1
DRG (DFN)
8 PINS
50.6
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
θJC(top)
θJB
43.9
54.9
43.0
64.0
95.0
25.2
91.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
13.2
2.0
0.6
1.9
ψJB
63.4
93.5
25.3
89.9
θJC(bottom)
N/A
N/A
5.7
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2010–2011, Texas Instruments Incorporated
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OPA320, OPA2320
OPA320S, OPA2320S
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
www.ti.com
PIN CONFIGURATIONS
DBV PACKAGE
SOT23-5
(TOP VIEW)
DRG PACKAGE
DFN-8
(TOP VIEW)
V+
OUT
V-
1
2
3
5
4
8
V+
OUT A
-IN A
+IN A
V-
1
2
3
4
Exposed
Thermal
Die Pad
on
7
6
5
OUT B
-IN B
+IN B
-IN
+IN
Underside(2)
DBV PACKAGE
SOT23-6
(TOP VIEW)
D, DGK PACKAGES
SO-8, MSOP-8
(TOP VIEW)
VOUT
V-
1
6
5
4
V+
2
3
SHDN
OUT A
1
8
7
6
5
V+
+IN
-IN
-IN A
+IN A
V-
2
3
4
OUT B
-IN B
DGS PACKAGE
MSOP-10
+IN B
(TOP VIEW)
V+
VOUT A
1
2
3
4
5
10
9
VOUT B
-IN B
+IN B
-IN A
+IN A
A
8
B
V-
7
SHDN B
SHDN A
6
(1) No internal connection.
(2) Connect thermal pad to V–.
6
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): OPA320 OPA2320 OPA320S OPA2320S
OPA320, OPA2320
OPA320S, OPA2320S
www.ti.com
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
TYPICAL CHARACTERISTICS
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT DISTRIBUTION
14
12
10
8
25
20
15
10
5
6
4
2
0
0
0.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
Offset Drift (mV/°C)
Offset Voltage (mV)
Figure 1.
Figure 2.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
OPEN-LOOP GAIN/PHASE vs FREQUENCY
100
160
140
120
100
80
0
VS = ±2.5V
80
-20
CL = 50pF
60
-40
40
-60
Phase
20
-80
0
60
-100
-120
-140
-160
-180
-20
-40
-60
-80
-100
40
Gain
20
Representative Units
VS = ±2.75V
0
-20
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
1
10
100
1k
10k 100k
1M
10M 100M
Common-Mode Voltage (V)
Frequency (Hz)
Figure 3.
Figure 4.
OPEN-LOOP GAIN vs TEMPERATURE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
140
135
130
125
120
115
110
105
100
1.5
1.45
1.4
+125°C
10kW Load
+85°C
2kW Load
+25°C
1.35
1.3
-40°C
1.25
-50
-25
0
25
50
75
100
125
150
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (°C)
Supply Voltage (V)
Figure 5.
Figure 6.
Copyright © 2010–2011, Texas Instruments Incorporated
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OPA320, OPA2320
OPA320S, OPA2320S
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
INPUT BIAS CURRENT vs SUPPLY VOLTAGE
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
1
0.8
6
5
4
0.6
3
0.4
2
0.2
1
0
0
-1
-2
-3
-4
-5
-6
-0.2
-0.4
-0.6
-0.8
-1
IB+
IB-
IOS
IB-
IB+
0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
Supply Voltage (±V)
Common-Mode Voltage (V)
Figure 7.
Figure 8.
INPUT BIAS CURRENT DISTRIBUTION
INPUT BIAS CURRENT vs TEMPERATURE
40
35
30
25
20
15
10
5
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
IOS
IB+
IB-
IB
IOS
-100
0
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Input Bias Current (pA)
Figure 9.
Figure 10.
CMRR AND PSRR vs FREQUENCY
CMRR AND PSRR vs TEMPERATURE
140
130
125
120
115
110
105
100
95
VS = 1.8V to 5.5V
120
100
80
60
40
20
0
CMRR
PSRR
PSRR
CMRR
90
100
1k
10k
100k
1M
10M
-50
-25
0
25
50
75
100
125
150
Frequency (Hz)
Temperature (°C)
Figure 11.
Figure 12.
8
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OPA320, OPA2320
OPA320S, OPA2320S
www.ti.com
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
0.1Hz TO 10Hz INPUT VOLTAGE NOISE
1000
100
10
6
5
VS = 1.8V to 5.5V
4
3
2
1
0
-1
-2
-3
-4
1
10
100
1k
10k
100k
1M
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Time (1s/div)
Figure 13.
Figure 14.
CLOSED-LOOP GAIN vs FREQUENCY
CLOSED-LOOP GAIN vs FREQUENCY
60
40
20
0
60
40
20
0
VS = +1.8V
VS = +5.5V
RL = 10kW
RL = 10kW
G = +100V/V
G = +100V/V
CL = 50pF
CL = 50pF
G = +10V/V
G = +1V/V
G = +10V/V
G = +1V/V
-20
-20
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 15.
Figure 16.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(MSOP-8)
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
6
5
4
3
2
1
0
3
5.5VS
2
1
3.3VS
-40°C
+25°C
+125°C
0
-1
-2
-3
1.8VS
RL = 10kW
CL = 50pF
VS = ±2.75 V
60
70 80
10k
100k
1M
10M
0
10
20
30
40
50
Frequency (Hz)
Output Current (mA)
Figure 17.
Figure 18.
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OPA320S, OPA2320S
SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
1000
70
G = 1, VS = 1.8V
VS = ±±2.7V
60
50
40
30
20
10
0
G = 1, VS = 5.5V
G = 10, VS = 1.8V
G = 10, VS = 5.5V
100
10
1
10
100
1k
10k 100k
1M
10M 100M
0
500
1000
1500
2000
2500
3000
Frequency (Hz)
Capacitive Load (pF)
Figure 19.
Figure 20.
THD+N vs AMPLITUDE
THD+N vs FREQUENCY
0.1
0.1
Frequency = 10kHz
VIN = 2VPP
VS = ±2.5V
G = +1V/V
0.01
0.001
0.01
0.001
Load = 600W
Load = 600W
Frequency = 10kHz
VS = ±2.5V
Load = 10kW
Load = 10kW
G = +1V/V
0.0001
0.0001
10
100
1k
10k
100k
0.01
0.1
1
10
Frequency (Hz)
VIN (VPP
)
Figure 21.
THD+N vs FREQUENCY
Figure 22.
CHANNEL SEPARATION vs FREQUENCY (for Dual)
0.1
0.01
0
Frequency = 10kHz
VS = ±2.75V
VIN = 4VPP
VS = ±2.5V
G = +1V/V
-20
-40
-60
Load = 600W
-80
0.001
0.0001
-100
-120
-140
Load = 10kW
10
100
1k
10k
100k
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 23.
Figure 24.
10
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SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
SLEW RATE vs SUPPLY VOLTAGE
SMALL-SIGNAL STEP RESPONSE
12
11.5
11
0.1
0.075
0.05
Gain = +1
VS = ±2.75V
CL = 50pF
VIN = 100mVPP
0.025
0
Rise
10.5
10
Fall
-0.025
-0.05
-0.075
-0.1
9.5
9
VOUT
VIN
1.6
2
2.4 2.8 3.2 3.6
4
4.4 4.8 5.2 5.6
-0.8
-0.4
0
0.4
0.8
1.2
1.6
Supply Voltage (V)
Time (ms)
Figure 25.
Figure 26.
SMALL-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE vs TIME
0.1
1.5
1
Gain = +1
VS = ±2.75V
0.075
0.05
VIN = 2VPP
VIN
0.5
0
Gain = -1
0.025
0
VOUT
VS = ±2.75V
VIN = 100mVPP
-0.025
-0.05
-0.075
-0.1
-0.5
-1
VOUT
VIN
-1.5
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
-0.4
0
0.4
0.8
1.2
1.6
Time (ms)
Time (ms)
Figure 27.
Figure 28.
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APPLICATION INFORMATION
RAIL-TO-RAIL INPUT
OPERATING VOLTAGE
The OPA320 product family features true rail-to-rail
input operation, with supply voltages as low as ±0.9V
(1.8V). The design of the OPA320 amplifiers include
an internal charge-pump that powers the amplifier
input stage with an internal supply rail at
approximately 1.6V above the external supply (VS+).
This internal supply rail allows the single differential
input pair to operate and remain very linear over a
very wide input common-mode range. A unique
zero-crossover input topology eliminates the input
offset transition region typical of many rail-to-rail,
complementary input stage operational amplifiers.
This topology allows the OPA320 to provide superior
The OPA320 series op amps are unity-gain stable
and can operate on a single-supply voltage (1.8V to
5.5V), or a split supply voltage (±0.9V to ±2.75V),
making them highly versatile and easy to use. The
power-supply pins should have local bypass ceramic
capacitors (typically 0.001μF to 0.1μF). The OPA320
amplifiers are fully specified from +1.8V to +5.5V and
over the extended temperature range of –40°C to
+125°C. Parameters that can exhibit variance with
regard to operating voltage or temperature are
presented in the Typical Characteristics.
common-mode performance (CMRR
>
110dB,
INPUT AND ESD PROTECTION
typical) over the entire common-mode input range,
which extends 100mV beyond both power-supply
rails. When driving analog-to-digital converters
(ADCs), the highly linear VCM range of the OPA320
assures maximum linearity and lowest distortion.
The OPA320 incorporates internal electrostatic
discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily
consists of current-steering diodes connected
between the input and power-supply pins. These ESD
protection diodes also provide in-circuit input
overdrive protection, provided that the current is
limited to 10mA as stated in the Absolute Maximum
Ratings. Many input signals are inherently
current-limited to less than 10mA; therefore, a limiting
resistor is not required. Figure 29 shows how a series
input resistor (RS) may be added to the driven input
to limit the input current. The added resistor
contributes thermal noise at the amplifier input and
the value should be kept to the minimum in
noise-sensitive applications.
PHASE REVERSAL
The OPA320 op amps are designed to be immune to
phase reversal when the input pins exceed the supply
voltages, therefore providing further in-system
stability and predictability. Figure 30 shows the input
voltage exceeding the supply voltage without any
phase reversal.
4
VIN
VS = ±2.5V
3
2
VOUT
V+
1
IOVERLOAD
0
-1
-2
-3
-4
10mA, Max
VOUT
OPA320
VIN
RS
Figure 29. Input Current Protection
-500
-250
0
250
500
750
1000
Time (ms)
Figure 30. No Phase Reversal
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FEEDBACK CAPACITOR IMPROVES
RESPONSE
result of signal rectification associated with the
internal semiconductor junctions. While all operational
amplifier pin functions can be affected by EMI, the
input pins are likely to be the most susceptible. The
OPA320 operational amplifier family incorporates an
internal input low-pass filter that reduces the
amplifiers response to EMI. Both common-mode and
differential mode filtering are provided by the input
filter. The filter is designed for a cut-off frequency of
approximately 580MHz (–3dB), with a roll-off of 20dB
per decade.
For optimum settling time and stability with
high-impedance feedback networks, it may be
necessary to add a feedback capacitor across the
feedback resistor, RF, as shown in Figure 31. This
capacitor compensates for the zero created by the
feedback network impedance and the OPA320 input
capacitance (and any parasitic layout capacitance).
The effect becomes more significant with higher
impedance networks.
CF
OUTPUT IMPEDANCE
The open-loop output impedance of the OPA320
common-source output stage is approximately 90Ω.
When the op amp is connected with feedback, this
value is reduced significantly by the loop gain. For
example, with 130dB (typ) of open-loop gain, the
output impedance is reduced in unity-gain to less
than 0.03Ω. For each decade rise in the closed-loop
gain, the loop gain is reduced by the same amount,
which results in a ten-fold increase in effective output
impedance. While the OPA320 output impedance
remains very flat over a wide frequency range, at
higher frequencies the output impedance rises as the
open-loop gain of the op amp drops. However, at
these frequencies the output also becomes capacitive
as a result of parasitic capacitance. This in turn
prevents the output impedance from becoming too
high, which can cause stability problems when driving
large capacitive loads. As mentioned previously, the
OPA320 has excellent capacitive load drive capability
for an op amp with its bandwidth.
RIN
RF
V+
VIN
CIN
R
IN ´ CIN = RF ´ CF
VOUT
OPA320
CL
CIN
NOTE: Where CIN is equal to the OPA320 input capacitance
(approximately 9pF) plus any parasitic layout capacitance.
Figure 31. Feedback Capacitor Improves
Dynamic Performance
It is suggested that a variable capacitor be used for
the feedback capacitor because input capacitance
may vary between op amps and layout capacitance is
difficult to determine. For the circuit shown in
Figure 31, the value of the variable feedback
capacitor should be chosen so that the input
resistance times the input capacitance of the OPA320
(typically 9pF) plus the estimated parasitic layout
capacitance equals the feedback capacitor times the
feedback resistor:
CAPACITIVE LOAD AND STABILITY
The OPA320 is designed to be used in applications
where driving a capacitive load is required. As with all
op amps, there may be specific instances where the
OPA320 can become unstable. The particular op amp
circuit configuration, layout, gain, and output loading
are some of the factors to consider when establishing
whether an amplifier is stable in operation. An op
amp in the unity-gain (+1V/V) buffer configuration and
driving a capacitive load exhibits a greater tendency
to become unstable than an amplifier operated at a
higher noise gain. The capacitive load, in conjunction
with the op amp output resistance, creates a pole
within the feedback loop that degrades the phase
margin. The degradation of the phase margin
increases as the capacitive loading increases. When
operating in the unity-gain configuration, the OPA320
remains stable with a pure capacitive load up to
approximately 1nF.
R
IN × CIN = RF × CF
Where:
CIN is equal to the OPA320 input capacitance
(sum of differential and common-mode) plus the
layout capacitance.
The capacitor value can be adjusted until
optimum performance is obtained.
EMI SUSCEPTIBILITY AND INPUT FILTERING
Operational amplifiers vary in susceptibility to
electromagnetic interference (EMI). If conducted EMI
enters the operational amplifier, the dc offset
observed at the amplifier output may shift from the
nominal value while EMI is present. This shift is a
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The equivalent series resistance (ESR) of some very
large capacitors (CL > 1µF) is sufficient to alter the
phase characteristics in the feedback loop such that
the amplifier remains stable. Increasing the amplifier
closed-loop gain allows the amplifier to drive
increasingly larger capacitance. This increased
capability is evident when observing the overshoot
response of the amplifier at higher voltage gains, as
shown in Figure 33. One technique for increasing the
capacitive load drive capability of the amplifier
operating in unity gain is to insert a small resistor
(RS), typically 10Ω to 20Ω, in series with the output,
as shown in Figure 32.
OVERLOAD RECOVERY TIME
Overload recovery time is the time it takes the output
of the amplifier to come out of saturation and recover
to the linear region. Overload recovery is particularly
important in applications where small signals must be
amplified in the presence of large transients.
Figure 34 and Figure 35 show the positive and
negative overload recovery times of the OPA320,
respectively. In both cases, the time elapsed before
the OPA320 comes out of saturation is less than
100ns. In addition, the symmetry between the positive
and negative recovery times allows excellent signal
rectification without distortion of the output signal.
This resistor significantly reduces the overshoot and
ringing associated with large capacitive loads. A
possible problem with this technique is that a voltage
divider is created with the added series resistor and
any resistor connected in parallel with the capacitive
load. The voltage divider introduces a gain error at
the output that reduces the output swing. The error
contributed by the voltage divider may be
insignificant. For instance, with a load resistance, RL
= 10kΩ and RS = 20Ω, the gain error is only about
0.2%. However, when RL is decreased to 600Ω,
which the OPA320 is able to drive, the error
increases to 7.5%.
3
VS = ±2.75V
2.5
G = -10
Output
2
1.5
1
0.5
0
Input
-0.5
-1
9.75
10
10.25
10.5
10.75
11
Time (250ns/div)
V+
Figure 34. Positive Recovery Time
RS
VOUT
OPA320
VIN
10W to
20W
1
0.5
0
RL
CL
Input
-0.5
-1
Figure 32. Improving Capacitive Load Drive
-1.5
-2
70
G = 1, VS = 1.8V
60
50
40
30
20
10
0
G = 1, VS = 5.5V
G = 10, VS = 1.8V
G = 10, VS = 5.5V
Output
VS = ±2.75V
G = -10
-2.5
-3
9.75
10
10.25
10.5
10.75
11
Time (250ns/div)
Figure 35. Negative Recovery Time
0
500
1000
1500
2000
2500
3000
Capacitive Load (pF)
Figure 33. Small-Signal Overshoot versus
Capacitive Load (100mVPPoutput step)
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SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
GENERAL LAYOUT GUIDELINES
The key elements to a transimpedance design, as
shown in Figure 36, are the expected diode
capacitance (CD), which should include the parasitic
input common-mode and differential-mode input
capacitance (4pF + 5pF for the OPA320); the desired
transimpedance gain (RF); and the gain-bandwidth
(GBW) for the OPA320 (20MHz). With these three
variables set, the feedback capacitor value (CF) can
be set to control the frequency response. CF includes
the stray capacitance of RF, which is 0.2pF for a
typical surface-mount resistor.
The OPA320 is a wideband amplifier. To realize the
full operational performance of the device, good
high-frequency printed circuit board (PCB) layout
practices are required. The bypass capacitors must
be connected between each supply pin and ground
as close to the device as possible. The bypass
capacitor traces should be designed for minimum
inductance.
LEADLESS DFN PACKAGE
(1)
CF
The OPA320 series uses the DFN style package
(also known as SON), which is a QFN with contacts
on only two sides of the package bottom. This
leadless package maximizes PCB space and offers
enhanced thermal and electrical characteristics
through an exposed pad. One of the primary
advantages of the DFN package is its low height
(0.8mm).
< 1pF
RF
10MW
V+
l
DFN packages are physically small, have a smaller
routing area, improved thermal performance, reduced
electrical parasitics, and a pinout scheme that is
consistent with other commonly-used packages (such
as SO and MSOP). Additionally, the absence of
external leads eliminates bent-lead issues.
VOUT
CD
OPA320
V-
(1) CF is optional to prevent gain peaking. It includes the stray
capacitance of RF.
The DFN package can easily be mounted using
standard PCB assembly techniques. See Application
Report, QFN/SON PCB Attachment (SLUA271) and
Application Report, Quad Flatpack No-Lead Logic
Packages (SCBA017), both available for download at
www.ti.com. The exposed leadframe die pad on the
bottom of the DFN package should be connected
to the most negative potential (V–).
Figure 36. Dual-Supply Transimpedance
Amplifier
To
achieve
a
maximally-flat,
second-order
Butterworth frequency response, the feedback pole
should be set to:
1
GBW
=
2pRFCF
4pRFCD
(1)
APPLICATION EXAMPLES
Bandwidth is calculated by:
TRANSIMPEDANCE AMPLIFIER
GBW
f
=
(Hz)
-3dB
Wide gain bandwidth, low input bias current, low input
voltage, and current noise make the OPA320 an ideal
wideband photodiode transimpedance amplifier.
Low-voltage noise is important because photodiode
capacitance causes the effective noise gain of the
circuit to increase at high frequency.
2pRFCD
(2)
For even higher transimpedance bandwidth, consider
the high-speed CMOS OPA380 (90MHz GBW),
OPA354 (100MHz GBW), OPA300 (180MHz GBW),
OPA355 (200MHz GBW), or OPA656/57 (400MHz
GBW).
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For single-supply applications, the +IN input can be
biased with a positive dc voltage to allow the output
to reach true zero when the photodiode is not
exposed to any light, and respond without the added
delay that results from coming out of the negative rail;
this configuration is shown in Figure 37. This bias
voltage also appears across the photodiode,
providing a reverse bias for faster operation.
photodiode
can
significantly
reduce
its
capacitance. Smaller photodiodes have lower
capacitance. Use optics to concentrate light on a
small photodiode.
3. Noise increases with increased bandwidth. Limit
the circuit bandwidth to only that required. Use a
capacitor across the RF to limit bandwidth, even if
not required for stability.
(1)
CF
4. Circuit board leakage can degrade the
performance of an otherwise well-designed
amplifier. Clean the circuit board carefully. A
circuit board guard trace that encircles the
summing junction and is driven at the same
voltage can help control leakage.
< 1pF
RF
10MW
For additional information, refer to the Application
Bulletins Noise Analysis of FET Transimpedance
Amplifiers (SBOA060), and Noise Analysis for
High-Speed Op Amps (SBOA066), available for
download at the TI web site.
V+
l
HIGH-IMPEDANCE SENSOR INTERFACE
VOUT
OPA320
+VBIAS
Many sensors have high source impedances that
may range up to 10MΩ, or even higher. The output
signal of sensors often must be amplified or
otherwise conditioned by means of an amplifier. The
input bias current of this amplifier can load the sensor
output and cause a voltage drop across the source
resistance, as shown in Figure 38, where (VIN+ = VS –
IBIAS × RS). The last term, IBIAS × RS, shows the
voltage drop across RS. To prevent errors introduced
to the system as a result of this voltage, an op amp
with very low input bias current must be used with
high impedance sensors. This low current keeps the
error contribution by IBIAS × RS less than the input
voltage noise of the amplifier, so that it does not
become the dominant noise factor. The OPA320
series of op amps feature very low input bias current
(typically 200fA), and are therefore ideal choices for
such applications.
(1) CF is optional to prevent gain peaking. It includes the stray
capacitance of RF.
Figure 37. Single-Supply Transimpedance
Amplifier
For additional information, refer to Application Bulletin
(SBOA055), Compensate Transimpedance Amplifiers
Intuitively, available for download at www.ti.com.
OPTIMIZING THE TRANSIMPEDANCE
CIRCUIT
To achieve the best performance, components should
be selected according to the following guidelines:
1. For lowest noise, select RF to create the total
required gain. Using a lower value for RF and
adding gain after the transimpedance amplifier
generally produces poorer noise performance.
The noise produced by RF increases with the
square-root of RF, whereas the signal increases
linearly. Therefore, signal-to-noise ratio improves
when all the required gain is placed in the
transimpedance stage.
RS
100kW
IB
VIN+
V+
OPA320
V-
VOUT
RF
RG
2. Minimize photodiode capacitance and stray
capacitance at the summing junction (inverting
input). This capacitance causes the voltage noise
of the op amp to be amplified (increasing
Figure 38. Noise as a Result of IBIAS
amplification at high frequency). Using
low-noise voltage source to reverse-bias
a
a
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SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
DRIVING ADCS
The OPA320 can be used to buffer the ADC switched
input capacitance and resulting charge injection while
providing signal gain. Figure 40 shows the OPA320
configured to drive the ADS8326.
The OPA320 series op amps are well-suited for
driving sampling analog-to-digital converters (ADCs)
with sampling speeds up to 1MSPS. The
zero-crossover distortion input stage topology allows
the OPA320 to drive ADCs without degradation of
differential linearity and THD.
+5V
50kW
(2.5V)
8
RG
REF1004-2.5
R1
R2
4
100kW
25kW
+5V
+5V
R3
R4
25kW
100kW
1/2
OPA2320
1/2
VOUT
OPA2320
RL
10kW
200kW
G = 5 +
RG
Figure 39. Two Op Amp Instrumentation Amplifier with Improved High-Frequency Common-Mode
Rejection
+5V
C1
100nF
+5V
(1)
R1
V+
OPA320
V-
100W
+IN
ADS8326
16-Bit
250kSPS
(1)
C3
-IN
1nF
VIN
0 to 4.096V
REF IN
Optional(2)
+5V
R2
SD1
BAS40
50kW
REF3240
-5V
4.096V
C2
C4
100nF
100nF
(1) Suggested value; may require adjustment based on specific application.
(2) Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing limitation. If a negative
power supply is available, this simple circuit creates a –0.3V supply to allow output swing to true ground potential.
Figure 40. Driving the ADS8326
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ACTIVE FILTER
MFB and Sallen-Key, low-pass and high-pass filter
synthesis is quickly accomplished using TI’s
FilterPro™ program. This software is available as a
free download at www.ti.com.
The OPA320 is well-suited for active filter applications
that require a wide bandwidth, fast slew rate,
low-noise,
single-supply
operational
amplifier.
R3
Figure 41 shows a 500kHz, second-order, low-pass
filter using the multiple−feedback (MFB) topology.
The components have been selected to provide a
maximally-flat Butterworth response. Beyond the
cutoff frequency, roll-off is –40dB/dec. The
Butterworth response is ideal for applications
requiring predictable gain characteristics, such as the
anti-aliasing filter used in front of an ADC.
549W
C2
150pF
V+
R1
R2
549W
1.24kW
One point to observe when considering the MFB filter
is that the output is inverted, relative to the input. If
this inversion is not required, or not desired, a
noninverting output can be achieved through one of
these options:
VIN
VOUT
OPA320
C1
1nF
V-
1. adding an inverting amplifier;
Figure 41. Second-Order Butterworth 500kHz
Low-Pass Filter
2. adding an additional second-order MFB stage; or
3. using a noninverting filter topology, such as the
Sallen-Key (shown in Figure 42).
220pF
V+
19.5kW
150kW
1.8kW
VIN = 1VRMS
VOUT
OPA320
3.3nF
47pF
V-
Figure 42. OPA320 Configured as a Three-Pole, 20kHz, Sallen-Key Filter
18
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SBOS513D –AUGUST 2010–REVISED NOVEMBER 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2011) to Revision D
Page
•
Changed status of OPA2320 SO-8 (D) to production data from product preview. ............................................................... 2
Changes from Revision B (March 2010) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added SHDN value to Electrical Characteristics condition line ............................................................................................ 3
Added new test condition row for Input Bias Current Over Temperature parameter ........................................................... 3
Changed test condition for Phase Margin parameter in Electrical Characteristics ............................................................... 3
Added test condition to Short-Circuit Current parameter in Electrical Characteristics ......................................................... 4
Changed Shutdown subsection of Electrical Characteristics along with associated notes .................................................. 4
Changed Power Supply subsection of Electrical Characteristics ......................................................................................... 4
Added values to Thermal Information tables, moved to new page, and updated format ..................................................... 5
Removed D (SO-8) package pinout drawing from Pin Configurations section ..................................................................... 6
Changed names of pins 2 and 6 for DGS (MSOP-10) package .......................................................................................... 6
Changed Figure 4 ................................................................................................................................................................. 7
Changed Figure 18 ............................................................................................................................................................... 9
Changed 100µs to 100ns in first paragraph of Overload Recovery Time section .............................................................. 14
Changed Figure 34 ............................................................................................................................................................. 14
Changed Figure 35 ............................................................................................................................................................. 14
Changed R2 value in Figure 40 from 500Ω to 50kΩ ........................................................................................................... 17
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PACKAGE OPTION ADDENDUM
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19-Nov-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
OPA2320AID
OPA2320AIDGKR
OPA2320AIDGKT
OPA2320AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
MSOP
MSOP
SOIC
D
8
8
8
8
8
8
5
5
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DGK
DGK
D
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
2500
1000
250
Green (RoHS
& no Sb/Br)
OPA2320AIDRGR
OPA2320AIDRGT
OPA320AIDBVR
OPA320AIDBVT
SON
DRG
DRG
DBV
DBV
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
SOT-23
SOT-23
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2320AIDGKR
OPA2320AIDGKT
OPA2320AIDRGR
OPA2320AIDRGT
OPA320AIDBVR
OPA320AIDBVT
MSOP
MSOP
SON
DGK
DGK
DRG
DRG
DBV
DBV
8
8
8
8
5
5
2500
250
330.0
180.0
330.0
180.0
180.0
180.0
12.4
12.4
12.4
12.4
8.4
5.3
5.3
3.3
3.3
3.2
3.2
3.4
3.4
3.3
3.3
3.1
3.1
1.4
1.4
8.0
8.0
8.0
8.0
4.0
4.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q2
Q2
Q3
Q3
1000
250
1.1
SON
1.1
SOT-23
SOT-23
3000
250
1.39
1.39
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2320AIDGKR
OPA2320AIDGKT
OPA2320AIDRGR
OPA2320AIDRGT
OPA320AIDBVR
OPA320AIDBVT
MSOP
MSOP
SON
DGK
DGK
DRG
DRG
DBV
DBV
8
8
8
8
5
5
2500
250
346.0
210.0
346.0
210.0
190.5
190.5
346.0
212.7
346.0
212.7
212.7
212.7
29.0
35.0
29.0
35.0
31.8
31.8
1000
250
SON
SOT-23
SOT-23
3000
250
Pack Materials-Page 2
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相关型号：
OPA320SAIDBVT
Precision, 20MHz, 0.9pA, Low-Noise, RRIO, CMOS Operational Amplifier with Shutdown
NSC
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