OPA375IDCKR [TI]

单路、5.5V、10MHz、低噪声 (4.6nV/√Hz)、68mA 输出电流、RRO 运算放大器 | DCK | 5 | -40 to 125;


型号：	OPA375IDCKR
厂家：	TEXAS INSTRUMENTS
描述：	单路、5.5V、10MHz、低噪声 (4.6nV/√Hz)、68mA 输出电流、RRO 运算放大器 \| DCK \| 5 \| -40 to 125 放大器运算放大器
文件：	总66页 (文件大小：5072K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

OPA375、OPA2375、OPA4375 500µV（最大值）、10MHz、低宽带噪声、RRO

运算放大器

1 特性

3 说明

• 低宽带噪声：3.5nV/√Hz

• 低失调电压：500µV（最大值）

• 低THD+N：0.00015%

• 增益带宽：10MHz

• 轨到轨输出

• 单位增益稳定

• 低I_Q：

– OPA375：890µA/通道

– OPA2375/OPA4375：990µA/通道

• 宽电源电压范围：

OPAx375 系列包括单通道 (OPA375) 、双通道

(OPA2375) 和四通道 (OPA2375) 通用 CMOS 运算放

大器，这些运算放大器提供 3.5nV/√Hz 的超低噪声系

数、500µV（最大值）的低失调电压和 10MHz 的高带

宽。OPAx375 系列器件凭借低噪声和高带宽特性，适

用于要求在成本和性能之间达到良好平衡的各种高精度

应用。此外，OPAx375 的输入偏置电流支持具有高源

阻抗的应用。

OPAx375 系列器件采用稳健耐用的设计，方便电路设

计人员使用；这得益于该器件具有单位增益稳定性、集

成的 RFI/EMI 抑制滤波器、在过驱条件下不会出现反

相并且具有高静电放电 (ESD) 保护功能 (2kV HBM)。

另外，电阻式开环输出阻抗使其易于在较高的容性负载

下保持稳定。

– OPA375：2.25V 至5.5V

– OPA2375/OPA4375：1.7V 至5.5V

• 低失调电压漂移：±0.16µV/°C

2 应用

该运算放大器经优化可在低电压下工作，OPA375 的工

作电压低至 2.25V (±1.125V)，OPA2375 和 OPA4375

的工作电压可低至 1.7V (±0.85V)。所有器件的最高工

作电压均为 5.5V (±2.75V)，额定温度范围为 –40°C

至125°C。

• 光电二极管放大器

• 精密传感器前端

• ADC 输入驱动器放大器

• 测试和测量设备

• 传感器现场变送器

• 可穿戴消费类应用

• 音频设备

单通道 OPA375 采用小尺寸的 SC70-5 封装。双通道

OPA2375 可采用多种封装选项，其中包括 1.5mm ×

2.0mm X2QFN 微型封装。

• 医疗仪器

• 有源滤波器

器件信息

100

器件型号⁽¹⁾

OPA375

封装尺寸（标称值）

1.25mm × 2.00mm

3.91mm × 4.90mm

3.00mm × 4.40mm

3.00mm × 3.00mm

1.60mm × 2.90mm

2.00mm × 2.00mm

1.50mm x 2.00mm

封装

SC70 (5)

SOIC (8)

TSSOP (8)

VSSOP (8)

SOT-23 (8)

WSON (8)

X2QFN (10)

OPA2375

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

100

Frequency (Hz)

10k

100k

D012

噪声频谱密度与频率间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBOS886

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

Table of Contents

8.4 Device Functional Modes..........................................31

9 Application and Implementation..................................32

9.1 Application Information............................................. 32

9.2 Single-Supply Electret Microphone Preamplifier

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................4

6 Pin Configuration and Functions...................................5

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings ....................................... 7

7.2 ESD Ratings .............................................................. 7

7.3 Recommended Operating Conditions ........................7

7.4 Thermal Information for Single Channel .................... 7

7.5 Thermal Information for Dual Channel .......................8

7.6 Electrical Characteristics ............................................9

7.7 Typical Characteristics: OPA375...............................12

7.8 Typical Characteristics: OPA2375.............................19

8 Detailed Description......................................................26

8.1 Overview...................................................................26

8.2 Functional Block Diagram.........................................26

8.3 Feature Description...................................................26

With Speech Filter.......................................................32

10 Power Supply Recommendations..............................35

11 Layout...........................................................................36

11.1 Layout Guidelines................................................... 36

11.2 Layout Example...................................................... 37

12 Device and Documentation Support..........................39

12.1 Documentation Support.......................................... 39

12.2 接收文档更新通知................................................... 39

12.3 支持资源..................................................................39

12.4 Trademarks.............................................................39

12.5 Electrostatic Discharge Caution..............................39

12.6 术语表..................................................................... 39

13 Mechanical, Packaging, and Orderable

Information.................................................................... 40

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision D (February 2021) to Revision E (August 2021)

Page

• 将OPA2375 VSSOP (DGK) 封装从预发布更改为正在供货..............................................................................1

• Removed preview tag for the VSSOP (DGK) package in the Device Comparison Table section...................... 4

• Added VSSOP Package thermal data for OPA2375 in the Thermal Information for Dual Channel section....... 7

Changes from Revision C (June 2020) to Revision D (February 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Changed Operating temperature from 125 to 150 in Absolute Maximum Ratings ........................................... 7

• Added Junction temperature spec to Absolute Maximum Ratings .................................................................... 7

• Removed OPA375 Table of Graphs and OPA2375 Table of Graphs tables from the Specifications section....12

• Removed Related Links section from the Device and Documentation Support section...................................39

Changes from Revision B (January 2020) to Revision C (June 2020)

Page

• 将OPA2375S X2QFN (RUG) 封装从预发布更改为正在供货........................................................................... 1

• Added X2QFN Package Drawing and Pin Functions for OPA2375S in Pin Configuration and Functions

section................................................................................................................................................................ 5

• Changed typical input current noise density value from 2 fA√HZ to 23 fA√Hz................................................9

• Changed total supply voltage total from 5V to 5.5V in Electrical Characteristics condition statement............... 9

• Deleted "Vs = 2.25 V to 5.5 V" test conditions for common-mode rejection ratio parameter in Electrical

Characteristics ...................................................................................................................................................9

Changes from Revision A (January 2019) to Revision B (January 2020)

Page

• 更改了特性部分的“低宽带噪声”规格以便与OPA2375 规格匹配................................................................... 1

• 向特性部分添加了THD+N 规格.........................................................................................................................1

• 在特性部分中添加了OPA2375 和OPA4375 的I_Q定义.................................................................................... 1

• 在特性部分中添加了OPA2375 和OPA4375 的电源电压范围定义....................................................................1

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

• 将首页上的噪声频谱密度与频率间的关系图更改为OPA2375 噪声图.................................................................1

• 更改了说明部分的措辞以反映整个OPAx375 系列.............................................................................................1

• 向器件信息表中添加了OPA2375 器件.............................................................................................................. 1

• Added Device Comparison Table section...........................................................................................................4

• Added pin out drawings for OPA2375 packages in Pin Configuration and Functions section............................5

• Added pin functions for OPA2375 packages...................................................................................................... 5

• Changed Human-body model (HBM) value from: ±1000 to ±3000 and Charged-device mode (CDM) value

from ±250 to ±1000.............................................................................................................................................7

• Added OPA2375 typical characteristic graphs in the Specifications section.................................................... 12

• Added EMI Rejection section with description information to Detailed Description section............................. 27

• Added Electrical Overstress section and diagram to Detailed Description section.......................................... 28

• Added Typical Specification and Distributions section to Detailed Description section.................................... 29

• Added Shutdown Function section with description for OPAx375S to Detailed Description section................ 30

• Added Packages With an Exposed Thermal Pad section to Detailed Description section...............................30

• Added dual channel layout example in the Layout section...............................................................................37

Changes from Revision * (November 2017) to Revision A (January 2019)

Page

• Added maximum input offset voltage drift specification in Electrical Characteristics .........................................9

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

5 Device Comparison Table

PACKAGE LEADS

NO. OF

DEVICE

SOIC

SC-70

DCK

VSSOP

DGK

WSON

DSG

TSSOP

SOT-23

DDF

X2QFN

RUG

CHANNELS

OPA375

—

OPA2375

—

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

6 Pin Configuration and Functions

IN+

Vœ

V+

INœ

OUT

Not to scale

图6-1. OPA375 DCK Package

5-Pin SC70

Top View

表6-1. Pin Functions: OPA375

I/O

DESCRIPTION

NAME

+IN

NO.

Noninverting input

Inverting input

–IN

OUT

V+

—

Output

Positive (highest) supply

Negative (lowest) supply or ground (for single-supply operation)

V–

OUT1

V+

OUT1

IN1œ

IN1+

Vœ

V+

IN1œ

IN1+

Vœ

OUT2

IN2œ

IN2+

OUT2

IN2œ

IN2+

Thermal

Pad

Not to scale

图6-2. OPA2375 D, DGK, PW, and DDF Package

8-Pin SOIC, VSSOP, TSSOP, and SOT-23

Top View

Connect thermal pad to V–. See 节8.3.8 for more information.

图6-3. OPA2375 DSG Package

8-Pin WSON With Exposed Thermal Pad

Top View

表6-2. Pin Functions: OPA2375

I/O

DESCRIPTION

NAME

IN1–

NO.

Inverting input, channel 1

IN1+

IN2–

IN2+

OUT1

OUT2

V–

Noninverting input, channel 1

Inverting input, channel 2

Noninverting input, channel 2

Output, channel 1

Output, channel 2

Negative (lowest) supply or ground (for single-supply operation)

—

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

表6-2. Pin Functions: OPA2375 (continued)

I/O

DESCRIPTION

NAME

NO.

V+

Positive (highest) supply

—

Vœ

SHDN1

SHDN2

IN2+

IN1œ

OUT1

V+

OUT2

Not to scale

图6-4. OPA2375S RUG Package

10-Pin X2QFN

Top View

表6-3. Pin Functions: OPA2375S

I/O

DESCRIPTION

NAME

NO.

Inverting input, channel 1

Noninverting input, channel 1

Inverting input, channel 2

Noninverting input, channel 2

Output, channel 1

IN1–

IN1+

IN2–

IN2+

OUT1

OUT2

Output, channel 2

Shutdown: low = amp disabled, high = amp enabled. Channel 1. See 节8.3.7 for more

information.

SHDN1

SHDN2

Shutdown: low = amp disabled, high = amp enabled. Channel 2. See 节8.3.7 for more

information.

Negative (lowest) supply or ground (for single-supply operation)

Positive (highest) supply

V–

I or —

V+

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

Supply voltage, V_S= (V+) –(V–)

Common-mode voltage ^{(3) (4)}

(V+) + 0.5

V_S+ 0.2

(V–) –0.5

Signal input pins

Differential voltage ⁽³⁾

Current ⁽³⁾

–10

–55

–65

Output short-circuit ⁽²⁾

Continuous

Operating ambient temperature, T_A

Junction temperature, T_J

Storage temperature, T_stg

150

°C

(1) Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device. These

are stress ratings only, based on process and design limitations, and this device has not been designed to function outsdie the

conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating

Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance.

(2) Short-circuit to ground, one amplifier per package.

(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

(4) Differential input voltages greater than 0.25 V applied continuously can result in a shift to the input offset voltage above the maximum

specification of this parameter. The magnitude of this effect increases as the ambient operating temperature rises.

7.2 ESD Ratings

VALUE

±3000

±2000

UNIT

OPA375: Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

OPA2375: Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

V_(ESD)

Electrostatic discharge

All Devices: Charged-device model (CDM), per JEDEC specification JESD22-C101

±1500

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

1.7⁽¹⁾

2.25

MAX

UNIT

V_S

V_I

5.5

Supply voltage, (V+) –(V–) , for OPA2375 and OPA4375

Supply voltage, (V+) –(V–), for OPA375 only

Input voltage range

(V–)

–40

(V+) –1.2

125

T_A

Specified temperature

°C

(1) Operation between 1.7 V and 1.8 V is only recommened for T_A= 0 - 85℃

7.4 Thermal Information for Single Channel

THERMAL METRIC ⁽¹⁾

OPA375

DCK

(SC70)

UNIT

5 PINS

240.9

151.7

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

℃/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

34.8

63.3

ψ_JB

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.4 Thermal Information for Single Channel (continued)

OPA375

DCK

(SC70)

THERMAL METRIC ⁽¹⁾

UNIT

5 PINS

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

n/a

℃/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report SPRA953C.

7.5 Thermal Information for Dual Channel

OPA2375, OPA2375S

DDF

(SOT-23-8)

DSG

(WSON)

(TSSOP)

DGK

(VSSOP)

RUG

(X2QFN)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

8 PINS

10 PINS

Junction-to-ambient thermal

resistance

R_θJA

131.1

153.8

78.2

185.6

177.0

140.3

°C/W

Junction-to-case (top) thermal

resistance

R_θJC(top)

73.2

74.5

24.4

73.3

n/a

80.2

73.1

6.6

97.5

44.6

4.7

74.5

116.3

12.6

114.6

n/a

68.6

98.7

12.4

97.1

n/a

52.6

69.7

1.0

Junction-to-board thermal

resistance

R_θJB

Junction-to-top

characterization parameter

ψ_JT

Junction-to-board

characterization parameter

72.7

n/a

44.6

19.8

67.5

n/a

ψ_JB

Junction-to-case (bottom)

thermal resistance

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953C.

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.6 Electrical Characteristics

OPA2375/4375 Specifications: V_S= (V+) –(V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at T_A= 25°C, R_L= 10 kΩ connected

to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}= V_S/ 2, unless otherwise noted.

OPA375 Specifications: V_S= (V+) –(V–) = 5.5 V at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±0.15

±0.5

±0.7

±2⁽⁴⁾

V_OS

Input offset voltage

V_S= 5.0 V

OPA2/4375⁽³⁾

OPA375⁽²⁾

T_A= –40°C to 125°C

±0.35

±0.16

±0.32

±0.7

dV_OS/dT

PSRR

Input offset voltage drift

µV/℃

OPA2/4375⁽³⁾

OPA375⁽²⁾

±6.3

±5.8

V_S= 2.25 V to 5.5 V, V_CM= V–

V_VCM= V–

Input offset voltage

versus power supply

μV/V

OPA2/4375⁽³⁾

Channel separation

f = 20 kHz

130

INPUT BIAS CURRENT

OPA375⁽²⁾

±10

±3

I_B

Input bias current

OPA2/4375⁽³⁾

OPA375⁽²⁾

±10

±0.5

I_OS

Input offset current

Input voltage noise

OPA2/4375⁽³⁾

NOISE

E_N

1.2

0.227

μV_PP

f = 0.1 to 10 Hz

f = 10 Hz

µV_RMS

OPA2/4375⁽³⁾

OPA375⁽²⁾

5.0

f = 1 kHz

Input voltage noise

density

e_N

OPA2/4375⁽³⁾

OPA375⁽²⁾

4.6

nV/√Hz

3.7

f = 10 kHz

f = 1 kHz

OPA2/4375⁽³⁾

3.5

i_N

Input current noise

fA/√Hz

INPUT VOLTAGE RANGE

Common-mode voltage

range

V_CM

(V+) -1.2

(V–)

OPA375⁽²⁾

120

100

110

(V–) < V_CM< (V+) –1.2 V

Common-mode

rejection ratio

CMRR

V_S= 1.8 V, (V–) < V_CM< (V+) –1.2 V

V_S= 5.5, (V–) < V_CM< (V+) –1.2 V

OPA2/4375⁽³⁾

INPUT CAPACITANCE

Z_ID

Differential

10 || 6

MΩ|| pF

GΩ|| pF

Z_ICM

Common-mode

OPEN-LOOP GAIN

(V–) + 40 mV < V_O< (V+) –40 mV, R_L= 10 kΩ

125

130

140

132

142

to V_S/2

OPA375⁽²⁾

(V–) + 150 mV < V_O< (V+) –150 mV, R_L= 2

kΩ to V_S/2

110

107

V_S= 1.8 V, (V–) + 150 mV < V_O< (V+) –150

mV, R_L= 2 kΩ to V_S/2

A_OL

Open-loop voltage gain

V_S= 5.5 V, (V–) + 150 mV < V_O< (V+) –150

mV, R_L= 2 kΩ to V_S/2

OPA2/4375⁽³⁾

V_S= 1.8 V, (V–) + 40m V < V_O< (V+) –40 mV,

R_L= 10 kΩ to V_S/2

110

V_S= 5.5 V, (V–) + 40m V < V_O< (V+) –40 mV,

R_L= 10 kΩ to V_S/2

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

OPA2375/4375 Specifications: V_S= (V+) –(V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at T_A= 25°C, R_L= 10 kΩ connected

to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}= V_S/ 2, unless otherwise noted.

OPA375 Specifications: V_S= (V+) –(V–) = 5.5 V at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FREQUENCY RESPONSE

GBW

Gain-bandwidth product

MHz

Slew rate

V_S= 5.5 V, G = +1, C_L= 20 pF

4.6

V/μs

To 0.1%, V_S= 5.5 V, V_STEP= 2 V, G = +1, CL =

20pF

0.65

1.2

t_S

Settling time

Phase margin

μs

To 0.01%, V_S= 5.5 V, V_STEP= 2 V, G = +1, CL =

20pF

0.2

G = +1, R_L= 10kΩ, C_L= 20 pF

Overload recovery time V_IN× gain > V_S

μs

OPA375⁽²⁾

0.00035

0.00015

V_S= 5.5 V, V_CM= 2.5 V, V_O= 1 V_RMS, G = +1, f =

1 kHz, R_L= 10 kΩ

Total harmonic

distortion + noise

THD+N

OPA2/4375⁽³⁾

Electro-magnetic

interference rejection

ratio

EMIRR

f = 1 GHz

OPA2/4375⁽³⁾

OPA375⁽²⁾

OUTPUT

Positive/Negative rail

headroom

V_S= 5.5 V, R_L= 10k

V_S= 5.5 V, R_L= no load

V_S= 5.5 V, R_L= 2 kΩ

V_S= 5.5 V, R_L= 10 kΩ

V_S= 5.5 V, R_L= no load

Positive rail headroom

Voltage output swing

from rail

OPA2/4375⁽³⁾

Negative rail headroom V_S= 5.5 V, R_L= 2 kΩ

V_S= 5.5 V, R_L= 10 kΩ

I_SC

Short-circuit current

Capacitive load drive

±68

See 图

7-58

C_LOAD

f = 10 MHz, I_O= 0 A

f = 2 MHz, I_O= 0 A

OPA375⁽²⁾

160

165

Ω

Open-loop output

impedance

Z_O

OPA2/4375⁽³⁾

POWER SUPPLY

890

990

OPA375⁽²⁾

1100

1200

1250

T_A= –40°C to 125°C

Quiescent current per

amplifier

I_Q

V_S= 5.5 V, I_O= 0 A

µA

OPA2/4375⁽³⁾

T_A= –40°C to 125°C

Turn-On Time

At T_A= 25°C, V_S= 5.5 V, V_Sramp rate > 0.3 V/µs OPA2/4375⁽³⁾

μs

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

OPA2375/4375 Specifications: V_S= (V+) –(V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at T_A= 25°C, R_L= 10 kΩ connected

to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}= V_S/ 2, unless otherwise noted.

OPA375 Specifications: V_S= (V+) –(V–) = 5.5 V at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SHUTDOWN

Quiescent current per

amplifier

I_QSD

3.5

µA

All amplifiers disabled, SHDN = V–

Output impedance

during shutdown

Z_SHDN

Amplifier disabled

10 || 6

GΩ|| pF

Logic high threshold

voltage (amplifier

enabled)

(V–) + 1.1

V_IH

Logic low threshold

voltage (amplifier

disabled)

(V–) + 0.2

V_IL

Amplifier enable time

(full shutdown) ⁽¹⁾

G = +1, V_CM= V-, V_O= 0.1 × V_S/2

t_ON

Amplifier enable time

(partial shutdown)⁽¹⁾

µs

t_OFF

Amplifier disable time ⁽¹⁾V_CM= V-, V_O= V_S/2

0.4

(V+) ≥SHDN ≥(V–) + 0.9 V

(V–) ≤SHDN ≤(V–) + 0.7 V

SHDN pin input bias

current (per pin)

µA

0.25

(1) Disable time (t_OFF) and enable time (t_ON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(2) This electrical characteristic only applies to the single-channel, OPA375

(3) This electrical characteristic only applies to the dual-channel OPA2375 and quad-channel OPA4375

(4) Specified by design and characterization; not production tested

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.7 Typical Characteristics: OPA375

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise noted)

40%

35%

30%

25%

20%

15%

10%

0.4

0.8

1.2

Offset Voltage Drift (mV/èC)

图7-2. Offset Voltage Drift Distribution

1.6

2.4

2.8

D001

D002

Offset Voltage(µV)

图7-1. Offset Voltage Production Distribution

200

100

-100

-200

-300

-400

-2

-4

-6

-60 -40 -20

80 100 120 140

-4

-3

-2

-1

Input Common Mode Voltage (V)

Temperature (èC)

D003

D004

图7-3. Offset Voltage vs Temperature

图7-4. Offset Voltage vs Common-Mode Voltage

0.5

0.4

0.3

0.2

0.1

300

200

100

-100

-200

-300

-400

-500

-0.1

-0.2

-0.3

-0.4

-0.5

-2.5

-2

-1.5

-1

-0.5

0.5

Input Common Mode Voltage (V)

1.5

2.5

3.5

V_S(V)

4.5

5.5

D004

D005

图7-5. Offset Voltage vs Common-Mode Voltage

图7-6. Offset Voltage vs Power Supply

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.7 Typical Characteristics: OPA375 (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise noted)

I_B-

I_B+

I_OS

I_B-

I_B+

I_OS

-20

-40

-60

-80

-100

-120

-2

-4

-6

-8

-4

-3

-2

-1

V_CM(V)

100

Temperature (èC)

150

D043

D044

图7-7. I_Band I_OSvs Common-Mode Voltage

图7-8. I_Band I_OSvs Temperature

100

-10

-20

-30

-40

-25

-50

-75

-25

-50

-75

Gain = -1

Gain = 10

Gain = +1

Gain

Phase

10k

100k

Frequency (Hz)

10M

10k

100k

Frequency (Hz)

10M

D006

D007

C_L= 10 pF

图7-9. Open-Loop Gain and Phase vs Frequency

图7-10. Closed-Loop Gain vs Frequency

120

PSRR- (dB)

PSRR+ (dB)

2.5

100

1.5

-40°C

125°C

25°C

85°C

0.5

-0.5

-1

85°C

25°C

-40°C

125°C

-1.5

-2

-2.5

-3

10k

100k

Output Current (mA)

Frequency (Hz)

D011

D010

图7-12. PSRR vs Frequency (Referred to Input)

图7-11. V_Ovs I Sourcing and Sinking

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.7 Typical Characteristics: OPA375 (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise noted)

120

110

100

-5

-10

10k

100k

-50

Temperature (èC)

100

150

Frequency (Hz)

D011

D012

V_CM= 0 V to 4.3

T_A= –40°C to

125°C

V_S= 5.5 V

图7-13. CMRR vs Frequency (Referred to Input)

图7-14. CMRR vs Temperature

100

Frequency (Hz)

10k

100k

Time (1 s/div)

D015

D014

图7-16. Input Voltage Noise Spectral Density vs Frequency

图7-15. 0.1-Hz to 10-Hz Flicker Noise

-95

-97

-99

-97

-99

-101

-103

-105

-103

-105

100

Frequency (Hz)

10k

100

Frequency (Hz)

10k

D017

V_S= 5.5 V

Gain = 1

V_ICM= 2.5 V

BW = 80 kHz

V_S= 5.5 V

Gain = 1

V_ICM= 2.5 V

R_L= 2 kΩ

R_L= 10 kΩ

V_OUT= 0.5 Vrms

BW = 80 kHz V_OUT= 0.5 Vrms

图7-17. THD + N vs Frequency

图7-18. THD + N vs Frequency

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.7 Typical Characteristics: OPA375 (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise noted)

1000

950

900

850

800

750

700

650

600

550

500

Gain = +1, R_L= 2 kW

Gain = +1, R_L= 10 kW

Gain = -1, R_L= 2 kW

Gain = -1, R_L= 10 kW

-20

-40

-60

-80

-100

-120

0.001

0.01

0.1

V_OUT(rms)

1.5

2.5

3.5

Supply Voltage (V)

4.5

5.5

D018

D020

V_S= 5.5 V

V_ICM= 2.5 V

V_OUT= 0.5 Vrms

图7-19. THD + N vs Amplitude

BW = 80 kHz

图7-20. Quiescent Current vs Supply Voltage

1000

950

A_VDD= 5.5 V

A_VDD= 1.8 V

900

850

800

750

700

650

600

550

500

-50

Temperature (èC)

100

150

-60 -40 -20

80 100 120 140

Temperature (èC)

D021

D022

R_L= 2 kΩ

图7-21. Quiescent Current vs Temperature

图7-22. Open-Loop Gain vs Temperature

1000

100

200

160

120

0.5

1.5

2.5

3.5

4.5

5.5

10k

100k

Frequency (Hz)

10M

Output Voltage (V)

C023

D024

V_ICM= V_OCM= 2.75

A_VDD= 5.5 V

图7-23. Open-Loop Gain vs Output Voltage

图7-24. Open-Loop Output Impedance vs Frequency

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.7 Typical Characteristics: OPA375 (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise noted)

Overshoot (+)

Overshoot (-)

Overshoot (+)

Overshoot (-)

Capacitive Load (pF)

90 100

Capacitance (pF)

90 100

D025

V_S= 5.5 V

G = 1

V_ICM= 2.75 V

V_OCM= 2.75 V

V_S= 1.8 V

G = 1

V_ICM= 0.9 V

V_OCM= 0.9 V

100-mV output step

图7-25. Small-Signal Overshoot vs Load Capacitance

图7-26. Small-Signal Overshoot vs Load Capacitance

Overshoot (+)

Overshoot (-)

Overshoot (+)

Overshoot (-)

Capacitive Load (pF)

90 100

Capacitance (pF)

90 100

D025

V_S= 5.5 V

V_ICM= 2.75 V

V_OCM= 2.75 V

V_S= 1.8 V

V_ICM= 0.9 V

V_OCM= 0.9 V

100-mV output step

Gain = –1

图7-27. Small-Signal Overshoot vs Load Capacitance

图7-28. Small-Signal Overshoot vs Load Capacitance

Input

Output

Input

Output

Time (2 ms/div)

Time (25 ms/div)

D028

D027

图7-30. Overload Recovery

图7-29. No Phase Reversal

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.7 Typical Characteristics: OPA375 (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise noted)

V_IN

V_OUT

V_IN

V_OUT

Time (1 ms/div)

Time (2 ms/div)

D030

D031

V_S= 1.8 V

C_L= 30 pF

V_ICM= 0.9 V

Gain = 1

V_OCM= 0.9 V

V_S= 5.5 V

V_OCM= 2.75 V

Gain = 1

C_L= 10 pF

2-V step

V_IN= 100 mVpp

V_ICM= 2.75 V

图7-31. Small-Signal Step Response

图7-32. Large Signal Step Response

Time (0.2 ms/div)

Time (0.1 ms/div)

D032

D033

V_S= 5.5 V

C_L= 0

V_ICM= 2.75 V

Gain = 1

V_OCM= 2.75 V

5-V step

V_S= 5.5 V

C_L= 0

V_ICM= 2.75 V

Gain = 1

V_OCM= 2.75 V

5-V step

图7-33. Large Signal Settling Time (Positive)

图7-34. Large Signal Settling Time (Negative)

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.7 Typical Characteristics: OPA375 (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise noted)

100

Sourcing

Sinking

V_S= 1.8 V

V_S= 5.5 V

-20

-40

-60

-80

-100

-50

Temperature (èC)

100

150

100

10k

Frequency (Hz)

100k

10M 100M

D034

D035

V_ICM= V_S/ 2

Gain = 1

V_OCM= V_S/ 2

C_L= 10 pF

图7-35. Short-Circuit Current vs Temperature

图7-36. Maximum Output Voltage vs Frequency

120

100

V_S= 1.8 V

V_S= 5.5 V

10M

100M

Frequency (Hz)

10G

Capacitive Load (pF)

D036

D037

V_ICM= V_OCM= V_S/ 2

图7-37. Electromagnetic Interference Rejection Ratio Referred

图7-38. Phase Margin vs Capacitive Load

to Noninverting Input (EMIRR+) vs Frequency

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.8 Typical Characteristics: OPA2375

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩconnected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

2500

2250

2000

1750

1500

1250

1000

750

500

250

-500 -400 -300 -200 -100

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Offset Voltage (µV)

100 200 300 400 500

D002

Offset Voltage Drift (mV/èC)

D001

V_CM= V–

图7-40. Offset Voltage Drift Distribution

图7-39. Offset Voltage Production Distribution

200

4800

4000

3200

2400

1600

800

160

120

-40

-80

-120

-160

-200

-800

-1600

-2400

-3200

-4000

-40

-20

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

Temperature (èC)

D003

D004

V_CM= V+

V_CM= V–

图7-42. Offset Voltage vs Temperature (NMOS Input Pair)

图7-41. Offset Voltage vs Temperature (PMOS Input Pair)

5000

4000

3000

2000

1000

200

160

120

-40

-80

-120

-160

-200

-1000

-2000

-3000

-4000

-3 -2.4 -1.8 -1.2 -0.6

Input Common Mode Voltage (V)

0.6 1.2 1.8 2.4

-3 -2.5 -2 -1.5 -1 -0.5

0.5

Input Common Mode Voltage (V)

1.5

D005

D006

Over full common-mode voltage range

图7-43. Offset Voltage vs Common-Mode Voltage (Full Range)

图7-44. Offset Voltage vs Common-Mode Voltage (PMOS Input

Pair)

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.8 Typical Characteristics: OPA2375 (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩconnected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

300

4000

240

3000

180

2000

120

1000

-60

-1000

-2000

-3000

-4000

-120

-180

-240

-300

1.8

1.9

2.1

2.2

Input Common Mode Voltage (V)

2.3

2.4

1.5

2.5

3.5

Supply Voltage (V)

4.5

5.5

D007

D008

图7-45. Offset Voltage vs Common-Mode Voltage (Transition

图7-46. Offset Voltage vs Power Supply

Region)

320

280

240

200

160

120

I_B-

I_B+

I_OS

-10

-20

-30

I_B-

I_B+

I_OS

-40

-50

-3 -2.5 -2 -1.5 -1 -0.5

V_CM(V)

-40

0.5

1.5

2.5

-20

40 60

Temperature (°C)

100 120 140

D009

D010

图7-47. I_Band I_OSvs Common-Mode Voltage

图7-48. I_Band I_OSvs Temperature

100

Time (1 s/div)

100

Frequency (Hz)

10k

100k

D011

D012

图7-49. 0.1-Hz to 10-Hz Flicker Noise

图7-50. Input Voltage Noise Spectral Density vs Frequency

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.8 Typical Characteristics: OPA2375 (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩconnected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

130

110

120

115

110

105

100

CMRR

PSRR+

PSRR-

-40

-20

40 60

Temperature (°C)

100 120 140

10k

100k

Frequency (Hz)

10M

D014

D013

V_S= 5.5 V, V_CM= V–to (V+) –1.2 V

图7-52. CMRR vs Temperature

图7-51. CMRR and PSRR vs Frequency (Referred to Input)

130

120

210

Gain

Phase

100

180

150

120

125

120

115

110

-20

-40

-20

40 60

Temperature (°C)

100 120 140

100

10k 100k

Frequency (Hz)

10M

D015

D016

C_L= 10 pF

V_CM= V–

图7-54. Open-Loop Gain and Phase vs Frequency

图7-53. PSRR vs Temperature

0.66

0.6

V_S=1.8V R_L=10kW

V_S=1.8V R_L=2kW

V_S=5.5V R_L=10kW

V_S=5.5V R_L=2kW

0.54

0.48

0.42

0.36

0.3

-20

-40

-60

-80

0.24

0.18

0.12

0.06

G = 1

G = -1

G = 10

G = 100

G = 1000

10k

100k

Frequency (Hz)

10M

-40

-20

40 60

Temperature (°C)

100 120 140

D017

D018

C_L= 10 pF

图7-55. Closed-Loop Gain vs Frequency

图7-56. Open-Loop Gain vs Temperature

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.8 Typical Characteristics: OPA2375 (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩconnected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

180

160

140

120

100

-20

-0.5

0.5

1.5

2.5 3.5

Output Voltage (V)

4.5

5.5

Capacitive Load (pF)

100

D019

D020

图7-57. Open-Loop Gain vs Output Voltage

图7-58. Phase Margin vs Capacitive Load

Input

Output

R_ISO= 0W, Overshoot (-)

R_ISO= 0W,Overshoot (+)

R_ISO= 50W, Overshoot (-)

R_ISO= 50W,Overshoot (+)

-1

-2

-3

-4

40 60

Capacitive Load (pF)

100

Time (10 µs/div)

D021

D022

V_CM= V_S/ 2, R_L= 1 kΩ

Gain = –1, 100-mV output step

图7-59. No Phase Reversal

图7-60. Small-Signal Overshoot vs Load Capacitance

R_ISO= 0W, Overshoot (-)

R_ISO= 0W,Overshoot (+)

R_ISO= 50W, Overshoot (-)

R_ISO= 50W,Overshoot (+)

2.5

-2.5

Input

Output

-5

Time (10 µs/div)

50 75

Capacitive Load (pF)

100

125

D024

D023

V_IN= 0.6 Vpp, G = –10, V_IN× gain > V_S

图7-62. Overload Recovery

V_CM= V_S/ 2, R_L= 1 kΩ

Gain = +1, 100-mV output step

图7-61. Small-Signal Overshoot vs Load Capacitance

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.8 Typical Characteristics: OPA2375 (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩconnected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

0.1

0.08

0.06

0.04

0.02

0.1

0.08

0.06

0.04

0.02

Input

Output

Input

Output

-0.02

-0.04

-0.06

-0.08

-0.1

-0.02

-0.04

-0.06

-0.08

-0.1

Time (1 µs/div)

D025

D027

C_L= 20 pF, Gain = 1, V_IN= 100-mVpp, R_L= 1 kΩ

图7-63. Small-Signal Step Response

C_L= 20 pF, Gain = –1, V_IN= 100-mVpp, R_L= 1 kΩ

图7-64. Small-Signal Step Response

1.25

Input

Output

Input

Output

0.75

0.5

0.75

0.5

0.25

-0.25

-0.5

-0.75

-1

-0.25

-0.5

-0.75

-1

-1.25

Time (1 µs/div)

D026

D028

C_L= 20 pF, Gain = +1, V_IN= 2-V step, R_L= 1 kΩ

图7-65. Large Signal Step Response

C_L= 20 pF, Gain = –1, V_IN= 2-V step, R_L= 1 kΩ

图7-66. Large Signal Step Response

0.1% Settling Time

Step Applied at t = 0

Time (0.25 ms/div)

D029

D050

C_L= 20 pF, Gain = 1, V_IN= 2-V step

C_L= 20 pF, Gain = –1, V_IN= 2-V step

图7-67. Large Signal Settling Time (Positive)

图7-68. Large Signal Settling Time (Negative)

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.8 Typical Characteristics: OPA2375 (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩconnected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

-80

-84

-40

R_L= 600 W

R_L= 2 kW

R_L= 10 kW

-88

-60

-92

-96

-100

-104

-108

-112

-116

-120

-80

-100

R_L= 10 kW

R_L= 2 kW

R_L= 600 W

-120

100

Frequency (Hz)

10k

10m

100m

V_OUT(rms)

D030

D031

V_CM= 2.5 V

Gain = +1, BW = 80 kHz, V_OUT= 0.5 Vrms

BW = 80 kHz

图7-69. THD + N vs Frequency

图7-70. THD + N vs Amplitude

2.8

2.6

2.4

2.2

-0.2

-0.4

-0.6

-0.8

-1

-40è

25è

85è

125è

85è

125è

1.8

1.6

1.4

1.2

-1.2

-1.4

-1.6

-1.8

-2

0.8

0.6

0.4

0.2

-2.2

-2.4

-2.6

-2.8

-3

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Output Current (mA)

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Output Current (mA)

D032

D033

图7-71. V_OUTvs Sourcing Current

图7-72. V_OUTvs Sinking Current

100

10k

Frequency (Hz)

100k

10M 100M

-40

-20

40 60

Temperature (°C)

100 120 140

D034

D035

C_L= 10 pF, Gain = +1, V_S= 5.5 V

图7-73. Maximum Output Voltage vs Frequency

图7-74. Short-Circuit Current vs Temperature

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

7.8 Typical Characteristics: OPA2375 (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩconnected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

1000

990

980

970

960

950

940

930

920

910

900

1000

990

980

970

960

950

940

930

920

910

900

1.5

2.5

3.5

Supply Voltage (V)

4.5

5.5

-40

-20

40 60

Temperature (°C)

100 120 140

D036

D037

图7-75. Quiescent Current vs Supply Voltage

图7-76. Quiescent Current vs Temperature

1200

1100

1000

900

800

700

600

500

400

300

200

100

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

10k

100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

D038

D040

图7-77. Open-Loop Output Impedance vs Frequency

A_VDD= 5.5 V, V_ICM= V_OCM= 2.75 V

图7-78. Channel Separation vs Frequency

120

6.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

Supply Voltage

Output

100

10M

100M

Frequency (Hz)

10G

Time (5 ms/div)

D039

D041

图7-79. Electromagnetic Interference Rejection Ratio Referred

V_S= 0 to 5.5 V, V_OUT= 0 to 2.75 V

to Noninverting Input (EMIRR+) vs Frequency

图7-80. Turn-On Time

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

8 Detailed Description

8.1 Overview

The OPAx375 family is an ultra low-noise, rail-to-rail output operational amplifier. The device operates from a

supply voltage of 2.25 V to 5.5 V (OPA375) and 1.7 V to 5.5 V (OPA2375 and OPA4375), are unity-gain stable,

and suitable for a wide range of general-purpose applications. The input common-mode voltage range includes

the negative rail and allows the OPAx375 op amp family to be used in most single-supply applications. Rail-to-

rail output swing significantly increases dynamic range, especially in low-supply applications, and makes it

suitable for many audio applications and driving sampling analog-to-digital converters (ADCs).

8.2 Functional Block Diagram

V+

Reference

Current

V_IN+

V_IN-

V_BIAS1

Class AB

Control

Circuitry

V_O

V_BIAS2

V-

(Ground)

8.3 Feature Description

8.3.1 THD + Noise Performance

The OPAx375 operational amplifier family has excellent distortion characteristics. OPA2375 and OPA4375 THD

+ Noise is below 0.00015% (G = +1, V_O= 1 V_RMS, V_CM= 1.8 V, V_S= 5.5 V) throughout the audio frequency

range, 20 Hz to 20 kHz, with a 10-kΩ load. The broadband noise of the 3.5 nV/√ Hz (OPA2375/4375) and 3.7

nV/√Hz (OPA375) is extremely low for a 10-MHz general purpose amplifier.

8.3.2 Operating Voltage

The OPAx375 operational amplifier family is fully specified and can operate from 1.7 V to 5.5 V (OPA2375/4375)

and 2.25 V to 5.5 V (OPA375). In addition, many specifications apply from –40°C to 125°C. Power-supply pins

must be bypassed with 0.1-µF ceramic capacitors.

8.3.3 Rail-to-Rail Output

Designed as low-power, low-voltage op amps, the OPAx375 devices deliver a robust output drive capability. A

class AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For

resistive loads of 10 kΩ, the output swings to within few mV of either supply rail, regardless of the applied

power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails, see

图7-71.

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

8.3.4 EMI Rejection

The TLV674x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the OPAx375 benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. 图 8-1

shows the results of this testing on the TLV674x. 表 8-1 shows the EMIRR IN+ values for the TLV674x at

particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational

Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op

amps and is available for download from www.ti.com.

120

100

10M

100M

Frequency (Hz)

10G

D039

图8-1. EMIRR Testing

表8-1. OPAx375 EMIRR IN+ for Frequencies of Interest

FREQUENCY

APPLICATION OR ALLOCATION

EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications

400 MHz

59.5 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

1.8 GHz

2.4 GHz

3.6 GHz

5 GHz

68.9 dB

77.8 dB

78.0 dB

88.8 dB

87.6 dB

GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

Radiolocation, aero communication and navigation, satellite, mobile, S-band

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz)

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

8.3.5 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress

(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the

output pin. Each of these different pin functions have electrical stress limits determined by the voltage

breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to

the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them

from accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. 图 8-2 shows an illustration of the ESD circuits contained in the OPAx375 (indicated by the dashed line

area). The ESD protection circuitry involves several current-steering diodes connected from the input and output

pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the

power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain

inactive during normal circuit operation.

TVS

R_F

+V_S

V_DD

OPAx990

100 Ω

R₁

R_S

INœ

IN+

Power-Supply

ESD Cell

R_L

I_D

V_IN

V_SS

œV_S

TVS

图8-2. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event

is long in duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit

ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).

During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit

(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.

Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if

activated in-circuit. A transient voltage suppressor (TVS) can be used to prevent against damage caused by

turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting

resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

The OPAx375 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins, as shown

above. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is

limited to 10 mA as stated in 节7.1. 图8-3 shows how a series input resistor may be added to the driven input to

limit the input current. The added resistor contributes thermal noise at the amplifier input and its value should be

kept to a minimum in noise-sensitive applications.

V+

I_OVERLOAD

10-mA max

V_OUT

Device

V_IN

5 kW

图8-3. Input Current Protection

8.3.6 Typical Specifications and Distributions

Designers often have questions about a typical specification of an amplifier in order to design a more robust

circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an

amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These

deviations often follow Gaussian ("bell curve"), or normal, distributions and circuit designers can leverage this

information to guardband their system, even when there is not a minimum or maximum specification in 节7.6.

0.00312% 0.13185%

0.13185% 0.00312%

0.00002%

2.145% 13.59% 34.13% 34.13% 13.59% 2.145%

1 1 1 1 1 1 1 1

ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1

ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61

ꢀ

图8-4. Ideal Gaussian Distribution

图 8-4 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma, is

the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-

thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the

mean (from µ–σto µ+σ).

Depending on the specification, values listed in the typical column of 节7.6 are represented in different ways. As

a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain bandwidth), then

the typical value is equal to the mean (µ). However, if a specification naturally has a mean near zero (like input

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in order to most

accurately represent the typical value.

You can use this chart to calculate approximate probability of a specification in a unit; for example, for OPA2375,

the typical input voltage offset is 150 µV, so 68.2% of all OPA2375 devices are expected to have an offset from

–150 µV to 150 µV.

Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits

will be removed from production material. For example, the OPA2375 device has a maximum offset voltage of

0.5 mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely,

TI assures that any unit with a larger offset than 0.5 mV will be removed from production material.

For specifications with no value in the minimum or maximum column, consider selecting a sigma value of

sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6-

σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an

option as a wide guardband to design a system around. In this case, the OPA2375 does not have a maximum or

minimum for offset voltage drift, but based on 图 7-40 and the typical value of 0.16 µV/°C in 节 7.6, it can be

calculated that the 6-σ value for offset voltage drift is about 0.96 µV/°C. When designing for worst-case system

conditions, this value can be used to estimate the worst possible offset across temperature without having an

actual minimum or maximum value.

However, process variation and adjustments over time can shift typical means and standard deviations, and

unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a

device. This information should be used only to estimate the performance of a device.

8.3.7 Shutdown Function

The OPAx375S devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In

this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active-low, meaning that

shutdown mode is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown

feature lies around 800 mV (typical) above the negative rail. Hysteresis has been included in the switching

threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins

should be driven with valid logic signals. A valid logic low is defined as a voltage between V–and V–+ 0.2 V. A

valid logic high is defined as a voltage between V–+ 1.2 V and V+. The shutdown pin must either be connected

to a valid high or a low voltage or driven, and not left as an open circuit. There is no internal pull-up to enable the

amplifier.

The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled, and

quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature

may be used to greatly reduce the average current and extend battery life. The enable time is 15 µs for full

shutdown of all channels; disable time is 3 µs. When disabled, the output assumes a high-impedance state. This

architecture allows the OPAx375S to be operated as a gated amplifier (or to have the device output multiplexed

onto a common analog output bus). Shutdown time (t_OFF) depends on loading conditions and increases as load

resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to

midsupply (V_S/ 2) is required. If using the OPAx375S without a load, the resulting turnoff time is significantly

increased.

8.3.8 Packages With an Exposed Thermal Pad

The OPAx375 family is available in packages such as the WSON-8 (DSG) which feature an exposed thermal

pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For

this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to

V– or left floating. Attaching the thermal pad to a potential other than V– is not allowed, and performance of

the device is not assured when doing so.

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

8.3.9 Common Mode Voltage Range

The input common-mode voltage range of the OPAx375 family extends to the negative rail and within 2 V of the

top rail for normal operation. However, this device can also operate with full rail-to-rail input 100 mV beyond the

top rail, but with reduced performance within 2 V of the top rail. The typical performance in this range is

summarized in for the OPA375. You can see the typical input offset voltage of the OPA2375/4375 in the 图 7-43

graph.

表8-2. OPA375 Typical Performance (V_S= 5 V, V_CM> V_S–1.2 V)

PARAMETER

MIN

TYP

MAX

UNIT

Offset voltage

Slew rate

1.5

V/µS

Input voltage noise density at f = 1 kHz

nV/√Hz

8.4 Device Functional Modes

The OPAx375 family has a single functional mode. The OPA2375 and OPA4375 are powered on as long as the

power-supply voltage is between 1.7 V (±0.85 V) and 5.5 V (±2.75 V). The OPA375 is powered on as long as the

power-supply voltage is between 2.25 V (±1.125 V) and 5.5 V (±2.75 V).

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The OPAx375 family features 10-MHz bandwidth and 4.75-V/µs slew rate with 890 µA (OPA375), 990 µA

(OPA2375/4375) of supply current per channel, providing good AC performance at low-power consumption. DC

applications are well served with a low input noise voltage of 3.5 nV/√ Hz (OPA2375/4375), 3.7 nV/√ Hz

(OPA375) at 10 kHz, low input bias current, and a typical input offset voltage of 0.15 mV.

9.2 Single-Supply Electret Microphone Preamplifier With Speech Filter

Electret microphones are commonly used in portable electronics because of the small size, low cost, and

relatively good signal-to-noise ratio (SNR). The small package size, low operating voltage and AC performance

of the OPA375 make the device a viable option for preamplifier circuits for electret microphones. The circuit

shown in 图9-1 is a single-supply preamplifier circuit for electret microphones.

3 V

R₁

200 kꢀ

R₁

2.2 kꢀ

3 V

Electret

Microphone

OPA375

V_OUT

C_G68 nF

R₂

200 kꢀ

R_F165 kꢀ

C_F3.3 nF

R_G

3.4 kꢀ

C_G68 nF

图9-1. Microphone Preamplifier

9.2.1 Design Requirements

The design requirements are as follows:

• Supply voltage: 3 V

• Input voltage: 7.93 mV_RMS(0.63 Pa with a –38-dB SPL microphone)

• Output: 1 V_RMS

• Bandwidth: 300 Hz to 3 kHz

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

9.2.2 Detailed Design Procedure

The transfer function defining the relationship between V_OUTand the AC input signal is shown in 方程式1.

≈

’

◊

= V

ì 1+

∆

OUT

IN _ AC

(1)

The required gain can be calculated based on the expected input signal level and desired output level as shown

in 方程式2.

V_OUT

1V_RMS

G_OPA

=126

V_{IN _ AC}7.93mV_RMS

(2)

Select a standard 10-kΩfeedback resistor and calculate R_Gfrom 方程式3.

R_F

10kW

126 -1

R_G=

= 80W ç 78.7W (closest standard value)

G_OPA-1

(3)

To minimize the attenuation in the desired passband from 300 Hz to 3 kHz, set the upper (f_H) and lower (f_L) cutoff

frequencies outside of the desired bandwidth as:

f_L= 200 Hz

(4)

and

f_H= 5 kHz

(5)

Select C_Gto set the f_Lcutoff frequency using 方程式6.

C_G=

= 10.11mF ç10mF

2ìp ì R_Gì f_L2ìp ì 78.7Wì 200Hz

(6)

(7)

Select C_Fto set the f_Hcutoff frequency using 方程式7.

C_F=

= 3.18nF ç 3.3nF (Standard Value)

2ì

ì R_Fì f_H2ì

ì10kWì5kHz

The input signal cutoff frequency must be set low enough such that low-frequency sound waves still pass

through. Therefore select C_INto achieve a 30-Hz cutoff frequency (f_IN) using 方程式8.

C_IN=

= 53nF ç 68nF (Standard Value)

2ì

ì(R || R₂)ì f_IN2ì

ì100kWì30Hz

(8)

The measured transfer function for the microphone preamplifier circuit is shown in 图9-2 and the measured THD

+ N performance of the microphone preamplifier circuit is shown in 图9-3.

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

9.2.3 Application Curves

œ20

œ40

œ60

œ80

œ10

200

2000

Frequency (Hz)

20000

0.005

0.05

0.5

RMS Output Voltage (V)

C039

C040

图9-2. Gain vs Frequency

图9-3. THD + N vs RMS Output Voltage

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

10 Power Supply Recommendations

The OPA2375 and OPA4375 devices are specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V). The

OPA375 device is specified for operation from 2.25 V to 5.5 V (±1.125 V to ±2.75 V). Many specifications of the

OPAx375 family apply from –40°C to 125°C.

CAUTION

Supply voltages larger than 7 V can permanently damage the device (see 节7.1).

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, see 节11.1.

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational

amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds, paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than

crossing in parallel with the noisy trace.

• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting

input minimizes parasitic capacitance, as shown in 图11-1.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

11.2 Layout Example

GND

OUTPUT

V-

GND

图11-1. Operational Amplifier Board Layout for Noninverting Configuration

V-

INPUT

OUTPUT

OPA375

V+

图11-2. Layout Example Schematic

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

GND

V+

INPUT A

OUTPUT B

V-

GND

图11-3. Example Layout for VSSOP-8 (DGK) Package

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, QFN/SON PCB Attachment

• Texas Instruments, Quad Flatpack No-Lead Logic Packages

• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

OPA375, OPA2375

ZHCSH34E –NOVEMBER 2017 –REVISED AUGUST 2021

www.ti.com.cn

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: OPA375 OPA2375

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

9-Sep-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

OPA2375IDDFR

OPA2375IDGKR

OPA2375IDR

ACTIVE SOT-23-THIN

DDF

DGK

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2000 RoHS & Green

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

-40 to 125

O75D

2J8T

ACTIVE

VSSOP

SOIC

NIPDAU

NIPDAUAG

NIPDAU

O2375D

O75D

O2375P

HIF

OPA2375IDSGR

OPA2375IPWR

OPA2375SIRUGR

OPA375IDCKR

OPA375IDCKT

WSON

TSSOP

X2QFN

SC70

DSG

RUG

DCK

19W

SC70

250

RoHS & Green

19W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

9-Sep-2021

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OPA2375IDDFR

SOT-23-

THIN

DDF

3000

180.0

8.4

3.2

1.4

4.0

8.0

OPA2375IDGKR

OPA2375IDR

VSSOP

SOIC

DGK

2500

3000

2000

3000

250

330.0

180.0

330.0

178.0

12.4

8.4

5.3

6.4

2.3

7.0

1.75

2.4

3.4

5.2

2.3

3.6

2.25

2.5

1.4

2.1

8.0

4.0

8.0

4.0

12.0

8.0

OPA2375IDSGR

OPA2375IPWR

OPA2375SIRUGR

OPA375IDCKR

OPA375IDCKT

WSON

TSSOP

X2QFN

SC70

DSG

1.15

1.6

12.4

8.4

12.0

8.0

RUG

DCK

0.56

1.2

9.0

8.0

SC70

9.0

1.2

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

OPA2375IDDFR

OPA2375IDGKR

OPA2375IDR

SOT-23-THIN

VSSOP

SOIC

DDF

DGK

3000

2500

3000

2000

3000

250

210.0

366.0

356.0

210.0

356.0

205.0

190.0

185.0

364.0

356.0

185.0

356.0

200.0

190.0

35.0

50.0

35.0

33.0

30.0

OPA2375IDSGR

OPA2375IPWR

OPA2375SIRUGR

OPA375IDCKR

OPA375IDCKT

WSON

TSSOP

X2QFN

SC70

DSG

RUG

DCK

SC70

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

0.32

0.18

PIN 1 INDEX AREA

2.1

1.9

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8

0.7

SEATING PLANE

0.05

0.00

SIDE WALL

0.08 C

METAL THICKNESS

DIM A

OPTION 1

0.1

OPTION 2

0.2

EXPOSED

THERMAL PAD

(DIM A) TYP

0.9 0.1

6X 0.5

1.5

1.6 0.1

0.32

0.18

PIN 1 ID

(45 X 0.25)

0.4

0.2

0.1

C A B

0.05

4218900/E 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

8X (0.25)

(0.55)

SYMM

(1.6)

6X (0.5)

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/E 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

SYMM

8X (0.25)

(0.45)

SYMM

(0.7)

6X (0.5)

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/E 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

6X 0.65

3.1

2.9

NOTE 3

1.95

0.30

0.19

4.5

4.3

1.2 MAX

0.1

C A

NOTE 4

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 - 8

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

8X (0.45)

(R0.05)

TYP

SYMM

6X (0.65)

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

(R0.05) TYP

8X (0.45)

SYMM

6X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DCK0005A

SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR

2.4

1.8

0.1 C

1.4

1.1

1.1 MAX

PIN 1

INDEX AREA

NOTE 4

(0.15)

(0.1)

2X 0.65

1.3

2.15

1.85

1.3

0.33

0.23

0.1

0.0

(0.9)

TYP

0.1

C A B

0.15

0.22

0.08

GAGE PLANE

TYP

0.46

0.26

TYP

SEATING PLANE

4214834/C 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-203.

4. Support pin may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DCK0005A

SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR

PKG

5X (0.95)

5X (0.4)

SYMM

(1.3)

2X (0.65)

(R0.05) TYP

(2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214834/C 03/2023

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DCK0005A

SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR

PKG

5X (0.95)

5X (0.4)

SYMM

(1.3)

2X(0.65)

(R0.05) TYP

(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:18X

4214834/C 03/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

6X 0.65

2.95

2.85

NOTE 3

1.95

0.38

0.22

0.1

C A B

1.65

1.55

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/C 10/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

8X (0.45)

SYMM

6X (0.65)

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/C 10/2022

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8X (0.45)

SYMM

6X (0.65)

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/C 10/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

OPA375IDCKR [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E