OPA381AIDGKR [TI]
精确低功耗高速互阻抗放大器 | DGK | 8 | -40 to 125;
| 型号： | OPA381AIDGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 精确低功耗高速互阻抗放大器 | DGK | 8 | -40 to 125 放大器 |
| 文件： | 总25页 (文件大小：837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA381
OPA2381
SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
Precision, Low Power, 18MHz
Transimpedance Amplifier
FD EATURES
DESCRIPTION
OVER 250kHz TRANSIMPEDANCE
BANDWIDTH
The OPA381 family of transimpedance amplifiers provides
18MHz of Gain Bandwidth (GBW), with extremely high
precision, excellent long-term stability, and very low 1/f noise.
The OPA381 features an offset voltage of 25µV (max), offset
drift of 0.1µV/°C (max), and bias current of 3pA. The OPA381
far exceeds the offset, drift, and noise performance that
conventional JFET op amps provide.
D
D
D
D
D
D
D
D
D
D
D
D
DYNAMIC RANGE: 5 Decades
EXCELLENT LONG-TERM STABILITY
LOW VOLTAGE NOISE: 10nV/√Hz
BIAS CURRENT: 3pA
OFFSET VOLTAGE: 25µV (max)
OFFSET DRIFT: 0.1µV/°C (max)
GAIN BANDWIDTH: 18MHz
QUIESCENT CURRENT: 800µA
FAST OVERLOAD RECOVERY
SUPPLY RANGE: 2.7V to 5.5V
SINGLE AND DUAL VERSIONS
MicroPACKAGE: DFN-8, MSOP-8
The signal bandwidth of a transimpedance amplifier depends
largely on the GBW of the amplifier and the parasitic
capacitance of the photodiode, as well as the feedback
resistor. The 18MHz GBW of the OPA381 enables a trans-
impedance bandwidth of > 250kHz in most configurations.
The OPA381 is ideally suited for fast control loops for power
level measurement on an optical fiber.
As a result of the high precision and low-noise characteristics
of the OPA381, a dynamic range of 5 decades can be
achieved. This capability allows the measurement of signal
currents on the order of 10nA, and up to 1mA in a single I/V
conversion stage. In contrast to logarithmic amplifiers, the
OPA381 provides very wide bandwidth throughout the full
dynamic range. By using an external pulldown resistor to
–5V, the output voltage range can be extended to include 0V.
AD PPLICATIONS
PRECISION I/V CONVERSION
D
D
D
D
PHOTODIODE MONITORING
OPTICAL AMPLIFIERS
CAT-SCANNER FRONT-END
PHOTO LAB EQUIPMENT
The OPA381 and OPA2381 are both available in MSOP-8
and DFN-8 (3mm x 3mm) packages. They are specified
from –40°C to +125°C.
RF
+5V
7
OPA381 RELATED DEVICES
OPA381
V
PRODUCT
FEATURES
2
OUT
(0V to 4.4V)
6
90MHz GBW, 2.7V to 5.5V Supply
Transimpedance Amplifier
OPA380
CDIODE
RP
OPA132
OPA300
OPA335
OPA350
OPA354
OPA355
OPA656/7
16MHz GBW, Precision FET Op Amp 15V
150MHz GBW, Low-Noise, 2.7V to 5.5V Supply
Photodiode
(Optional
Pulldown
Resistor)
65pF
Ω
1M
10µV V , Zero-Drift, 2.5V to 5V Supply
OS
−
5V
500µV V , 38MHz, 2.5V to 5V Supply
OS
Ω
100k
100MHz GBW CMOS, RRIO, 2.5V to 5V Supply
200MHz GBW CMOS, 2.5V to 5V Supply
230MHz, Precision FET, 5V
3
75pF
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2004, Texas Instruments Incorporated
www.ti.com
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
(1)
ELECTROSTATIC DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
(2)
Signal Input Terminals , Voltage . . . . . (V−) −0.5V to (V+) + 0.5V
Current . . . . . . . . . . . . . . . . . . . . . 10mA
. . . . . . . . . . . . . . . . . . . . . . . . Continuous
(3)
Short-Circuit Current
proper handling and installation procedures can cause damage.
Operating Temperature Range . . . . . . . . . . . . . . . −40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
OPA381 ESD Rating (Human Body Model) . . . . . . . . . . . . . . . 2000V
OPA2381 ESD Rating (Human Body Model) . . . . . . . . . . . . . . 1500V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2)
(3)
Input terminals are diode clamped to the power-supply rails. Input
signals that can swing more than 0.5V beyond the supply rails
should be current limited to 10mA or less.
Short-circuit to ground; one amplifier per package.
(1)
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA381AIDGKT
OPA381AIDGKR
OPA381AIDRBT
OPA381AIDRBR
OPA2381AIDGKT
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
OPA381
OPA381
OPA2381
OPA2381
MSOP-8
DFN-8
DGK
DRB
DGK
DRB
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
A64
A65
A62
A63
MSOP-8
DFN-8
OPA2381AIDGKR Tape and Reel, 2500
OPA2381AIDRBT Tape and Reel, 250
OPA2381AIDRBR Tape and Reel, 3000
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
PIN ASSIGNMENTS
Top View
OPA381
OPA381
NC(1)
V+
NC(1)
V+
NC(1)
1
2
3
4
8
7
6
5
NC(1)
1
2
3
4
8
7
6
5
Exposed
Thermal
Die Pad
on
−
−
In
In
Out
Out
+In
+In
Underside
−
NC(1)
−
NC(1)
V
V
DFN−8
MSOP−8
NOTE: (1) NC indicates no internal connection.
OPA2381
OPA2381
V+
V+
Out A
1
8
Out A
1
2
3
4
8
7
6
5
Exposed
Thermal
Die Pad
on
−
Out B
−
In A
In A
2
3
4
7
6
5
Out B
−
−
In B
+In A
In B
+In B
+In A
Underside
−
−
+In B
V
V
MSOP−8
DFN−8
2
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS: V = +2.7V to +5.5V
S
Boldface limits apply over the temperature range, T = −40°C to +125°C.
A
All specifications at T = +25°C, R = 10kΩ connected to V /2, and V
= V /2, unless otherwise noted.
A
L
S
OUT
S
OPA381
TYP
MIN
MAX
PARAMETER
CONDITION
UNITS
OFFSET VOLTAGE
Input Offset Voltage
Drift
V
V
= +5V, V
= 0V
7
25
0.1
20
20
µV
OS
S CM
dV /dT
0.03
3.5
µV/°C
µV/V
µV/V
OS
vs Power Supply
PSRR
V
= +2.7V to +5.5V, V
= 0V
S
CM
Over Temperature
V
= +2.7V to +5.5V, V
= 0V
S
CM
(1)
Long-Term Stability
See Note (1)
1
Channel Separation, dc
µV/V
INPUT BIAS CURRENT
Input Bias Current
I
V
V
= V /2
3
50
pA
pA
B
CM
S
Over Temperature
Input Offset Current
See Typical Characteristics
I
= V /2
6
100
OS
CM
S
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz
Input Voltage Noise Density, f = 10kHz
Input Voltage Noise Density, f > 1MHz
Input Current Noise Density, f = 10kHz
e
e
e
i
V
V
V
V
= +5V, V
= +5V, V
= +5V, V
= +5V, V
= 0V
= 0V
= 0V
= 0V
3
µV
PP
n
n
n
n
S
S
S
S
CM
CM
CM
CM
70
10
20
nV/√Hz
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
V
V−
(V+) − 1.8V
V
CM
CMRR
V
= +5V, (V−) < V
CM
< (V+) − 1.8V
95
110
dB
S
INPUT IMPEDANCE
Differential Capacitance
1
pF
Ω || pF
13
Common-Mode Resistance and Capacitance
10 || 2.5
OPEN-LOOP GAIN
Open-Loop Voltage Gain
A
0.05V < V < (V+) − 0.6V, V
CM
= V /2, V = 5V
110
106
135
135
dB
dB
OL
O
S
S
(2)
0V < V < (V+) − 0.6V, V = 0V, R = 10kΩ to −5V , V = 5V
O
CM
P
S
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
GBW
SR
18
12
7
MHz
V/µs
µs
µs
ns
G = +1
(3)
Settling Time, 0.0015%
V
= +5V, 4V Step, G = +1, OPA381
= +5V, 4V Step, G = +1, OPA2381
S
(3)
Settling Time, 0.003%
V
7
S
(4), (5)
Overload Recovery Time
V
• G = > V
200
IN
S
OUTPUT
Voltage Output Swing from Positive Rail
Voltage Output Swing from Negative Rail
Voltage Output Swing from Positive Rail
Voltage Output Swing from Negative Rail
Output Current
R
R
= 10kΩ
= 10kΩ
400
30
600
50
mV
mV
mV
mV
mA
mA
L
L
(2)
(2)
R
R
= 10kΩ to −5V
= 10kΩ to −5V
400
−20
10
600
0
P
P
I
OUT
I
Short-Circuit Current
20
SC
LOAD
Capacitive Load Drive
C
See Typical Characteristics
250
Open-Loop Output Impedance
R
F = 1MHz, I = 0
Ω
O
O
POWER SUPPLY
Specified Voltage Range
Quiescent Current (per amplifier)
Over Temperature
V
2.7
5.5
1
V
S
I
I
= 0A
0.8
mA
mA
Q
O
1.1
TEMPERATURE RANGE
Specified and Operating Range
Storage Range
−40
−65
+125
+150
°C
°C
Thermal Resistance
MSOP-8
q
JA
150
65
°C/W
°C/W
DFN-8
(1)
(2)
High temperature operating life characterization of zero-drift op amps applying the techniques used in the OPA381 have repeatedly demonstrated randomly
distributed variation approximately equal to measurement repeatability of 1µV. This consistency gives confidence in the stability and repeatability of these zero-
drift techniques.
Tested with output connected only to R , a pulldown resistor connected between V
P
and −5V, as shown in Figure 3. See also Applications section, Achieving
OUT
Output Swing to Negative Rail.
Transimpedance frequency of 250kHz.
Time required to return to linear operation.
From positive rail.
(3)
(4)
(5)
3
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = +2.7V to +5.5V
S
All specifications at T = +25°C, R = 10kΩ connected to V /2, and V
OUT
= V /2, unless otherwise noted.
S
A
L
S
POWER−SUPPLY REJECTION RATIO AND
COMMON−MODE REJECTION vs FREQUENCY
OPEN−LOOP GAIN AND PHASE vs FREQUENCY
Phase
140
120
100
80
200
150
100
50
140
120
100
80
PSRR
60
60
0
40
20
−
−
−
−
40
50
Gain
0
20
100
150
200
CMRR
−
−
−
20
40
60
0
−
20
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
PHASE MARGIN vs LOAD CAPACITANCE
QUIESCENT CURRENT vs TEMPERATURE
90
80
70
60
50
40
30
20
10
1.00
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
Ω
RS = 100
100pF
Ω
50k
5.5V
2.7V
RS
CL
Ω
RS = 50
Ω
RS = 0
0
100 200 300 400 500 600 700 800 900 1000
CL Load Capacitance (pF)
−
−
40 25
0
25
50
75
100
125
_
Temperature ( C)
QUIESCENT CURRENT vs SUPPLY VOLTAGE
INPUT BIAS CURRENT vs TEMPERATURE
1.00
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
1000
100
10
1
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
−
−
40 25
0
25
50
75
100
125
Supply Voltage (V)
_
Temperature ( C)
4
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = +2.7V to +5.5V (continued)
S
All specifications at T = +25°C, R = 10kΩ connected to V /2, and V
= V /2, unless otherwise noted.
S
A
L
S
OUT
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
INPUT BIAS CURRENT
(VS = 5.5V)
vs COMMON−MODE VOLTAGE
(V+)
50
40
30
20
10
0
−
−
(V+)
(V+)
1
2
−
IB
_
+125 C
+25°C
−
(V ) + 2
−
10
20
30
40
50
+
IB
−
−
−
−
−
_
40 C
−
(V ) + 1
−
(V )
0
5
10
15
20
25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Output Current (mA)
Common−Mode Voltage (V)
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(VS = 2.7V)
(V+)
−
(V+) 0.35
−
(V+) 0.70
−
(V+) 1.05
−
(V+) 1.40
_
+125 C
_
+25 C
−
(V ) + 1.40
−
_
40 C
−
(V ) + 1.05
−
(V ) + 0.70
−
(V ) + 0.35
−
(V )
0
5
10
15
20
25
Output Current (mA)
µ
_
Offset Voltage Drift ( V/ C)
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
GAIN BANDWIDTH vs POWER SUPPLY VOLTAGE
20
19
18
17
16
15
14
13
12
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power Supply Voltage (V)
µ
Offset Voltage ( V)
5
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = +2.7V to +5.5V (continued)
S
All specifications at T = +25°C, R = 10kΩ connected to V /2, and V
OUT
= V /2, unless otherwise noted.
S
A
L
S
TRANSIMPEDANCE AMP CHARACTERISTIC
CDIODE = 100pF
150
140
130
120
110
100
90
80
70
60
Circuit for Transimpedance Amplifier Characteristic curves on this page.
R
= 10MΩ
CF
C
= 0.5pF
F
F
C
F
= 1pF
= 4pF
Ω
= 1M
R
F
RF
C
F
R
= 100kΩ
= 10kΩ
F
CSTRAY
C
= 12pF
R
F
F
50
40
30
20
OPA381
C
(parasitic) = 0.2pF
STRAY
CDIODE
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
100M
100M
TRANSIMPEDANCE AMP CHARACTERISTIC
150
TRANSIMPEDANCE AMP CHARACTERISTIC
150
140
130
120
110
100
90
C
= 50pF
C
= 20pF
140
130
120
110
100
90
80
70
60
DIODE
DIODE
R
= 10MΩ
Ω
R
= 10M
F
F
C
= 1pF
Ω
= 1M
R
Ω
= 1M
R
F
F
F
C
= 0.5pF
F
C
= 3pF
F
R
= 100kΩ
= 10kΩ
Ω
R
= 100k
C
= 2pF
= 5pF
F
F
F
80
C
= 8pF
70
R
Ω
R
= 10k
F
F
F
C
60
50
40
F
50
40
30
30
20
C
(parasitic) = 0.2pF
20
STRAY
C
(parasitic) = 0.2pF
STRAY
10
10
100
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
1k
10k
100k
Frequency (Hz)
1M
10M
TRANSIMPEDANCE AMP CHARACTERISTIC
TRANSIMPEDANCE AMP CHARACTERISTIC
150
140
130
120
110
100
90
150
140
130
120
110
100
90
C
= 1pF
C
= 10pF
DIODE
DIODE
Ω
R
= 10M
Ω
= 10M
R
F
F
Ω
R
= 1M
Ω
= 1M
R
F
F
C
= 0.5pF
F
C
= 0.5pF
F
Ω
R
= 100k
Ω
R
= 100k
C
= 2pF
F
F
F
80
80
70
70
Ω
= 10k
Ω
R
R
= 10k
F
F
C
= 2pF
60
50
40
30
60
50
F
C
= 4pF
F
40
30
20
C
(parasitic) = 0.2pF
STRAY
20
C
(parasitic) = 0.2pF
STRAY
10
10
100
100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
6
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = +2.7V to +5.5V (continued)
S
All specifications at T = +25°C, and R = 10kΩ connected to V /2, unless otherwise noted.
A
L
S
LARGE−SIGNAL STEP RESPONSE
(with pull−down)
SMALL−SIGNAL STEP RESPONSE
(with or without pull−down)
200kHz (CF = 16pF)
1MHz
(CF = 3pF)
C
F
3pF
Ω
50k
Ω
50k
OPA381
OPA381
Ω
10k
10kΩ
−5V
V
−
VP = 0V or 5V
P
Time (100ns/div)
Time (100ns/div)
OVERLOAD RECOVERY
LARGE−SIGNAL STEP RESPONSE
(without pull−down)
6
4
40pF
VOUT
20kΩ
200kHz
(CF = 16pF)
250µA
OPA381
1MHz
(CF = 3pF)
IIN
10kΩ
2
Nonlinear Linear
VP
Operation Operation
C
F
0
Ω
50k
OPA381
0.8
0
OPA381
OPA2381
IIN
−
VP = 0V or 5V
Ω
10k
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
Time (100ns/div)
CHANNEL SEPARATION vs INPUT FREQUENCY
INPUT VOLTAGE NOISE SPECTRAL DENSITY
160
140
120
100
80
1000
100
10
OPA2381
60
40
20
0
−
−
20
40
1
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
Input Frequency (Hz)
Frequency (Hz)
7
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
OPERATING VOLTAGE
APPLICATIONS INFORMATION
BASIC OPERATION
OPA381 series op amps are fully specified from 2.7V to
5.5V over a temperature range of −40°C to +125°C.
Parameters that vary significantly with operating
voltages or temperature are shown in the Typical
Characteristics.
The OPA381 is a high-precision transimpedance
amplifier with very low 1/f noise. Due to its unique
architecture, the OPA381 has excellent long-term input
voltage offset stability.
The OPA381 performance results from an internal
auto-zero amplifier combined with a high-speed
amplifier. The OPA381 has been designed with circuitry
to improve overload recovery and settling time over that
achieved by a traditional composite approach. It has
been specifically designed and characterized to
accommodate circuit options to allow 0V output
operation (see Figure 3).
INTERNAL OFFSET CORRECTION
The OPA381 series op amps use an auto-zero topology
with a time-continuous 18MHz op amp in the signal
path. This amplifier is zero-corrected every 100µs using
a proprietary technique. Upon power-up, the amplifier
requires approximately 400µs to achieve specified V
OS
accuracy, which includes one full auto-zero cycle of
approximately 100µs and the start-up time for the bias
circuitry. Prior to this time, the amplifier will function
properly but with unspecified offset voltage.
The OPA381 is used in inverting configurations, with the
noninverting input used as a fixed biasing point.
Figure 1 shows the OPA381 in a typical configuration.
Power-supply pins should be bypassed with 1µF
ceramic or tantalum capacitors. Electrolytic capacitors
are not recommended.
This design has virtually no aliasing and low noise. Zero
correction occurs at a 10kHz rate, but there is virtually
no fundamental noise energy present at that frequency
due to internal filtering. For all practical purposes, any
glitches have energy at 20MHz or higher and are easily
filtered, if necessary. Most applications are not sensitive
to such high-frequency noise, and no filtering is
required.
CF
RF
INPUT VOLTAGE
+5V
µ
1 F
The input common-mode voltage range of the OPA381
series extends from V− to (V+) –1.8V. With input signals
above this common-mode range, the amplifier will no
longer provide a valid output value, but it will not latch
or invert.
λ
(1)
VOUT
(0.5V to 4.4V)
OPA381
VBIAS = 0.5V
INPUT OVERVOLTAGE PROTECTION
NOTE: (1) VOUT = 0.5V in dark conditions.
Device inputs are protected by ESD diodes that will
conduct if the input voltages exceed the power supplies
by more than approximately 500mV. Momentary
voltages greater than 500mV beyond the power supply
can be tolerated if the current is limited to 10mA. The
OPA381 family features no phase inversion when the
inputs extend beyond supplies if the input is current
limited.
Figure 1. OPA381 Typical Configuration
8
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
OUTPUT RANGE
ACHIEVING OUTPUT SWING TO GROUND
The OPA381 is specified to swing within at least 600mV
of the positive rail and 50mV of the negative rail with a
10kΩ load while maintaining good linearity. Swing to the
negative rail while maintaining linearity can be extended
to 0V—see the section, Achieving Output Swing to
Ground. See the Typical Characteristic curve, Output
Voltage Swing vs Output Current.
Some applications require output voltage swing from
0V to a positive full-scale voltage (such as +4.096V)
with excellent accuracy. With most single-supply op
amps, problems arise when the output signal
approaches 0V, near the lower output swing limit of a
single-supply op amp. A good single-supply op amp
may swing close to single-supply ground, but will not
reach 0V.
The OPA381 can swing slightly closer than specified to
the positive rail; however, linearity will decrease and a
high-speed overload recovery clamp limits the amount
of positive output voltage swing available—see
Figure 2.
The output of the OPA381 can be made to swing to 0V,
or slightly below, on a single-supply power source. This
extended output swing requires the use of another
resistor and an additional negative power supply. A
pulldown resistor may be connected between the
output and the negative supply to pull the output down
to 0V; see Figure 3.
25
VS = 5.5V
20
15
10
5
RF
0
λ
V+ = +5V
−
5
−
10
15
20
25
OPA381
VOUT
−
−
−
Ω
−
RP = 10k to 5V
Ω
RL = 10k to VS/2
Ω
RP = 10k
−
V
= Gnd
−
1
0
1
2
3
4
5
6
VOUT (V)
−
=
VS
RP
µ
−
−
VS = 5V
500 A
Negative Supply
Figure 2. Effect of High-Speed Overload
Recovery Clamp on Output Voltage
Figure 3. Amplifier with Pull-Down Resistor to
Achieve V = 0V
OUT
OVERLOAD RECOVERY
The OPA381 has been designed to prevent output
saturation. After being overdriven to the positive rail, it
will typically require only 200ns to return to linear
operation. The time required for negative overload
recovery is greater, unless a pulldown resistor
connected to a more negative supply is used to extend
the output swing all the way to the negative rail—see the
following section, Achieving Output Swing to Ground.
The OPA381 has an output stage that allows the output
voltage to be pulled to its negative supply rail using this
technique. However, this technique only works with
some types of output stages. The OPA381 has been
designed to perform well with this method. Accuracy is
excellent down to 0V. Reliable operation is assured over
the specified temperature range.
9
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
D
D
the desired transimpedance gain (R );
BIASING PHOTODIODES IN SINGLE-SUPPLY
CIRCUITS
F
the Gain Bandwidth Product (GBW) for the
OPA381 (18MHz).
The +IN input can be biased with a positive DC voltage
to offset the output voltage and allow the amplifier
output to indicate a true zero photodiode measurement
when the photodiode is not exposed to any light. It will
also prevent the added delay that results from coming
out of the negative rail. This bias voltage appears
across the photodiode, providing a reverse bias for
faster operation. An RC filter placed at this bias point will
reduce noise. (Refer to Figure 4.) This bias voltage can
also serve as an offset bias point for an ADC with range
that does not include ground.
With these three variables set, the feedback capacitor
value (C ) can be set to control the frequency response.
C
F
is the stray capacitance of R , which is 0.2pF for
STRAY
F
a typical surface-mount resistor.
To achieve a maximally flat 2nd-order Butterworth
frequency response, the feedback pole should be set
to:
GBW
4pRFCTOT
1
+
Ǹ
ǒ
STRAYǓ
2pRF CF ) C
(1)
Bandwidth is calculated by:
(1)
CF
GBW
2pRFCTOT
< 1pF
f*3dB
+
Hz
Ǹ
(2)
RF
These
equations
will
result
in
maximum
Ω
10M
transimpedance bandwidth. For even higher
transimpedance bandwidth, the high-speed CMOS
OPA380 (90MHz GBW), the OPA300 (150MHz GBW),
or the OPA656 (230MHz GBW) may be used.
V+
ID
λ
OPA381
For additional information, refer to Application Bulletin
AB−050 (SBOA055), Compensate Transimpedance
Amplifiers Intuitively, available for download at
www.ti.com.
VOUT = IDRF + VBIAS
µ
0.1 F
Ω
100k
+VBIAS
−
[0V to (V+) 1.8V]
(1)
CF
NOTE: (1) CF is optional to prevent gain peaking.
It includes the stray capacitance of RF.
RF
Ω
10M
Figure 4. Photodiode with Filtered Reverse Bias
Voltage
(2)
CSTRAY
+5V
TRANSIMPEDANCE AMPLIFIER
λ
Wide bandwidth, low input bias current and low input
voltage and current noise make the OPA381 an ideal
wideband photodiode transimpedance amplifier. Low
voltage noise is important because photodiode
capacitance causes the effective noise gain of the
circuit to increase at high frequency.
(3)
OPA381
VOUT
CTOT
R
P (optional
pulldown resistor)
−
5V
The key elements to a transimpedance design are
shown in Figure 5:
NOTE: (1) CF is optional to prevent gain peaking.
(2) CSTRAY is the stray capacitance of RF
(typically, 0.2pF for a surface−mount resistor).
(3) CTOT is the photodiode capacitance plus OPA381
input capacitance.
D
the total input capacitance (C
), consisting of the
) plus the parasitic
TOT
photodiode capacitance (C
DIODE
common-mode and differential-mode input
capacitance (2.5pF + 1pF for the OPA381);
Figure 5. Transimpedance Amplifier
10
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
TRANSIMPEDANCE BANDWIDTH AND
NOISE
R
= 50kΩ
(a)
F
Limiting the gain set by R can decrease the noise
F
CSTRAY = 0.2pF
occurring at the output of the transimpedance circuit.
However, all required gain should occur in the
transimpedance stage, since adding gain after the
transimpedance amplifier generally produces poorer
noise performance. The noise spectral density
λ
OPA381
VOUT
produced by R increases with the square-root of R ,
F
F
whereas the signal increases linearly. Therefore,
signal-to-noise ratio is improved when all the required
gain is placed in the transimpedance stage.
VBIAS
Total noise increases with increased bandwidth. Limit
the circuit bandwidth to only that required. Use a
R
= 50kΩ
(b)
F
capacitor, C , across the feedback resistor, R , to limit
F
F
bandwidth (even if not required for stability), if total
output noise is a concern.
CSTRAY = 0.2pF
CF = 16pF
Figure 6a shows the transimpedance circuit without any
feedback capacitor. The resulting transimpedance gain
of this circuit is shown in Figure 7. The –3dB point is
λ
approximately 3MHz. Adding
a 16pF feedback
OPA381
VOUT
capacitor (Figure 6b) will limit the bandwidth and result
in a –3dB point at approximately 200kHz (seen in
Figure 7). Output noise will be further reduced by
VBIAS
adding a filter (R
and C
) to create a second
FILTER
FILTER
pole (Figure 6c). This second pole is placed within the
feedback loop to maintain the amplifier’s low output
impedance. (If the pole was placed outside the
feedback loop, an additional buffer would be required
and would inadvertently increase noise and dc error).
R
= 50kΩ
(c)
F
CSTRAY = 0.2pF
Using R
resistance, and C
plus OPA381 input capacitance, the noise zero, f , is
to represent the equivalent diode
DIODE
C
= 22pF
for equivalent diode capacitance
F
TOT
Z
R
FILTER
= 102kΩ
calculated by:
λ
ǒ
Ǔ
OPA381
VOUT
FILTER
RDIODE ) RF
fZ
+
C
ǒ
Ǔ
2pRDIODERF CTOT ) CF
(3)
= 3.9nF
VBIAS
Figure 6. Transimpedance Circuit Configurations
with Varying Total and Integrated Noise Gain
11
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
120
500
400
300
200
100
0
CDIODE = 10pF
See Figure 6a
CDIODE = 10pF
100
80
60
40
20
0
−
3dB at 200kHz
µ
310 Vrms
See Figure 6c
See Figure 6a
µ
68 Vrms
See Figure 6b
µ
25 Vrms
See Figure 6c
See Figure 6b
1M 10M 100M
−
20
100
1k
10k
100k
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 7. Transimpedance Gains for Circuits in
Figure 6
Figure 9. Integrated Output Noise for Circuits in
Figure 6
Figure 10 shows the effects of diode capacitance on
integrated output noise, using the circuit in Figure 6c.
The effects of these circuit configurations on output
noise are shown in Figure 8 and on integrated output
noise in Figure 9. A 2-pole Butterworth filter (maximally
flat in passband) is created by selecting the filter values
using the equation:
For additional information, refer to Noise Analysis of
FET Transimpedance Amplifiers (SBOA060), and
Noise Analysis for High Speed Op Amps (SBOA066),
available for download from the TI web site.
CFRF + 2CFILTERRFILTER
(4)
The circuit in Figure 6b rolls off at 20dB/decade. The
circuit with the additional filter shown in Figure 6c rolls
off at 40dB/decade, resulting in improved noise
performance.
60
CDIODE
= 100pF
µ
56 Vrms
50
40
30
20
10
0
CDIODE
= 50pF
µ
37 Vrms
CDIODE
= 20pF
µ
28 Vrms
400
CDIODE = 10pF
CDIODE
= 1pF
µ
25 Vrms
See Figure 6c
300
CDIODE
= 10pF
µ
23 Vrms
See Figure 6a
200
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
100
See Figure 6b
Figure 10. Integrated Output Noise for Various
Values of C for Circuit in Figure 6c
See Figure 6c
1k 10k
DIODE
0
100
100k
1M
10M
100M
Frequency (Hz)
Figure 8. Output Noise for Circuits in Figure 6
12
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
BOARD LAYOUT
CAPACITIVE LOAD AND STABILITY
Minimize photodiode capacitance and stray
capacitance at the summing junction (inverting input).
This capacitance causes the voltage noise of the op
amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to
reverse-bias a photodiode can significantly reduce its
capacitance. Smaller photodiodes have lower
capacitance. Use optics to concentrate light on a small
photodiode.
The OPA381 series op amps can drive greater than
100pF pure capacitive load. Increasing the gain
enhances the amplifier’s ability to drive greater
capacitive loads. See the Phase Margin vs Load
Capacitance typical characteristic curve.
One method of improving capacitive load drive in the
unity-gain configuration is to insert a 10Ω to 20Ω
resistor inside the feedback loop, as shown in
Figure 12. This reduces ringing with large capacitive
loads while maintaining DC accuracy.
Circuit board leakage can degrade the performance of
an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that
encircles the summing junction and is driven at the
same voltage can help control leakage. See Figure 11.
RF
(3)
CF
RF
V+
RS
λ
Ω
20
λ
VOUT
OPA381
OPA381
VOUT
(1)
VB
CL
RL
V−
Guard ring
(2)
VPD
NOTES: (1) VB = GND or pedestal voltage to reverse bias the photodiode.
Figure 11. Connection of Input Guard
(2) VPD = GND or −5V.
≥
(3) CF x RF 2CL x RS.
OTHER WAYS TO MEASURE SMALL
CURRENTS
Figure 12. Series Resistor in Unity-Gain Buffer
Configuration Improves Capacitive Load Drive
Logarithmic amplifiers are used to compress extremely
wide dynamic range input currents to a much narrower
range. Wide input dynamic ranges of 8 decades, or
100pA to 10mA, can be accommodated for input to a
12-bit ADC. (Suggested products: LOG101, LOG102,
LOG104, LOG112.)
DRIVING 16-BIT ANALOG-TO-DIGITAL
CONVERTERS (ADC)
The OPA381 series is optimized for driving a 16-bit ADC
such as the ADS8325. The OPA381 op amp buffers the
converter input capacitance and resulting charge
injection while providing signal gain. Figure 13 shows
the OPA381 in a single-ended method of interfacing the
ADS8325 16-bit, 100kSPS ADC. For additional
information, refer to the ADS8325 data sheet.
Extremely small currents can be accurately measured
by integrating currents on a capacitor. (Suggested
product: IVC102.)
Low-level currents can be converted to high-resolution
data words. (Suggested product: DDC112.)
For further information on the range of products
available, search www.ti.com using the above specific
model names or by using keywords transimpedance
and logarithmic.
13
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SBOS313B − AUGUST 2004 − REVISED NOVEMBER 2004
CF
RF
SW1
C1
Ω
100
OPA381
ADS8325
R1
1nF
µ
1 F
Ω
1M
VIN
V+
µ
1 F
RC values shown are optimized for the
ADS8325
values may vary for other ADCs.
VOUT
OPA381
VBIAS
Figure 13. Driving 16-Bit ADCs
INVERTING AMPLIFIER
Its excellent dc precision characteristics make the
OPA381 also useful as an inverting amplifier. Figure 14
shows it configured for use on a single-supply set to a
gain of 10.
Figure 15. Precision Integrator
CF
R1
DFN (DRB) THERMALLY-
ENHANCED PACKAGE
Ω
100k
One of the package options for the OPA381 and
OPA2381 is the DFN-8 package, a thermally-enhanced
package designed to eliminate the use of bulky heat
sinks and slugs traditionally used in thermal packages.
The absence of external leads eliminates bent-lead
concerns and issues.
V+
R2
Ω
10k
VIN
VOUT
=
OPA381
VBIAS
R2
−
VBIAS
x VIN
R1
Although the power dissipation requirements of a given
application might not require a heat sink, for mechanical
reliability, the exposed power pad must be soldered to
the board and connected to V− (pin 4). This package
can be easily mounted using standard PCB assembly
techniques. See Application Note SLUA271,QFN/SON
PCB Attachment, located at www.ti.com. These DFN
packages have reliable solderability with either SnPb or
Pb-free solder paste.
Figure 14. Inverting Gain
PRECISION INTEGRATOR
With its low offset voltage, the OPA381 is well-suited for
use as an integrator. Some applications require a
means to reset the integration. The circuit shown in
Figure 15 uses a mechanical switch as the reset
mechanism. The switch is opened at the beginning of
the integration period. It is shown in the open position,
which is the integration mode. With the values of R and
1
C shown, the output changes −1V/s per volt of input.
1
14
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2381AIDGKR
OPA2381AIDGKT
OPA2381AIDRBT
OPA381AIDGKR
OPA381AIDGKT
OPA381AIDRBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SON
DGK
DGK
DRB
DGK
DGK
DRB
8
8
8
8
8
8
2500 RoHS & Green Call TI | NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
A62
A62
A63
A64
A64
A65
250
250
RoHS & Green Call TI | NIPDAUAG
RoHS & Green NIPDAU
VSSOP
VSSOP
SON
2500 RoHS & Green Call TI | NIPDAUAG
250
250
RoHS & Green Call TI | NIPDAUAG
RoHS & Green NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2381AIDRBT
OPA381AIDRBT
SON
SON
DRB
DRB
8
8
250
250
180.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2381AIDRBT
OPA381AIDRBT
SON
SON
DRB
DRB
8
8
250
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008B
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.65 0.05
(0.2) TYP
4
5
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.1
C A B
C
0.5
0.3
8X
(OPTIONAL)
0.05
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.63)
SYMM
(1.06)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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