OPA3832 [TI]
250MHz 三路、低功耗、高速、固定增益运算放大器;
| 型号： | OPA3832 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 250MHz 三路、低功耗、高速、固定增益运算放大器 放大器 运算放大器 |
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OPA3832
®
www.ti.com ............................................................................................................................................ SBOS370A–DECEMBER 2006–REVISED AUGUST 2008
Triple, Low-Power, High-Speed, Fixed-Gain Operational Amplifier
Using complementary common-emitter outputs
provides an output swing to within 30mV of ground
and 60mV of the positive supply. The high output
drive current and low differential gain and phase
errors also make it ideal for single-supply consumer
video products.
1
FEATURES
2
•
•
•
HIGH BANDWIDTH: 80MHz (G = +2)
LOW SUPPLY CURRENT: 3.9mA/ch (VS = +5V)
FLEXIBLE SUPPLY RANGE:
±1.5V to ±5.5V Dual Supply
+3V to +11V Single Supply
Low distortion operation is ensured by high bandwidth
(80MHz) and slew rate (350V/µs), making the
OPA3832 an ideal input buffer stage to 3V and 5V
CMOS converters. Unlike earlier low-power,
single-supply amplifiers, distortion performance
improves as the signal swing is decreased. A low
9.3nV/√Hz input voltage noise supports wide dynamic
range operation.
•
INPUT RANGE INCLUDES GROUND ON
SINGLE SUPPLY
•
•
•
4.9VPP OUTPUT SWING ON +5V SUPPLY
HIGH SLEW RATE: 350V/µs
LOW INPUT VOLTAGE NOISE: 9.3nV/√Hz
APPLICATIONS
The OPA3832 is available in an industry-standard
SO-14 package or a small TSSOP-14 package.
•
•
•
•
SINGLE-SUPPLY VIDEO LINE DRIVERS
CCD IMAGING CHANNELS
LOW-POWER ULTRASOUND
PORTABLE CONSUMER ELECTRONICS
RELATED PRODUCTS
DESCRIPTION
SINGLES
DUALS
TRIPLES
QUADS
OPA4830
—
Rail-to-Rail Output
Rail-to-Rail Fixed-Gain
OPA830 OPA2830
OPA832 OPA2832
—
—
DESCRIPTION
General-Purpose
(1800V/µs slew rate)
OPA690 OPA2690 OPA3690
OPA820 OPA2822
—
The OPA3832 is a triple, low-power, high-speed,
fixed-gain amplifier designed to operate on a single
+3V to +11V supply. Operation on ±1.5V to ±5.5V
supplies is also supported. The input range extends
below ground and to within 1.7V of the positive
supply.
Low-Noise,
High dc Precision
—
OPA4820
0.1mF
V1
100W
100W
100W
4.99kW
1/3
OPA3832
0.1mF
4.99kW
400W
400W
400W
400W
REFT
+3.5V
REFB
+1.5V
V2
0.1mF
1/3
OPA3832
+In
ADS826
10-Bit
400W
100pF
60MSPS
-In
CM
V3
0.1mF
1/3
OPA3832
400W
Selection
Logic
Multiplexed Converter Driver
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
OPA3832
SBOS370A–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA3832ID
OPA3832IDR
OPA3832IPW
OPA3832IPWR
Rails, 50
OPA3832
SO-14
D
–40°C to +85°C
–40°C to +85°C
OPA3832
OPA3832
Tape and Reel, 2500
Rails, 90
OPA3832
TSSOP-14
PW
Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply
12VDC
Internal Power Dissipation
See Thermal
Characteristics
Differential Input Voltage(2)
±1.2V
–0.5V to ±VS + 0.3V
–65°C to +125°C
+300°C
Input Voltage Range
Storage Voltage Range: D, PW
Lead Temperature (soldering, 10s)
Maximum Junction Temperature (TJ)
Maximum Junction Temperature: Continuous Operation, Long Term Reliability
ESD Rating:
+150°C
+140°C
Human Body Model (HBM)
2000V
1000V
200V
Charge Device Model (CDM)
Machine Model (MM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Noninverting input to internal inverting mode.
PIN ASSIGNMENT
D, PW PACKAGES
SO-14, TSSOP-14
(TOP VIEW)
DIS A
DIS B
1
2
3
4
5
6
7
14 Output B
13 -Input B
12 +Input B
11 -VS
400W
400W
B
DIS C
+VS
+Input A
-Input A
Output A
10 +Input C
C
A
400W
400W
400W
400W
9
8
-Input C
Output C
2
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3832
OPA3832
www.ti.com ............................................................................................................................................ SBOS370A–DECEMBER 2006–REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
OPA3832ID, IPW
0°C to –40°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(1) +70°C(2) +85°C(2)
UNITS
LEVEL(3)
AC PERFORMANCE
Small-Signal Bandwidth
G = +1, VO ≤ 0.5VPP
G = +2, VO ≤ 0.5VPP
G = –1, VO ≤ 0.5VPP
VO ≤ 0.5VPP
G = +2, 2V Step
0.5V Step
250
80
MHz
MHz
MHz
dB
typ
min
min
typ
C
B
B
C
B
B
B
B
55
57
54
56
54
55
110
6
Peaking at a Gain of +1
Slew Rate
325
5.0
5.0
45
220
5.8
5.8
63
210
6.0
6.0
65
200
6.0
6.0
66
V/µs
ns
min
max
max
max
Rise Time
Fall Time
0.5V Step
ns
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
G = +2, 1V Step
VO = 2VPP, 5MHz
RL = 150Ω
ns
–57
–65
–60
–75
9.2
–54
–62
–50
–64
–52
–61
–49
–60
–50
–60
–48
–57
dBc
dBc
max
max
max
max
typ
B
B
B
B
C
C
C
C
C
RL = 500Ω
3rd-Harmonic
RL = 150Ω
dBc
RL = 500Ω
dBc
Input Voltage Noise
f > 1MHz
nV/√Hz
pA/√Hz
%
Input Current Noise
f > 1MHz
2.2
typ
NTSC Differential Gain
NTSC Differential Phase
All Hostile Crosstalk, Input Referred
RL = 150Ω
0.10
0.16
–55
typ
RL = 150Ω
typ
2 Channels Driven at 5MHz, 1VPP
3rd Channel Measured
dBc
typ
DC PERFORMANCE(4)
Gain Error
G = +2
G = –1
±0.3
±0.2
±1.5
±1.6
±1.6
±1.7
±1.7
%
%
min
A
B
±1.5
max
Internal RF and RG
Maximum
400
400
455
345
460
340
±0.1
±9.3
±27
+12
±45
±2
462
338
±0.1
±9.7
±27
+13
±45
±2.5
±10
Ω
Ω
max
max
max
max
max
max
max
max
max
B
B
B
A
B
A
B
A
B
Minimum
Average Drift
%/°C
mV
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
INPUT
±1.4
—
±8.0
+10
±1.5
µV/°C
µA
+5.5
—
nA/°C
µA
±0.1
—
±10
nA/°C
Negative Input Voltage Range
Positive Input Voltage Range
Input Impedance
–5.4
3.2
–5.2
3.1
–5.0
3.0
–4.9
2.9
V
V
max
min
B
B
Differential Mode
Common-Mode
10 || 2.1
kΩ || pF
kΩ || pF
typ
typ
C
C
400 || 1.2
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +13°C at high temperature limit for over
temperature specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(4) Current is considered positive out of node.
Copyright © 2006–2008, Texas Instruments Incorporated
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3
Product Folder Link(s): OPA3832
OPA3832
SBOS370A–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
OPA3832ID, IPW
0°C to –40°C to
MIN/
MAX
TEST
PARAMETER
OUTPUT
CONDITIONS
+25°C
+25°C(1) +70°C(2) +85°C(2)
UNITS
LEVEL(3)
Output Voltage Swing
RL = 1kΩ to GND
RL = 150Ω to GND
±4.9
±4.6
±82
120
0.2
±4.8
±4.5
±63
±4.75
±4.45
±58
±4.75
±4.4
±53
V
V
max
max
min
typ
A
A
A
C
C
Current Output, Sinking and Sourcing
Short-Circuit Current
mA
mA
Ω
Output Shorted to Either Supply
Closed-Loop Output Impedance
DISABLE (Disabled LOW)
Power Down Supply Current (+VS)
DIsable Time
G = +2, f ≤ 100kHz
typ
VDIS = 0, All Channels
VIN = 1VDC
0.95
40
2.5
2.6
2.7
mA
µs
ns
dB
pF
mV
mV
V
max
typ
A
C
C
C
C
C
C
A
A
A
Enable Time
VIN = 1VDC
20
typ
Off Isolation
G = +2V/V, 5MHz
–75
typ
Output Capacitance in Disable
Turn-On Glitch
typ
G = +2V/V, RL = 150Ω, VIN = 0V
G = +2V/V, RL = 150Ω, VIN = 0V
8
2
typ
Turn-Off Glitch
typ
Enable Voltage
4.5
3.0
4.5
3.0
4.5
3.0
min
max
max
Disable Voltage
V
Control Pin Input Bias Current (DIS)
POWER SUPPLY
VDIS = 0V, Each Channel
125
300
350
400
µA
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
±1.4
—
V
V
min
max
max
min
B
A
A
A
±5.5
14.4
12
±5.5
16.1
10.8
±5.5
17.9
9.3
All Channels, VS = ±5V
All Channels, VS = ±5V
12.75
12.75
mA
mA
Power-Supply Rejection Ratio
(–PSRR)
Input-Referred
66
61
60
59
dB
min
A
THERMAL CHARACTERISTICS
Specification: ID, IPW
–40 to +85
°C
typ
C
Thermal Resistance
D
SO-14
85
°C/W
°C/W
typ
typ
C
C
PW
TSSOP-14
100
4
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3832
OPA3832
www.ti.com ............................................................................................................................................ SBOS370A–DECEMBER 2006–REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
OPA3832ID, IPW
0°C to
–40°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(1) +70°C(2) +85°C(2)
UNITS
LEVEL(3)
AC PERFORMANCE
Small-Signal Bandwidth
G = +1, VO ≤ 0.5VPP
G = +2, VO ≤ 0.5VPP
G = –1, VO ≤ 0.5VPP
VO ≤ 0.5VPP
G = +2, 2V Step
0.5V Step
210
80
MHz
MHz
MHz
dB
typ
min
min
typ
C
B
B
C
B
B
B
B
56
60
55
58
55
58
105
7
Peaking at a Gain of +1
Slew Rate
350
5.2
5.2
46
230
5.8
5.8
64
220
5.8
5.8
66
220
5.9
5.9
67
V/µs
ns
min
max
max
max
Rise Time
Fall Time
0.5V Step
ns
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
G = +2, 1V Step
VO = 2VPP, 5MHz
RL = 150Ω
ns
–54
–60
–57
–79
9.3
–51
–57
–50
–65
–50
–55
–49
–62
–49
–54
–47
–58
dBc
dBc
max
max
max
max
typ
B
B
B
B
C
C
C
C
RL = 500Ω
3rd-Harmonic
RL = 150Ω
dBc
RL = 500Ω
dBc
Input Voltage Noise
Input Current Noise
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE(4)
Gain Error
f > 1MHz
nV/√Hz
pA/√Hz
%
f > 1MHz
2.3
typ
RL = 150Ω
0.11
0.14
typ
RL = 150Ω
typ
G = +2
G = –1
±0.3
±0.2
400
400
±1.5
±1.5
455
345
±1.6
±1.6
460
340
±0.1
±7.5
±25
+12
±45
±2
±1.7
±1.7
462
338
±0.1
±8.0
±25
+13
±45
±2.5
±10
%
%
min
max
max
max
max
max
max
max
max
max
max
A
B
A
A
B
A
B
A
B
A
B
Internal RF and RG, Maximum
Minimum
Ω
Ω
Average Drift
%/°C
mV
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
±1.5
—
±6.5
+10
±1.5
µV/°C
µA
VCM = 2.0V
VCM = 2.0V
+5.5
—
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
INPUT
nA/°C
µA
±0.1
—
±10
nA/°C
Least Positive Input Voltage
Most Positive Input Voltage
Input Impedance, Differential Mode
Common-Mode
–0.5
3.3
–0.2
3.2
0
+0.1
3.0
V
max
min
typ
B
B
C
C
3.1
V
10 || 2.1
400 || 1.2
kΩ || pF
kΩ || pF
typ
OUTPUT
Least Positive Output Voltage
RL = 1kΩ to 2.0V
RL = 150Ω to 2.0V
RL = 1kΩ to 2.0V
RL = 150Ω to 2.0V
0.03
0.18
4.94
4.86
±75
100
0.2
0.16
0.3
0.18
0.35
4.6
0.20
0.40
4.4
V
V
max
max
min
min
min
typ
A
A
A
A
A
C
C
Most Positive Output Voltage
4.8
V
4.6
4.5
4.4
V
Current Output, Sinking and Sourcing
Short-Circuit Output Current
±58
±53
±50
mA
mA
Ω
Output Shorted to Either Supply
Closed-Loop Output Impedance
G = +2, f ≤ 100kHz
typ
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +6°C at high temperature limit for over
temperature specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(4) Current is considered positive out of node.
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): OPA3832
OPA3832
SBOS370A–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
OPA3832ID, IPW
0°C to
–40°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(1) +70°C(2) +85°C(2)
UNITS
LEVEL(3)
DISABLE (Disabled LOW)
Power Down Supply Current (+VS)
DIsable Time
VDIS = 0, All Channels
VIN = 1VDC
0.7
40
1.4
1.5
1.5
mA
µs
ns
dB
pF
mV
mV
V
max
typ
A
C
C
C
C
C
C
A
A
A
Enable Time
VIN = 1VDC
20
typ
Off Isolation
G = +2V/V, 5MHz
–75
typ
Output Capacitance in Disable
Turn-On Glitch
typ
G = +2V/V, RL = 150Ω, VIN = 0V
G = +2V/V, RL = 150Ω, VIN = 0V
2
6
typ
Turn-Off Glitch
typ
Enable Voltage
4.5
3.0
4.5
3.0
4.5
3.0
min
max
max
Disable Voltage
V
Control Pin Input Bias Current (DIS)
POWER SUPPLY
VDIS = 0V, Each Channel
125
300
350
400
µA
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IPW
Thermal Resistance
+2.8
—
V
typ
max
max
min
min
C
A
A
A
A
+11
12.6
11.1
61
+11
14.7
10.5
60
+11
16.8
9
V
All Channels, VS = +5V
All Channels, VS = +5V
Input-Referred
11.7
11.7
66
mA
mA
dB
59
–40 to +85
°C
typ
C
D
SO-14
85
°C/W
°C/W
typ
typ
C
C
PW
TSSOP-14
100
6
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3832
OPA3832
www.ti.com ............................................................................................................................................ SBOS370A–DECEMBER 2006–REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = +3.3V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted.
OPA3832ID, IPW
0°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(1)
+70°C(2)
UNITS
LEVEL(3)
AC PERFORMANCE
Small-Signal Bandwidth
G = +1, VO ≤ 0.5VPP
G = +2, VO ≤ 0.5VPP
G = –1, VO ≤ 0.5VPP
VO ≤ 0.5VPP
1V Step
180
90
MHz
MHz
MHz
dB
typ
min
min
typ
C
B
B
C
B
B
B
B
59
63
57
61
100
8
Peaking at a Gain of +1
Slew Rate
150
4.4
4.4
48
110
5.6
5.6
70
100
5.7
5.7
80
V/µs
ns
min
max
max
max
Rise Time
0.5V Step
Fall Time
0.5V Step
ns
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
1V Step
ns
5MHz
RL = 150Ω
RL = 500Ω
RL = 150Ω
RL = 500Ω
f > 1MHz
–60
–67
–66
–80
9.4
–54
–63
–60
–66
–51
–57
–55
–62
dBc
dBc
max
max
max
max
typ
B
B
B
B
C
C
3rd-Harmonic
dBc
dBc
Input Voltage Noise
Input Current Noise
DC PERFORMANCE(4)
Gain Error
nV/√Hz
pA/√Hz
f > 1MHz
2.4
typ
G = +2
G = –1
±0.3
±0.2
±1.5
±1.6
±1.6
%
%
min
A
B
±1.5
max
Internal RF and RG
Maximum
400
400
455
345
460
340
±0.1
±7.7
±27
+12
±45
±2
Ω
Ω
max
max
max
max
max
max
max
max
max
B
B
B
A
B
A
B
A
B
Minimum
Average Drift
%/°C
mV
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
INPUT
±1.4
—
±6.5
+10
±1.5
µV/°C
µA
VCM = 0.75V
VCM = 0.75V
+5.5
—
nA/°C
µA
±0.1
—
±10
nA/°C
Least Positive Input Voltage
Most Positive Input Voltage
Input Impedance
–0.5
1.5
–0.3
1.4
–0.2
1.3
V
V
max
min
B
B
Differential Mode
Common-Mode
10 || 2.1
kΩ || pF
kΩ || pF
typ
typ
C
C
400 || 1.2
OUTPUT
Least Positive Output Voltage
RL = 1kΩ to 0.75V
RL = 150Ω to 0.75V
RL = 1kΩ to 0.75V
RL = 150Ω to 0.75V
0.03
0.1
3
0.16
0.3
0.18
0.35
2.6
V
V
max
max
min
min
min
typ
B
B
B
B
A
C
C
Most Positive Output Voltage
2.8
V
3
2.8
2.6
V
Current Output, Sinking and Sourcing
Short-Circuit Output Current
±35
80
±25
±20
mA
mA
Ω
Output Shorted to Either Supply
See Figure 2, f < 100kHz
Closed-Loop Output Impedance
0.2
typ
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +4°C at high temperature limit for over
temperature specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(4) Current is considered positive out of node.
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ELECTRICAL CHARACTERISTICS: VS = +3.3V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted.
OPA3832ID, IPW
0°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(1)
+70°C(2)
UNITS
LEVEL(3)
DISABLE (Disabled LOW)
Power-Down Supply Current (+VS)
DIsable Time
VDIS = 0, All Channels
VIN = 1VDC
0.4
40
0.8
0.85
mA
µs
ns
dB
pF
mV
mV
V
max
typ
A
C
C
C
C
C
C
A
A
A
Enable Time
VIN = 1VDC
20
typ
Off Isolation
G = +2V/V, 5MHz
–75
typ
Output Capacitance in Disable
Turn-On Glitch
typ
G = +2V/V, RL = 150Ω, VIN = 0V
G = +2V/V, RL = 150Ω, VIN = 0V
2
6
typ
Turn-Off Glitch
typ
Enable Voltage
2.8
1.3
130
2.8
1.3
140
min
max
max
Disable Voltage
V
Control Pin Input Bias Current (DIS)
POWER SUPPLY
VDIS = 0V, Each Channel
73
µA
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IPW
Thermal Resistance
+2.8
—
V
typ
max
max
min
typ
C
A
A
A
C
+11
12.2
10.2
+11
14.5
9.5
V
All Channels, VS = +3.3V
All Channels, VS = +3.3V
Input-Referred
11.4
11.4
60
mA
mA
dB
–40 to +85
°C
typ
C
D
SO-14
85
°C/W
°C/W
typ
typ
C
C
PW
TSSOP-14
100
8
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TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
3
0
3
0
VO = 0.2VPP
RL = 150W
G = -1V/V
VO = 0.5VPP
-3
-3
G = +2V/V
-6
-6
VO = 1VPP
VO = 2VPP
-9
-9
-12
-15
-12
-15
G = +2V/V
VO = 4VPP
100
RL = 150W
1
10
100
400
1
10
400
Frequency (MHz)
Frequency (MHz)
Figure 2.
Figure 1.
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
0.4
0.3
2.0
0.4
0.3
2.0
G = +2V/V
G = -1V/V
RL = 150W
1.5
1.5
RL = 150W
Large-Signal Pulse Response 1V
Right Scale
0.2
1.0
0.2
1.0
0.1
0.5
0.1
0.5
Small-Signal Pulse
Response 0.1V
Left Scale
Small-Signal Pulse
Response 0.1V
Left Scale
0
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1.0
-1.5
-2.0
-0.1
-0.2
-0.3
-0.4
-0.5
-1.0
-1.5
-2.0
Large-Signal Pulse Response 1V
Right Scale
Time (10ns/div)
Time (10ns/div)
Figure 3.
Figure 4.
REQUIRED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
40
35
30
25
20
15
10
5
3
0
1dB Peaking Targeted
CL = 10pF
-3
CL = 1000pF
CL = 100pF
-6
-9
RS
VI
1/3
OPA3832
1kW(1)
CL
-12
-15
NOTE: (1) 1kW is optional.
0
10
100
1k
1
10
100
400
Capacitive Load (pF)
Figure 5.
Frequency (MHz)
Figure 6.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
-55
-60
-65
-70
-75
-80
-85
-90
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
G = +2V/V
2nd-Harmonic
RL = 500W
f = 5MHz
2nd-Harmonic
3rd-Harmonic
3rd-Harmonic
G = +2V/V
VO = 2VPP
f = 5MHz
100
1k
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5 9.0
Load Resistance (W)
Output Swing (VPP
)
Figure 7.
Figure 8.
HARMONIC DISTORTION vs FREQUENCY
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-40
-40
-50
G = +2V/V
PI
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
1/3
OPA3832
PO
RL = 500W
50W
20MHz
500W
VO = 2VPP
400W
2nd-Harmonic
-60
400W
10MHz
-70
-80
-90
3rd-Harmonic
5MHz
-100
-110
0.1
1
10
20
-26
-22
-18
-14
-10
-6
-2
2
6
Frequency (MHz)
Single-Tone Load Power (dBm)
Figure 9.
Figure 10.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
OUTPUT SWING vs LOAD RESISTANCE
5
4
6
5
Output
G = +2V/V
Positive Output Voltage
Current Limit
VS
= 5V
4
3
3
RL = 500W
2
2
RL = 50W
RL = 100W
1W Internal
1
1
Power Limit
0
0
One Channel Only
-1
-2
-3
-1
-2
-3
-4
-5
1W Internal
Power Limit
One Channel Only
-4 Output
Negative Output Voltage
Current Limit
-5
-6
-160 -120 -80
-40
0
40
80
120
160
10
100
1k
IO (mA)
RL (W)
Figure 11.
Figure 12.
10
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
CHANNEL-TO-CHANNEL CROSSTALK REJECTION
COMPOSITE VIDEO dG/dP
ALL HOSTILE CROSSTALK REJECTION
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
1.2
1.0
0.8
0.6
0.4
0.2
0
+5V
No Pull-Down
With 1.3kW Pull-Down
V
I
1/3
Video
Loads
OPA3832
75W
Optional
1.3kW
400W
Pull-Down
400W
All Hostile
dP
dP
-5V
Channel-to-Channel
dG
dG
0.1
1
10
100
1
2
3
4
Frequency (MHz)
Number of 150W Loads
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, Differential Gain = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
3
0
3
0
VO = 0.2VPP
G = -1V/V
RL = 500W
VO = 1VPP
-3
-3
G = +2V/V
VO = 0.5VPP
-6
-6
-9
-9
VO = 2VPP
-12
-15
-12
-15
1
10
100
300
1
10
100
300
Frequency (MHz)
Figure 15.
Frequency (MHz)
Figure 16.
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
G = -1V/V
RL = 150W
G = +2V/V
Large-Signal Pulse Response 1V
Right Scale
RL = 150W
Small-Signal Pulse
Response 0.1V
Left Scale
Small-Signal Pulse
Response 0.1V
Left Scale
Large-Signal Pulse Response 1V
Right Scale
Time (10ns/div)
Time (10ns/div)
Figure 17.
Figure 18.
COMPOSITE VIDEO dG/dP
DISABLE FEEDTHROUGH vs FREQUENCY
1.2
1.0
0.8
0.6
0.4
0.2
0
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
Input Referred
+5V
VI
1/3
OPA3832
Video
Loads
400W
400W
dP
dG
1
10
100
1
2
3
4
Frequency (MHz)
Number of 150W Loads
Figure 19.
12
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, Differential Gain = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
-30
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
G = +2V/V
RL = 500W
f = 5MHz
2nd-Harmonic
-40
-50
-60
-70
-80
-90
Input Limited
3rd-Harmonic
2nd-Harmonic
G = +2V/V
VO = 2VPP
f = 5MHz
3rd-Harmonic
100
1k
3
4
5
6
7
8
9
10
11
Load Resistance (W)
(+) Supply Voltage (V)
Figure 20.
Figure 21.
G = +2V/V, HARMONIC DISTORTION vs FREQUENCY
G = –1V/V, HARMONIC DISTORTION vs FREQUENCY
-30
-30
G = +2V/V
RL = 500W
VO = 2VPP
G = -1V/V
RL = 500W
f = 5MHz
-40
-50
-40
-50
2nd-Harmonic
2nd-Harmonic
-60
-60
-70
-70
-80
-80
-90
-90
3rd-Harmonic
3rd-Harmonic
-100
-110
-100
-110
0.1
1
10
20
0.1
1
10
20
Frequency (MHz)
Frequency (MHz)
Figure 22.
Figure 23.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-40
-40
-50
-60
-70
-80
-90
-100
G = +2V/V
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
PI
1/3
OPA3832
PO
RL = 500W
50W
500W
f = 5MHz
400W
20MHz
2nd-Harmonic
400W
10MHz
3rd-Harmonic
5MHz
-24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Single-Tone Load Power (2dBm/div)
Output Voltage Swing (VPP
)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, Differential Gain = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO AND
COMMON-MODE REJECTION RATIO VS FREQUENCY
INPUT VOLTAGE AND CURRENT NOISE
100
10
1
80
70
60
50
40
30
20
10
0
CMRR
+PSRR
Voltage Noise (9.3nV/ÖHz)
Current Noise (2.3pA/ÖHz)
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 26.
Figure 27.
OUTPUT SWING vs LOAD RESISTANCE
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
5.0
100
G = +2V/V
VS = +5V
400W
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Most Positive Output Voltage
+5V
400W
10
1
1/3
OPA3832
ZO
200W
Least Negative Output Voltage
0.1
10
100
1k
1k
10k
100k
1M
10M
100M
RL (W)
Frequency (Hz)
Figure 28.
Figure 29.
VOLTAGE RANGES vs TEMPERATURE
TYPICAL DC DRIFT OVER TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5
10
8
Input Offset Voltage (VOS
)
2.0
1.5
1.0
0.5
0
Most Positive Output Voltage
Most Positive Input Voltage
6
Bias Current (IB)
4
RL = 150W
2
Least Positive Output Voltage
0
10 x Input Offset (IOS
)
-0.5
-1.0
-2
-4
Least Positive Input Voltage
-0.5
-1.0
-40 -20
0
20
40
60
80
100 120 140
-50
0
50
90
Ambient Temperature (20°C/div)
Ambient Temperature (10°C/div)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, Differential Gain = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
11
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
100
80
60
40
20
0
5
3
VDIS
1
Output Current, Sinking
Output Current, Sourcing
10
9
-1
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
8
Supply Current
VIN = = 0.5VDC
7
6
-40 -20
0
20
40
60
80
100 120 140
Time (10ms/div)
Ambient Temperature (20°C/div)
Figure 32.
Figure 33.
DISABLE/ENABLE GLITCH
5
3
1
VDIS
-1
4
3
2
At Matched Load
1
0
-1
-2
-3
-4
Time (10ms/div)
Figure 34.
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TYPICAL CHARACTERISTICS: VS = +3.3V
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
3
0
3
0
VO = 0.2VPP
G = -1V/V
RL = 150W
VO = 1VPP
-3
-3
VO = 0.5VPP
G = +2V/V
-6
-6
-9
-9
VO = 1.5VPP
-12
-15
-12
-15
G = +2V/V
RL = 150W
1
10
100
300
1
10
100
300
Frequency (MHz)
Figure 35.
Frequency (MHz)
Figure 36.
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
G = +2V/V
G = -1V/V
RL = 150W
Large-Signal Pulse Response 1V
Right Scale
RL = 150W
Small-Signal Pulse
Response 0.1V
Left Scale
Small-Signal Pulse
Response 0.1V
Left Scale
Large-Signal Pulse Response 1V
Right Scale
Time (10ns/div)
Time (10ns/div)
Figure 37.
Figure 38.
REQUIRED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
60
50
40
30
20
10
0
3
0
1dB Peaking Targeted
CL = 10pF
CL = 1000pF
CL = 100pF
-3
-6
VI
1/3
OPA3832
-9
(1)
CL
1kW
400W
-12
-15
400W
NOTE: (1) 1kW is optional.
1
10
100
1k
1
10
100
300
Capacitive Load (pF)
Frequency (MHz)
Figure 39.
Figure 40.
16
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TYPICAL CHARACTERISTICS: VS = +3.3V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
-55
-60
-65
-70
-75
-80
-60
-70
2nd-Harmonic
2nd-Harmonic
-80
3rd-Harmonic
3rd-Harmonic
-90
G = +2V/V
VO = 1VPP
f = 5MHz
G = +2V/V
RL = 500W
f = 5MHz
-100
100
1k
0.50
0.75
1.00
1.25
)
1.50
Load Resistance (W)
Output Voltage Swing (VPP
Figure 41.
Figure 42.
TWO-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
HARMONIC DISTORTION vs FREQUENCY
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-40
-50
G = +2V/V
RL = 500W
VO = 1VPP
PI
1/3
OPA3832
PO
50W
20MHz
500W
400W
-60
400W
2nd-Harmonic
-70
10MHz
-80
-90
5MHz
-100
-110
3rd-Harmonic
0.1
1
10
20
-26 -24 -22 -20 -18 -16 -14 -12 -10
Single-Tone Load Power (dBm)
Figure 44.
-8
Frequency (MHz)
Figure 43.
OUTPUT SWING vs LOAD RESISTANCE
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
G = +2V/V
VS = +3.3V
Most Positive Output Voltage
Least Positive Output Voltage
10
100
1k
RL (W)
Figure 45.
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APPLICATION INFORMATION
effective load on the output at high frequencies is
150Ω || 800Ω. The 255Ω and 1.13kΩ resistors at the
noninverting input provide the common-mode bias
voltage. This parallel combination equals the dc
resistance at the inverting input RF), reducing the dc
output offset arising from input bias current.
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
The OPA3832 is a unity-gain stable, very high-speed
voltage-feedback op amp designed for single-supply
operation (+3V to +11V). The input stage supports
input voltages below ground and to within 1.7V of the
positive supply. The complementary common-emitter
output stage provides an output swing to within 25mV
of ground and the positive supply. The OPA3832 is
compensated to provide stable operation with a wide
range of resistive loads.
VS = +3.3V
6.8mF
+
0.1mF
1.13kW
0.1mF
66.5W
+0.75V
VIN
Figure 46 shows the ac-coupled, gain of +2V/V
configuration used for the +5V Specifications and
Typical Characteristic Curves. For test purposes, the
input impedance is set to 50Ω with the 66.7Ω resistor
to ground in parallel with the 200Ω bias network.
1/3
OPA3832
255W
VOUT
RL
150W
400W
400W
+0.75
Voltage
swings
reported
in
the
Electrical
0.75V
Characteristics are taken directly at the input and
output pins. For the circuit of Figure 46, the total
effective load on the output at high frequencies is
150Ω || 800Ω. The 332Ω and 505Ω resistors at the
noninverting input provide the common-mode bias
voltage. This parallel combination equals the dc
resistance at the inverting input RF), reducing the dc
output offset resulting from input bias current.
Figure 47. AC-Coupled, G = +2, +3.3V
Single-Supply Specification and Test Circuit
Figure 48 shows the dc-coupled, gain of +2, dual
power-supply circuit configuration used as the basis
of the ±5V Electrical Characteristics and Typical
Characteristics. For test purposes, the input
impedance is set to 50Ω with a resistor to ground and
the output impedance is set to 150Ω with a series
output resistor. Voltage swings reported in the
specifications are taken directly at the input and
output pins. For the circuit of Figure 48, the total
effective load will be 150Ω || 800Ω. Two optional
components are included in Figure 48. An additional
resistor (175Ω) is included in series with the
noninverting input. Combined with the 25Ω dc source
resistance looking back towards the signal generator,
this configuration gives an input bias current
cancelling resistance that matches the 200Ω source
resistance seen at the inverting input (see the DC
Accuracy and Offset Control section). In addition to
the usual power-supply decoupling capacitors to
ground, a 0.01µF capacitor is included between the
two power-supply pins. In practical printed circuit
board (PCB) board layouts, this optional capacitor will
typically improve the 2nd-harmonic distortion
performance by 3dB to 6dB.
VS = +5V
6.8mF
+
0.1mF
505W
0.1mF
66.7W
2V
VIN
1/3
332W
VOUT
OPA3832
RL
150W
400W
400W
+2V
+2V
Figure 46. AC-Coupled, G = +2, +5V Single-Supply
Specification and Test Circuit
Figure 47 shows the ac-coupled, gain of +2V/V
configuration used for the +3.3V Specifications and
Typical Characteristic Curves. For test purposes, the
input impedance is set to 66.5Ω with a resistor to
ground. Voltage swings reported in the Electrical
Characteristics are taken directly at the input and
output pins. For the circuit of Figure 47, the total
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pole set to 3.2kHz for the component values shown).
+5V
As discussed for Figure 46, this configuration allows
0.1mF
6.8mF
+
the midpoint bias formed by one 2kΩ and one 3kΩ
resistor to appear at both the input and output pins.
The midband signal gain is set to +2 (6dB) in this
case. The capacitor to ground on the noninverting
input is intentionally set larger to dominate input
parasitic terms. At a gain of +2, the OPA3832 on a
single supply will show 80MHz small- and large-signal
bandwidth. The resistor values have been slightly
adjusted to account for this limited bandwidth in the
amplifier stage. Tests of this circuit, shown in
Figure 49, illustrate a precise 1MHz, –3dB point with
50W Source
175W
VIN
150W
VO
1/3
OPA3832
50W
0.01mF
400W
a
maximally-flat passband (above the 3.2kHz
ac-coupling corner), and a maximum stop band
attenuation of 36dB.
400W
6.8mF
0.1mF
+
9
6
-5V
3
Figure 48. DC-Coupled, G = +2, Bipolar Supply
Specification and Test Circuit
0
-3
-6
-9
-12
-15
-18
SINGLE-SUPPLY ACTIVE FILTER
The OPA3832, while operating on a single +3.3V or
+5V supply, lends itself well to high-frequency active
filter designs. Again, the key additional requirement is
to establish the dc operating point of the signal near
the supply midpoint for highest dynamic range.
Figure 50 shows an example design of a 1MHz
low-pass Butterworth filter using the Sallen-Key
topology.
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 49. 1MHz, 2nd-Order, Butterworth
Low-Pass Filter
Both the input signal and the gain setting resistor are
ac-coupled using 0.1µF blocking capacitors (actually
giving bandpass response with the low-frequency
+5V
470pF
3kW
0.1mF
205W
866W
VI
1/3
2VI
OPA3832
300pF
2kW
1MHz, 2nd-Order
400W
Butterworth Filter
400W
0.1mF
Figure 50. Single-Supply, High-Frequency Active Filter
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HIGH-SPEED INSTRUMENTATION
AMPLIFIER
9
6
Figure 51 shows an instrumentation amplifier based
3
on the OPA3832. The offset matching between inputs
makes this an attractive input stage for this
application. The differential-to-single-ended gain for
0
-3
this circuit is 2.0V/V. The inputs are high impedance,
-6
with only 1pF to ground at each input. The loads on
-9
the OPA3832 outputs are equal for the best harmonic
distortion possible.
-12
-15
-18
VOUT
20log
|V1 - V2|
1
10
100
400
V1
200W
200W
1/3
Frequency (MHz)
OPA3832
400W
400W
400W
Figure 52. High-Speed Instrumentation Amplifier
Response
1/3
OPA3832
400W
VOUT
400W
400W
1/3
OPA3832
V2
Figure 51. High-Speed Instrumentation Amplifier
As shown in Figure 52, the OPA3832 used as an
instrumentation amplifier has
a
55MHz, –3dB
bandwidth. This data plots a 1VPP output signal using
a low-impedance differential input source.
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MULTIPLEXED CONVERTER DRIVER
The output resistors isolate the outputs from each
other when switching between channels. The
feedback network of the disabled channels forms part
of the load seen by the enabled amplifier, attenuating
the signal slightly.
The converter driver in Figure 53 multiplexes among
the three input signals. The OPA3832s enable and
disable times support multiplexing among video
signals. The make-before-break disable characteristic
of the OPA3832 ensures that the output is always
under control. To avoid large switching glitches,
switch during the sync or retrace portions of the video
signal—the two inputs should be almost equal at
these times. The output is always under control, so
the switching glitches for two 0V inputs are < 20mV.
With standard video signals levels at the inputs, the
maximum differential voltage across the disabled
inputs will not exceed the ±1.2V maximum rating.
0.1mF
V1
100W
100W
100W
4.99kW
1/3
OPA3832
0.1mF
4.99kW
400W
400W
400W
400W
REFT
+3.5V
REFB
+1.5V
V2
0.1mF
1/3
OPA3832
+In
ADS826
10-Bit
400W
100pF
60MSPS
-In
CM
V3
0.1mF
1/3
OPA3832
400W
Selection
Logic
Multiplexed Converter Driver
Figure 53. Multiplexed Converter Driver
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LOW-PASS FILTER
The circuit in Figure 54 realizes
a 7th-order
Butterworth low-pass filter with a –3dB bandwidth of
2MHz. This filter is based on the KRC active filter
topology that uses an amplifier with the fixed gain ≥
1. The OPA3832 makes a good amplifier for this type
of filter. The component values have been adjusted to
compensate of the parasitic effects of the op amp.
1.2pF
560pF
49.9W
47.5W
110W
VIN
2.2pF
255W
124W
820pF
1/3
1/3
OPA3832
220pF
OPA3832
400W
400W
400W
400W
1.8pF
48.7W
7TH-ORDER BUTTERWORTH
FILTER RESPONSE
10
95.3W
0
-10
-20
-30
-40
-50
-60
-70
-80
1/3
OPA3832
680pF
VOUT
400W
400W
0
1
10
100
Frequency (MHz)
Figure 54. 7th-Order Butterworth Filter
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DESIGN-IN TOOLS
the available output voltage and current will always
be greater than that shown in the over-temperature
specifications, because the output stage junction
temperatures will be higher than the minimum
specified operating ambient.
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA3832 in its two package options. Both
of these are offered free of charge as unpopulated
PCBs, delivered with a user's guide. The summary
information for these fixtures is shown in Table 1.
To maintain maximum output stage linearity, no
output short-circuit protection is provided. This
configuration will not normally be a problem, since
most applications include a series matching resistor
at the output that will limit the internal power
dissipation if the output side of this resistor is shorted
to ground. However, shorting the output pin directly to
the adjacent positive power-supply pin (8-pin
packages) will, in most cases, destroy the amplifier. If
additional short-circuit protection is required, consider
a small series resistor in the power-supply leads. This
resistor will reduce the available output voltage swing
under heavy output loads.
Table 1. Demonstration Fixtures by Package
ORDERING
NUMBER
LITERATURE
NUMBER
PRODUCT
OPA3832ID
OPA3832IPW
PACKAGE
SO-14
DEM-OPA-SO-3B
SBOU018
SBOU019
TSSOP-14
DEM-OPA-SSOP-3B
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA3832 product folder.
DRIVING CAPACITIVE LOADS
MACROMODEL AND APPLICATIONS
SUPPORT
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
Computer simulation of circuit performance using
Analog-to-Digital
additional external capacitance which may be
recommended to improve ADC linearity.
Converter
(ADC)—including
SPICE is often
a quick way to analyze the
performance of the OPA3832 and its circuit designs.
This is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can play a major role on circuit performance. A
SPICE model for the OPA3832 is available through
the TI web page (www.ti.com). The applications
department is also available for design assistance.
These models predict typical small signal ac,
transient steps, dc performance, and noise under a
wide variety of operating conditions. The models
include the noise terms found in the electrical
specifications of the data sheet. These models do not
attempt to distinguish between the package types in
their small-signal ac performance.
A
high-speed, high open-loop gain amplifier like the
OPA3832 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the primary considerations are frequency
response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by inserting a series isolation resistor between the
amplifier output and the capacitive load.
The Typical Characteristic curves show the
recommended RS versus capacitive load and the
resulting frequency response at the load. Parasitic
capacitive loads greater than 2pF can begin to
degrade the performance of the OPA3832. Long PCB
traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
the output pin (see the Board Layout Guidelines
section).
OPERATING SUGGESTIONS
OUTPUT CURRENT AND VOLTAGES
The OPA3832 provides outstanding output voltage
capability. For the +5V supply, under no-load
conditions at +25°C, the output voltage typically
swings closer than 90mV to either supply rail.
The minimum specified output voltage and current
specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at
cold startup will the output current and voltage
decrease to the numbers shown in the ensured
tables. As the output transistors deliver power, the
junction temperatures will increase, decreasing the
VBEs (increasing the available output voltage swing)
and increasing the current gains (increasing the
available output current). In steady-state operation,
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a
gain of +2, the frequency response at the output pin
is already slightly peaked without the capacitive load,
requiring relatively high values of RS to flatten the
response at the load. Increasing the noise gain will
also reduce the peaking.
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DISTORTION PERFORMANCE
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 1 shows the
general form for the output noise voltage using the
terms shown in Figure 55:
The OPA3832 provides good distortion performance
into a 150Ω load. Relative to alternative solutions, it
provides exceptional performance into lighter loads
and/or operating on a single +3.3V supply. Generally,
until the fundamental signal reaches very high
frequency or power levels, the 2nd-harmonic will
dominate the distortion with a negligible 3rd-harmonic
component. Focusing then on the 2nd-harmonic,
increasing the load impedance improves distortion
directly. Remember that the total load includes the
feedback network; in the noninverting configuration
(see Figure 47) this is the sum of RF + RG, while in
the inverting configuration, only RF needs to be
included in parallel with the actual load.
2
2
2
2
E
E
I
R
4kTR NG
I
R
4kTR NG
F
O
NI
BN
S
S
BI
F
(1)
Dividing this expression by the noise gain
(NG = (1 + RF/RG)) gives the equivalent input-referred
spot noise voltage at the noninverting input, as shown
in Figure 55:
2
2
IBIRF
NG
4kTRF
NG
2
EN
ENI
IBNRS
4kTRS
(2)
Evaluating these two equations for the circuit and
component values shown in Figure 46 gives a total
output spot noise voltage of 18.8nV/√Hz and a total
equivalent input spot noise voltage of 9.42nV/√Hz.
This total includes the noise added by the resistors.
This total input-referred spot noise voltage is not
much higher than the 9.2nV/√Hz specification for the
op amp voltage noise alone.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback op
amps usually achieve their slew rate at the expense
of a higher input noise voltage. The 9.2nV/√Hz input
voltage noise for the OPA3832, however, is much
lower than comparable amplifiers. The input-referred
voltage noise and the two input-referred current noise
terms (2.2pA/√Hz) combine to give low output noise
under
a
wide variety of operating conditions.
DC ACCURACY AND OFFSET CONTROL
Figure 55 shows the op amp noise analysis model
with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current
density terms in either nV/√Hz or pA/√Hz.
The balanced input stage of
a
wideband
voltage-feedback op amp allows good output dc
accuracy in a wide variety of applications. The
power-supply current trim for the OPA3832 gives
even tighter control than comparable products.
Although the high-speed input stage does require
relatively high input bias current (typically 5µA out of
each input terminal), the close matching between
them may be used to reduce the output dc error
caused by this current. This configuration matches
the dc source resistances appearing at the two
inputs. Evaluating the configuration of Figure 48
(which has matched dc input resistances), using
worst-case +25°C input offset voltage and current
ENI
1/3
EO
OPA3832
RS
IBN
ERS
RF
Ö4kTRS
Ö4kTRF
specifications, gives
voltage equal to:
a worst-case output offset
IBI
RG
4kT
RG
4kT = 1.6E - 20J
at 290°K
•
•
•
•
(NG = noninverting signal gain at dc)
±(NG × VOS(MAX)) + RF × IOS(MAX)
= ±(2 × 80mV) + (400Ω × 1.5µA)
)
Figure 55. Noise Analysis Model
= –15.4mV to +16.6mV
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A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most of these techniques are based
on adding a dc current through the feedback resistor.
In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
be noninverting, the offset control is best applied as
an inverting summing signal to avoid interaction with
the signal source. If the signal path is intended to be
inverting, applying the offset control to the
noninverting input may be considered. Bring the dc
offsetting current into the inverting input node through
resistor values that are much larger than the signal
path resistors. This configuration ensures that the
adjustment circuit has minimal effect on the loop gain
and thus the frequency response.
dissipation will occur if the load requires current to be
forced into the output at high output voltages or
sourced from the output at low output voltages. This
condition puts a high current through a large internal
voltage drop in the output transistors.
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier such as the OPA3832
requires careful attention to board layout parasitics
and external component types. Recommendations
that will optimize performance include:
a) Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability; on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
THERMAL ANALYSIS
Maximum desired junction temperature sets the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
b) Minimize the distance ( < 0.25") from the
power-supply
pins
to
high-frequency
0.1µF
Operating junction temperature (TJ) is given by
TA + PD × θJA. The total internal power dissipation
(PD) is the sum of quiescent power (PDQ) and
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each
additional power dissipated in the output stage (PDL
)
to deliver load power. Quiescent power is simply the
specified no-load supply current times the total supply
voltage across the part. PDL depends on the required
output signal and load, though for resistive loads
connected to midsupply (VS/2), PDL is at a maximum
when the output is fixed at a voltage equal to VS/4 or
power-supply
connection
should
always
be
decoupled with one of these capacitors. An optional
supply decoupling capacitor (0.1µF) across the two
power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
2
3VS/4. Under this condition, PDL = VS /(4 × RL), where
RL includes feedback network loading.
Note that it is the power in the output stage, and not
into the load, that determines internal power
dissipation.
As a worst-case example, compute the maximum TJ
using an OPA3832 (TSSOP-14 package) in the circuit
of Figure 48 operating at the maximum specified
ambient temperature of +85°C and driving both
channels at a 150Ω load at mid-supply.
c) Careful selection and placement of external
components will preserve the high-frequency
performance. Resistors should be
a very low
reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal film or carbon
composition axially-leaded resistors can also provide
good high-frequency performance. Again, keep the
leads and PCB traces as short as possible. Never
use wire-wound type resistors in a high-frequency
application. Since the output pin and inverting input
pin are the most sensitive to parasitic capacitance,
always position the series output resistor, if any, as
close as possible to the output pin. Other network
components, such as noninverting input termination
resistors, should also be placed close to the package.
3
52
150W 800W
PD
10V 12.75mA
276mV
4
Maximum TJ
85°C
0.276W 100°C W
113°C
Although this value is still well below the specified
maximum junction temperature, system reliability
considerations may require lower ensured junction
temperatures. The highest possible internal
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d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the typical characteristic curve, Figure 5.
Low parasitic capacitive loads (< 5pF) may not need
an RS since the OPA3832 is nominally compensated
to operate with a 2pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded phase
margin). If a long trace is required, and the 6dB
e) Socketing
a
high-speed part is not
recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
that can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA3832 directly onto the
board.
INPUT AND ESD PROTECTION
The OPA3832 is built using a very high-speed,
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 56.
signal loss intrinsic to
a
doubly-terminated
transmission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook
for microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary onboard, and
in fact, a higher impedance environment will improve
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance defined
(based on board material and trace dimensions), a
matching series resistor into the trace from the output
of the OPA3832 is used as well as a terminating
shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the
input impedance of the destination device; this total
effective impedance should be set to match the trace
+VCC
External
Pin
Internal
Circuitry
-VCC
Figure 56. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (that is, in systems with ±15V supply parts
driving into the OPA3832), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible, since high
values degrade both noise performance and
frequency response.
impedance. If the 6dB attenuation of
a
doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in this
case and set the series resistor value as shown in the
typical characteristic curve, Figure 5. This
configuration will not preserve signal integrity as well
as a doubly-terminated line. If the input impedance of
the destination device is low, there will be some
signal attenuation as a result of the voltage divider
formed by the series output into the terminating
impedance.
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Revision History
Changes from Original (December 2006) to Revision A ................................................................................................ Page
•
•
•
Deleted grey from rows labelled as D in the package designator rows in the Ordering Information table............................ 2
Deleted footnote (2) from the Ordering Information table...................................................................................................... 2
Changed storage voltage range row in Absolute Maximum Ratings table to storage temperature range with a rating
of –65°C to +125°C................................................................................................................................................................ 2
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Product Folder Link(s): OPA3832
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA3832ID
ACTIVE
ACTIVE
SOIC
D
14
14
50
90
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
OPA3832
OPA3832
OPA3832IPW
TSSOP
PW
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA3832ID
D
SOIC
14
14
50
90
506.6
530
8
3940
3600
4.32
3.5
OPA3832IPW
PW
TSSOP
10.2
Pack Materials-Page 1
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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