OPA3875 [TI]
具有 2:1 高速多路复用器的三通道、700MHz 运算放大器;
| 型号： | OPA3875 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 2:1 高速多路复用器的三通道、700MHz 运算放大器 放大器 运算放大器 复用器 |
| 文件： | 总27页 (文件大小：796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA3875
www.ti.com ............................................................................................................................................ SBOS341D–DECEMBER 2006–REVISED AUGUST 2008
Triple 2:1 High-Speed Video Multiplexer
1
FEATURES
DESCRIPTION
2
•
700MHz SMALL-SIGNAL BANDWIDTH
(AV = +2)
The OPA3875 offers a very wideband, 3-channel, 2:1
multiplexer in a small SSOP-16 package. Using only
11mA/ch, the OPA3875 provides three, gain of +2,
video amplifier channels with greater than 400MHz
large-signal bandwidth (4VPP). Gain accuracy and
switching glitch are improved over earlier solutions
•
•
•
•
•
•
•
425MHz, 4VPP BANDWIDTH
0.1dB GAIN FLATNESS to 150MHz
4ns CHANNEL SWITCHING TIME
LOW SWITCHING GLITCH: 40mVPP
3100V/µs SLEW RATE
using
a new (patented) input stage switching
approach. This technique uses current steering as the
input switch while maintaining an overall closed-loop
design. Gain matching between each of the
3-channel pairs is also significantly improved using
this technique (<0.2% gain mismatch). With greater
than 700MHz small-signal bandwidth at a gain of 2,
the OPA3875 gives a typical 0.1dB gain flatness to
greater than 150MHz.
0.025%/0.025° DIFFERENTIAL GAIN, PHASE
HIGH GAIN ACCURACY: 2.0V/V ±0.4%
APPLICATIONS
•
•
•
•
•
RGB SWITCHING
LCD PROJECTOR INPUT SELECT
WORKSTATION GRAPHICS
TRIPLE ADC INPUT MUX
DROP-IN UPGRADE TO LT1675
System power may be reduced using the chip enable
feature for the OPA3875. Taking the chip enable line
high powers down the OPA3875 to less than 900µA
total supply current. Muxing multiple OPA3875
outputs together, then using the chip enable to select
which channels are active, increases the number of
possible inputs to the 3-channel outputs.
+5V
75W
75W
Where a single channel of the OPA3875 is required,
consider the OPA875.
RGB
Channel 0
75W
75W
OPA3875
SELECT ENABLE RED OUT GREEN OUT BLUE OUT
1
0
X
0
0
1
R0
R1
Off
G0
G1
Off
B0
B1
Off
75W
RGB
Out
OPA3875
(Patented)
75W
75W
75W
OPA3875 RELATED PRODUCTS
RGB
75W
Channel 1
DESCRIPTION
OPA875
OPA4872
OPA3693
Single-Channel OPA3875
Quad 510MHz 4:1 Multiplexer
Triple 650MHz Video Buffer
-5V
EN
Channel
Select
RGB Switching
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
OPA3875
SBOS341D–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA3875IDBQ
Rails, 75
OPA3875
SSOP-16
DBQ
–45°C to +85°C
OP3875
OPA3875IDBQR
Tape and Reel, 2500
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range, unless otherwise noted.
OPA3875
UNIT
Power Supply
±6.5
V
Internal Power Dissipation
Input Voltage Range
See Thermal Analysis
±VS
–65 to +125
+260
V
Storage Temperature Range
Lead Temperature (soldering, 10s)
Operating Junction Temperature
Continuous Operating Junction Temperature
ESD Rating:
°C
°C
°C
°C
+150
+140
Human Body Model (HBM)
Charge Device Model (CDM)
Machine Model (MM)
2000
1500
200
V
V
V
PIN CONFIGURATION
Top View
SSOP
OPA3875
V+
R0
G0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
x2
x2
x2
OUT_R
OUT_G
OUT_B
V-
B0
GND
GND
R1
V-
SEL
G1
EN
B1
SSOP-16
2
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OPA3875
www.ti.com ............................................................................................................................................ SBOS341D–DECEMBER 2006–REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
At G = +2, RL = 150Ω, unless otherwise noted.
OPA3875
MIN/MAX OVER
TYP
TEMPERATURE
0°C to
70°C(3)
–40°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
See Figure 1
+25°C
+25°C(2)
+85°C(3)
UNITS
LEVEL(1)
AC PERFORMANCE
Small-Signal Bandwidth
Large-Signal Bandwidth
Bandwidth for 0.1dB Gain Flatness
Maximum Small-Signal Gain
Minimum Small-Signal Gain
SFDR
VO = 200mVPP, RL = 150Ω
VO = 4VPP, RL = 150Ω
VO = 200mVPP
700
425
150
2.0
525
390
515
380
505
370
MHz
MHz
MHz
V/V
min
min
typ
B
B
C
B
B
B
B
B
C
C
B
C
C
VO = 200mVPP, RL = 150Ω, f = 5MHz
VO = 200mVPP, RL = 150Ω, f = 5MHz
10MHz, VO = 2VPP, RL = 150Ω
f > 100kHz
2.02
1.98
–65
7.0
2.03
1.97
–64
7.2
2.05
1.95
–63
7.4
max
min
max
max
max
typ
2.0
V/V
–68
6.7
dBc
nV/√Hz
pA/√Hz
%
Input Voltage Noise
Input Current Noise
f > 100kHz
3.8
4.2
4.6
4.9
NTSC Differential Gain
NTSC Differential Phase
Slew Rate
RL = 150Ω
0.025
0.025
3100
460
600
RL = 150Ω
°
typ
VO = ±2V
2800
2700
2600
V/µs
ps
min
typ
Rise Time and Fall Time
VO = 0.5V Step
VO = 1.4V Step
ps
typ
CHANNEL-TO-CHANNEL PERFORMANCE
Gain Match
Channel to Channel, RL = 150Ω
All inputs, RL = 150Ω
All three outputs
±0.05
±0.1
±3
±0.25
±0.5
±9
±0.3
±0.6
±10
±0.35
±0.7
±12
%
%
max
max
max
typ
A
A
A
C
C
Output Offset Voltage Mismatch
All Hostile Crosstalk
mV
dB
dB
f = 50MHz, RL = 150Ω
f = 50MHz, RL = 150Ω
–50
–58
Channel-to-Channel Crosstalk
typ
CHANNEL AND CHIP-SELECT PERFORMANCE
SEL (Channel Select) Swtiching Time
EN (Chip Select) Switching Time
RL = 150Ω
4
9
ns
ns
typ
typ
C
C
C
C
C
C
B
B
A
A
Turn On
Turn Off
60
40
15
–68
ns
typ
SEL (Channel Select) Switching Glitch
EN (Chip-Select) Switching Glitch
All Hostile Disable Feedthrough
Maximum Logic 0
All Inputs to Ground, At Matched Load
All Inputs to Ground, At Matched Load
50MHz, Chip Disabled (EN = High)
EN, SEL
mVPP
mVPP
dB
typ
typ
typ
0.8
2.0
0.8
2.0
0.8
2.0
V
max
min
max
max
Minimum Logic 1
EN, SEL
V
EN Logic Input Current
SEL Logic Input Current
DC PERFORMANCE
Output Offset Voltage
Average Output Offset Voltage Drift
Input Bias Current
0V to 4.5V
75
100
200
125
250
150
300
µA
0V to 4.5V
160
µA
RIN = 0Ω, G = +2V/V
RIN = 0Ω, G = +2V/V
±2.5
±5
±14
±18
1.4
±15.8
±50
±17
±50
mV
µV/°C
µA
max
max
max
max
max
A
B
A
B
A
±19.5
±40
±20.5
±40
Average Input Bias Current Drift
Gain Error (from 2V/V)
INPUT
nA/°C
%
VO = ±2V
0.4
1.5
1.6
Input Voltage Range
±2.8
1.75
0.9
V
MΩ
pF
pF
pF
typ
typ
typ
typ
typ
C
C
C
C
C
Input Resistance
Input Capacitance
Channel Selected
Channel Deselected
Chip Disabled
0.9
0.9
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C tested specifications.
(3) Junction temperature = ambient at low temperature limit; junction temperature = ambient +36°C at high temperature limit for over
temperature specifications.
Copyright © 2006–2008, Texas Instruments Incorporated
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SBOS341D–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2, RL = 150Ω, unless otherwise noted.
OPA3875
MIN/MAX OVER
TYP
TEMPERATURE
0°C to
70°C(3)
–40°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(2)
+85°C(3)
UNITS
LEVEL(1)
OUTPUT
Output Voltage Range
Output Current
Output Resistance
±3.5
±70
0.3
800
800
2
±3.4
±50
±3.35
±45
±3.3
±40
V
mA
Ω
min
min
typ
A
A
C
A
A
C
VO = 0V, Linear Operation
Chip enabled
Chip Disabled, Maximum
Chip Disabled, Minumum
Chip Disabled
912
688
915
685
918
682
Ω
max
min
typ
Ω
Output Capacitance
pF
POWER SUPPLY
Specified Operating Voltage
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Maximum Quiescent Current
Power-Supply Rejection Ratio
±5
V
V
typ
min
max
max
min
max
min
min
C
B
A
A
A
A
A
A
±3.0
±6.3
34
±3.0
±6.3
35
±3.0
±6.3
36
V
Chip Selected, VS = ±5V
Chip Selected, VS = ±5V
Chip Deselected
33
33
0.9
56
55
mA
mA
mA
dB
dB
31
30
27
1.2
50
1.4
48
1.5
47
(+PSRR)
(–PSRR)
Input-Referred
Input-Referred
51
49
48
THERMAL CHARACTERISTICS
Specified Operating Range D Package
–40 to +85
85
°C
typ
typ
C
C
Thermal Resistance θJA
Junction-to-Ambient
DBQ
SSOP-16
°C/W
4
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OPA3875
www.ti.com ............................................................................................................................................ SBOS341D–DECEMBER 2006–REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V
At G = +2 and RL = 150Ω, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
7
6
1
4
3
2
1
0
0.3
8
7
Frequency Response
Left Scale
RL = 150W
G = +2V/V
0.2
6
5
0.1
4
0
3
VO = 4VPP
Gain Flatness
Right Scale
2
-0.1
-0.2
-0.3
-0.4
1
VO = 1VPP
0
VO = 500mVPP
-1
-2
-3
VO = 5VPP
VO = 2VPP
RL = 150W
G = +2V/V
1M
10M
100M
Frequency (Hz)
1G
0
100 200 300 400 500 600 700 800 900 1000
Frequency (100MHz/div)
Figure 1.
Figure 2.
NONINVERTING PULSE RESPONSE
ALL INPUT DISABLE FEEDTHROUGH vs FREQUENCY
-20
0.5
0.4
2.5
RL = 150W
Input-Referred
EN = +5V
2.0
-30
-40
G = +2V/V
Large-Signal 4VPP
Right Scale
0.3
1.5
0.2
1.0
-50
Small-Signal 0.4VPP
Left Scale
0.1
0.5
-60
0
0
-70
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
-1.0
-1.5
-2.0
-2.5
-80
-90
-100
-110
100MHz Square-Wave Input
Time (1ns/div)
1M
10M
100M
Frequency (Hz)
1G
Figure 3.
Figure 4.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
80
70
60
50
40
30
20
10
0
8
7
0.1dB Peaking Targeted
CL = 10pF
6
5
4
3
CL = 47pF
2
1
RS
CL = 100pF
x2
75W
0
(1)
CL
1kW
-1
-2
-3
CL = 22pF
75W
NOTE: (1) 1kW is optional.
1
10
100
1000
1
10
100
400
Capacitive Load (pF)
Frequency (MHz)
Figure 5.
Figure 6.
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SBOS341D–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
-60
-65
-70
-75
-80
-85
-90
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
VO = 2VPP
f = 10MHz
VO = 2VPP
RL = 150W
f = 10MHz
2nd-Harmonic
2nd-Harmonic
3rd-Harmonic
3rd-Harmonic
dBc = dB Below Carrier
dBc = dB Below Carrier
100
1k
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Resistance (W)
Supply Voltage (±V)
Figure 7.
Figure 8.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
VO = 2VPP
RL = 150W
RL = 150W
f = 10MHz
2nd-Harmonic
2nd-Harmonic
3rd-Harmonic
3rd-Harmonic
dBc = dB Below Carrier
dBc = dB Below Carrier
0.5
1.5
2.5
3.5
4.5
5.5
6.5 7.0
1
10
100
Output Voltage Swing (VPP
)
Frequency (MHz)
Figure 9.
Figure 10.
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-50
RL = 100W
OUTPUT VOLTAGE AND CURRENT LIMITIATIONS
5
4
1W Internal
Power Limit
Load Power at Matched 50W Load
3
-60
-70
dBc = dB Below Carrier
2
100W Load Line
25W Load Line
1
0
50MHz
-1
-2
-3
-4
-5
-80
20MHz
10MHz
50W Load Line
-90
1W Internal
Power Limit
-100
-200 -150 -100 -50
0
50
100
150
200
-6
-4
-2
0
2
4
6
8
10
IO (mA)
Single-Tone Load Power (dBm)
Figure 11.
Figure 12.
6
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www.ti.com ............................................................................................................................................ SBOS341D–DECEMBER 2006–REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
CHANNEL SWITCHING
CHANNEL-TO-CHANNEL SWITCHING TIME
1.5
1.0
1.5
1.0
0.5
0.5
Output Voltage
0
0
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
Output Voltage
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VSEL
VSEL
RL = 150W
VIN_Ch0 = +0.5VDC
VIN_Ch1 = 400MHz, 1VPP
VIN_Ch0 = 0VDC
VIN_Ch1 = -0.5VDC
-0.5
-0.5
Time (5ns/div)
Time (5ns/div)
Figure 13.
Figure 14.
CHANNEL SWITCHING GLITCH
DISABLE/ENABLE TIME
40
1.5
1.0
30
20
Output Voltage
At Matched Load
(0V input both channels)
0.5
0
10
-0.5
-1.0
-1.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-10
-20
VEN
6
VSEL
4
2
VIN_Ch1 = 0V
0
VIN_Ch0 = 200MHz, 1VPP
-2
-0.5
Time (20ns/div)
Time (10ns/div)
Figure 15.
Figure 16.
DISABLE/ENABLE SWITCHING GLITCH
CHANNEL-TO-CHANNEL CROSSTALK
20
15
10
5
-20
-30
-40
-50
-60
-70
-80
-90
Input-Referred
At Matched Load
0
B0 Selected
B1 Driven
-5
-10
6
4
2
0
R1 Selected
R0 Driven
VEN
-2
1M
10M
100M
Frequency (Hz)
1G
Time (100ns/div)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
ALL HOSTILE AND ADJACENT-CHANNEL CROSSTALK vs
FREQUENCY
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
10k
Input-Referred
Disabled
1k
100
10
Adjacent Channel Crosstalk
1
All Hostile Crosstalk
Enabled
0.1
1M
10M
100M
Frequency (Hz)
1G
100k
1M
10M
100M
1G
Frequency (Hz)
Figure 19.
INPUT IMPEDANCE vs FREQUENCY
Figure 20.
PSRR vs FREQUENCY
10M
1M
60
50
40
30
20
10
0
-PSRR
+PSRR
100k
10k
1k
100
100k
1M
10M
100M
1G
100
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Figure 21.
Frequency (Hz)
Figure 22.
SUPPLY CURRENT vs TEMPERATURE
TYPICAL DC DRIFT OVER TEMPERATURE
40
38
36
34
32
30
28
26
24
22
20
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
Output Offset Voltage (VOS
)
Left Scale
Input Bias Current (IB)
Right Scale
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 23.
Figure 24.
8
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OPA3875
www.ti.com ............................................................................................................................................ SBOS341D–DECEMBER 2006–REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE
100
10
Voltage Noise (6.7nV/ÖHz)
Input Current Noise (3.8pA/ÖHz)
1
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 25.
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APPLICATIONS INFORMATION
that the 75Ω input matching impedance is set here by
the parallel combination of 92Ω and 402Ω. In order
not to disturb the sync, color burst, and blanking if
present, the inverting amplifiers are only switched on
during active video.
2:1 HIGH-SPEED VIDEO MULTIPLEXER
OPERATION
The OPA3875 can be used as a triple 2:1 high-speed
video multiplexer, as illustrated in the front page
schematic for an RGB signal. Figure 26 shows a
simplified version of the front page schematic in
which one output is shown with its input and output
impedance matching resistors.
LOGO INSERTER
Figure 28 illustrates the principle of overlaying a
picture in a picture. The picture comes through U1;
the signal to be overlayed comes through U2. Here
we have a reference voltage of 0.714V in channel 2
indicating that we will highlight a section of the picture
with white (for NTSC-related RGB video). How much
white comes through depends on the combination of
select 1 and select 2 pins as well as the series output
resistance of each OPA3875. To match the 75Ω
output impedance of the video cable, the parallel
combination of the series output resistance (R and
nR) needs to be 75Ω. The two select pins gives us 2
bits of control. By selecting n = 2, you have the
capability of a 0% highlight (full original video signal),
33% highlight, 66% highlight, and 100% highlight (all
white). By selecting n = 3, you have 0%, 25%, 75%,
and 100% highlight capabilities, etc.
RGB VIDEO INVERTER
Figure 27 illustrates an extension of the previously
shown RGB switching circuit with a noninverting
signal going through channel 1 and an inverted signal
going through channel two. Here, the output
impedance of the OPA3875 is set to 75Ω. Looking at
the input part of this circuit, we see that the RGB
signal is inverted with an OPA3693 fixed gain set in
an inverting configuration with a reference voltage on
the noninverting node. The reference voltage, set
here at 0.714V, has a gain of 1 at the output of the
OPA3691 as the input signal is AC-coupled (not
represented here). This bias voltage is required to
prevent the video from swinging negative. Note also
+5V
1/3 OPA3875
VIN_1
x1
75W
75W
VOUT
402W
402W
VIN_2
x1
75W
-5V
EN
Channel
Select
Figure 26. Triple 2:1 High-Speed Video Multiplexer
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+5V
OPA3875
RIN
GIN
BIN
x1
x1
x1
75W
75W
75W
92W
92W
92W
ROUT
GOUT
BOUT
402W
402W
300W
402W
300W
300W
300W
1/3
402W
x1
x1
OPA3693
VREF
VREF
VREF
300W
402W
1/3
OPA3693
402W
300W
1/3
x1
OPA3693
Channel
Select
VREF = 0.749V
-5V
EN
Figure 27. RGB Video Inverter
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+5V
U1
OPA3875
RIN
x1
x1
x1
x1
x1
x1
RO
RO
RO
75W
75W
75W
ROUT
GOUT
BOUT
402W
402W
GIN
BIN
402W
402W
402W
402W
VREF
-5V
EN
Select 1
Select 2
U2
OPA3875
x1
x1
x1
x1
x1
x1
nRO
nRO
nRO
402W
402W
402W
402W
402W
402W
VREF = 0.714V
RO || nRO = 75W
VREF
-5V
EN
Figure 28. Logo Inserter
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ADC INPUT MUX
Figure 29 shows the OPA3875 used as a multiplexer in a high-speed data acquisition signal chain.
+5V
250W
OPA3875
+3.3V
VCC
VIN1
x1
250W
250W
IN
IN
1/2
VCM
ADS5232
402W
402W
250W
250W
+3.3V
VCC
VIN2
x1
250W
IN
IN
1/2
VCM
250W
ADS5232
402W
402W
250W
250W
+3.3V
VCC
VIN3
x1
x1
x1
x1
250W
250W
IN
IN
1/2
VCM
ADS5232
402W
VIN4
402W
250W
VIN5
VIN6
-5V
Channel
Select
EN
Figure 29. ADC Input Multiplexer
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DESIGN-IN TOOLS
problem have been suggested. When the primary
considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest
and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series
isolation resistor between the amplifier output and the
capacitive load. This isolation resistor does not
eliminate the pole from the loop response, but rather
shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the
capacitive load pole, thus increasing the phase
margin and improving stability.
DEMONSTRATION FIXTURE
A printed circuit board (PCB) is available to assist in
the initial evaluation of circuit performance using the
OPA3875. The fixture is offered free of charge as an
unpopulated PCB, delivered with a user's guide. The
summary information for this fixture is shown in
Table 1.
Table 1. OPA3875 Demonstration Fixture
LITERATURE
NUMBER
The Typical Characteristics show the recommended
RS versus capacitive load and the resulting frequency
response at the load; see Figure 5 and Figure 6,
respectively. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the
OPA3875. Long PCB traces, unmatched cables, and
connections to multiple devices can easily cause this
value to be exceeded. Always consider this effect
carefully, and add the recommended series resistor
as close as possible to the OPA3875 output pin (see
the Board Layout Guidelines section).
PRODUCT
PACKAGE
ORDERING NUMBER
OPA3875IDBQ
SSOP-16
DEM-OPA-SSOP-3E
SBOU043
The demonstration fixture can be requested at the
Texas Instruments web site at (www.ti.com) through
the OPA3875 product folder.
MACROMODELS AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF amplifier circuits
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the OPA875 is available through the Texas
Instruments web site at www.ti.com. Use three of
these models to simulate the OPA3875. These
models do a good job of predicting small-signal AC
and transient performance under a wide variety of
operating conditions. They do not do as well in
predicting the harmonic distortion or dG/dP
characteristics. These models do not attempt to
distinguish between the package types in their
small-signal AC performance nor do they predict
channel-to-channel effects.
DC ACCURACY
The OPA3875 offers excellent DC signal accuracy.
Parameters that influence the output DC offset
voltage are:
•
•
•
•
•
Output offset voltage
Input bias current
Gain error
Power-supply rejection ratio
Temperature
Leaving both temperature and gain error parameters
aside, the output offset voltage envelope can be
described as shown in Equation 1:
PSRR+
VOSO_envelope = VOSO + (RS·Ib) x G ± |5 - (VS+)| x 10-
20
PSRR-
20
CMRR
20
± |-5 - (VS+)| x 10-
+ VCM x 10-
OPERATING SUGGESTIONS
(1)
With:
VOSO: Output offset voltage
DRIVING CAPACITIVE LOADS
RS: Input resistance seen by R0, R1, G0, G1, B0,
or B1.
Ib: Input bias current
G: Gain
VS+: Positive supply voltage
VS–: Negative supply voltage
PSRR+: Positive supply PSRR
PSRR–: Negative supply PSRR
One of the most demanding, yet very common load
conditions is capacitive loading. Often, the capacitive
load is the input of an ADC—including additional
external capacitance that may be recommended to
improve ADC linearity. A high-speed device such as
the OPA3875 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the device open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
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Evaluating the front-page schematic, using
a
NOISE PERFORMANCE
worst-case, +25°C offset voltage, bias current and
PSRR specifications and operating at ±6V, gives a
worst-case output equal to Equation 2:
The OPA3875 offers an excellent balance between
voltage and current noise terms to achieve low output
noise. As long as the AC source impedance looking
out of the noninverting node is less than 100Ω, this
current noise will not contribute significantly to the
total output noise. Figure 30 shows this device noise
analysis model with all the noise terms included. In
this model, all noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
pA/√Hz.
50
-
20
14mV + 75W x 18mA x 2 ± |5 - 6| x 10
51
20
-
± |-5 - (-6)| x 10
= ±22.7mV
(2)
DISTORTION PERFORMANCE
+5V
The OPA3875 provides good distortion performance
into a 100Ω load on ±5V supplies. Relative to
alternative solutions, it provides exceptional
performance into lighter loads. Generally, until the
fundamental signal reaches very high frequency or
power levels, the 2nd-harmonic dominates the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the
load impedance improves distortion directly. Also,
providing an additional supply decoupling capacitor
(0.01µF) between the supply pins (for bipolar
operation) improves the 2nd-order distortion slightly
(3dB to 6dB).
en
1/3 OPA3875
x1
x1
RS
ib
eo
eRS
4kTRS
402W
402W
-5V
Channel
Select
EN
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The Typical
Characteristics show the 2nd-harmonic increasing at
a little less than the expected 2X rate while the
3rd-harmonic increases at a little less than the
expected 3X rate. Where the test power doubles, the
2nd-harmonic increases only by less than the
expected 6dB, whereas the 3rd-harmonic increases
by less than the expected 12dB. This also shows up
in the two-tone, 3rd-order intermodulation spurious
(IM3) response curves. The 3rd-order spurious levels
are extremely low at low output power levels. The
output stage continues to hold them low even as the
fundamental power reaches very high levels. As the
Figure 30. Noise Model
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 3 shows the
general form for the output noise voltage using the
terms shown in Figure 30.
en2 + (ibRS)2 + 4kTRS
eo = 2
(3)
Dividing this expression by the device gain (2V/V)
gives the equivalent input-referred spot noise voltage
at the noninverting input as shown in Equation 4.
Typical
Characteristics
show,
the
spurious
en2 + (ibRS)2 + 4kTRS
intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not
decrease significantly. For two tones centered at
20MHz, with 4dBm/tone into a matched 50Ω load
(that is, 1VPP for each tone at the load, which requires
4VPP for the overall 2-tone envelope at the output
pin), the Typical Characteristics show a 82dBc
difference between the test-tone power and the
3rd-order intermodulation spurious levels.
en =
(4)
Evaluating these two equations for the OPA3875
circuit and component values shown in Figure 26
gives a total output spot noise voltage of 13.6nV/√Hz
and a total equivalent input spot noise voltage of
6.8nV/√Hz. This total input-referred spot noise
voltage is higher than the 6.7nV/√Hz specification for
the mux voltage noise alone. This number reflects the
noise added to the output by the bias current noise
times the source resistor.
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THERMAL ANALYSIS
b) Minimize the distance (< 0.25") from the
power-supply pins to high frequency 0.1µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections (on pins 9, 11, 13, and 15)
should always be decoupled with these capacitors.
An optional supply decoupling capacitor across the
two power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
Heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired
junction temperature will set the maximum allowed
internal power dissipation as discussed in this
document. In no case should the maximum junction
temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by TA
+
PD × θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load but, for a grounded resistive load, is
at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal bipolar
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA3875. Resistors should be
a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially leaded resistors can
also provide good high-frequency performance.
Again, keep their leads and PCB trace length as short
as possible. Never use wirewound type resistors in a
2
supplies). Under this condition PDL = VS /(4 × RL),
where RL includes feedback network loading.
Note that it is the power in the output stage and not in
the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ
using an OPA3875 in the circuit of Figure 26
operating at the maximum specified ambient
temperature of +85°C with all three outputs driving a
grounded 100Ω load to +2.5V:
high-frequency
application.
Other
network
components, such as noninverting input termination
resistors, should also be placed close to the package.
PD = 10V ´ 36mA + 3(52/4 ´ (100W || 804W)) = 571mW
Maximum TJ = +85°C + (0.57W ´ 85°C/W) = 133°C
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the plot of Figure 5. Low parasitic
capacitive loads (< 5pF) may not need an RS
because the OPA3875 is nominally compensated to
operate with a 2pF parasitic load. If a long trace is
required, and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally
not necessary on board, and in fact, a higher
impedance environment will improve distortion as
shown in the Distortion versus Load plots.
This worst-case condition is approaching the
maximum +150°C junction temperature. Normally,
this extreme case is not encountered. Careful
attention to internal power dissipation is required.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with
a
high
frequency amplifier such as the OPA3875 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a) Minimize parasitic capacitance to any AC
ground for all of the signal I/O pins. Parasitic
capacitance on the output pin can cause instability:
on the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To
reduce unwanted capacitance, a window around the
signal I/O pins should be opened in all of the ground
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.
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With a characteristic board trace impedance defined
based on board material and trace dimensions, a
matching series resistor into the trace from the output
of the OPA3875 is used as well as a terminating
shunt resistor at the input of the destination device.
Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and
the input impedance of the destination device; this
total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA3875 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If
INPUT AND ESD PROTECTION
The OPA3875 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins have limited ESD protection using internal
diodes to the power supplies as shown in Figure 31.
+VCC
External
Pin
Internal
Circuitry
the 6dB attenuation of
a
doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the
series resistor value as shown in Figure 5. This will
-VCC
not preserve signal integrity as well as
a
Figure 31. Internal ESD Protection
doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA3875), current-limiting
series resistors should be added into the two inputs.
Keep these resistor values as low as possible
because high values degrade both noise performance
and frequency response.
e) Socketing a high-speed part like the OPA3875
is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA3875 onto the board.
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Revision History
Changes from Revision C (September 2007) to Revision D .......................................................................................... Page
•
Changed storage temperature range rating in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to
+125°C................................................................................................................................................................................... 2
Changes from Revision B (December 2006) to Revision C ........................................................................................... Page
•
Changed the ordering number column in Table 1. .............................................................................................................. 14
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA3875IDBQ
ACTIVE
ACTIVE
SSOP
SSOP
DBQ
DBQ
16
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
OP3875
OP3875
OPA3875IDBQR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA3875IDBQR
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DBQ 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
OPA3875IDBQR
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DBQ SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA3875IDBQ
16
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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