OPA387DBVT [TI]
超高精度 (2uV)、零漂移 (0.003uV/°C)、低输入偏置电流运算放大器（单路） | DBV | 5 | -40 to 125;
| 型号： | OPA387DBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 超高精度 (2uV)、零漂移 (0.003uV/°C)、低输入偏置电流运算放大器（单路） | DBV | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总39页 (文件大小：3347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA387, OPA2387, OPA4387
ZHCSMQ4F –NOVEMBER 2020 –REVISED FEBRUARY 2022
OPAx387 超高精度、零漂移、低输入偏置电流运算放大器
1 特性
3 说明
• 超低失调电压：±2µV（最大值，已测试）
• 零漂移：±0.003µV/°C
• 低输入偏置电流：150pA（最大值，已测试）
• 低噪声：1 kHz 时为8.5 nV√Hz
• 无1/f 噪声：177nVPP（0.1Hz 至10Hz）
• 共模输入范围超出电源轨±100mV
• 增益带宽：5.7 MHz
OPA387、OPA2387 和 OPA4387 (OPAx387) 精密放
大器系列提供出色的性能。通过零漂移技术，
OPAx387 的失调电压和失调漂移可提供出色的长期稳
定性。仅需 570 µA 的静态电流，OPAx387 就能实现
5.7 MHz 的带宽、8.5 nV/√Hz 的宽带噪声和 177
nVPP 的 1/f 噪声。这些规格对于在 16 位至 24 位模数
转换器 (ADC) 中实现超高精度和不降低线性度至关重
要。OPAx387 在温度范围内具有平坦的偏置电流；因
此，高输入阻抗应用在温度范围内几乎不需校准。
• 静态电流：每个放大器570µA
• 单电源：1.7V 至5.5V
• 双电源：±0.85V 至±2.75V
• 输入已滤除EMI 和RFI
所有版本的额定工作温度范围均为-40°C 至+125°C。
器件信息
封装(1)
2 应用
封装尺寸（标称值）
1.50mm × 1.50mm
2.90mm × 1.60mm
4.90mm × 3.90mm
3.00mm × 3.00mm
2.00mm × 2.00mm
5.00mm × 4.40mm
器件型号
OPA387
DFN (6)(2)
• 电子温度计
• 称重计
• 温度变送器
• 呼吸机
• 数据采集(DAQ)
• 半导体测试
• 实验室和现场仪表
• 商用网络和服务器PSU
• 模拟输入模块
• 压力变送器
SOT-23 (5)
SOIC (8)(2)
VSSOP (8)
WSON (8)
TSSOP (14)
OPA2387
OPA4387
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
(2) 封装为预发布版。
50
45
40
35
30
25
20
15
10
5
ADC
OPA387
Object
Radiation
Detector
OPA387 是一款超低失调、低噪声ADC 驱动器
0
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Input Offset Voltage (mV)
c110
超低输入失调电压
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS984
OPA387, OPA2387, OPA4387
ZHCSMQ4F –NOVEMBER 2020 –REVISED FEBRUARY 2022
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Table of Contents
7.4 Device Functional Modes..........................................17
8 Application and Implementation..................................18
8.1 Application Information............................................. 18
8.2 Typical Applications.................................................. 18
9 Power Supply Recommendations................................21
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Documentation Support.......................................... 22
11.3 接收文档更新通知................................................... 22
11.4 支持资源..................................................................22
11.5 Trademarks............................................................. 22
11.6 Electrostatic Discharge Caution..............................22
11.7 术语表..................................................................... 23
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information: OPA387.................................... 8
6.5 Thermal Information: OPA2387.................................. 8
Thermal Information: OPA4387........................................ 8
6.6 Electrical Characteristics.............................................9
6.7 Typical Characteristics.............................................. 11
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................17
Information.................................................................... 23
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (December 2021) to Revision F (February 2022)
Page
• 添加了OPA2387 DSG (WSON-8) 封装和相关内容............................................................................................1
Changes from Revision D (October 2021) to Revision E (December 2021)
Page
• 将OPA4387 器件状态从“预告信息（预发布）”更改为“量产数据（正在供货）”....................................... 1
Changes from Revision C (October 2021) to Revision D (October 2021)
Page
• 添加了OPA4387 预告信息（预发布）器件和相关内容...................................................................................... 1
• 将低输入偏置电流的“特性”要点从135pA 更改为150pA................................................................................1
• Deleted input offset voltage MAX values for over temperature and common-mode voltage test conditions for
clarity.................................................................................................................................................................. 9
• Added input offset voltage over temperature TYP value to represent performance shown in typical
characteristics ....................................................................................................................................................9
• Changed maximum input bias current for OPA387 and OPA2387 from 135 pA to 150 pA................................ 9
• Changed maximum input offset current for OPA387 and OPA2387 from 270 pA to 300 pA..............................9
• Changed maximum open-loop voltage gain for OPA387 and OPA2387 from 132 dB to 135 dB....................... 9
• Changed settling time to 0.01% from 2.5 µs to 5.5 µs........................................................................................9
• Changed high linearity output swing from rail for RL = 2 kΩfrom 75 mV to 150 mV ........................................9
• Changed short-circuit current for OPA387 at Vs = 1.7 V from ±25 mA to ±15 mA .......................................... 9
• Added open-loop output impedance at 1 MHz .................................................................................................. 9
• Changed Figure 6-13, PSRR and CMRR vs Frequency, to fit to CMRR and PSRR specifications in the
Electrical Characteristic table ...........................................................................................................................11
• Changed Figure 6-24, Phase Margin vs Capacitive Load, to add test condition.............................................. 11
Changes from Revision B (August 2021) to Revision C (October 2021)
Page
• 将OPA387 从预告信息（预发布）更改为量产数据（正在供货）...................................................................... 1
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Changes from Revision A (December 2020) to Revision B (August 2021)
Page
• 添加了OPA387 预告信息（预发布）器件和相关内容........................................................................................ 1
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5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
+IN
4
œIN
Not to scale
图5-1. OPA387: DBV (5-Pin SOT-23) Package, Top View
表5-1. Pin Functions: OPA387
PIN
TYPE
DESCRIPTION
NAME
NO.
4
Input
Input
Inverting input
–IN
+IN
NC
3
Noninverting input
No internal connection (can be left floating)
Output
—
—
OUT
V–
V+
1
Output
2
5
Power
Power
Negative (lowest) power supply
Positive (highest) power supply
OUT A
1
2
3
4
8
7
6
5
V+
OUT A
œIN A
+IN A
Vœ
V+
1
2
3
4
8
7
6
5
œIN A
+IN A
Vœ
OUT B
œIN B
+IN B
OUT B
Thermal
Pad
œIN B
+IN B
Not to scale
Not to scale
图5-2. OPA2387: DGK (8-Pin VSSOP) Package, Top
图5-3. OPA2387: DSG (8-Pin WSON With Exposed
View
Thermal Pad) Package, Top View
表5-2. Pin Functions: OPA2387
PIN
NO.
DGK (VSSOP) DSG (WSON)
TYPE
DESCRIPTION
NAME
–IN A
2
6
3
5
1
7
4
8
2
6
3
5
1
7
4
8
Input
Input
Inverting input, channel A
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Output, channel A
–IN B
+IN A
+IN B
OUT A
OUT B
V–
Input
Input
Output
Output
Power
Power
Output, channel B
Negative (lowest) power supply
Positive (highest) power supply
V+
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表5-2. Pin Functions: OPA2387 (continued)
PIN
NO.
TYPE
DESCRIPTION
NAME
DGK (VSSOP) DSG (WSON)
Thermal Pad
Thermal pad
Connect thermal pad to V–
—
—
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OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
图5-4. OPA4387: PW (14-Pin TSSOP) Package, Top View
表5-3. Pin Functions: OPA4387
PIN
TYPE
DESCRIPTION
NAME
–IN A
NO.
2
Input
Input
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Output, channel A
6
–IN B
–IN C
–IN D
+IN A
+IN B
+IN C
+IN D
OUT A
OUT B
OUT C
OUT D
V–
9
Input
13
3
Input
Input
5
Input
10
12
1
Input
Input
Output
Output
Output
Output
Power
Power
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) power supply
Positive (highest) power supply
V+
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Single-supply
6
±3
VS
V
Supply voltage, VS = (V+) –(V–)
Dual-supply
Common-mode
Differential
(V+) + 0.5
(V–) –0.5
Input voltage, all pins
V
(V+) –(V–) + 0.2
Input current, all pins
Output short circuit(2)
Operating temperature
Junction temperature
Storage temperature
±10
Continuous
150
mA
Continuous
–55
TA
°C
°C
°C
TJ
150
–55
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7
NOM
MAX
5.5
UNIT
V
Single-supply
Dual-supply
VS
TA
Supply voltage, VS = (V+) –(V–)
±0.85
–40
±2.75
125
Specified temperature
°C
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UNIT
6.4 Thermal Information: OPA387
OPA387
DBV (SOT-23)
5 PINS
187.1
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
107.4
57.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
33.5
ψJT
57.1
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2387
OPA2387
THERMAL METRIC(1)
DGK (VSSOP)
DSG (WSON)
8 PINS
71.9
UNIT
8 PINS
165
53
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
88.8
87
39.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.9
3.2
ΨJT
85
39.2
ΨJB
RθJC(bot)
N/A
14.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Thermal Information: OPA4387
OPA4387
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
109.6
27.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ΨJT
54.9
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VS = 1.7 V to 5.5 V, VCM = VS / 2, VOUT = VS / 2, and min and max specification
established from manufacturing final test (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5.5 V
VS = 1.7 V
±0.25
±0.35
±0.4
±2
±2.5
VOS
Input offset voltage
µV
TA = –40°C to +125°C(1)
OPA387, OPA2387
OPA4387
±0.003
±0.012
±0.018
±0.35
±0.5
TA = –40°C to +125°C(1)
μV/°C
μV/V
dVOS/dT
PSRR
Input offset voltage drift
OPA387, OPA2387
OPA4387
±0.05
±30
Power supply rejection
ratio
TA = –40°C to +125°C(1)
±1
INPUT BIAS CURRENT
OPA387, OPA2387
OPA4387
±150
±300
±200
±350
±300
±500
±400
±700
IB
Input bias current
pA
pA
OPA387, OPA2387
OPA4387
TA = –40°C to +125°C(1)
OPA387, OPA2387
OPA4387
±60
IOS
Input offset current
Input voltage noise
OPA387, OPA2387
OPA4387
TA = –40°C to +125°C(1)
NOISE
177
27
nVPP
f = 0.1 Hz to 10 Hz
nVRMS
f = 1 Hz
8.5
8.5
8.5
8.5
70
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 1 kHz
eN
Input voltage noise density
Input current noise
nV/√Hz
fA/√Hz
V
iN
INPUT VOLTAGE
VS = 1.7 V
VS = 5.5 V
(V+)
(V–) –0.1
(V–) –0.2
115
Common-mode voltage
range
VCM
(V+) + 0.1
138
150
(V–) –0.1 V < VCM < (V+), VS = 1.7 V
OPA387, OPA2387
OPA4387
140
(V–) –0.2 V < VCM < (V+)
+ 0.1 V, VS = 5.5 V
130
Common-mode rejection
ratio
CMRR
dB
(V–) –0.1 V < VCM < (V+), TA = –40°C to +125°C(1)
110
132
(V–) –0.2 V < VCM < (V+) + 0.1, VS = 5.5 V,
TA = –40°C to +125°C(1)
130
INPUT CAPACITANCE
ZID
Differential
100 || 3
60 || 3
MΩ|| pF
GΩ|| pF
ZICM
Common-mode
OPEN-LOOP GAIN
OPA387, OPA2387
135
120
125
132
120
125
145
145
(V–) + 100 mV < VOUT
(V+) –100 mV
<
<
OPA4387
TA = –40°C to +125°C(1)
OPA387, OPA2387
OPA4387
AOL
Open-loop voltage gain
dB
(V–) + 150 mV < VOUT
(V+) –150 mV,
RL = 2 kΩ
TA = –40°C to +125°C(1)
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6.6 Electrical Characteristics (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VS = 1.7 V to 5.5 V, VCM = VS / 2, VOUT = VS / 2, and min and max specification
established from manufacturing final test (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
5.7
2.8
1.5
5.5
500
MHz
Slew rate
4-V step, G = +1
V/μs
To 0.1%, 1-V step , G = +1
To 0.01%, 1-V step , G = +1
VIN × G > VS
tS
Settling time
μs
Overload recovery time
ns
Chopping clock
frequency(1)
100
150
kHz
Total harmonic distortion +
noise
THD+N
VOUT = 1 VRMS, G = +1, f = 1 kHz
0.002 %
OUTPUT
OPA387, OPA2387
1
10
20
30
60
60
30
No load
OPA4387
5
Voltage output swing from
rail
mV
OPA387, OPA2387
OPA4387
20
RL = 2 kΩ
TA = –40°C to +125°C(1)
(V–) +
(V+) –
0.075
0.075
High linearity output swing
range(1)
AOL > 120 dB
V
(V–) +
0.150
(V+) –
0.150
RL = 2 kΩ
VS = 5.5 V
VS = 1.7 V
±55
±25
OPA2387DGK
ISC
Short-circuit current
Phase margin
mA
OPA387, OPA2387DSG,
OPA4387
±15
40
CL = 100 pF, G = +1
f = 1 MHz
degrees
Open-loop output
impedance
RO
250
Ω
POWER SUPPLY
570
25
675
700
100
Quiescent current per
amplifier
IQ
IO = 0 mA
μA
μs
TA = –40°C to 125°C(1)
Turn-on time
At VS = 5.5 V, VS ramp rate > 0.3 V/µs, settle to 1%
(1) Specification established from device population bench system measurements across multiple lots.
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6.7 Typical Characteristics
at TA = 25°C, VS = ±2.75 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 50 pF (unless otherwise noted)
50
45
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
5
0
-2
0
-1.5
-1
-0.5
0
0.5
1
1.5
2
-5
-4
-3
-2
-1
0
1
2
3
4
5
Input Offset Voltage (mV)
Input Offset Voltage (mV)
c110
c100
VS = 5.5 V, TA = 25°C
VS = 5.5 V, TA = –40°C
图6-1. Offset Voltage Distribution
图6-2. Offset Voltage Distribution
40
35
30
25
20
15
10
5
60
50
40
30
20
10
0
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
-0.02
-0.01
0
0.01
0.02
Input Offset Voltage (mV)
Offset Voltage Drift (mV/èC)
c101
c103
VS = 5.5 V, TA = 125°C
VS = 5.5 V
图6-3. Offset Voltage Distribution
图6-4. Offset Voltage Drift Distribution
3
2
3
2
1
1
VCM = -2.95 V
VCM = 2.85 V
0
0
-1
-2
-3
-1
-2
-3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-3
-2
-1
0
Input Common Mode Voltage (V)
1
2
3
c108
c111
图6-5. Offset Voltage vs Temperature
图6-6. Offset Voltage vs Common-Mode Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.75 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 50 pF (unless otherwise noted)
1
0.75
0.5
160
140
120
100
80
165
150
135
120
105
90
Gain
Phase
0.25
0
60
-0.25
-0.5
-0.75
-1
40
75
20
60
Vs = 1.7 V
0
45
-20
30
1.5
2
3
Supply Voltage (V)
4
5
5.5
100m
1
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
c112
c114
图6-7. Offset Voltage vs Supply Voltage
图6-8. Open-Loop Gain and Phase vs Frequency
0.5
0.25
0
60
VS = ê0.85 V
VS = ê2.75 V
40
20
0
-20
-40
-60
-0.25
G = -1
G = +1
G = +10
G = +100
-0.5
-75
-50
-25
0
25
50
75
100 125 150
100
1k
10k 100k
Frequency (Hz)
1M
10M
Temperature(èC)
C129
c113
图6-9. Open-Loop Gain vs Temperature
图6-10. Closed-Loop Gain vs Frequency
VS = ê2.75 V, (V-) - 0.2 V Ç VCM Ç (V+) + 0.1 V
1000
800
600
400
200
0
0.1
IB-
IB+
IOS
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
VS = ê0.85 V, (V-) - 0.1 V Ç VCM Ç (V+)
-200
-400
-75
-50
-25
0
25
50
75
100 125 150
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
Temperature (èC)
Input Common Mode Voltage (V)
C121
图6-11. Input Bias Current vs Common-Mode Voltage
图6-12. CMRR vs Temperature
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.75 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 50 pF (unless otherwise noted)
160
CMRR
PSRR−
PSRR+
140
120
100
80
60
40
20
0
10m 100m
1
10
100
1k
10k 100k 1M 10M
Frequency (Hz)
Time (1 s/div)
C130
图6-13. PSRR and CMRR vs Frequency
图6-14. 0.1-Hz to 10-Hz Noise
20
-40
-60
10
7
-80
-100
-120
-140
-160
-180
-200
5
4
3
2
1
100m
1
10
100
Frequency (Hz)
1k
10k
100k
100
1k
10k 100k
Frequency (Hz)
1M
10M
c115
C122
图6-15. Input Voltage Noise Spectral Density vs Frequency
图6-16. Channel-to-Channel Crosstalk
0.1
-60
1
0.1
-40
-60
-80
G = -1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 600 W
G = +1, RL = 10 kW
G = +1, RL = 2 kW
G = +1, RL = 600 W
G = -1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 600 W
G = +1, RL = 10 kW
G = +1, RL = 2 kW
G = +1, RL = 600 W
0.01
-80
0.01
0.001
0.0001
-100
0.001
-100
-120
0.0001
-120
20k
10m
100m
Output Amplitude (VRMS
1
20
200
2k
)
Frequency (Hz)
C136
C137
VS = 5.5 V, f = 1 kHz, BW = 80 kHz
VS = 5.5 V, VOUT = 3 VRMS, BW = 80 kHz
图6-18. THD+N vs Output Amplitude
图6-17. THD+N Ratio vs Frequency
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.75 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 50 pF (unless otherwise noted)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1
2
3
Supply Voltage (V)
4
5
6
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
c107
c102
图6-19. Quiescent Current vs Supply Voltage
图6-20. Quiescent Current vs Temperature
1000
100
10
80
RISO = 0 W
RISO = 25 W
RISO = 50 W
60
40
20
0
1
0.1
100
Load Capacitance (pF)
1k
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
C124
C138
G = –1, 10 mV step
图6-22. Small-Signal Overshoot vs Capacitive Load
图6-21. Open-Loop Output Impedance vs Frequency
80
60
RISO = 0 W
RISO = 25 W
RISO = 50 W
Riso = 0
60
40
20
0
45
30
15
0
100
Load Capacitance (pF)
1k
100
1k
C127
Load Capacitance (pF)
G = +1, 10 mV step
G = +1
图6-23. Small-Signal Overshoot vs Capacitive Load
图6-24. Phase Margin vs Capacitive Load
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.75 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 50 pF (unless otherwise noted)
VIN
VOUT
VIN
VOUT
Time (100 µs/div)
Time (500 ns/div)
G = –1
C125
C133
图6-25. No Phase Reversal
图6-26. Overload Recovery
VIN
VOUT
VIN
VOUT
Time (1 µs/div)
G = +1
Time (1 µs/div)
4-V step
C128
c105
图6-27. Small-Signal Step Response
图6-28. Large-Signal Step Response
Rising Edge
Falling Edge
Time (10 µs/div)
C135
0.01% settling = ±100 µV
图6-29. Settling Time
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7 Detailed Description
7.1 Overview
The OPAx387 family of zero-drift amplifiers is engineered with state-of-the-art, proprietary, precision zero-drift
technology. These amplifiers offer ultra-low input offset voltage and drift, and achieve excellent input and output
dynamic linearity. The OPAx387 operate from 1.7 V to 5.5 V, are unity-gain stable, and are designed for a wide
range of general-purpose and precision applications. The OPAx387 strengths also include a 5.7-MHz bandwidth,
8.5-nV/√Hz noise spectral density, and no 1/f noise, making the OPAx387 an excellent choice for interfacing
with sensor modules, and buffering high-fidelity, digital-to-analog converters (DACs).
7.2 Functional Block Diagram
GM_FF
CCOMP
CLK
CLK
+IN
–IN
OUT
GM1
GM2
GM3
CCOMP
Ripple Reduction
Technology
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7.3 Feature Description
7.3.1 Input Bias Current
During normal operation, the typical input bias current of the OPAx387 is 30 pA. The device exhibits low drift
over the full temperature range of –40°C to +125°C. There are no antiparallel diodes between the input pins
(+IN and –IN); therefore, the differential input maximum voltage is limited only by diodes connected to the
supply voltage pins. However, use caution in cases where the input differential voltage exceeds the nominal
operating input differential voltage. When inputs are separated, the switching offset-cancellation path internal to
the amplifier exceeds normal operating conditions, and can potentially create long settling behavior upon return
to normal operation. The equivalent input circuit of OPAx387 is shown in 图7-1.
V+
450
+IN
–
CORE
450
–IN
+
V–
图7-1. Equivalent Input Circuit
7.3.2 EMI Susceptibility and Input Filtering
Operational amplifiers can exhibit sensitivity to electromagnetic interference (EMI). Typically, conducted EMI
(that is, EMI that enters the device through conduction) is more commonly observed than radiated EMI (that is,
EMI that enters the device through radiation). When conducted EMI enters the operational amplifier, the dc offset
at the amplifier output can shift from the nominal value. This shift is a result of signal rectification associated with
the internal semiconductor junctions. Although all operational amplifier pin functions can be affected by EMI, the
input pins are likely to be the most susceptible. The OPAx387 operational amplifier family incorporates an
internal input low-pass filter that reduces the amplifier response to EMI. Both common-mode and differential-
mode filtering are provided by the input filter. The conducted EMI rejection of the OPAx387 is seen in 图7-2.
140
130
120
110
100
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
5G
c104
图7-2. EMI Rejection Ratio
7.4 Device Functional Modes
The OPAx387 have a single functional mode and are operational when the power-supply voltage is greater than
1.7 V (±0.85 V). The maximum specified power-supply voltage for the OPAx387 is 5.5 V (±2.75 V).
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The OPAx387 are unity-gain stable, precision, operational amplifiers featuring state-of-the-art, zero-drift
technology. The use of proprietary zero-drift circuitry gives the benefit of low input offset voltage over time and
temperature, as well as lower 1/f noise component. As a result of the high PSRR, the devices work well in
applications that run directly from battery power without regulation. The OPAx387 family is optimized for full rail-
to-rail input, allowing for low-voltage, single-supply operation or split-supply use. These miniature, high-precision,
low-noise amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the supplies
without input crossover distortion, and a rail-to-rail output that swings within 5 mV of the supplies under normal
test conditions. The OPAx387 precision amplifiers are designed for upstream analog signal-chain applications in
low or high gains, as well as downstream signal-chain functions, such as DAC buffering.
8.1.1 Zero-Drift Clocking
The OPAx387 use an advanced zero-drift architecture to achieve ultra-low offset and offset drift. This
architecture uses a clock and switches internally to create a dc error-correction path. The clocking is filtered
internally, and typically not observable for most configurations. Take the following precautions to minimize clock
noise in the signal chain. The clocking creates a small charge-injection pulse at the input of the amplifier;
therefore, do not use high-value resistors (> 100 kΩ) in series with the inputs to avoid higher clock voltage noise
at the output. The charge injection pulses are minimized when the impedance to the input pins is matched. If
higher value resistors are used, then use matching impedances on both amplifier input pins.
8.2 Typical Applications
8.2.1 Bidirectional Current Sensing
This single-supply, low-side, bidirectional current-sensing design example detects load currents from –1 A to +1
A. The single-ended output spans from 110 mV to 3.19 V. This design uses the OPAx387 because of the device
low offset voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier
and the other amplifier provides the reference voltage. 图8-1 shows the design example schematic.
VCC
VREF
VCC
R5
+
U1B
ILOAD
R2
R6
+
–
R1
R3
+
VBUS
+
VSHUNT
RSHUNT
VOUT
U1A
VCC
R4
–
RL
图8-1. Bidirectional Current-Sensing Schematic
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8.2.1.1 Design Requirements
This solution has the following requirements:
• Supply voltage: 3.3 V
• Input: –1 A to +1 A
• Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
8.2.1.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor, RSHUNT, to develop the shunt voltage, VSHUNT. The
shunt voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by 方程式1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
(1)
where
VSHUNT = ILOAD ´ RSHUNT
•
R4
GainDiff_Amp
=
R3
•
R6
R5 + R6
VREF = VCC
´
•
There are two types of errors in this design: gain and offset. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of
the difference amplifier, ultimately translating to an offset error.
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set to
100 mV. 方程式2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of 100 mV
and maximum load current of 1 A.
VSHUNT(Max)
100 mV
= 100 mW
RSHUNT(Max)
=
=
ILOAD(Max)
1 A
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
is selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to +100 mV. This voltage is
divided down by R1 and R2 before reaching the operational amplifier, U1A. Make sure that the voltage present at
the noninverting node of U1A is within the common-mode range of the device. Use an operational amplifier, such
as the OPAx387, that has a common-mode range that extends below the negative supply voltage. The offset
error is minimal because the OPAx387 has a typical offset voltage of merely ±0.25 µV (±5 µV, maximum).
Given a symmetric load current of –1 A to +1 A, the voltage divider resistors, R5 and R6, must be equal. To be
consistent with the shunt resistor, a tolerance of 0.5% is selected. To minimize power consumption, 10‑kΩ
resistors are used.
To set the gain of the difference amplifier, the common-mode range and output swing of the OPAx387 must be
considered. 方程式 3 and 方程式 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPAx387 given a 3.3‑V supply.
–100 mV < VCM < 3.4 V
(3)
(4)
100 mV < VOUT < 3.2 V
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The gain of the difference amplifier can now be calculated as shown in 方程式5.
V
OUT_Max - VOUT_Min
3.2 V - 100 mV
100 mW ´ [1 A - (- 1A)]
V
V
= 15.5
=
GainDiff_Amp
=
R
SHUNT ´ (IMAX - IMIN
)
(5)
The resistor value selected for R1 and R3 is 1 kΩ. 15.4 kΩis selected for R2 and R4 because this number is the
nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
were selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
8.2.1.3 Application Curve
3.30
1.65
0
-1.0
-0.5
0
0.5
1.0
Input Current (A)
图8-2. Bidirectional Current-Sensing Circuit Performance: Output Voltage vs Input Current
8.2.2 Load Cell Measurement
图 8-3 shows the OPAx387 in a high-CMRR dual-op amp instrumentation amplifier with a trim resistor and six-
wire load cell for precision measurement.
R3
25 kꢀ
R4
100 kꢀ
5 V
REF5025
RG
R4
R2
100 kꢀ
25 kꢀ
5 V
5 V
5 V
+SENSE
œ
OPAx387
œ
OPAx387
VOUT
+
+
R2
GND
GND
10 kꢀ
œSENSE
200 kΩ
Load Cell
G = 5 +
GND
RG
GND
图8-3. Load Cell Measurement Schematic
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9 Power Supply Recommendations
The OPAx387 family of devices is specified for operation from 1.7 V to 5.5 V for single supplies, and ±0.85 V to
±2.75 V for dual supplies. Key parameters that can exhibit significant variance with regard to operating voltage
are presented in 节6.7.
CAUTION
Supply voltages greater than 6 V can permanently damage the device (see 节6.1).
10 Layout
10.1 Layout Guidelines
Pay attention to good layout practice. Keep traces short and, when possible, use a printed-circuit board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-µF
capacitor close to the supply pins. These guidelines must be applied throughout the analog circuit to improve
performance, and provide benefits such as reducing the electromagnetic interference (EMI) susceptibility.
For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. Cancel these thermally-generated potentials by making sure that the potentials
are equal on both input pins. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher depending on materials used.
10.2 Layout Example
RIN
VIN
+
VOUT
RG
RF
GND
图10-1. Schematic Representation
VS
Minimize
parasitic
inductance by
CBYPASS
VOUT
placing bypass
capacitor close
to V+.
OUT
V+
V–
+IN –IN
RG
Keep high
impedance
input signal
away from
noisy traces.
VIN
RF
Route trace under package for output to
feedback resistor connection.
图10-2. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
11.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
备注
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following: Texas Instruments, Circuit board layout techniques
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: OPA387 OPA2387 OPA4387
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2387DGKR
OPA2387DGKT
OPA2387DSGR
OPA2387DSGT
OPA387DBVR
OPA387DBVT
OPA4387PWR
OPA4387PWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
WSON
WSON
SOT-23
SOT-23
TSSOP
TSSOP
DGK
DGK
DSG
DSG
DBV
DBV
PW
8
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2B2T
2B2T
2N3H
2N3H
2IMT
2IMT
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
SN
NIPDAU
NIPDAU
SN
8
8
5
5
SN
14
14
SN
OPA4387
OPA4387
PW
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2387DGKR
OPA2387DGKT
OPA2387DSGR
OPA2387DSGT
OPA387DBVR
OPA387DBVT
OPA4387PWR
OPA4387PWT
VSSOP
VSSOP
WSON
WSON
SOT-23
SOT-23
TSSOP
TSSOP
DGK
DGK
DSG
DSG
DBV
DBV
PW
8
8
2500
250
330.0
330.0
180.0
180.0
178.0
178.0
330.0
180.0
12.4
12.4
8.4
5.3
5.3
2.3
2.3
3.3
3.3
6.9
6.9
3.4
3.4
2.3
2.3
3.2
3.2
5.6
5.6
1.4
1.4
8.0
8.0
4.0
4.0
4.0
4.0
8.0
8.0
12.0
12.0
8.0
Q1
Q1
Q2
Q2
Q3
Q3
Q1
Q1
8
3000
250
1.15
1.15
1.4
8
8.4
8.0
5
3000
250
9.0
8.0
5
9.0
1.4
8.0
14
14
3000
250
12.4
12.4
1.6
12.0
12.0
PW
1.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2387DGKR
OPA2387DGKT
OPA2387DSGR
OPA2387DSGT
OPA387DBVR
OPA387DBVT
OPA4387PWR
OPA4387PWT
VSSOP
VSSOP
WSON
WSON
SOT-23
SOT-23
TSSOP
TSSOP
DGK
DGK
DSG
DSG
DBV
DBV
PW
8
8
2500
250
366.0
366.0
210.0
210.0
190.0
190.0
356.0
210.0
364.0
364.0
185.0
185.0
190.0
190.0
356.0
185.0
50.0
50.0
35.0
35.0
30.0
30.0
35.0
35.0
8
3000
250
8
5
3000
250
5
14
14
3000
250
PW
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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