OPA388-Q1 [TI]
符合汽车标准的宽带宽、零温漂、零交叉、精密放大器;
| 型号： | OPA388-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 符合汽车标准的宽带宽、零温漂、零交叉、精密放大器 放大器 |
| 文件： | 总34页 (文件大小：3276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA388-Q1, OPA2388-Q1
ZHCSP72A –AUGUST 2020 –REVISED NOVEMBER 2021
OPAx388-Q1 自动、精密、零漂移、零交叉、
真正的轨至轨输入/输出运算放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 提供功能安全
OPA388-Q1 和OPA2388-Q1 (OPAx388-Q1) 是自动低
噪声、快速稳定、零漂移高精度运算放大器，可实现轨
到轨输入和输出运行。优异交流性能与仅为 0.25μV
的失调电压以及 0.005µV/°C 的温度漂移相结合，使
OPAx388-Q1 成为驱动高精度高分辨率模数转换器
(ADC) 的理想选择。零交叉技术更大程度地减小了共
模范围内的失调电压变化。低漂移和超低 1/f 噪声相结
合，使 OPAx388-Q1 能够监视和检测故障情况，而不
会影响信号完整性。
– 可帮助进行功能安全系统设计的文档(OPA388-
Q1)
– 可帮助进行功能安全系统设计的文档
(OPA2388-Q1: VSSOP)
• 零漂移：±0.005µV/°C
• 零交叉：140dB CMRR 真正RRIO
• 低噪声：1 kHz 时为7.0 nV√Hz
• 无1/f 噪声：140nVPP（0.1Hz 至10Hz）
• 快速稳定：2µs（1V，0.01%）
• 增益带宽：10MHz
这些器件的额定工业温度范围均为-40°C 至+125°C。
器件信息
封装(1)
封装尺寸（标称值）
2.90mm × 1.60mm
4.90mm × 3.90mm
3.00mm × 3.00mm
器件型号
OPA388-Q1
SOT-23 (5)
• 单电源：2.5V 至5.5V
• 双电源：±1.25V 至±2.75V
• 真正的轨至轨输入
SOIC (8) - 预发布
OPA2388-Q1
VSSOP (8)
• 输入已滤除EMI 和RFI
• 行业标准封装：VSSOP-8、SOT-23-5
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
2 应用
• 混合动力汽车/电动汽车逆变器和电机控制
• 电池管理系统(BMS)
• 直流/直流转换器
• 车载充电器(OBC) 和无线充电器
VCC
5
4
VREF
VCC
R5
3
2
+
U1B
1
ILOAD
R6
0
R2
+
œ1
œ2
R1
+
VBUS
+
œ
VSHUNT
RSHUNT
VOUT
œ3
U1A
VCC
R4
VCM = œ2.85 V
R3
œ
RL
VCM = 2.85 V
œ4
œ5
0
1
2
3
œ3
œ2
œ1
Input Common-mode Voltage (V)
双向电流分流监控器中的OPA388-Q1
C003
OPA388-Q1 在整个共模范围内采用超低失调电压
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS989
OPA388-Q1, OPA2388-Q1
ZHCSP72A –AUGUST 2020 –REVISED NOVEMBER 2021
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Application ................................................ 19
9 Power Supply Recommendations................................22
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Device Support........................................................23
11.2 Documentation Support.......................................... 23
11.3 接收文档更新通知................................................... 23
11.4 支持资源..................................................................23
11.5 Trademarks............................................................. 23
11.6 Electrostatic Discharge Caution..............................24
11.7 术语表..................................................................... 24
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information: OPA388-Q1.............................. 5
6.5 Thermal Information: OPA2388-Q1............................ 5
6.6 Electrical Characteristics.............................................6
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................18
Information.................................................................... 24
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (August 2020) to Revision A (November 2021)
Page
• 添加了OPA2388-Q1 量产数据（正在供货）器件和相关内容.............................................................................1
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5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
+IN
4
œIN
Not to scale
图5-1. OPA388-Q1 DBV (5-Pin SOT-23) Package, Top View
Pin Functions: OPA388-Q1
PIN
TYPE
DESCRIPTION
NAME
NO.
4
Input
Input
Inverting input
–IN
+IN
NC
3
Noninverting input
No internal connection (can be left floating)
Output
—
—
OUT
V–
V+
1
Output
2
5
Power
Power
Negative (lowest) power supply
Positive (highest) power supply
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
图5-2. OPA2388-Q1 D (8-Pin SOIC, Preview) and DGK (8-Pin VSSOP) Packages, Top View
Pin Functions: OPA2388-Q1
PIN
TYPE
DESCRIPTION
NAME
NO.
2
Input
Input
Inverting input, channel A
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Output, channel A
–IN A
–IN B
+IN A
+IN B
6
3
Input
5
Input
OUT A
OUT B
V–
1
Output
Output
Power
Power
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Single-supply
6
±3
VS
V
Supply voltage, VS = (V+) –(V–)
Dual-supply
Common-mode
Differential
(V+) + 0.5
(V–) –0.5
Signal input pins voltage
V
(V+) –(V–) + 0.2
Signal input pins current
Output short circuit(2)
Operating temperature
Junction temperature
Storage temperature
±10
Continuous
150
mA
Continuous
TA
°C
°C
°C
–55
TJ
150
Tstg
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C5
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
MAX
5.5
UNIT
V
Single-supply
Dual-supply
VS
TA
Supply voltage, VS = (V+) –(V–)
±1.25
–40
±2.75
125
Specified temperature
°C
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6.4 Thermal Information: OPA388-Q1
OPA388-Q1
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
145.7
94.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
43.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
24.7
ΨJT
43.1
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2388-Q1
OPA2388-Q1
THERMAL METRIC(1)
DGK (VSSOP)
UNIT
8 PINS
165
53
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
87
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.9
ΨJT
85
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, VS = ±1.25 V to ±2.75 V (2.5 V to 5.5 V), and RLOAD = 10 kΩconnected to VS / 2 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
OPA388-Q1
±0.25
±1.5
±5
±5
OPA2388-Q1
VOS
Input offset voltage
µV
±7.5
±0.05
±1
TA = –40°C to +125°C
TA = –40°C to +125°C
TA = –40°C to +125°C
dVOS/dT Input offset voltage drift
PSRR Power-supply rejection ratio
INPUT BIAS CURRENT
±0.005
±0.1
µV/°C
µV/V
±30
±350
±400
±700
±700
±800
±800
TA = 0°C to +85°C
IB
Input bias current
pA
pA
RIN = 100 kΩ
RIN = 100 kΩ
TA = –40°C to +125°C
TA = 0°C to +85°C
IOS
Input offset current
TA = –40°C to +125°C
NOISE
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
0.14
7
µVPP
f = 100 Hz
7
eN
Input voltage noise density
nV/√Hz
f = 1 kHz
7
f = 10 kHz
7
IN
Input current noise density f = 1 kHz
100
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
(V–) –
VCM
(V+) + 0.1
V
0.1
VS = ±1.25 V
VS = ±2.75 V
124
124
138
140
(V–) –0.1 V < VCM < (V+) + 0.1 V
Common-mode rejection
ratio
(V–) < VCM < (V+) + 0.1 V,
TA = –40°C to +125°C
CMRR
dB
VS = ±1.25 V
VS = ±2.75 V
114
124
134
140
(V–) –0.05 V < VCM < (V+) + 0.1 V,
TA = –40°C to +125°C
INPUT IMPEDANCE
Differential input
impedance
zid
zic
100 || 2
60 || 4.5
MΩ|| pF
TΩ|| pF
Common-mode input
impedance
OPEN-LOOP GAIN
126
120
148
126
(V–) + 0.15 V < VO < (V+) –0.15 V
TA = –40°C to +125°C
TA = –40°C to +125°C
(V–) + 0.25 V < VO < (V+) –0.25 V,
RLOAD = 2 kΩ
AOL
Open-loop voltage gain
dB
126
120
148
148
(V–) + 0.30 V < VO < (V+) –0.30 V,
RLOAD = 2 kΩ
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6.6 Electrical Characteristics (continued)
at TA = 25°C, VCM = VOUT = VS / 2, VS = ±1.25 V to ±2.75 V (2.5 V to 5.5 V), and RLOAD = 10 kΩconnected to VS / 2 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Unity-gain bandwidth
10
5
MHz
V/µs
Slew rate
G = 1, 4-V step
Total harmonic distortion +
noise
THD+N
tS
G = 1, f = 1 kHz, VO = 1 VRMS
0.0005%
To 0.1%
0.75
2
VS = ±2.5 V, G = 1,
1-V step
Settling time
µs
µs
To 0.01%
tOR
Overload recovery time
VIN × G = VS
Positive rail
Negative rail
10
OUTPUT
No load
1
15
20
50
15
20
60
25
5
20
RLOAD = 2 kΩ
Voltage output swing from
rail
No load
5
VO
mV
10
40
10
RLOAD = 2 kΩ
TA = –40°C to +125°C, both rails, RLOAD = 10 kΩ
VS = 5.5 V
VS = 2.5 V
±60
ISC
CLOAD
ZO
Short-circuit current
Capacitive load drive
mA
±30
See 图6-25
Open-loop output
impedance
100
f = 1 MHz, IO = 0 A, see 图6-24
Ω
POWER SUPPLY
1.7
1.7
1.9
1.9
2.4
2.4
2.6
2.6
VS = ±1.25 V (VS = 2.5 V), IO = 0 A
TA = –40°C to +125°C
Quiescent current per
amplifier
IQ
mA
VS = ±2.75 V (VS = 5.5 V), IO = 0 A
TA = –40°C to +125°C
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6.7 Typical Characteristics
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF (unless otherwise noted)
表6-1. Table of Graphs
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
图6-1
Offset Voltage Drift Distribution From –40°C to +125°C
Offset Voltage vs Temperature
图6-2
图6-3
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Power Supply
图6-4
图6-5
Offset Voltage Long Term Drift
图6-6
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain and Phase vs Frequency
Input Bias Current vs Common-Mode Voltage
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency
CMRR vs Temperature
图6-7
图6-8
图6-9
图6-10
图6-11
图6-12
图6-13
PSRR vs Temperature
图6-14
0.1-Hz to 10-Hz Noise
图6-15
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
图6-16
图6-17
THD+N vs Output Amplitude
图6-18
Spectral Content
图6-19, 图6-20
图6-21
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
No Phase Reversal
图6-22
图6-23
图6-24
图6-25
图6-26
Positive Overload Recovery
图6-27
Negative Overload Recovery
图6-28
Small-Signal Step Response (10-mV Step)
Large-Signal Step Response (4-V Step)
Settling Time
图6-29, 图6-30
图6-31 , 图6-32
图6-33, 图6-34
图6-35
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
图6-36
图6-37
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF (unless otherwise noted)
15
10
5
50
45
40
35
30
25
20
15
10
5
0
0
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
TA = –40°C to +125°C
C002
C001
图6-1. Offset Voltage Production Distribution
图6-2. Offset Voltage Drift Distribution
5
4
3
2
1
0
5
4
3
2
1
0
œ1
œ1
œ2
œ3
œ4
œ5
œ2
œ3
œ4
œ5
VCM = œ2.85 V
VCM = 2.85 V
0
25
50
75
100 125 150
0
1
2
3
œ75 œ50 œ25
œ3
œ2
œ1
Temperature (°C)
Input Common-mode Voltage (V)
C001
C003
图6-3. Offset Voltage vs Temperature
图6-4. Offset Voltage vs Common-Mode Voltage
20
5
4
3
2
1
0
15
10
5
0
œ1
-5
œ2
œ3
œ4
œ5
-10
-15
-20
VS
=
1.25 V
VS
=
2.75 V
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
0
20
40
60
80
Days
100
120
140
160
Supply Voltage (V)
C001
C309
3 typical units
图6-6. Offset Voltage Long Term Drift
图6-5. Offset Voltage vs Supply Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF (unless otherwise noted)
160
140
1±0
100
80
180
135
90
60
40
20
0
Open-Loop Gain
G = +1
G= +10
G= +100
Open-Loop Phase
60
40
45
±0
0
0
±±0
±40
-20
-45
100
1k
10k
100k
1M
10M
1
10
100
1k 10k 100k 1M 10M
Frequency (Hz)
Frequency (Hz)
C004
C0±1
图6-8. Closed-Loop Gain and Phase vs Frequency
图6-7. Open-Loop Gain and Phase vs Frequency
1500
1.5
1.3
1.0
0.8
0.5
0.3
1000
500
0
ios
œ500
0.0
0
1
2
3
0
25
50
75
100 125 150
œ3
œ2
œ1
œ75 œ50 œ25
Input Common-mode Voltage (V)
Temperature (°C)
C001
C001
图6-9. Input Bias Current vs Common-Mode Voltage
图6-10. Input Bias Current vs Temperature
3
2.5
2
160
140
120
100
80
1.5
25°C
1
0.5
0
-0.5
-1
125°C
60
œ40°C
CMRR
+PSRR
œPSRR
-1.5
-2
40
20
-2.5
-3
0
0
10
20
30
40
50
60
70
80
90 100
1
10
100
1k
10k
100k
1M
10M
Output Current (mA)
Frequency (Hz)
C001
C004
图6-12. CMRR and PSRR vs Frequency
图6-11. Output Voltage Swing vs Output Current (Maximum
Supply)
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF (unless otherwise noted)
180
160
140
120
100
0.001
0.01
0.1
1
180
160
140
120
100
0.001
0.01
0.1
1
10
10
0
25
50
75 100 125 150
œ75 œ50 œ25
0
25
50
75 100 125 150
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
图6-14. PSRR vs Temperature
图6-13. CMRR vs Temperature
1000
100
10
1
Time (1 s/div)
1
10
100
1k
10k
100k
Frequency (Hz)
C017
C002
图6-15. 0.1-Hz to 10-Hz Noise
图6-16. Input Voltage Noise Spectral Density vs Frequency
0.01
-80
0.1
-60
G = -1, 10k-ꢀ Load
G = -1, 2k-ꢀ Load
G = -1, 600-ꢀ Load
G = +1, 10k-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 600-ꢀ Load
0.01
-80
0.001
-100
G = -1, 600-ꢀ Load
G = -1, 2k-ꢀ Load
G = -1, 10k-ꢀ Load
G = +1, 600-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 10k-ꢀ Load
0.001
0.0001
-100
-120
0.0001
-120
20k
20
200
2k
0.001
0.01
0.1
1
Frequency (Hz)
Output Amplitude (VRMS
)
C004
C004
图6-17. THD+N Ratio vs Frequency
图6-18. THD+N vs Output Amplitude
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF (unless otherwise noted)
0
œ20
0
œ20
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ180
œ100
œ120
œ140
œ160
œ180
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C004
C004
G = +1, f = 1 kHz, VO = 4.5 VPP, RL = 10 kΩ, BW = 90 kHz
G = +1, f = 1 kHz, VO = 4.5 VPP, RL = 2 kΩ, BW = 90 kHz
图6-19. Spectral Content (With 10-kΩLoad)
图6-20. Spectral Content (With 2-kΩLoad)
2.5
2.5
2
1.5
1
2
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
2
2.5
3
0
25
50
75
100 125 150
œ75 œ50 œ25
Supply Voltage (V)
Temperature (°C)
C001
C001
图6-21. Quiescent Current vs Supply Voltage
图6-22. Quiescent Current vs Temperature
180
160
140
120
100
0.001
1k
100
10
VS
=
2.75 V
0.01
0.1
1
VS
=
1.1 V
1
100m
10m
10
100
1k
10k
100k
1M
10M
100M
0
25
50
75 100 125 150
œ75 œ50 œ25
Frequency (Hz)
Temperature (°C)
C003
C001
图6-24. Open-Loop Output Impedance vs Frequency
图6-23. Open-Loop Gain vs Temperature
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
VIN
90
G = -1
80
70
60
50
VOUT
40
30
G = +1
20
10
Time (45 ms/div)
10
100
1000
Capacitive Load (pF)
C004
C017
10-mV step
图6-25. Small-Signal Overshoot vs Capacitive Load
图6-26. No Phase Reversal
VIN
VOUT
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
C017
C017
图6-27. Positive Overload Recovery
图6-28. Negative Overload Recovery
VOUT
VIN
VOUT
VIN
Time (2.5 µs/div)
Time (2.5 µs/div)
C017
C017
G = +1, 10-mV step
G = –1, 10-mV step
图6-29. Small-Signal Step Response
图6-30. Small-Signal Step Response
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF (unless otherwise noted)
VOUT
VIN
VOUT
VIN
Time (500 ns/div)
Time (500 ns/div)
C017
C017
Falling output, 4-V Step
Rising output, 4-V step
图6-31. Large-Signal Step Response
图6-32. Large-Signal Step Response
0.01% Settling = ±200µV
0.01% Settling = ±100µV
Time (500 ns/div)
Time (500 ns/div)
C017
C017
0.01% settling = ±100 µV, 1-V positive step
0.01% settling = ±200 µV, 1-V negative step
图6-33. Settling Time
图6-34. Settling Time
100
90
80
70
60
50
40
30
20
10
0
7
6
5
4
3
2
1
0
Maximum output voltage without
slew-rate induced distortion.
ISC, Sink
VS
=
2.5V
0.9V
ISC, Source
VS
=
100
1k
10k
100k
1M
10M
0
25
50
75
100 125 150
œ75 œ50 œ25
Frequency (Hz)
Temperature (°C)
C001
C001
图6-35. Short-Circuit Current vs Temperature
图6-36. Maximum Output Voltage vs Frequency
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 100 pF (unless otherwise noted)
160
140
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1000M
C004
PRF = –10 dBm
图6-37. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx388-Q1 zero-drift amplifiers are engineered with the unique combination of a proprietary precision
auto-calibration technique and a low-noise, low-ripple, input charge pump. These amplifiers offer ultra-low input
offset voltage and drift and achieve excellent input and output dynamic linearity. The OPAx388-Q1 operate from
2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose and precision
applications. The integrated, low-noise charge pump allows true rail-to-rail input common-mode operation
without distortion associated with complementary rail-to-rail input topologies (input crossover distortion). The
OPAx388-Q1 strengths also include 10-MHz bandwidth, 7-nV/√ Hz noise spectral density, and no 1/f noise,
making these devices an excellent choice for interfacing with sensor modules and buffering high-fidelity digital-
to-analog converters (DACs).
7.2 Functional Block Diagram
Low-noise
Charge-pump
GM_FF
CCOMP
CLK
CLK
+IN
OUT
œIN
GM1
GM2
GM3
CCOMP
Ripple Reduction
Technology
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7.3 Feature Description
7.3.1 Input Voltage and Zero-Crossover Functionality
The OPAx388-Q1 input common-mode voltage range extends 0.1 V beyond the supply rails. This amplifier
family is designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers. Operating a complementary rail-to-rail input amplifier with signals traversing the transition region
results in unwanted non-linear behavior and polluted spectral content. 图 7-1 and 图 7-2 contrast the
performance of a traditional complementary rail-to-rail input stage amplifier with the performance of the zero-
crossover OPAx388-Q1. Significant harmonic content and distortion is generated during the differential pair
transition (such a transition does not exist in the OPAx388-Q1). Crossover distortion is eliminated through the
use of a single differential pair coupled with an internal low-noise charge pump. The OPAx388-Q1 maintain
noise, bandwidth, and offset performance throughout the input common-mode range, thus reducing printed
circuit board (PCB) and bill of materials (BOM) complexity through the reduction of power-supply rails.
20
15
0
œ20
Complementary Input Stage
OPA388 Zero-Crossover Input Stage
10
œ40
5
œ60
Traditional Rail-to-Rail
Input Stage
0
œ80
œ5
œ100
œ120
œ140
œ10
œ15
œ20
VCM = œ2.85 V
VCM = 2.85 V
OPA388 Zero-Crossover Input Stage
0
1
2
3
10
100
1k
10k
œ3
œ2
œ1
Input Common-mode Voltage (V)
Frequency (Hz)
C003
C004
图7-1. Input Crossover Distortion
图7-2. Input Crossover Distortion Spectral Content
Nonlinearity
Typically, input bias current is approximately ±30 pA. Input voltages exceeding the power supplies, however, can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in 图7-3.
Current-limiting resistor
required if input voltage
exceeds supply rails by
> 0.3V.
+5V
IOVERLOAD
10 mA max
VOUT
VIN
5 kΩ
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图7-3. Input Current Protection
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7.3.2 Input Differential Voltage
The typical input bias current of the OPAx388-Q1 during normal operation is approximately 30 pA. In overdriven
conditions, the bias current can increase significantly. The most common cause of an overdriven condition
occurs when an operational amplifier is outside of the linear range of operation. When the output of the
operational amplifier is driven to one of the supply rails, the feedback loop requirements cannot be satisfied and
a differential input voltage develops across the input pins. This differential input voltage results in activation of
parasitic diodes inside the front-end input chopping switches that combine with 10-kΩ electromagnetic
interference (EMI) filter resistors to create the equivalent circuit shown in 图 7-4. Notice that the input bias
current remains within specification in the linear region.
100 W
Clamp
+In
-In
CORE
100 W
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图7-4. Equivalent Input Circuit
7.3.3 Internal Offset Correction
The OPAx388-Q1 operational amplifiers use an auto-calibration technique with a time-continuous, 200-kHz
operational amplifier in the signal path. These amplifiers are zero-corrected every 5 µs using a proprietary
technique. At power up, the amplifiers require approximately 1 ms to achieve the specified VOS accuracy. This
design has no aliasing or flicker noise.
7.3.4 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to EMI. If conducted EMI enters the operational amplifier, the dc
offset at the amplifier output can shift from its nominal value when EMI is present. This shift is a result of signal
rectification associated with the internal semiconductor junctions. Although all operational amplifier pin functions
can be affected by EMI, the input pins are likely to be the most susceptible. The OPAx388-Q1 operational
amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both
common-mode and differential-mode filtering are provided by the input filter. The filter is designed for a cutoff
frequency of approximately 20 MHz (–3 dB), with a rolloff of 20 dB per decade.
7.4 Device Functional Modes
The OPAx388-Q1 have a single functional mode and are operational when the power-supply voltage is greater
than 2.5 V (±1.25 V). The maximum specified power-supply voltage for the OPAx388-Q1 is 5.5 V (±2.75 V).
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The OPAx388-Q1 are unity-gain stable, precision operational amplifiers free from unexpected output and phase
reversal. The use of proprietary zero-drift circuitry gives the benefit of low input offset voltage over time and
temperature, as well as lowering the 1/f noise component. As a result of the high PSRR, these devices work well
in applications that run directly from battery power without regulation. The OPAx388-Q1 are optimized for full rail-
to-rail input, allowing for low-voltage, single-supply operation or split-supply use. These miniature, high-precision,
low-noise amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the supplies
without input crossover distortion and a rail-to-rail output that swings within 5 mV of the supplies under normal
test conditions. The OPAx388-Q1 precision amplifiers are designed for upstream analog signal chain
applications in low or high gains, as well as downstream signal chain functions such as DAC buffering.
8.2 Typical Application
This single-supply, low-side, bidirectional current-sensing design example detects load currents from –1 A to +1
A. The single-ended output spans from 110 mV to 3.19 V. This design uses the OPA388-Q1 because of the low
offset voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and
the other amplifier provides the reference voltage.
图8-1 shows the circuit drawing.
VCC
VREF
VCC
R5
+
U1B
ILOAD
R6
R2
+
R1
+
VBUS
+
œ
VSHUNT
RSHUNT
VOUT
U1A
VCC
R4
R3
œ
RL
图8-1. Bidirectional Current-Sensing
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8.2.1 Design Requirements
This solution has the following requirements:
• Supply voltage: 3.3 V
• Input: –1 A to 1 A
• Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
8.2.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor (RSHUNT) to develop the shunt voltage, VSHUNT. The
shunt voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by 方程式1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
(1)
where
VSHUNT = ILOAD ´ RSHUNT
•
R4
GainDiff_Amp
=
R3
•
R6
R5 + R6
VREF = VCC
´
•
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of
the difference amplifier, ultimately translating to an offset error.
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set to
100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
VSHUNT(Max)
100 mV
= 100 mW
RSHUNT(Max)
=
=
ILOAD(Max)
1 A
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
was selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to 100 mV. This voltage is
divided down by R1 and R2 before reaching the operational amplifier, U1A. Make sure that the voltage present at
the noninverting node of U1A is within the common-mode range of the device. Therefore, use an operational
amplifier, such as the OPA388-Q1, that has a common-mode range that extends below the negative supply
voltage. Finally, to minimize offset error, the OPA388-Q1 has a typical offset voltage of merely ±0.25 µV (±5 µV
maximum).
Given a symmetric load current of –1 A to +1 A, the voltage divider resistors (R5 and R6) must be equal. To be
consistent with the shunt resistor, a tolerance of 0.5% was selected. To minimize power consumption, 10-kΩ
resistors are used.
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To set the gain of the difference amplifier, the common-mode range and output swing of the OPA388-Q1 must be
considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPA388-Q1 given a 3.3-V supply.
–100 mV < VCM < 3.4 V
(3)
(4)
100 mV < VOUT < 3.2 V
The gain of the difference amplifier can now be calculated as shown in Equation 5.
V
OUT_Max - VOUT_Min
3.2 V - 100 mV
100 mW ´ [1 A - (- 1A)]
V
V
= 15.5
=
GainDiff_Amp
=
R
SHUNT ´ (IMAX - IMIN
)
(5)
The resistor value selected for R1 and R3 was 1 kΩ. 15.4 kΩ was selected for R2 and R4 because this number
is the nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
were selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
8.2.3 Application Curve
3.30
1.65
0
-1.0
-0.5
0
0.5
1.0
Input Current (A)
图8-2. Bidirectional Current-Sensing Circuit Performance: Output Voltage vs Input Current
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9 Power Supply Recommendations
The OPAx388-Q1 family of operational amplifiers can be used with single or dual supplies from an operating
range of VS = 2.5 V (±1.25 V) up to 5.5 V (±2.75 V). Key parameters that vary over the supply voltage or
temperature range are shown in 节6.7.
CAUTION
Supply voltages greater than 7 V can permanently damage the device (see 节6.1).
10 Layout
10.1 Layout Guidelines
Pay attention to good layout practice. Keep traces short and, if possible, use a printed-circuit board (PCB)
ground plane with surface-mount components placed as close as possible to the device pins. Place a 0.1-µF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
For lowest offset voltage and precision performance, optimize the circuit layout and mechanical conditions. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by making sure
these potentials are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or greater, depending on the materials used.
10.2 Layout Example
VIN
+
VOUT
RG
RF
图10-1. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
RF
VS+
N/C
N/C
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
图10-2. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
备注
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
11.1.1.2 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
11.1.1.3 TI Precision Designs
The OPAx388-Q1 family is featured on TI Precision Designs, available online at www.ti.com/ww/en/analog/
precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications
experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,
bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following: Texas Instruments, Circuit board layout techniques
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
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11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: OPA388-Q1 OPA2388-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2388QDGKRQ1
OPA388QDBVRQ1
ACTIVE
ACTIVE
VSSOP
SOT-23
DGK
DBV
8
5
2500 RoHS & Green
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
O28Q
388Q
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2021
OTHER QUALIFIED VERSIONS OF OPA2388-Q1, OPA388-Q1 :
Catalog : OPA2388, OPA388
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2388QDGKRQ1
OPA388QDBVRQ1
VSSOP
SOT-23
DGK
DBV
8
5
2500
3000
330.0
180.0
12.4
8.4
5.3
3.4
1.4
8.0
4.0
12.0
8.0
Q1
Q3
3.23
3.17
1.37
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2388QDGKRQ1
OPA388QDBVRQ1
VSSOP
SOT-23
DGK
DBV
8
5
2500
3000
366.0
213.0
364.0
191.0
50.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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