OPA4134UA [TI]
四路 SoundPlus™ 高性能音频运算放大器 | D | 14 | -40 to 85;
| 型号： | OPA4134UA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 四路 SoundPlus™ 高性能音频运算放大器 | D | 14 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总33页 (文件大小：902K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA134, OPA2134, OPA4134
SBOS058A –DECEMBER 1997–REVISED OCTOBER 2015
OPAx134 SoundPlus™ High Performance Audio Operational Amplifiers
1 Features
3 Description
The OPA134 series are ultra-low distortion, low-noise
operational amplifiers fully specified for audio
applications. A true FET input stage is incorporated to
provide superior sound quality and speed for
exceptional audio performance. This, in combination
with high output drive capability and excellent DC
performance, allows for use in a wide variety of
demanding applications. In addition, the OPA134 has
a wide output swing, to within 1 V of the rails,
allowing increased headroom and making it ideal for
use in any audio circuit.
1
•
Superior Sound Quality
Ultra Low Distortion: 0.00008%
Low Noise: 8 nV/√Hz
True FET-Input: IB = 5pA
High Speed:
•
•
•
•
–
–
Slew Rate: 20 V/µs
Bandwidth: 8 MHz
•
•
•
High Open-Loop Gain: 120 dB (600 Ω)
Wide Supply Range: ±2.5 V to ±18 V
Single, Dual, and Quad Versions
The OPA134 SoundPlus™ audio operational
amplifiers are easy to use and free from phase-
inversion and the overload problems often found in
common FET-input operational amplifiers. They can
be operated from ±2.5-V to ±18-V power supplies.
Input cascode circuitry provides excellent common-
mode rejection and maintains low input bias current
over its wide input voltage range, minimizing
distortion. OPA134 series operational amplifiers are
unity-gain stable and provide excellent dynamic
behavior over a wide range of load conditions,
including high load capacitance. The dual and quad
versions feature completely independent circuitry for
lowest crosstalk and freedom from interaction, even
when overdriven or overloaded.
2 Applications
•
•
•
•
•
•
•
•
Professional Audio and Music
Line Drivers
Line Receivers
Multimedia Audio
Active Filters
Preamplifiers
Integrators
Crossover Networks
THD+Noise vs Frequency
Single and dual versions are available in 8-pin DIP
and SO-8 surface-mount packages in standard
configurations. The quad is available in 14-pin DIP
and SO-14 surface mount packages. All are specified
for –40°C to 85°C operation. A SPICE macromodel is
available for design analysis.
0.01
0.001
VO = 10Vrms
RL = 2kW
VS
=
1ꢀ
(1)
Device Information
0.0001
0.00001
PART NUMBER
PACKAGE
BODY SIZE (NOM)
3.91 mm × 4.90 mm
6.35 mm × 9.81 mm
3.91 mm × 4.90 mm
6.35 mm × 9.81 mm
3.91 mm × 8.65 mm
SOIC (8)
OPA134
VS
= 1ꢁ
VS
= 1ꢂ
PDIP (8)
SOIC (8)
PDIP (8)
SOIC (14)
20
100
1k
Frequency (Hz)
10k 20k
OPA2134
OPA4134
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA134, OPA2134, OPA4134
SBOS058A –DECEMBER 1997–REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Electrical Characteristics........................................... 5
6.5 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 16
Power Supply Recommendations...................... 18
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1 Device Support .................................................... 20
11.2 Documentation Support ....................................... 20
11.3 Related Links ........................................................ 20
11.4 Community Resources.......................................... 21
11.5 Trademarks........................................................... 21
11.6 Electrostatic Discharge Caution............................ 21
11.7 Glossary................................................................ 21
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2000) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
2
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SBOS058A –DECEMBER 1997–REVISED OCTOBER 2015
5 Pin Configuration and Functions
OPA134: P and D Packages
8-Pin PDIP and 8-Pin SOIC
Top View
OPA2134: P and D Packages
8-Pin PDIP and 8-Pin SOIC
Top View
Offset Trim
1
2
3
4
8
7
6
5
Offset Trim
V+
Out A
–In A
+In A
V–
1
2
3
4
8
7
6
5
V+
–In
+In
V–
A
Out B
–In B
+In B
Output
NC
B
OPA4134: P and D Packages
14-Pin PDIP and 14-Pin SOIC
Top View
Out A
–In A
+In A
V+
1
2
3
4
5
6
7
14 Out D
13 –In D
A
D
12 +In D
11 V–
+In B
–In B
Out B
10 +In C
B
C
9
8
–In C
Out C
Pin Functions: OPA134
PIN
I/O
DESCRIPTION
NAME
Offset Trim
–In
NO.
1
I
I
Input offset voltage adjust
Inverting input
2
+In
3
I
Noninverting input
V–
4
—
—
O
—
I
Negative power supply
NC
5
No internal connection. Can be left floating.
Output
Output
V+
6
7
Positive power supply
Offset Trim
8
Input offset voltage adjust
Pin Functions: OPA2134 and OPA4134
PIN
I/O
DESCRIPTION
OPA2134
NO.
OPA4134
NO.
NAME
Out A
–In A
+In A
V+
1
2
1
2
O
I
Output channel A
Inverting input channel A
Noninverting input channel A
Positive power supply
Noninverting input channel B
Inverting input channel B
Output channel B
3
3
I
8
4
—
I
+In B
–In B
Out B
Out C
–In C
+In C
5
5
6
6
I
7
7
O
O
I
—
—
—
8
Output channel C
9
Inverting input channel C
Noninverting input channel C
10
I
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SBOS058A –DECEMBER 1997–REVISED OCTOBER 2015
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Pin Functions: OPA2134 and OPA4134 (continued)
PIN
I/O
DESCRIPTION
OPA2134
NO.
OPA4134
NO.
NAME
V–
4
11
12
13
14
—
I
Negative power supply
Noninverting input channel D
Inverting input channel D
Output channel D
+In D
–In D
Out D
—
—
—
I
O
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
(V–) –0.7
–40
MAX
36
UNIT
V
Supply voltage, V+ to V–
Input voltage
Output short circuit(2)
Operating temperature
Junction temperature
Lead temperature (soldering, 10 s)
(V+) +0.7
Continuous
125
V
°C
°C
°C
°C
150
300
Tstg
Storage temperature
–55
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
OPA134 in PDIP and SOIC Package, OPA2134 and OPA4134 in PDIP Package
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
OPA2134 in SOIC Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
OPA4134 in SOIC Package
V(ESD) Electrostatic discharge
Electrostatic discharge
V
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±200
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.5
–40
NOM
MAX
±18
85
UNIT
V
VS
TA
Supply voltage, VS = (V+) – (V–)
Specified temperature
±15
°C
4
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SBOS058A –DECEMBER 1997–REVISED OCTOBER 2015
6.4 Electrical Characteristics
At TA = +25°C, VS = ±15 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
RL = 2 kΩ
0.00008%
0.00015%
–98
G = 1, f = 1 kHz, VO = 3
Vrms
Total Harmonic Distortion + Noise
RL = 600 Ω
Intermodulation Distortion
Headroom(1)
G = 1, f = 1 kHz, VO = 1 Vp-p
dB
THD < 0.01%, RL = 2 kΩ , VS = 18 V
23.6
dBu
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate(2)
8
±20
1.3
0.7
1
MHz
V/µs
MHz
µs
±15
Full Power Bandwidth
Settling Time 0.1%
Settling Time 0.01%
Overload Recovery Time
NOISE
G = 1, 10-V Step, CL = 100 pF
G = 1, 10-V Step, CL = 100 pF
(VIN) × (Gain) = VS
µs
0.5
µs
Noise Voltage,
f = 20 Hz to 20 kHz
1.2
µVrms
Input Voltage
Noise
Noise Density,
f = 1 kHz
8
3
nV/√Hz
fA/√Hz
Current Noise Density, f = 1 kHz
OFFSET VOLTAGE
±0.5
±1
±2
±3(3)
Input Offset Voltage
mV
TA = –40°C to 85°C
TA = –40°C to 85°C
Input Offset Voltage vs Temperature
±2
µV/°C
dB
Input Offset Voltage vs Power Supply
(PSRR)
VS = ±2.5 V to ±18 V
90
106
DC, RL = 2 kΩ
135
130
Channel Seperation (Dual, Quad)
dB
f = 20 kHz, RL = 2 kΩ
INPUT BIAS CURRENT
Input Bias Current(4)
VCM = 0 V
VCM = 0 V
5
±100
±5
pA
nA
pA
See Typical
Characteristics
Input Bias Current vs Temperature(3)
Input Offset Current(4)
±2
±50
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
(V–)+2.5
86
13
100
90
(V+)–2.5
V
VCM = –12.5 V to 12.5 V
TA = –40°C to 85°C
Common-Mode Rejection
dB
INPUT IMPEDANCE
Differential
1013 || 2
1013 || 5
Ω || pF
Ω || pF
Common-Mode
OPEN-LOOP GAIN
VCM = –12.5 V to 12.5 V
RL = 10 kΩ , VO = –14.5 V to 13.8 V
RL = 2 kΩ , VO = –13.8 V to 13.5 V
RL = 600 Ω , VO = –12.8 V to 12.5 V
104
104
104
120
120
120
Open-Loop Voltage Gain
dB
(1) dBu = 20*log (Vrms/0.7746) where Vrms is the maximum output voltage for which THD+Noise is less than 0.01%. See THD+Noise text.
(2) Proposed by design.
(3) Proposed by wafer-level test to 95% confidence level.
(4) High-speed test at TJ = 25°C.
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SBOS058A –DECEMBER 1997–REVISED OCTOBER 2015
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Electrical Characteristics (continued)
At TA = +25°C, VS = ±15 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
RL = 10 kΩ
RL = 2 kΩ
RL = 600 Ω
(V–)+0.5
(V–)+1.2
(V–)+2.2
(V+)–1.2
(V+)–1.5
(V+)–2.5
Voltage Output
V
Output Current
±35
0.01
10
mA
Ω
Output Impedance, Closed-Loop(5)
Output Impedance, Open-Loop
Short-Circuit Current
f = 10 kHz
f = 10 kHz
Ω
±40
mA
Capacitive Lead Drive (Stable
Operation)
See Typical
Characteristics
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current (per amplifier)
TEMPERATURE RANGE
Specified Range
±15
4
V
V
±2.5
±18
5
IO = 0
mA
–40
–55
85
°C
°C
Operating Range
125
(5) See Figure 14
6
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SBOS058A –DECEMBER 1997–REVISED OCTOBER 2015
6.5 Typical Characteristics
At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
5
1
0.1
G = +1
RL
f = 1kHz
RL = 2kW
2kW
600W
0.01
0.1
0.001
OPA134
OP176
G = +10
0.010
OPA134
0.0001
Baseline
G = +1
VO = 3Vrms
0.001
0.0005
0.00001
30m
10
30
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Output Amplitude (Vpp)
Figure 1. Total Harmonic Distortion + Noise vs Frequency
Figure 2. SMPTE Intermodulation Distortion vs Output
Amplitude
0.01
1
VS
=
1ꢀV
THD < 0.01%
VO = 10Vrms
RL = 2kW
RL = 2kW
f = 1kHz
OPA134 – 11.7Vrms
OP176 – 11.1Vrms
0.1
0.001
VS
=
1ꢀ
0.010
OPA134
Baseline
0.0001
OPA134
OP176
0.001
VS
= 1ꢁ
VS
= 1ꢂ
0.00001
0.0005
20
100
1k
Frequency (Hz)
10k 20k
0.1
10
20
1
Output Amplitude (Vrms)
Figure 3. Total Harmonic Distortion + Noise vs Frequency
Figure 4. Headroom – Total Harmonic Distortion + Noise vs
Output Amplitude
1k
0.01
2nd Harmonic
3rd Harmonic
OP176+
Resistor
0.001
100
= 600W
L
R
0.0001
10
OPA134+
Resistor
= 2kW
L
R
0.00001
1
Resistor Noise
Vn (total) = Ö(ni RS)2 + en2 + 4kTRS
Only
VO = 1Vrms
10k 20k
0.000001
0.1
20
100
1k
10
100
1k
10k
100k
1M
10M
Source Resistance (W)
Frequency (Hz)
Figure 6. Voltage Noise vs Source Resistance
Figure 5. Harmonic Distortion + Noise vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
1k
100
10
1
RS = 20W
100
Peak-to-Peak
RMS
Voltage Noise
10
Current Noise
1
0.1
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
Frequency (Hz)
Noise Bandwidth (Hz)
Figure 7. Input Voltage and Current Noise Spectral Density
vs Frequency
Figure 8. Input-Referred Noise Voltage vs Noise Bandwidth
160
140
120
100
80
0
50
40
G = +100
–45
–90
–135
–180
30
f
20
G = +10
60
10
40
0
G
G = +1
20
–10
–20
0
–20
1k
10k
100k
1M
10M
0.1
1
10
100
1k
10k 100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 10. Closed-Loop Gain vs Frequency
Figure 9. Open-Loop Gain and Phase vs Frequency
120
160
140
120
100
80
RL = ∞
100
80
60
40
20
0
–PSR
RL = 2kW
Dual and quad devices.
G = 1, all channels.
Quad measured channel
A to D or B to C—other
combinations yield improved
rejection.
+PSR
CMR
10
100
1k
10k
100k
1M
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 11. Power Supply and Common-Mode Rejection vs
Frequency
Figure 12. Channel Separation vs Frequency
8
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Typical Characteristics (continued)
At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
30
Maximum output voltage
10
1
Note: Open-Loop
Output Impedance
at f = 10kHz is 10W
VS
=
1ꢀV
without slew-rate
induced distortion
20
10
0
0.1
G = +100
0.01
0.001
0.0001
G = +10
G = +2
G = +1
VS
VS
=
ꢀV
=
2ꢁꢀV
10k
100k
Frequency (Hz)
1M
10M
10
100
1k
10k
100k
Frequency (Hz)
Figure 14. Closed-Loop Output Impedance vs Frequency
Figure 13. Maximum Output Voltage vs Frequency
100k
10
High Speed Test
Warmed Up
9
8
7
6
5
4
3
2
1
0
High Speed Test
10k
1k
100
10
Dual
1
Single
0.1
–75
–50
–25
0
25
50
75
100
125
–15
–10
–5
0
5
10
15
Ambient Temperature (°C)
Common-Mode Voltage (V)
Figure 15. Input Bias Current vs Temperature
Figure 16. Input Bias Current vs Input Common-Mode
Voltage
120
150
140
130
120
110
100
RL = 600W
RL = 2kW
110
PSR
100
CMR
90
RL = 10kW
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
Ambient Temperature (°C)
Figure 17. Open-Loop Gain vs Temperature
Figure 18. CMR, PSR vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
15
14
13
12
11
10
4.3
4.2
4.1
4.0
3.9
3.8
60
50
40
30
20
10
VIN = 15V
–55°C
25°C
125°C
85°C
± ±SC
–10
–11
–12
–13
–14
–15
85°C
± ±Q
125°C
–55°C
25°C
VIN = –15V
10
0
20
30
40
50
60
–75
–50
–25
0
25
50
75
100
125
Output Current (mA)
Ambient Temperature (°C)
Figure 19. Quiescent Current and Short-Circuit Current vs
Temperature
Figure 20. Output Voltage Swing vs Output Current
18
12
Typical production
Typical production
16
distribution of packaged
distribution of packaged
10
units.
units.
14
12
10
8
8
6
4
2
0
6
4
2
0
Offset Voltage Drift (µV/°C)
Offset Voltage (V)
Figure 22. Offset Voltage Drift Production Distribution
Figure 21. Offset Voltage Production Distribution
200ns/div
1μs/div
Figure 23. Small-Signal Step Response G = 1, CL = 100 pF
Figure 24. Large-Signal Step Response G = 1, CL = 100 pF
10
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Typical Characteristics (continued)
At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
100
60
50
40
30
20
10
0
G = +1
0.01%
10
G = –1
0.1%
1
G = 10
0.1
1
10
100
1000
100pF
1nF
10nF
Closed-Loop Gain (V/V)
Load Capacitance
Figure 25. Settling Time vs Closed-Loop Gain
Figure 26. Small-Signal Overshoot vs Load Capacitance
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7 Detailed Description
7.1 Overview
The OPA134 series are ultra-low distortion, low-noise operational amplifiers fully specified for audio applications.
A true FET input stage is incorporated to provide superior sound quality and speed for exceptional audio
performance. This, in combination with high output drive capability and excellent DC performance, allows for use
in a wide variety of demanding applications. In addition, the OPA134 has a wide output swing, to within 1 V of
the rails, allowing increased headroom and making it ideal for use in any audio circuit.
7.2 Functional Block Diagram
Input Offset
Adjust
(OPA134 only)
+IN
-IN
+
œ
Output
Input Offset
Adjust
Compensation
(OPA134 only)
7.3 Feature Description
7.3.1 Total Harmonic Distortion
The OPA134 series of operational amplifiers have excellent distortion characteristics. THD+Noise is below
0.0004% throughout the audio frequency range, 20 Hz to 20 kHz, with a 2-kΩ load. In addition, distortion remains
relatively flat through its wide output voltage swing range, providing increased headroom compared to other
audio amplifiers, including the OP176/275.
Headroom is a subjective measurement, and can be thought of as the maximum output amplitude allowed while
still maintaining a low level of distortion. In an attempt to quantify headroom, TI defines very low distortion as
0.01%. Headroom is expressed as a ratio which compares the maximum allowable output voltage level to a
standard output level (1 mW into 600 Ω, or 0.7746 Vrms). Therefore, OPA134 series of operational amplifiers,
which have a maximum allowable output voltage level of 11.7 Vrms (THD+Noise < 0.01%), have a headroom
specification of 23.6 dBu. See Figure 4.
7.3.2 Distortion Measurements
The distortion produced by OPA134 series of operational amplifiers is below the measurement limit of all known
commercially-available equipment. However, a special test circuit can extend the measurement capabilities.
Operational amplifier distortion can be considered an internal error source which can be referred to the input.
Figure 27 shows a circuit which causes the operational amplifier distortion to be 101 times greater than that
which the operational amplifier normally produces. The addition of R3 to the otherwise standard non-inverting
amplifier configuration alters the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged,
but the feedback available for error correction is reduced by a factor of 101, thus extending the resolution by 101.
The input signal and load applied to the operational amplifier are the same as with conventional feedback without
R3. The value of R3 should be kept small to minimize its effect on the distortion measurements.
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Feature Description (continued)
R1
R2
SIG. DIST.
R1
R2
R3
10W
11W
∞
GAIN GAIN
1
101
1kW
∞
101 100W 1kW
11
R3
OPA134
VO = 3Vrms
101
101 10W 1kW
R2
Signal Gain = 1+
R1
R2
Distortion Gain = 1+
R1 II R3
Generator
Output
Analyzer
Input
Audio Precision
System One
Analyzer(1)
IBM PC
or
RL
1kW
Compatible
NOTE: (1) Measurement BW = 80kHz
Figure 27. Distortion Test Circuit
This technique can be verified by duplicating measurements at high gain or high frequency, where the distortion
is within the measurement capability of the test equipment. Measurements for this data sheet were made with an
Audio Precision distortion and noise analyzer, which greatly simplifies repetitive measurements. The
measurement technique can, however, be performed with manual distortion measurement instruments.
7.3.3 Source Impedance and Distortion
For lowest distortion with a source or feedback network with an impedance greater than 2 kΩ, the impedance
seen by the positive and negative inputs in noninverting applications should be matched. The p-channel JFETs in
the FET input stage exhibit a varying input capacitance with applied common-mode input voltage. In inverting
configurations, the input does not vary with input voltage, because the inverting input is held at virtual ground.
However, in noninverting applications the inputs do vary, and the gate-to-source voltage is not constant. The
effect is increased distortion due to the varying capacitance for unmatched source impedances greater than 2
kΩ.
To maintain low distortion, match unbalanced source impedance with the appropriate values in the feedback
network as shown in Figure 28. Of course, the unbalanced impedance may be from gain-setting resistors in the
feedback path. If the parallel combination of R1 and R2 is greater than 2 kΩ, use a matching impedance on the
noninverting input. As always, minimize resistor values to reduce the effects of thermal noise.
R1
R2
VOUT
OPA134
VIN
If RS > 2kW or R II R2 > 2kW
1
RS = R1 II R2
Figure 28. Impedance Matching for Maintaining Low Distortion in Non-Inverting Circuits
7.3.4 Phase Reversal Protection
The OPA134 series of operational amplifiers are free from output phase-reversal problems. Many audio
operational amplifiers, such as the OP176, exhibit phase-reversal of the output when the input common-mode
voltage range is exceeded. This can occur in voltage-follower circuits, causing serious problems in control loop
applications. The OPA134 series operational amplifiers are free from this undesirable behavior even with inputs
of 10-V beyond the input common-mode range.
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Feature Description (continued)
7.3.5 Output Current Limit
Output current is limited by internal circuitry to approximately ±40 mA at 25°C. The limit current decreases with
increasing temperature, as shown in Figure 19.
7.4 Device Functional Modes
7.4.1 Noise Performance
Circuit noise is determined by the thermal noise of external resistors and operational amplifier noise. Operational
amplifier noise is described by two parameters: noise voltage and noise current. The total noise is quantified by
the equation:
Vn(total) = i R 2 en + 4kTRS
2
(
)
n
S
(1)
With low source impedance, the current noise term is insignificant and voltage noise dominates the noise
performance. At high source impedance, the current noise term becomes the dominant contributor.
Low-noise bipolar operational amplifiers such as the OPA27 and OPA37 provide low voltage noise at the
expense of a higher current noise. However, OPA134 series operational amplifiers provide both low voltage
noise and low current noise. This provides optimum noise performance over a wide range of sources, including
reactive source impedances; refer to Figure 6. Above 2-kΩ source resistance, the operational amplifier
contributes little additional noise; the voltage and current terms in the total noise equation become insignificant
and the source resistance term dominates. Below 2 kΩ, operational amplifier voltage noise dominates over the
resistor noise, but compares favorably with other audio operational amplifiers such as the OP176.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA134 series operational amplifiers are unity-gain stable, and suitable for a wide range of audio and
general-purpose applications. All circuitry is independent in the dual version, assuring normal behavior when one
amplifier in a package is overdriven or short-circuited. Power supply pins should be bypassed with 10-nF ceramic
capacitors or larger to minimize power supply noise.
8.1.1 Operating Voltage
The OPA134 series of operational amplifiers operate with power supplies from ±2.5 V to ±18 V with excellent
performance. Although specifications are production tested with ±15-V supplies, most behavior remains
unchanged throughout the full operating voltage range. Parameters which vary significantly with operating
voltage are shown in Typical Characteristics.
8.1.2 Offset Voltage Trim
Offset voltage of OPA134 series amplifiers is laser-trimmed, and usually requires no user adjustment. The
OPA134 (single operational amplifier version) provides offset trim connections on pins 1 and 8, identical to 5534
amplifiers. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure 29. This adjustment
should be used only to null the offset of the operational amplifier, not to adjust system offset or offset produced
by the signal source. Nulling offset could change the offset voltage drift behavior of the operational amplifier.
While it is not possible to predict the exact change in drift, the effect is usually small.
V+
Trim Range: 4mV typ
10nF
100kW
7
1
2
8
OPA134
6
3
OPA134 single op amp only.
4
10nF
Use offset adjust pins only to null
offset voltage of op amp—see text.
V–
Figure 29. OPA134 Offset Voltage Trim Circuit
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8.2 Typical Application
The OPAx134 family offers outstanding dc precision and AC performance. These devices operate up to 36-V
supply rails and offer ultralow distortion and noise, as well as 8-MHz bandwidth and high capacitive load drive.
These features make the OPAx134 a robust, high-performance operational amplifier for high-voltage professional
audio applications.
2.94 kꢀ
1 nF
590 ꢀ
499 ꢀ
Input
œ
Output
39 nF
+
Figure 30. OPA134 2nd Order 30-kHz, Low Pass Filter Schematic
8.2.1 Design Requirements
•
•
•
•
Gain = 5 V/V (inverting)
Low pass cutoff frequency = 30 kHz
–40 db/dec filter response
Maintain less than 3-dB gain peaking in the gain versus frequency response
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 30. The voltage
transfer function is:
-1 R1R3C2C5
Output
Input
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
2
1
3
4
3 4 2 5
(2)
This circuit produces a signal inversion. For this circuit the gain at DC and the low pass cutoff frequency are
calculated using Equation 3.
R4
Gain =
R1
1
fC =
1 R R C C
(
3 4 2 5
)
2p
(3)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
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Typical Application (continued)
8.2.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
100k
1M
Frequency (Hz)
Figure 31. OPA134 2nd Order 30-kHz, Low Pass Filter Response
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9 Power Supply Recommendations
The OPAx134 is specified for operation from 5 V to 36 V (±2.5 V to ±18 V); many specifications apply from
–40°C to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 36 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 10-nF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 10-nF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
VIN
+
VOUT
RG
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
Offset trim
Offset trim
RG
GND
VIN
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
Use low-ESR, ceramic
bypass capacitor
GND
Use low-ESR,
ceramic bypass
capacitor
VOUT
VSœ
Ground (GND) plane on another layer
Figure 32. OPA134 Layout Example for the Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 WEBENCH Filter Designer Tool
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
11.1.1.2 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.3 TI Precision Designs
The OPAx134 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
EMI Rejection Ratio of Operational Amplifiers, SBOA128
Circuit Board Layout Techniques, SLOA089
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
OPA134
OPA2134
OPA4134
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
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SBOS058A –DECEMBER 1997–REVISED OCTOBER 2015
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
SoundPlus, TINA-TI, E2E are trademarks of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA134PA
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
OPA134PA
Samples
OPA134PAG4
OPA134UA
LIFEBUY
ACTIVE
PDIP
SOIC
P
D
8
8
50
75
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
N / A for Pkg Type
OPA134PA
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
OPA
134UA
Samples
Samples
OPA134UA/2K5
OPA134UAE4
OPA134UAG4
ACTIVE
LIFEBUY
LIFEBUY
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
OPA
134UA
75
75
RoHS & Green
RoHS & Green
OPA
134UA
OPA
134UA
OPA2134PA
OPA2134PAG4
OPA2134UA
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
SOIC
P
P
D
8
8
8
50
50
75
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
N / A for Pkg Type
N / A for Pkg Type
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
OPA2134PA
Samples
Samples
Samples
OPA2134PA
OPA
2134UA
OPA2134UA/2K5
OPA2134UA/2K5E4
OPA2134UAE4
ACTIVE
LIFEBUY
LIFEBUY
LIFEBUY
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
OPA
2134UA
Samples
OPA
2134UA
75
75
50
RoHS & Green
RoHS & Green
RoHS & Green
OPA
2134UA
OPA2134UAG4
OPA
2134UA
OPA4134UA
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
OPA4134UA
Samples
Samples
OPA4134UA/2K5
2500 RoHS & Green
2500 RoHS & Green
OPA4134UA
OPA4134UA/2K5E4
OPA4134UAE4
LIFEBUY
LIFEBUY
ACTIVE
SOIC
SOIC
SOIC
D
D
D
14
14
8
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
OPA4134UA
OPA4134UA
50
RoHS & Green
SN412008DRE4
2500 RoHS & Green
OPA
2134UA
Samples
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA134UA/2K5
OPA2134UA/2K5
OPA4134UA/2K5
SOIC
SOIC
SOIC
D
D
D
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
16.4
6.4
6.4
6.5
5.2
5.2
9.0
2.1
2.1
2.1
8.0
8.0
8.0
12.0
12.0
16.0
Q1
Q1
Q1
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA134UA/2K5
OPA2134UA/2K5
OPA4134UA/2K5
SOIC
SOIC
SOIC
D
D
D
8
8
2500
2500
2500
356.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
14
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA134PA
OPA134PAG4
OPA134UA
P
P
D
D
D
P
P
D
D
D
D
D
PDIP
PDIP
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
8
8
50
50
75
75
75
50
50
75
75
75
50
50
506
506
13.97
11230
11230
3940
3940
3940
11230
11230
3940
3940
3940
3940
3940
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
13.97
8
506.6
506.6
506.6
506
8
OPA134UAE4
OPA134UAG4
OPA2134PA
8
8
8
8
8
13.97
OPA2134PAG4
OPA2134UA
8
506
13.97
8
506.6
506.6
506.6
506.6
506.6
8
8
8
8
8
OPA2134UAE4
OPA2134UAG4
OPA4134UA
8
8
14
14
OPA4134UAE4
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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