OPA4187IRUMT [TI]
零漂移（10µV、0.001µV/°C）、多路复用器友好型、低噪声、RRO、CMOS 四路精密运算放大器（四路） | RUM | 16 | -40 to 125;
| 型号： | OPA4187IRUMT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 零漂移（10µV、0.001µV/°C）、多路复用器友好型、低噪声、RRO、CMOS 四路精密运算放大器（四路） | RUM | 16 | -40 to 125 放大器 运算放大器 复用器 |
| 文件： | 总45页 (文件大小：2408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA187, OPA2187, OPA4187
SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
OPAx187 0.001-µV/°C Drift, Low Power, Rail-to-Rail Output
36-V Operational Amplifiers Zero-Drift Series
1 Features
3 Description
The OPAx187 series operational amplifiers use auto-
1
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•
•
•
•
•
•
•
•
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•
Low Offset Voltage: 10 µV (maximum)
Zero Drift: 0.001 µV/°C
Low Noise: 15 nV/√Hz
zeroing techniques to simultaneously provide low-
offset voltage (1 µV), and near zero drift over time
and temperature. These miniature, high-precision,
low-quiescent current amplifiers offer high-input
impedance and rail-to-rail output swing within 5 mV of
the rails into high-impedance loads. The input
common-mode range includes the negative rail.
Either single or dual supplies can be used in the
range of 4.5 V to 36 V (±2.25 V to ±18 V).
PSRR: 160 dB
CMRR: 140 dB
AOL: 160 dB
Quiescent Current: 100 µA
Wide Supply Voltage: ±2.25 V to ±18 V
Rail-to-Rail Output Operation
Input Includes Negative Rail
Low Bias Current: 100 pA (typical)
EMI Filtered Inputs
The single version of the OPAx187 device is
available in microsize 8-pin VSSOP, 5-pin SOT-23,
and 8-pin SOIC packages. The dual version is offered
in 8-pin VSSOP and 8-pin SOIC packages. The quad
version is offered in 14-pin SOIC, 14-pin TSSOP, and
16-pin WQFN packages. All versions are specified for
operation from –40°C to +125°C.
Microsize Packages
2 Applications
Device Information(1)
•
•
•
•
•
•
•
•
•
•
Bridge Amplifier
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.90 mm × 3.91 mm
2.90 mm × 1.60 mm
3.00 mm × 3.00 mm
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
8.70 mm × 3.90 mm
5.00 mm × 4.40 mm
Strain Gauge
SOIC (8)
Test and Measurement Equipment
Transducer Application
Temperature Measurement
Electronic Scales
OPA187
SOT-23 (5)
VSSOP (8)
SOIC (8)
OPA2187
OPA4187
VSSOP (8)
SOIC (14)
TSSOP (14)
Medical Instrumentation
RTD Amplifier
WQFN (16)
(Preview)
Precision Active Filters
Low-Side Current Monitoring
4.00 mm × 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
OPAx187 Offers Precision Low-Side Current Measurement Capability
+
Load
VSUPPLY
100 kꢀ
GND
œ
VSUPPLY
100 ꢀ
+
VOUT
OPA187
RSHUNT
100 ꢀ
œ
GND
I
I
100 kꢀ
GND
G = 1000 • RSHUNT • I
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA187, OPA2187, OPA4187
SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Applications ................................................ 21
Power Supply Recommendations...................... 25
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information: OPA187 .................................. 6
6.5 Thermal Information: OPA2187 ................................ 6
6.6 Thermal Information: OPA4187 ................................ 6
6.7 Electrical Characteristics: High-Voltage Operation.. 7
6.8 Electrical Characteristics: Low-Voltage Operation... 8
6.9 Typical Characteristics.............................................. 9
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1 Device Support .................................................... 27
11.2 Documentation Support ....................................... 27
11.3 Related Links ........................................................ 28
11.4 Receiving Notification of Documentation Updates 28
11.5 Community Resources.......................................... 28
11.6 Trademarks........................................................... 28
11.7 Electrostatic Discharge Caution............................ 28
11.8 Glossary................................................................ 28
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2018) to Revision D
Page
•
•
Changed OPA4187 SOIC and TSSOP packages from product preview to production data................................................. 1
Changed offset drift (high and low supply) max to ±15nV/°C................................................................................................. 8
Changes from Revision B (October 2018) to Revision C
Page
•
First release of production OPA187 SOIC device.................................................................................................................. 1
Changes from Revision A (July 2017) to Revision B
Page
•
•
•
•
•
•
•
Changed OPA187 SOIC status to preview ............................................................................................................................ 1
Changed OPA4187 SOIC, TSSOP and WQFN status to preview......................................................................................... 1
Changed offset drift (high supply) typical from ±5 nV/℃ to ±1 nV/℃ and max from ±50 nV/℃ to ±20 nV/℃ ...................... 7
Changed input bias current max (high supply) from ±5 nA to ±7.5 nA .................................................................................. 7
Changed input offset current max (high supply) from ±5 nA to ±14.5 nA .............................................................................. 7
Changed offset drift (low supply) typical from ±5 nV/℃ to ±1 nV/℃ and max from ±50 nV/℃ to ±20 nV/℃ ........................ 8
Changed Offset Voltage Production Distribution figure........................................................................................................ 10
Changes from Original (December 2016) to Revision A
Page
•
•
•
•
•
Deleted VSON package option from the Description ............................................................................................................. 1
Deleted VSON package option from the Device Information table ........................................................................................ 1
Added WQFN package option to the Device Information table.............................................................................................. 1
Deleted OPA187 DRG package option from Pin Configuration and Functions ..................................................................... 3
Added WQFN package to Pin Configuration and Functions .................................................................................................. 4
2
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Product Folder Links: OPA187 OPA2187 OPA4187
OPA187, OPA2187, OPA4187
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SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
5 Pin Configuration and Functions
OPA187: DBV Package
5-Pin SOT-23
OPA187: D and DGK Packages
8-Pin SOIC and 8-pin VSSOP
Top View
Top View
OUT
Vœ
1
2
3
5
V+
NC
œIN
+IN
Vœ
1
2
3
4
8
7
6
5
NC
V+
œ
OUT
NC
+
+IN
4
œIN
Not to scale
Not to scale
(1) NC denotes no internal connection.
Pin Functions: OPA187
PIN
I/O
DESCRIPTION
NAME
+IN
–IN
DBV
D and DGK
3
4
3
I
Non-inverting input
Inverting input
2
I
NC
—
1
1, 5, 8
—
O
—
—
No connection (can be left floating)
Output signal
OUT
V+
6
7
4
5
Positive (highest) supply voltage
Negative (lowest) supply voltage
V–
2
OPA2187: D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Pin Functions: OPA2187
PIN
I/O
DESCRIPTION
NAME
+IN A
–IN A
+IN B
–IN B
OUT A
OUT B
V+
D and DGK
3
2
5
6
1
7
8
4
I
I
Non-inverting input, channel A
Inverting input, channel A
Non-inverting input, channel B
Inverting input, channel B
Output, channel A
I
I
O
O
—
—
Output, channel B
Positive (highest) supply voltage
Negative (lowest) supply voltage
V–
Copyright © 2016–2018, Texas Instruments Incorporated
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OPA187, OPA2187, OPA4187
SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
www.ti.com
OPA4187: D and PW Packages
14-pin SOIC and 14-Pin TSSOP
Top View
OPA4187: RUM Package (Preview)
16-pin WQFN
Top View
OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
Pin Functions: OPA4187
PIN
I/O
DESCRIPTION
NAME
D and PW
RUM
+IN A
–IN A
+IN B
–IN B
+IN C
–IN C
+IN D
–IN D
OUT A
OUT B
OUT C
OUT D
V+
3
2
2
1
I
I
Non-inverting input, channel A
Inverting input, channel A
Non-inverting input, channel B
Inverting input, channel B
Non-inverting input, channel C
Inverting input, channel C
Non-inverting input, channel D
Inverting input, channel D
Output, channel A
5
4
I
6
5
I
10
9
9
I
8
I
12
13
1
11
12
15
6
I
I
O
O
O
O
—
—
—
7
Output, channel B
8
7
Output, channel C
14
4
14
3
Output, channel D
Positive (highest) supply voltage
Negative (lowest) supply voltage
No internal connection (can be left floating)
V–
11
—
10
13, 16
NC
4
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Product Folder Links: OPA187 OPA2187 OPA4187
OPA187, OPA2187, OPA4187
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SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
Supply, VS = (V+) – (V–)
Voltage
Current
Signal input pin(2)
Signal output pin(3)
Signal input pin(2)
Signal output pin(3)
Output short-circuit(4)
Operating range, TA
(V–) – 0.5
(V–) – 0.5
–10
(V+) + 0.5
(V+) + 0.5
10
V
mA
mA
–55
55
Continuous
–55
Continuous Continuous
150
Temperature Junction, TJ
Storage, Tstg
150
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to ±10 mA or less.
(3) Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more than 0.5 V beyond the supply rails
should be current limited to ±55 mA or less.
(4) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5 (±2.25)
–40
NOM
MAX
36 (±18)
150
UNIT
V
(V+) – (V–)
TA
Supply voltage
Operating temperature
°C
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SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
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6.4 Thermal Information: OPA187
OPA187
5 PINS
8 PINS
THERMAL METRIC(1)
UNIT
DGK
(VSSOP)
DBV (SOT-23)
D (SOIC)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
273.8
159
37
100.1
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
126.8
85.9
10.9
84.9
n/a
42.4
41.0
4.8
49
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
77.1
n/a
ψJB
40.3
n/a
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2187
OPA2187
THERMAL METRIC(1)
8 PINS
DGK (VSSOP)
159
UNIT
D (SOIC)
100.1
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
37
42.4
41.0
4.8
49
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
77.1
n/a
ψJB
40.3
n/a
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4187
OPA4187
THERMAL METRIC(1)
14 PINS
PW (TSSOP)
16 PINS
RUM (WQFN)
35.3
UNIT
D (SOIC)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
107.8
29.6
52.6
1.5
83.8
70.7
59.5
11.6
37.7
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
32.7
12.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
51.6
n/a
12.9
RθJC(bot)
3.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
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Product Folder Links: OPA187 OPA2187 OPA4187
OPA187, OPA2187, OPA4187
www.ti.com
SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
6.7 Electrical Characteristics: High-Voltage Operation
at TA = +25°C, VS = ±4 V to ±18 V (VS = +8 V to +36 V), RL = 10 kΩ connected to VS / 2(1), and VCM = VOUT = VS / 2(1) (unless
otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±1
±10
μV
VOS
Input offset voltage
TA = –40°C to +125°C
±0.001
±0.015
μV/°C
VS = 4.5 V to 36 V, TA = –40°C to
+125°C
PSRR
Power-supply rejection ratio
±0.01
±1
μV/V
INPUT BIAS CURRENT
VCM = VS / 2
±100
±100
±350
±7.5
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to +125°C
±500
±14.5
IOS
Input offset current
TA = –40°C to +125°C
NOISE
en
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 1 kHz
0.4
60
µVPP
nVrms
nV/√Hz
fA/√Hz
Input voltage noise
Input voltage noise density
Input current noise density
20
in
f = 1 kHz
160
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
(V–) – 0.1
126
(V+) – 2
V
(V–) – 0.1 V < VCM < (V+) – 2 V, VS
±18 V
=
140
145
dB
CMRR
Common-mode rejection ratio
(V–) < VCM < (V+) – 2 V, VS = ±18 V,
TA = –40°C to +125°C
130
dB
INPUT IMPEDANCE
ZID
ZIC
Differential
Common-mode
100 || 6
6 || 4.2
MΩ || pF
1012 Ω || pF
OPEN-LOOP GAIN
TA = –40°C to +125°C, VS = ±4 V to ±18
AOL
Open-loop voltage gain
V, (V–) + 0.3 V < VO < (V+) – 0.3 V, RL
=
132
160
dB
10 kΩ
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
550
0.2
46
48
8
kHz
V/μs
μs
Slew rate
VO = 10-V step, G = +1
VS = ±18 V, G = 1, 10-V step
VS = ±18 V, G = 1, 10-V step
VIN × G = VS
0.1%
tS
Settling time
0.01%
μs
tOR
Overload recovery time
μs
1 kHz, G = +1, VOUT = 3.5 VRMS, No
Load
THD+N
OUTPUT
Total harmonic distortion + noise
0.035%
VS = ±4 V to ±18 V, No Load
5
15
VS = ±4 V to ±18 V, RL = 10 kΩ
75
100
Voltage output swing from rail
Short-circuit current
mV
VS = ±4 V to ±18 V, RL = 10 kΩ, TA
–40°C to +125°C
=
100
125
VS = ±18 V, Sinking
–30
+30
1.4
mA
mA
kΩ
ISC
VS = ±18 V, Sourcing
RO
Open-loop output resistance
Capacitive load drive
f = 550 kHz, IO = 0, See Figure 21
CLOAD
See Typical Characteristics
POWER SUPPLY
VS = ±4 V to VS = ±18 V
100
145
150
μA
μA
IQ
Quiescent current (per amplifier)
IO = 0 mA, TA = –40°C to +125°C
(1) VS / 2 = midsupply.
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6.8 Electrical Characteristics: Low-Voltage Operation
at TA = +25°C, VS = ±2.25 V to < ±4 V (VS = +4.5 V to < +8 V), RL = 10 kΩ connected to VS / 2(1), and VCM = VOUT = VS / 2(1)
(unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±1
±15
μV
VOS
Input offset voltage
TA = –40°C to +125°C
±0.001
±0.015
μV/°C
VS = 4.5 V to 36 V,
TA = –40°C to +125°C
PSRR
Power-supply rejection ratio
±0.01
±1
μV/V
INPUT BIAS CURRENT
VCM = VS / 2
±100
±100
±350
±5
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to +125°C
±500
±5
IOS
Input offset current
TA = –40°C to +125°C
NOISE
en
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 1 kHz
0.4
60
µVPP
nVrms
nV/√Hz
fA/√Hz
Input voltage noise
Input voltage noise density
Input current noise density
20
in
f = 1 kHz
160
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
(V–) – 0.1
114
(V+) – 2
V
(V–) – 0.1 V < VCM < (V+) – 2 V, VS
±2.25 V
=
130
137
dB
CMRR
Common-mode rejection ratio
(V–) < VCM < (V+) – 2 V, VS = ±2.25 V,
TA = –40°C to +125°C
120
dB
INPUT IMPEDANCE
ZID
ZIC
Differential
Common-mode
100 || 6
6 || 4.2
MΩ || pF
1012 Ω || pF
OPEN-LOOP GAIN
TA = –40°C to +125°C, VS = ±2.25 V
to ±4 V, (V–) + 0.3 V < VO < (V+) – 0.3
V, RL = 10 kΩ
AOL
Open-loop voltage gain
120
140
dB
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
550
0.2
kHz
V/μs
μs
Slew rate
VO = 1-V step, G = +1
tOR
Overload recovery time
Total harmonic distortion + noise
VIN × G = VS
8
THD+N
OUTPUT
1 kHz, G = +1, VOUT = 1 Vrms, No Load
0.05%
VS = ±2.25 V to ±4 V, No Load
5
15
25
VS = ±2.25 V to ±4 V, RL = 10 kΩ
15
Voltage output swing from rail
Short-circuit current
mV
VS = ±2.25 V to ±4 V, RL = 10 kΩ, TA
–40°C to +125°C
=
15
30
VS = ±2.25, Sinking
–20
+20
1.4
mA
mA
kΩ
ISC
VS = ±2.25, Sourcing
RO
Open-loop output resistance
Capacitive load drive
f = 550 kHz, IO = 0, See Figure 21
CLOAD
See Typical Characteristics
POWER SUPPLY
VS = ±2.25 V to VS = ±4 V
100
145
150
μA
μA
IQ
Quiescent current (per amplifier)
IO = 0 mA, TA = –40°C to +125°C
(1) VS / 2 = midsupply.
8
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SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
6.9 Typical Characteristics
Table 1. Typical Characteristic Graphs
DESCRIPTION
FIGURE
Figure 1
Offset Voltage Production Distribution
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Power Supply
Figure 4
Figure 5
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
IB vs Common-Mode Voltage
Figure 6
Figure 7
Figure 8
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current
CMRR and PSRR vs Frequency (Referred-to-Input)
CMRR vs Temperature
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26, Figure 27
Figure 28, Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
PSRR vs Temperature
0.1-Hz to 10-Hz Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (G = 1) (10-mV Output Step)
No Phase Reversal
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (10 mV)
Large-Signal Step Response
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Crosstalk vs Frequency
EMIRR IN+ vs Frequency
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
15%
10%
5%
0
20
18
16
14
12
10
8
6
4
2
0
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
Offset Voltage (µV)
Offset Voltage Drift (mV/èC)
C002
Figure 2. Offset Voltage Drift Distribution
Figure 1. Offset Voltage Production Distribution
10
8
10
8
6
6
4
4
2
2
0
0
œ2
œ4
œ6
œ8
œ10
œ2
œ4
œ6
œ8
œ10
VCM = œ18.1 V
VCM = 16 V
0
25
50
75
100 125 150
œ75 œ50 œ25
0
5
10
15
20
œ20
œ15
œ10
œ5
Temperature (°C)
VCM (V)
C001
C003
Figure 3. Offset Voltage vs Temperature
Figure 4. Offset Voltage vs Common-Mode Voltage
5
4
140
120
100
80
135
Open-loop Gain
Phase
3
2
90
45
0
1
60
0
40
œ1
œ2
œ3
œ4
œ5
20
0
VS = ± 2.25 V
œ20
œ40
-45
10M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
C001
VSUPPLY (V)
C001
Figure 5. Offset Voltage vs Power Supply
Figure 6. Open-Loop Gain and Phase vs Frequency
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
350
40
G = +1
G= +10
G= -1
250
150
20
0
50
œ50
œ150
œ250
œ350
-20
-40
100
1k
10k
100k
1M
10M
0
5
10
15
20
œ20
œ15
œ10
œ5
Frequency (Hz)
VCM (V)
C004
C001
Figure 7. Closed-Loop Gain vs Frequency
Figure 8. IB vs Common-Mode Voltage
15.0
12.5
10.0
7.5
3
2.5
2
1.5
1
0.5
0
125°C
25°C
œ40°C
-0.5
-1
5.0
-1.5
-2
2.5
ios
-2.5
-3
0.0
0
25
50
75
100 125 150
œ75 œ50 œ25
0
10
20
30
IO (mA)
40
50
60
Temperature (°C)
C001
C001
Figure 9. Input Bias Current vs Temperature
Figure 10. Output Voltage Swing vs Output Current
180
170
160
150
140
130
120
0.001
180
160
140
120
100
80
0.01
0.1
1
60
CMRR
+PSRR
œPSRR
40
20
0
1
10
100
1k
10k
100k
1M
10M
0
25 50 75 100 125 150
œ75 œ50 œ25
Frequency (Hz)
Temperature (°C)
C004
C001
Figure 11. CMRR and PSRR vs Frequency
(Referred-to-Input)
Figure 12. CMRR vs Temperature
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
180
170
160
150
140
130
120
0.001
0.01
0.1
Time (1 s/div)
1
C017
0
25
50
75 100 125 150
œ75 œ50 œ25
Temperature (°C)
C001
Figure 13. PSRR vs Temperature
Figure 14. 0.1-Hz to 10-Hz Noise
10
1
-40
1000
100
10
G = -1, 10k-ꢀ Load
G = -1, 2k-ꢀ Load
G = -1, 600-ꢀ Load
G = +1, 10k-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 600-ꢀ Load
-60
-80
0.1
-100
-120
0.01
0.001
-140
20
200
2k
20k
1
Frequency (Hz)
1
10
100
1k
10k
100k
C004
Frequency (Hz)
C002
Figure 16. THD+N Ratio vs Frequency
Figure 15. Input-Referred Voltage Noise Spectral Density vs
Frequency (G = +101)
140
120
100
80
1
-60
0.1
-80
0.01
60
G = -1, 10k-ꢀ Load
G = -1, 2k-ꢀ Load
G = -1, 600-ꢀ Load
G = +1, 10k-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 600-ꢀ Load
-100
-120
0.001
0.0001
40
20
0.001
0.01
0.1
1
10
0
Output Amplitude (VRMS
)
0
2
4
6
8
10
12
14
16
18
20
C004
Supply Voltage (V)
C001
Figure 17. THD+N vs Output Amplitude
Figure 18. Quiescent Current vs Supply Voltage
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
150
120
90
60
30
0
200
190
180
170
160
150
140
0.0001
0.001
0.01
VS = ± 2.25 V
VS = ± 18 V
0.1
0
25
50
75
100 125 150
0
25 50 75 100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
Figure 19. Quiescent Current vs Temperature
Figure 20. Open-Loop Gain vs Temperature
10000
1000
100
10
70
60
50
40
30
20
10
RISO = 0 Ω
RISO = 25 Ω
RISO = 50 Ω
1
0.1
10
100
1k
10k
100k
1M
10M
100M
10
100
Frequency (Hz)
Capacitive Load (pF)
C001
C004
Figure 21. Open-Loop Output Impedance vs Frequency
Figure 22. Small-Signal Overshoot vs
Capacitive Load (G = +1) (10-mV Output Step)
VIN
VOUT
VIN
VOUT
Time (40 ms/div)
Time (2 µs/div)
C017
C017
Figure 23. No Phase Reversal
Figure 24. Positive Overload Recovery
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
VIN
VOUT
VOUT
VIN
Time (2 µs/div)
Time (1 µs/div)
C017
C017
Figure 25. Negative Overload Recovery
Figure 26. Small-Signal Step Response
(100 mV)
VOUT
VIN
VOUT
VIN
Time (2.5 µs/div)
Time (25 µs/div)
C017
C017
Figure 27. Small-Signal Step Response
(100 mV)
Figure 28. Large-Signal Step Response
VOUT
VIN
0.01% Settling = ±1mV
t0 = 45 µs
50
Time (25 µs/div)
45
55
Time (5 µs/div)
60
65
C017
C017
Figure 29. Large-Signal Step Response
Figure 30. Large-Signal Settling Time
(10-V Positive Step)
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
60
0.01% Settling = ±1mV
50
ISC, Sink
40
30
20
10
0
ISC, Source
t0 = 45 µs
50
45
55
60
65
0
25
50
75
100 125 150
œ75 œ50 œ25
Time (5 µs/div)
Temperature (°C)
C017
C001
Figure 31. Large-Signal Settling Time
(10-V Negative Step)
Figure 32. Short-Circuit Current vs Temperature
40
35
30
25
20
15
10
5
-60
-80
Maximum output voltage without
slew-rate induced distortion.
VS = ±18V
-100
-120
-140
-160
VS = ±4V
VS = ±2.25V
0
100
1k
10k
100k
1M
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
C001
C004
Figure 33. Maximum Output Voltage vs Frequency
Figure 34. Crosstalk vs Frequency
180
160
140
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1000M
C004
Figure 35. EMIRR IN+ vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx187 operational amplifier combines precision offset and drift with excellent overall performance,
making the device ideal for many precision applications. The precision offset drift of only 0.001 µV/°C provides
stability over the entire temperature range. In addition, this device offers excellent overall performance with high
CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require
decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
The OPAx187 device is part of a family of zero-drift, low-power, rail-to-rail output operational amplifiers. These
devices operate from 4.5 V to 36 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero input offset voltage
drift over temperature and time. This choice of architecture also offers outstanding ac performance, such as ultra-
low broadband noise and zero flicker noise.
7.2 Functional Block Diagram
Figure 36 shows a representation of the proprietary OPAx187 architecture. Functional blocks CHOP1 and
CHOP2 operate such that the non-idealities of GM1 are cancelled while the input signal is left in-phase. The
integrated notch filter of the OPAx187 family suppresses most of the auto-zero amplifier carrier.
V+
C2
Notch
CHOP1
GM1
CHOP2
Filter
GM2
GM3
+
-
+
+
OUT
+IN
-IN
-
+
-
-
C1
+
-
GM_FF
V-
Figure 36. Functional Block Diagram
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7.3 Feature Description
The OPAx187 is unity-gain stable and free from unexpected output phase reversal. This device uses a
proprietary, periodic autocalibration technique to provide ultra-low input offset voltage and near zero input offset
voltage drift over temp and temperature. For lowest offset voltage and precision performance, optimize circuit
layout and mechanical conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in
the thermocouple junctions formed from connecting dissimilar conductors. Cancel these thermally-generated
potentials by making sure they are equal on both input pins. Other layout and design considerations include:
Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
Thermally isolate components from power supplies or other heat sources.
Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which may cause
thermoelectric voltages of 0.1 µV/°C or higher, depending on the materials used.
7.3.1 Operating Characteristics
The OPAx187 device is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
7.3.2 Phase-Reversal Protection
The OPAx187 device has an internal phase-reversal protection. Many op amps exhibit a phase reversal when
the input is driven beyond its linear common-mode range. This condition is most often encountered in non-
inverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output
to reverse into the opposite rail. The OPAx187 input prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. Figure 37 shows this performance.
VIN
VOUT
Time (40 ms/div)
C017
Figure 37. No Phase Reversal
7.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers, such as the OPAx187, use switching on their inputs to correct for the intrinsic offset and drift
of the amplifier. Charge injection from the integrated switches on the inputs can introduce very short transients in
the input bias current of the amplifier. The extremely short duration of these pulses prevents them from being
amplified, however they may be coupled to the output of the amplifier through the feedback network. The most
effective method to prevent transients in the input bias current from producing additional noise at the amplifier
output is to use a low-pass filter such as an RC network.
7.3.4 Internal Offset Correction
The OPAx187 op amp uses an auto-calibration technique with a time-continuous 125-kHz op amp in the signal
path. This amplifier is zero-corrected every 22 μs using a proprietary technique. Upon power-up, the amplifier
requires approximately 100 μs to achieve the specified VOS accuracy. This design has no aliasing or flicker noise.
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Feature Description (continued)
7.3.5 EMI Rejection
The OPAx187 device uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx187
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 38 shows the results of this testing on the OPAx187. Table 2 lists the EMIRR IN+ values for the
OPAx187 at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be
found in EMI Rejection Ratio of Operational Amplifiers, available for download from www.ti.com.
180
160
140
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1000M
C004
Figure 38. EMIRR Testing
Table 2. OPAx187 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION/ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency
(UHF) applications
400 MHz
81.8 dB
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF
applications
900 MHz
1.8 GHz
2.4 GHz
102.7 dB
115.4 dB
150.7 dB
GSM applications, mobile personal communications, broadband, satellite, L-band
(1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-
band (2 GHz to 4 GHz)
3.6 GHz
5 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
142.0 dB
173.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
7.3.6 Capacitive Load and Stability
The device dynamic characteristics are optimized for a range of common operating conditions. The combination
of low closed-loop gain and high capacitive loads decreases the amplifier phase margin and can lead to gain
peaking or oscillations. As a result, larger capacitive loads must be isolated from the output. The simplest way to
achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output.
Figure 39 illustrates small-signal overshoot versus capacitive load for several values of ROUT. Also, for details of
analysis techniques and application circuits, refer to Feedback Plots Define Op Amp AC Performance, available
for download from www.ti.com.
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G = 1, RL = 10 kΩ, 10-mV Output Step
70
60
50
40
30
20
RISO = 0 Ω
RISO = 25 Ω
RISO = 50 Ω
10
10
100
Capacitive Load (pF)
C004
Figure 39. Small-Signal Overshoot Versus Capacitive Load
7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See Figure 40 for an illustration of the ESD circuits contained in the OPAx187 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx187
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in Figure 40), the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should
this condition occur, there is a risk that some internal ESD protection circuits may be biased on, and conduct
current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 40 shows a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source via the current-steering diodes. This state is not a
normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then
the current through the steering diodes can become quite high. The current level depends on the ability of the
input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, external TVS (Transient Voltage
Suppressor) diodes may be added to the supply pins, as shown in Figure 40. The TVS voltage must be selected
such that the diode does not turn on during normal operation. However, the TVS voltage should be low enough
so that the TVS diode conducts if the supply pin begins to rise above the safe operating supply voltage level.
TVS(See Note 2)
RF
+VS
V+
RI
ESD Current-
Steering Diodes
-IN
RS(See Note 3)
+IN
OUT
Op Amp
Core
Edge-Triggered ESD
Absorption Circuit
RL
ID
VIN
(See
Vœ
Note 1)
-VS
TVS
(See Note 2)
Copyright © 2016, Texas Instruments Incorporated
NOTE 1: VIN = +VS + 500 mV.
NOTE 2: TVS: +VS(max) > VTVSBR (min) > +VS.
NOTE 3: Suggested value is approximately 1 kΩ.
Figure 40. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
The OPAx187 input terminals are protected from excessive differential voltage with back-to-back diodes, as
shown in Figure 40. In most circuit applications, the input protection circuitry has no consequence. However, in
low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the
amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this
forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not
inherently limited, an input series resistor can be used to limit the signal input current. This input series resistor
degrades the low-noise performance of the OPAx187. Figure 40 shows an example configuration that
implements a current-limiting feedback resistor.
7.4 Device Functional Modes
The OPAx187 has a single functional mode and is operational when the power-supply voltage is greater than 4.5
V (±2.25 V). The maximum power supply voltage for the OPAx187 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx187 operational amplifier combines precision offset and drift with excellent overall performance,
making it ideal for many precision applications. The precision offset drift of only 0.001 µV/°C provides stability
over the entire temperature range. In addition, the device pairs excellent CMRR, PSRR, and AOL dc performance
with outstanding low-noise operation. As with all amplifiers, applications with noisy or high-impedance power
supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
The following application examples highlight only a few of the circuits where the OPAx187 can be used.
8.2 Typical Applications
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 41 is a high-side voltage-to-current (V-I) converter. The converter translates an input
voltage of 0 V to 2 V into an output current of 0 mA to 100 mA. Figure 42 shows the measured transfer function
for this circuit. The low offset voltage and offset drift of the OPA2187 facilitate excellent dc accuracy for the
circuit.
V+
RS2
470 ꢀ
RS3
4.7 ꢀ
IRS2
IRS3
R4
VRS2
10 kꢀ
VRS3
C7
2200 pF
R5
330 ꢀ
Q2
+
R3
200 ꢀ
+
Q1
C6
1000 pF
+
VIN
R2
10 ꢀ
œ
VRS1
VLOAD
ILOAD
RS1
2 kꢀ
RLOAD
IRS1
Copyright © 2016, Texas Instruments Incorporated
Figure 41. High-Side Voltage-to-Current (V-I) Converter
Copyright © 2016–2018, Texas Instruments Incorporated
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Typical Applications (continued)
8.2.1.1 Design Requirements
The design requirements are:
•
•
•
Supply voltage: 5 V DC
Input: 0 V to 2 V DC
Output: 0 mA to 100 mA DC
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
This application benefits from an operational amplifier with low offset voltage, low temperature drift, and rail-to-
rail output. The OPAx187 CMOS operational amplifier is a high-precision, ultra-low offset, ultra-low drift amplifier,
optimized for wide-voltage, single-supply operation, with an output swing to within 5 mV of the positive rail. The
OPAx187 family uses chopping techniques to provide low initial offset voltage and near-zero drift over time and
temperature. Low offset voltage and low drift reduce the offset error in the system, making this device
appropriate for precise dc control. The rail-to-rail output stage of the OPAx187 makes sure that the output swing
of the operational amplifier is able to fully control the gate of the MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in reference design
TIPD102, a step-by-step process to design a High-Side Voltage-to-Current (V-I) Converter.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIPD102, High-Side Voltage-to-Current (V-I) Converter (SLAU502).
8.2.1.3 Application Curve
Figure 42 shows the measured transfer function for the high-side voltage-to-current converter shown in
Figure 41.
0.1
Load
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
Figure 42. Measured Transfer Function for High-Side V-I Converter
22
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OPA187, OPA2187, OPA4187
www.ti.com
SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
8.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
NOTE
The TINA-TI files shown in the following sections require that either the TINA software
(from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software
from the TINA-TI folder.
Figure 43 shows an example of how the OPAx187 is used as a high-voltage, high-impedance front-end for a
precision, discreet instrumentation amplifier with attenuation. The INA159 provides the attenuation that allows
this circuit to easily interface with 3.3-V or 5-V analog-to-digital converters (ADCs). Click the following link
download the TINA-TI file: Discrete INA.
15 V
OPA187
VOUTP
5 V
RP
10 kΩ
VDIFF / 2
- 15 V
Ref 1
Ref 2
RG
500 Ω
(1)
INA159
VOUT
+
VCM
10V
Sense
RN
10 kΩ
15 V
œVDIFF / 2
OPA187
VOUTN
-15 V
Copyright © 2016, Texas Instruments Incorporated
(1) VOUT = VDIFF × (41 / 5) + (Ref 1) / 2.
Figure 43. Discrete INA + Attenuation for ADC With 3.3-V Supply
8.2.3 Bridge Amplifier
Figure 44 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI
file: Bridge Amplifier Circuit.
15 V
R
15 V
R
R
R
R
œ
OPA187
VOUT
+
R
VREF
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Bridge Amplifier
Copyright © 2016–2018, Texas Instruments Incorporated
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8.2.4 Low-Side Current Monitor
Figure 45 shows the OPAx187 configured in a low-side current-sensing application. The load current (ILOAD
)
creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the OPAx187, with a gain
of 201. The load current is set from 0 A to 500 mA, which corresponds to an output voltage range from 0 V to 10
V. The output range can be adjusted by changing the shunt resistor or gain of the configuration. Click the
following link to download the TINA-TI file: Current-Sensing Circuit.
V
Load
15 V
+
VOUT = ILOAD * RSHUNT(1 + RF / RIN)
OPA187
œ
VOUT
RSHUNT
100 mꢀ
VOUT / ILOAD= 1 V / 49.75 mA
ILOAD
RIN
RF
100 ꢀ
20 kꢀ
CF
150
pF
Copyright © 2016, Texas Instruments Incorporated
Figure 45. Low-Side Current Monitor
8.2.5 Programmable Power Supply
Figure 46 shows the OPAx187 configured as a precision programmable power supply using the 16-bit, voltage
output DAC8581 and the OPA548 high-current amplifier. This application amplifies the digital-to-analog converter
(DAC) voltage by a value of five, and handles a large variety of capacitive and current loads. The OPAx187 in
the front-end provides precision and low drift across a wide range of inputs and conditions. Click the following
link to download the TINA-TI file: Programmable Power-Supply Circuit.
C1
500 nF
R1
R4
10 kꢀ
40 kꢀ
R2
GND
1 kꢀ
C2
500 nF
+30V
+15V
œ
R3
10 kꢀ
OPA548
+
VOUT
œ
OPA187
+
Output = ± 25V
DAC8581
œ30V
œ15V
Input = ± 5V
Copyright © 2016, Texas Instruments Incorporated
Figure 46. Programmable Power Supply
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SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
8.2.6 RTD Amplifier With Linearization
See Analog Linearization Of Resistance Temperature Detectors, for an in-depth analysis of Figure 47. Click the
following link to download the TINA-TI file: RTD Amplifier With Linearization.
15 V
(5 V)
Out
In
REF5050
1 µF
1 µF
R2
49.1 kΩ
R3
60.4 kΩ
R1
4.99 kΩ
0°C = 0 V
200°C = 5 V
OPA187
VOUT
R5
105.8 kΩ(1)
RTD
Pt100
R4
1 kΩ
Copyright © 2016, Texas Instruments Incorporated
(1) R5 provides positive-varying excitation to linearize output.
Figure 47. RTD Amplifier With Linearization
9 Power Supply Recommendations
The OPAx187 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. The Typical Characteristics presents parameters that can exhibit significant variance with
regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the
Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
Copyright © 2016–2018, Texas Instruments Incorporated
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OPA187, OPA2187, OPA4187
SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
www.ti.com
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Low-ESR, 0.1-µF ceramic bypass capacitors must be connected between each supply pin and ground; place
the capacitors as close to the device as possible. A single bypass capacitor from V+ to ground is applicable
to single-supply applications.
•
•
•
To reduce parasitic coupling, run the input traces as far away from the supply lines as possible.
A ground plane helps distribute heat and reduces EMI noise pickup.
Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
•
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
VIN
+
VOUT
RG
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
N/C
N/C
RG
GND
VIN
GND
œIN
+IN
Vœ
V+
OUT
N/C
VOUT
Use low-ESR, ceramic
bypass capacitor
GND
Use low-ESR,
ceramic bypass
capacitor
Ground (GND) plane on another layer
Copyright © 2017, Texas Instruments Incorporated
VOUT
VSœ
Figure 48. Layout Example
26
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OPA187, OPA2187, OPA4187
www.ti.com
SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models, in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that lets users format results various ways. Virtual instruments offer users the ability to select input
waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts which offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets users create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH Design Center, WEBENCH® Filter Designer lets users
design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
Texas Instruments, Operational Amplifier Gain Stability, Part 3: AC Gain-Error Analysis
Texas Instruments, Operational Amplifier Gain Stability, Part 2: DC Gain-Error Analysis
Texas Instruments, Using Infinite-Gain, MFB Filter Topology In Fully Differential Active Filters
Texas Instruments, Op Amp Performance Analysis
Texas Instruments, Single-Supply Operation of Operational Amplifiers
Texas Instruments, Tuning in Amplifiers
Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes
Copyright © 2016–2018, Texas Instruments Incorporated
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SBOS807D –DECEMBER 2016–REVISED DECEMBER 2018
www.ti.com
11.3 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
TECHNICAL
DOCUMENTS
TOOLS AND
SOFTWARE
SUPPORT AND
COMMUNITY
PARTS
PRODUCT FOLDER SAMPLE AND BUY
OPA187
OPA2187
OPA4187
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on the Alert me button to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
DesignSoft, TINA are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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Product Folder Links: OPA187 OPA2187 OPA4187
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jan-2019
PACKAGING INFORMATION
Orderable Device
OPA187ID
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
D
8
5
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
OPA187
OPA187IDBVR
OPA187IDBVT
OPA187IDGKR
OPA187IDGKT
OPA187IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
PREVIEW
DBV
DBV
DGK
DGK
D
3000
250
Green (RoHS
& no Sb/Br)
1CUV
5
Green (RoHS
& no Sb/Br)
1CUV
8
2500
250
Green (RoHS
& no Sb/Br)
1D96
8
Green (RoHS
& no Sb/Br)
1D96
8
2500
75
Green (RoHS
& no Sb/Br)
OPA187
OP2187
16TV
OPA2187ID
SOIC
D
8
Green (RoHS
& no Sb/Br)
OPA2187IDGKR
OPA2187IDGKT
OPA2187IDR
OPA4187ID
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
2500
250
Green (RoHS
& no Sb/Br)
8
Green (RoHS
& no Sb/Br)
16TV
8
2500
50
Green (RoHS
& no Sb/Br)
OP2187
OPA4187
OPA4187
OPA4187
OPA4187
SOIC
D
14
14
14
14
Green (RoHS
& no Sb/Br)
OPA4187IDR
OPA4187IPW
OPA4187IPWR
SOIC
D
2500
90
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
PW
PW
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jan-2019
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA187IDBVR
OPA187IDBVT
OPA187IDGKR
OPA187IDGKT
OPA187IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000
250
180.0
180.0
330.0
330.0
330.0
330.0
180.0
330.0
330.0
8.4
3.23
3.23
5.3
5.3
6.4
5.3
5.3
6.4
6.5
3.17
3.17
3.4
3.4
5.2
3.4
3.4
5.2
9.0
1.37
1.37
1.4
1.4
2.1
1.4
1.4
2.1
2.1
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8.4
8.0
8
2500
250
12.4
12.4
12.4
12.4
12.4
12.4
16.4
12.0
12.0
12.0
12.0
12.0
12.0
16.0
8
8
2500
2500
250
OPA2187IDGKR
OPA2187IDGKT
OPA2187IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
2500
OPA4187IDR
SOIC
D
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jan-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA187IDBVR
OPA187IDBVT
OPA187IDGKR
OPA187IDGKT
OPA187IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000
250
213.0
213.0
366.0
366.0
367.0
367.0
210.0
367.0
367.0
191.0
191.0
364.0
364.0
367.0
367.0
185.0
367.0
367.0
35.0
35.0
50.0
50.0
35.0
35.0
35.0
35.0
38.0
8
2500
250
8
8
2500
2500
250
OPA2187IDGKR
OPA2187IDGKT
OPA2187IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
2500
OPA4187IDR
SOIC
D
14
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/D 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/D 11/2018
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/D 11/2018
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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