OPA4189IDR [TI]
OPAx189 Precision, Lowest-Noise, 36-V, Zero-Drift, 14-MHz, MUX-Friendly, Rail-to-Rail Output Operational Amplifiers;
| 型号： | OPA4189IDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPAx189 Precision, Lowest-Noise, 36-V, Zero-Drift, 14-MHz, MUX-Friendly, Rail-to-Rail Output Operational Amplifiers |
| 文件： | 总52页 (文件大小：4071K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA189, OPA2189, OPA4189
SBOS830I – SEPTEMBER 2017 – REVISED OCTOBER 2021
OPAx189 Precision, Lowest-Noise, 36-V, Zero-Drift, 14-MHz,
MUX-Friendly, Rail-to-Rail Output Operational Amplifiers
1 Features
3 Description
•
Ultra-high precision:
The OPA189, OPA2189, and OPA4189 (OPAx189)
high-precision operational amplifiers are ultra-low
noise, fast-settling, zero-drift devices that provide rail-
to-rail output operation and feature a unique MUX-
friendly architecture and controlled start-up system.
These features and excellent ac performance,
combined with only 0.4 µV of offset voltage and
0.005µV/°C of drift over temperature for the single-
channel version, make the OPAx189 a great choice
for precision instrumentation, signal measurement,
and active filtering applications. Moreover, the MUX-
friendly input architecture prevents inrush current
when applying large input differential voltages,
which improves settling performance in multichannel
systems, all while providing robust ESD protection
during shipment, handling, and assembly.
– Zero-drift: 0.005 μV/°C (OPA189)
– Ultra-low offset voltage: 3 μV maximum
(OPA189)
Excellent dc precision:
– CMRR: 168 dB
•
•
•
– Open-loop gain: 170 dB
Low noise:
– en at 1 kHz: 5.2 nV/√Hz
– 0.1-Hz to 10-Hz noise: 0.1 µVPP
Excellent dynamic performance:
– Gain bandwidth: 14 MHz
– Slew rate: 20 V/µs
– Fast settling: 10-V step, 0.01% in 1.1 µs
Robust design:
– MUX-friendly inputs
– RFI/EMI filtered inputs
Wide supply range: 4.5 V to 36 V
Quiescent current: 1.7 mA (maximum)
Rail-to-rail output
•
All versions are specified from –40°C to +125°C.
•
•
•
•
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
4.90 mm × 3.90 mm
2.90 mm × 1.60 mm
3.00 mm × 3.00 mm
4.90 mm × 3.90 mm
3.00 mm × 3.00 mm
5.00 mm × 4.40 mm
8.65 mm × 3.91 mm
SOIC (8)
Input includes negative rail
OPA189
SOT-23 (5)
VSSOP (8)
SOIC (8)
2 Applications
•
•
•
•
•
Battery test
Analog input module
Weigh scale
DC power supply, ac source, electronic load
Multifunction relay
OPA2189
OPA4189
VSSOP (8)
TSSOP (14)
SOIC (14)
(1) For all available packages, see the package option
addendum at the end of the data sheet.
Analog Inputs
OPAx189 MUX-friendly Inputs
Prevents Loading of Source
OPAx189
Bridge Sensor
OPAx189
+
4:2
HV
MUX
Robust MUX-Friendly Inputs
without Anti-Parallel Diodes
Thermocouple
+
OPAx189
Current Sensing
Competitor HV Amp
Photo
Detector
Classical High-Voltage Op Amp
Anti-Parallel Diodes Loads Source
High-Voltage Level Translation
Input
LED
High-Voltage Multiplexed Input
Optical Sensor
Copyright © 2017, Texas Instruments Incorporated
Time
Copyright © 2017, Texas Instruments IncorporatedC003
OPAx189 Preserves R-C Settling Performance in a
Switched or Multiplexed Application
OPAx189 MUX-Friendly Input Settles Quickly and
Maintains High Input Impedance When Switched
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA189, OPA2189, OPA4189
SBOS830I – SEPTEMBER 2017 – REVISED OCTOBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings ....................................... 7
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions ........................7
7.4 Thermal Information: OPA189 ................................... 8
7.5 Thermal Information: OPA2189 ................................. 8
7.6 Thermal Information: OPA4189 ................................. 8
7.7 Electrical Characteristics ............................................9
7.8 Typical Characteristics..............................................12
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................20
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Applications.................................................. 28
9.3 System Examples..................................................... 33
10 Power Supply Recommendations..............................34
11 Layout...........................................................................35
11.1 Layout Guidelines................................................... 35
11.2 Layout Example...................................................... 35
12 Device and Documentation Support..........................36
12.1 Device Support....................................................... 36
12.2 Documentation Support.......................................... 36
12.3 Receiving Notification of Documentation Updates..36
12.4 Support Resources................................................. 36
12.5 Trademarks.............................................................37
12.6 Electrostatic Discharge Caution..............................37
12.7 Glossary..................................................................37
13 Mechanical, Packaging, and Orderable
Information.................................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (August 2021) to Revision I (September 2021)
Page
•
Changed OPA4189 from advanced information (preview) to production data (active) ......................................1
Changes from Revision G (April 2021) to Revision H (August 2021)
Page
•
•
Added OPA4189 in SOIC-14 (D) package as advanced information (preview)..................................................1
Changed OPA4189IPW thermal information to final values............................................................................... 8
Changes from Revision F (July 2020) to Revision G (April 2021)
Page
•
Added OPA4189 in TSSOP-14 (PW) package as advanced information (preview)........................................... 1
Changes from Revision E (May 2019) to Revision F (July 2020)
Page
•
•
•
Changed OPA2189 VSSOP-8 (DGK) package from preview to production data (active).................................. 1
Added Added input offset for OPA2189IDGK..................................................................................................... 9
Added Added input offset drift for OPA2189IDGK.............................................................................................. 9
Changes from Revision D (December 2018) to Revision E (May 2019)
Page
•
•
•
•
•
•
Changed OPA189 SOT-23 (DBV) package from preview to production data (active)........................................1
Changed Figure 3, Input Bias Current Production Distribution, to show updated data.................................... 12
Changed Figure 4, Input Offset Current Production Distribution, to show updated data..................................12
Changed Figure 8, Open-Loop Gain and Phase vs Frequency, for clarity.......................................................12
Changed Figure 9, Closed-Loop Gain vs Frequency, for clarity.......................................................................12
Added new Figure 39, OPA2189 Long-Term Drift ........................................................................................... 12
Changes from Revision C (October 2018) to Revision D (November 2018)
Page
•
•
•
•
Changed OPA2189 SOIC (D) package from preview to production data........................................................... 1
Added input bias current for OPA2189ID............................................................................................................9
Added input offset current for OPA2189ID..........................................................................................................9
Added crosstalk for OPA2189ID.........................................................................................................................9
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•
•
Changed Maximum Output Voltage Amplitude vs Frequency to reflect undistorted operating range.............. 12
Added OPA189 long-term drift and OPA2189 channel separation curves........................................................12
Changes from Revision B (October 2018) to Revision C (October 2018)
Page
•
First release of production-data sheet for OPA189IDGK....................................................................................1
Changes from Revision A (November 2017) to Revision B (October 2018)
Page
•
•
Added input offset for OPA2189ID......................................................................................................................9
Added input offset drift for OPA2189ID...............................................................................................................9
Changes from Revision * (September 2017) to Revision A (October 2017)
Page
•
First release of production-data sheet for OPA189ID device .............................................................................1
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5 Device Comparison Table
PRODUCT
FEATURES
OPA188
OPA388
OPA333
OPA192
OPA140
OPA209
25-µV, 0.085-µV/°C, 8.8-nV/√ Hz, Rail-to-Rail Output, 36-V, Zero-Drift CMOS
5-µV, 0.05-µV/°C, 7-nV/√ Hz, 10-MHz, True Rail-to-Rail Input/Output, 5.5-V, Zero-Drift CMOS
10-µV, 0.05-µV/°C, 25-µA, Rail-to-Rail Input/Output, 5.5-V, Zero-Drift CMOS
25-µV, 0.8-µV/°C, 1-mA, 10-MHz, Rail-to-Rail Input/Output, 36-V, e-Trim CMOS
120-µV, 10-MHz, 5.1-nV/√ Hz, 36-V JFET Input Industrial Op Amp
2.2-nV/√ Hz, 150-µV, 18-MHz, 36-V Bipolar Op Amp in SOT-23 package
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6 Pin Configuration and Functions
NC
œIN
+IN
Vœ
1
2
3
4
8
7
6
5
NC
V+
OUT
Vœ
1
2
3
5
V+
œ
OUT
NC
+
+IN
4
œIN
Not to scale
Not to scale
Figure 6-2. OPA189 DBV (5-Pin SOT-23) Package,
Top View
Figure 6-1. OPA189 D (8-Pin SOIC) and DGK (8-Pin
VSSOP) Packages, Top View
Table 6-1. Pin Functions: OPA189
PIN
I/O
DESCRIPTION
D (SOIC)
DGK (VSSOP)
NAME
DBV (SOT-23)
–IN
+IN
NC
OUT
V–
2
4
3
I
Inverting input
3
I
Noninverting input
1, 5, 8
—
1
—
O
—
—
No internal connection (can be left floating)
Output
6
4
7
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
OUT A
1
2
3
4
8
7
6
5
V+
œIN A
+IN A
Vœ
OUT B
œIN B
+IN B
Not to scale
Figure 6-3. OPA2189 D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
Table 6-2. Pin Functions: OPA2189
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Output channel A
3
6
I
5
I
1
O
O
—
—
7
Output channel B
4
Negative supply
V+
8
Positive supply
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OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
Figure 6-4. OPA4189 D (14-Pin SOIC) and PW (14-Pin TSSOP) Packages, Top View
Table 6-3. Pin Functions: OPA4189
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
I
I
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Inverting input channel C
Noninverting input channel C
Inverting input channel D
Noninverting input channel D
Output channel A
3
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output channel B
8
Output channel C
14
11
4
Output channel D
Negative supply
V+
Positive supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Single-supply
40
Supply voltage
VS = (V+) – (V–)
Dual-supply
Common-mode
Differential
±20
(V+) + 0.5
(V+) – (V–) + 0.2
±10
(V–) – 0.5
Voltage
Current
Signal input pins
Output short circuit(2)
Temperature
mA
Continuous
–55
Continuous
150
Operating, TA
Junction, TJ
Storage, Tstg
150
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single-supply
Dual-supply
Supply voltage, VS = (V+) – (V–)
Specified temperature
±2.25
–40
±18
125
°C
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UNIT
SBOS830I – SEPTEMBER 2017 – REVISED OCTOBER 2021
7.4 Thermal Information: OPA189
OPA189
DGK (VSSOP)
8 PINS
166.4
THERMAL METRIC(1)
D (SOIC)
8 PINS
122.0
57.6
DBV (SOT)
5 PINS
134.5
90.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
54.2
67.3
87.9
41.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
12.7
5.5
22.5
ΨJB
66.2
86.4
41.6
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2189
OPA2189
THERMAL METRIC(1)
D (SOIC)
8 PINS
115.7
51.1
DGK (VSSOP)
8 PINS
150.2
43.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
60.8
71.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.8
2.9
ΨJB
59.7
70
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: OPA4189
OPA4189
THERMAL METRIC(1)
D (SOIC)
14 PINS
73.4
PW (TSSOP)
14 PINS
106.4
22.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.0
30.2
52.0
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.5
1.0
ΨJB
29.8
50.8
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.7 Electrical Characteristics
at TA = 25°C, VS = ±18V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±0.4
±3
±4
±3
±5
±8
±5
±8
Input offset voltage,
OPA189
µV
TA = –40°C to 125°C
VS = ±2.25V
±0.5
±0.8
µV
µV
µV
µV
µV
Input offset voltage,
OPA2189IDGK &
OPA4189IPW
VOS
VS = ±18V
TA = –40°C to 125°C, VS = ±18V
±1.5
Input offset voltage,
OPA2189ID
TA = –40°C to 125°C
TA = –40°C to 125°C
Input offset voltage drift,
OPA189
±0.005
±0.02
µV/°C
Input offset voltage
drift, OPA2189IDGK &
OPA4189IPW
TA = 0°C to 85°C
±0.006
±0.01
±0.015
±0.03
µV/°C
µV/°C
dVOS/dT
PSRR
TA = -40°C to 125°C
TA = 0°C to 85°C
±0.007
±0.01
±0.03
±0.05
±0.05
µV/°C
µV/°C
µV/V
Input offset voltage drift,
OPA2189ID
TA = –40°C to 125°C
Power-supply rejection ratio TA = –40°C to 125°C
±0.005
INPUT BIAS CURRENT
±70
±70
±300
±1
pA
nA
pA
nA
pA
nA
pA
nA
pA
nA
pA
nA
Input bias current, OPA189
TA = 0°C to 85°C
TA = –40°C to 125°C
±10
±300
±1.5
±10
±500
±2
Input bias current,
OPA2189
IB
ZIN = 100 kΩ || 500 pF
TA = 0°C to 85°C
TA = –40°C to 125°C
±70
Input bias current,
OPA4189
TA = 0°C to 85°C
TA = –40°C to 125°C
±15
±600
±1.6
±3
±140
±140
±140
Input offset current,
OPA189
TA = 0°C to 85°C
TA = –40°C to 125°C
±600
±2.5
±5
Input offset current,
OPA2189
IOS
ZIN = 100 kΩ || 500 pF
TA = 0°C to 85°C
TA = –40°C to 125°C
±1
Input offset current,
OPA4189
TA = 0°C to 85°C
±2.5
±5
TA = –40°C to 125°C
NOISE
17
0.1
5.2
5.2
5.2
5.2
165
nVRMS
µVPP
En
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
en
Input voltage noise density
nV/√Hz
fA/√Hz
in
Input current noise density f = 1 kHz
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7.7 Electrical Characteristics (continued)
at TA = 25°C, VS = ±18V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
(V+) – 2.5
V
VS = ±2.25 V
120
146
120
110
140
168
(V–) – 0.1 V ≤ VCM ≤ (V+) – 2.5 V
VS = ±18 V
VS = ±18 V
VS = ±2.25 V
Common-mode rejection
ratio
CMRR
dB
(V–) – 0.1 V ≤ VCM ≤ (V+) – 2.5 V,
TA = –40°C to 125°C
INPUT IMPEDANCE
zid
zic
Differential input impedance
0.1 || 5.5
60 || 1.7
GΩ || pF
TΩ || pF
Common-mode input
impedance
OPEN-LOOP GAIN
(V–) + 0.3 V < VO < (V+)
– 0.3 V,
RLOAD = 10 kΩ
150
140
150
140
170
170
(V–) + 0.3 V < VO < (V+)
– 0.3 V,
RLOAD = 10 kΩ,
TA = –40°C to 125°C
AOL
Open-loop voltage gain
VS = ±18 V
dB
(V–) + 0.6 V < VO < (V+)
– 0.6 V,
RLOAD = 2 kΩ
(V–) + 0.6 V < VO < (V+)
– 0.6 V,
RLOAD = 2 kΩ,
TA = –40°C to 125°C
FREQUENCY RESPONSE
UGB
GBW
SR
Unity-gain Bandwith
AV = 1
8
14
20
MHz
V/µs
Gain-bandwith Product
Slew rate
AV = 1000
G = 1, 10-V step
Total harmonic distortion +
noise
THD+N
G = 1, f = 1 kHz, VO = 3.5 VRMS
0.00006%
OPA2189ID, at dc
150
120
Crosstalk
dB
OPA2189ID, f = 100 kHz
VS = ±18 V, G = 1, 10-V
step
To 0.1%
0.8
tS
Settling time
µs
ns
VS = ±18 V, G = 1, 10-V
step
To 0.01%
1.1
tOR
Overload recovery time
VIN × G = VS
320
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7.7 Electrical Characteristics (continued)
at TA = 25°C, VS = ±18V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
No load
5
20
80
5
15
110
500
15
Positive rail
Negative rail
RLOAD = 10 kΩ
RLOAD = 2 kΩ
No load
Voltage output swing from
rail
VO
mV
RLOAD = 10 kΩ
RLOAD = 2 kΩ
OPA189 & OPA2189
OPA4189
20
80
20
20
±65
110
500
120
140
TA = –40°C to 125°C, both rails,
RLOAD = 10 kΩ
ISC
Short-circuit current
Capacitive load drive
mA
Ω
CLOAD
See Small-Signal Overshoot vs Capacitive Load
Open-loop output
impedance
f = 1 MHz, IO = 0 A, see Open-Loop Output Impedance vs
Frequency
ZO
380
1.3
POWER SUPPLY
TA = 25°C
1.7
1.8
Quiescent current per
amplifier
VS = ±2.25 V to ±18 V (VS = 4.5 V to
36 V)
IQ
mA
TA = –40°C to 125°C
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7.8 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 7-1. Typical Characteristic Graphs
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
Figure 7-1
Offset Voltage Drift Distribution From –40°C to 125°C
Input Bias Current Production Distribution
Input Offset Current Production Distribution
Offset Voltage vs Temperature
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Supply Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Input Bias Current vs Common-Mode Voltage
Input Bias Current and Offset vs Temperature
Output Voltage Swing vs Output Current (Sourcing)
Output Voltage Swing vs Output Current (Sinking)
CMRR and PSRR vs Frequency
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Figure 7-20
Figure 7-21
Figure 7-22
Figure 7-23
Figure 7-24
Figure 7-25
Figure 7-26
Figure 7-27
Figure 7-28
Figure 7-29
Figure 7-30, Figure 7-31
Figure 7-32, Figure 7-33
Figure 7-34
Figure 7-35
Figure 7-36
Figure 7-37
Figure 7-38
Figure 7-39
Figure 7-40
CMRR vs Temperature
PSRR vs Temperature
0.1-Hz to 10-Hz Voltage Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open-Loop Gain vs Temperature (10-kΩ)
Open-Loop Gain vs Temperature (2-kΩ)
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
No Phase Reversal
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (10-mV Step)
Large-Signal Step Response (10-V Step)
Settling Time
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
OPA189 Long-Term Drift
OPA2189 Long-Term Drift
Channel Separation
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
14
12
10
8
45
40
35
30
25
20
15
10
5
6
4
2
0
0
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
C001
C002
µ = 46.67 nV
σ = 374.5 nV
N = 2554
µ = 2.83 nV/°C
σ = 2.78 nV/°C
N = 96
VOS (maximum) = ±3 µV
dVOS / dT (maximum) = ±0.02 µV/°C
Figure 7-1. Offset Voltage Production Distribution
Figure 7-2. Offset Voltage Drift Distribution
35%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
32.5%
30%
27.5%
25%
22.5%
20%
17.5%
15%
12.5%
10%
7.5%
5%
2.5%
0
0
-600 -480 -360 -240 -120
-300 -240 -180 -120 -60
0
Positive Input Bias Current (pA)
60 120 180 240 300
0
Input Offset Current (pA)
120 240 360 480 600
Figure 7-3. Input Bias Current Production Distribution
Figure 7-4. Input Offset Current Production Distribution
5
4
20
15
10
5
3
2
1
0
0
œ1
œ2
œ3
œ4
œ5
œ5
œ10
VCM = 15.5 V
VCM = œ 18.1 V
œ15
œ20
0
25
50
75
100 125 150
0
5
10
15
20
œ75 œ50 œ25
œ20
œ15
œ10
œ5
Temperature (°C)
Input Common-mode Voltage (V)
C001
C003
5 Typical Units
Figure 7-5. Offset Voltage vs Temperature
5 Typical Units
Figure 7-6. Offset Voltage vs Common-Mode Voltage
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
160
140
120
100
80
210
180
150
120
90
2.0
1.5
1.0
0.5
0.0
60
60
œ0.5
œ1.0
œ1.5
œ2.0
40
30
VS = 4.5 V
20
0
Open Loop Gain
Open Loop Phase
0
-30
-60
-20
0
9
18
27
36
1
10
100
1k
10k
Freq
100k
1M
10M
Supply Voltage (V)
C001
5 Typical Units
Figure 7-7. Offset Voltage vs Supply Voltage
Figure 7-8. Open-Loop Gain and Phase vs Frequency
80
60
40
20
0
500
400
G = +1
G = -1
G = +10
G = +100
G = +1000
300
200
100
0
œ100
œ200
œ300
œ400
œ500
-20
0
5
10
15
20
œ20
œ15
œ10
œ5
100
1k
10k 100k
Frequency (Hz)
1M
10M
Input Common-mode Voltage (V)
C001
Figure 7-9. Closed-Loop Gain vs Frequency
Figure 7-10. Input Bias Current vs Common-Mode Voltage
24.0
18
œ40°C
20.0
16.0
12.0
8.0
17
25°C
16
IBP
15
125°C
IBN
14
4.0
85°C
13
0.0
IOS
12
œ4.0
0
25
50
75
100 125 150
0
10
20
30
40
50
60
70
80
90
œ75 œ50 œ25
Temperature (°C)
IO (mA)
C001
C001
Sourcing
Figure 7-12. Output Voltage Swing vs Output Current
Figure 7-11. Input Bias Current and Offset vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
-12
160
CMRR
140
-13
+PSRR
120
100
80
60
40
20
0
125°C
85°C
œPSRR
-14
-15
-16
-17
-18
œ40°C
25°C
0
10
20
30
40
50
60
70
80
90
1
10
100
1k
10k
100k
1M
10M
IO (mA)
Frequency (Hz)
C001
C004
Sinking
Figure 7-13. Output Voltage Swing vs Output Current
Figure 7-14. CMRR and PSRR vs Frequency
180
170
160
150
140
130
120
0.001
180
170
160
150
140
130
120
0.001
0.01
0.1
0.01
0.1
1
1
0
25
50
75 100 125 150
0
25
50
75 100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
Figure 7-15. CMRR vs Temperature
Figure 7-16. PSRR vs Temperature
100
10
1
Time (1 s/div)
1
10
100
1k
10k 100k 1M
10M 100M
Frequency (Hz)
C017
C006
Figure 7-17. 0.1-Hz to 10-Hz Voltage Noise
Figure 7-18. Input Voltage Noise Spectral Density vs Frequency
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1
0.1
-40
1
0.1
-40
G = -1, 2k-ꢀ Load
G = -1, 600-ꢀ Load
G = -1, 10k-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 600-ꢀ Load
G = +1, 10k-ꢀ Load
G = -1, 600-ꢀ Load
G = -1, 2k-ꢀ Load
G = -1, 10k-ꢀ Load
G = +1, 600-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 10k-ꢀ Load
-60
-60
0.01
-80
0.01
-80
0.001
0.0001
0.00001
-100
-120
-140
0.001
0.0001
0.00001
-100
-120
-140
20
200
2k
20k
0.01
0.1
1
10
Frequency (Hz)
Output Amplitude (VRMS
)
C004
C004
VOUT = 3.5 V
VRMS, BW = 90 kHz
f = 1 kHz,
BW = 90 kHz
Figure 7-19. THD+N Ratio vs Frequency
Figure 7-20. THD+N vs Output Amplitude
1.5
1.2
0.9
0.6
0.3
0
2
1.5
1
VS
=
18 V
VS = 4.5 V
VS
=
2.25 V
0.5
0
0
9
18
27
36
0
25
50
75
100 125 150
œ75 œ50 œ25
Supply Voltage (V)
Temperature (°C)
C001
C001
Figure 7-21. Quiescent Current vs Supply Voltage
Figure 7-22. Quiescent Current vs Temperature
180
170
160
150
140
130
120
0.001
0.01
0.1
180
170
160
150
140
130
120
0.001
0.01
0.1
VS
=
18 V
VS
=
18 V
VS
=
2.25
VS
=
2.25
1
1
0
25
50
75
100
125
0
25
50
75
100
125
œ50
œ25
œ50
œ25
Temperature (°C)
Temperature (°C)
C001
C001
2-kΩ Load
Figure 7-24. Open-Loop Gain vs Temperature
10-kΩ Load
Figure 7-23. Open-Loop Gain vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1k
65
60
55
50
100
10
1
45
40
35
30
25
20
15
10
5
0
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
10
100
1000
Zotc
Capacitive Load (pF)
C004
10-mV Step
Figure 7-25. Open-Loop Output Impedance vs Frequency
Figure 7-26. Small-Signal Overshoot vs Capacitive Load
Vout (V)
Vin (V)
VIN
VOUT
Time (1 ms/div)
Time (0.2 µs/div)
C017
C017
Figure 7-27. No Phase Reversal
Figure 7-28. Positive Overload Recovery
VIN
VOUT
Input
Output
Time (0.2 µs/div)
Time (500 ns/div)
C017
C017
10-mV Step
G = +1
Figure 7-29. Negative Overload Recovery
Figure 7-30. Small-Signal Step Response
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Output
Input
Input
Output
Time (500 ns/div)
Time (500 ns/div)
C017
C017
10-mV Step
G = –1
10-V Step
G = –1
Figure 7-31. Small-Signal Step Response
Figure 7-32. Large-Signal Step Response
.01% Settling = ±1 mV
Output
Input
Time (500 ns/div)
Time (500 ns/div)
C017
C017
10-V Step
G = +1
10-V Step
Figure 7-34. Settling Time
Figure 7-33. Large-Signal Step Response
40
35
30
25
20
15
10
5
100
90
80
70
60
50
40
Vs
Vs
=
=
18V
2.25V
Sinking
Sourcing
0
0
25
50
75
100
125
150
œ75
œ50
œ25
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (°C)
C001
Figure 7-36. Maximum Output Voltage Amplitude vs Frequency
Figure 7-35. Short-Circuit Current vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0.25
0.2
120
100
80
60
40
20
0
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
10M
100M
Frequency (Hz)
1G
10G
0
250 500 750 1000 1250 1500 1750 2000
Elapsed Time (hours)
C005
PRF = –10 dBm
Figure 7-37. EMIRR vs Frequency
Figure 7-38. OPA189 Long-Term Drift
0.25
-60
0.2
0.15
0.1
-80
-100
-120
-140
-160
-180
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
0
250
500
750 1000 1250 1500 1750 2000
Elapsed Time (hours)
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 7-39. OPA2189 Long-Term Drift
Figure 7-40. OPA2189 Channel Separation
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8 Detailed Description
8.1 Overview
The OPAx189 operational amplifiers combine precision offset and drift with excellent overall performance,
making these devices an excellent choice for many precision applications. The precision offset drift of only
0.005 µV/°C provides stability over the entire temperature range. In addition, these devices offer excellent linear
performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance
power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are
adequate. See the Layout Guidelines section for details and layout example.
The OPAx189 are part of a family of zero-drift, MUX-friendly, rail-to-rail output operational amplifiers. These
devices operate from 4.5 V to 36 V, are unity-gain stable, and are designed for a wide range of general-purpose
and precision applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero
input offset voltage drift over temperature and time. This choice of architecture also offers outstanding ac
performance, such as ultra-low broadband noise, zero flicker noise, and outstanding distortion performance
when operating below the chopper frequency.
8.2 Functional Block Diagram
The Functional Block Diagram shows a representation of the proprietary OPAx189 architecture.
Slew Boost Circuit
CCOMP
CLK
CLK
+IN
Protection
Switches
OUT
œIN
GM3
GM1
GM2
Ripple
Reduction FB
Loop
GM_FF
CCOMP
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8.3 Feature Description
The OPAx189 series of op amps can be used with single or dual supplies from an operating range of VS = 4.5
V (±2.25 V) up to VS = 36 V (±18 V). These devices do not require symmetrical supplies; they only require a
minimum supply voltage of 4.5 V (±2.25 V). For VS less than ±2.5 V, the
common-mode input range does not include midsupply. Supply voltages higher than 40 V can permanently
damage the device; see the Absolute Maximum Ratings table for details. Key parameters are given over the
specified temperature range, TA = –40°C to +125°C, in the Electrical Characteristics table. Key parameters that
vary over the supply voltage, temperature range, or frequency are shown in the Typical Characteristics section.
The OPAx189 is unity-gain stable and free from unexpected output phase reversal. This device uses a
proprietary, periodic autocalibration technique to provide low input offset voltage and very low input offset
voltage drift over time and temperature. For lowest offset voltage and precision performance, optimize circuit
layout and mechanical conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in
the thermocouple junctions formed from connecting dissimilar conductors. Cancel these thermally-generated
potentials by ensuring they are equal on both input pins. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which may cause
thermoelectric voltages of 0.1 µV/°C or higher, depending on the materials used. See the Layout Guidelines
section for details and a layout example.
8.3.1 Operating Characteristics
The OPAx189 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many specifications apply from –
40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics section.
8.3.2 Phase-Reversal Protection
The OPAx189 has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx189 input prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 8-1.
Vout (V)
Vin (V)
Time (1 ms/div)
C017
Figure 8-1. No Phase Reversal
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8.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers such as the OPAx189 use switching on the inputs to correct for the intrinsic offset and drift
of the amplifier. Charge injection from the integrated switches on the inputs can introduce short transients in
the input bias current of the amplifier. The extremely short duration of these pulses prevents the pulses from
amplifying, however the pulses may be coupled to the output of the amplifier through the feedback network.
The most effective method to prevent transients in the input bias current from producing additional noise at the
amplifier output is to use a low-pass filter such as an RC network.
8.3.4 EMI Rejection
The OPAx189 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx189
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 8-2 shows the results of this testing on the OPAx189. Table 8-1 lists the EMIRR +IN values for the
OPAx189 at particular frequencies commonly encountered in real-world applications. Applications listed in Table
8-1 may be centered on or operated near the particular frequency shown. Detailed information can also be found
in the EMI Rejection Ratio of Operational Amplifiers application report, available for download from www.ti.com.
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1G
10G
C005
Figure 8-2. EMIRR Testing
Table 8-1. OPAx189 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION AND ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency
(UHF) applications
400 MHz
48.4 dB
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF
applications
900 MHz
1.8 GHz
2.4 GHz
52.8 dB
69.1 dB
88.9 dB
GSM applications, mobile personal communications, broadband, satellite, L-band
(1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite,
S-band (2 GHz to 4 GHz)
3.6 GHz
5 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
82.5 dB
95.5 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of
RF signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has
a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but
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this section provides the EMIRR +IN, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
•
•
•
Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance
EMIRR is more simple to measure on noninverting pins than on other pins because the noninverting
input terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the
noninverting input terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier may result in adverse
effects, as the amplifier would not have sufficient loop gain to correct for signals with spectral content outside the
bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected DC offsets,
transient voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes
from noisy radio signals and digital clocks and interfaces.
The EMIRR +IN of the OPAx189 is plotted versus frequency as shown in Figure 8-2. If available, any dual and
quad op amp device versions have nearly similar EMIRR +IN performance. The OPAx189 unity-gain bandwidth
is 14 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the op amp
bandwidth.
8.3.5 EMIRR +IN Test Configuration
Figure 8-3 shows the circuit configuration for testing the EMIRR +IN. An RF source is connected to the op
amp noninverting input terminal using a transmission line. The op amp is configured in a unity-gain buffer
topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance
mismatch at the op amp input causes a voltage reflection; however, this effect is characterized and accounted
for when determining the EMIRR IN+. The multimeter samples and measures the resulting DC offset voltage.
The LPF isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
Ambient temperature: 25˘C
V+
œ
+
Low-Pass
Filter
50 ꢀ
RF Source
DC Bias: 0 V
Modulation: None (CW)
Digital
Multimeter
Sample /
Averaging
Vœ
Frequency Sweep: 201 pt. Log
Not shown: 0.1 µF and 10 µF supply decoupling
Figure 8-3. EMIRR +IN Test Configuration
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8.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect from accidental
ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is
helpful. See Figure 8-4 for an illustration of the ESD circuits contained in the OPAx189 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
TVS(2)
RF
V+
RI
ESD Current-
Steering Diodes
-IN
(3)
OUT
Op Amp
Core
RS
+IN
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
Vœ
TVS(2)
(1) VIN = V+ + 500 mV.
(2) TVS: 40 V > VTVSBR (min) > V+ ; where VTVSBR (min) is the minimum specified value for the transient voltage suppressor breakdown
voltage.
(3) Suggested value is approximately 5 kΩ in overvoltage conditions.
Figure 8-4. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or
more steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger or threshold voltage that is above the normal operating voltage of the OPAx189
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in Figure 8-4), the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
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circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should
this condition occur, there is a risk that some internal ESD protection circuits may be biased on, and conduct
current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 8-4 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+)
by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can
sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high
current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier,
and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise
to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies V+ or V– are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source through the current-steering diodes. This state
is not a normal bias condition; the amplifier most likely does not operate normally. If the supplies are low
impedance, then the current through the steering diodes can become quite high. The current level depends on
the ability of the input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, external zener diodes must be
added to the supply pins, as shown in Figure 8-4. The zener voltage must be selected such that the diode does
not turn on during normal operation. However, the zener voltage must be low enough so that the zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
8.3.7 MUX-Friendly Inputs
The OPAx189 features a proprietary input stage design that allows an input differential voltage to be applied
while maintaining high input impedance. Typically, high-voltage CMOS or bipolar-junction input amplifiers feature
anti-parallel diodes that protect input transistors from large VGS voltages that may exceed the semiconductor
process maximum and permanently damage the device. Large VGS voltages can be forced when applying a
large input step, switching between channels, or attempting to use the amplifier as a comparator.
OPAx189 solves these problems with a switched-input technique that prevents large input bias currents when
large differential voltages are applied. This solves many issues seen in switched or multiplexed applications,
where large disruptions to RC filtering networks are caused by fast switching between large potentials. OPAx189
offers outstanding settling performance due to these design innovations and built-in slew rate boost and wide
bandwidth. The OPAx189 can also be used as a comparator. Differential and common-mode Absolute Maximum
Ratings still apply relative to the power supplies.
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8.3.8 Noise Performance
Figure 8-5 shows the total circuit noise for varying source impedances with the operational amplifier in a
unity-gain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPAx189 and OPA211 are shown with total circuit noise calculated. The op amp itself contributes both a voltage
noise component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest
noise op amp for a given application depends on the source impedance. For low source impedance, current
noise is negligible, and voltage noise generally dominates. The OPAx189 family has both low voltage noise and
low current noise because of the CMOS input of the op amp. As a result, the current noise contribution of the
OPAx189 series is negligible for any practical source impedance, which makes this device the better choice for
applications with high source impedance.
The equation in Figure 8-5 shows the calculation of the total circuit noise, with these parameters:
•
•
•
•
•
en = voltage noise
in = current noise
RS = source impedance
k = Boltzmann's constant = 1.38 × 10–23 J/K
T = temperature in kelvins (K)
For more details on calculating noise, see the Basic Noise Calculations section.
10µ
OPA211
1µ
100n
OPAx189
10n
1n
RS = 3.6 kΩ
Resistor Noise
100 1k
0.1n
1
10
10k
100k
1M
10M
Source Resistance, RS (Ω)
Copyright © 2017, Texas Instruments IncorporaCte00d3
NOTE: RS = 3.6 kΩ is indicated in Figure 8-5. This is the source impedance above which OPAx189 is a lower noise option than the
OPA211.
Figure 8-5. Noise Performance of the OPAx189 and OPA211 in Unity-Gain Buffer Configuration
8.3.9 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 8-5. The source impedance is usually fixed; consequently, select the
op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 8-6 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPAx189 means that the current noise contribution can be neglected.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations. For additional resources on noise calculations visit TI's Precision Labs Series
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(A) Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where:
R1
R2
2
42
= l1 + p „ A5 + A0 + kA4 2 o + E0 „ 45 + lE0 „ d
41 „ 42
2
2
2
2
¨
:
: ;
1
;
:
;
:
;
>
?
84/5
'
1
hp
æ4
1
41
41 + 42
GND
œ
EO
8
: ;
2
A = 4 „ G$ „ 6(-) „ 45
¥
5
d
h
Thermal noise of RS
+
*V
¾
RS
41 „ 42
8
: ;
3
A4
= ¨4 „ G$ „ 6(-) „ d
2
h
d
h
Thermal noise of R1 || R2
æ4
1
41 + 42
*V
¾
+
,
h
VS
Source
GND
G$ = 1.38065 „ 10F23
: ;
4
d
œ
Boltzmann Constant
-
Temperature in kelvins
: ;
5
>
?
-
6(-) =
2
7
3.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
Noise at the output is given as EO, where:
R1
R2
2
:
;
45 + 41 „ 42
42
'
1
= l1 +
p „ A0 2 + kA4
2 o2 + FE0 „ H
+4 æ4
5
IG
¨
: ;
6
:
;
>
84/5
?
1
45 + 41
45 + 41 + 42
RS
œ
EO
:
;
45 + 41 „ 42
8
+
: ;
7
¨
4 „ G$ „ 6(-) „ H
A4
=
I
d
h
Thermal noise of (R1 + RS) || R2
+4 æ4
5
1
2
45 + 41 + 42
*V
¾
+
VS
œ
,
GND
G$ = 1.38065 „ 10F23
d
h
: ;
8
Boltzmann Constant
Source
GND
-
: ;
9
>
?
6(-) = .15 + 6(°%)
273
-
Temperature in kelvins
where:
•
en is the voltage noise spectral density of the amplifier. For the OPAx189 series of operational amplifiers, en =
5.2 nV/ √ Hz at 1 kHz.
•
in is the current noise spectral density of the amplifier. For the OPAx189 series of operational amplifiers, in =
165 fA/ √ Hz at 1 kHz.
Figure 8-6. Noise Calculation in Gain Configurations
8.4 Device Functional Modes
The OPAx189 has a single functional mode, and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx189 is 36 V (±18 V).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPAx189 operational amplifier combines precision offset and drift with excellent overall performance,
making the series an excellent for many precision applications. The precision offset drift of only 0.005 µV/°C
provides stability over the entire temperature range. In addition, the device pairs excellent CMRR, PSRR, and
AOL dc performance with outstanding low-noise operation. As with all amplifiers, applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.
The following application examples highlight only a few of the circuits where the OPAx189 can be used.
9.2 Typical Applications
9.2.1 25-kHz Low-Pass Filter
R4
2.94 kꢀ
C5
1 nF
œ
R1
590 ꢀ
R3
499 ꢀ
Output
+
Input
OPAx189
C2
39 nF
Copyright © 2017, Texas Instruments Incorporated
Figure 9-1. 25-kHz Low-Pass Filter
9.2.1.1 Design Requirements
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPAx189 devices are designed to construct high-speed, high-precision active filters. Figure 9-1 shows a
second-order, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
•
•
•
Gain = 5 V/V (inverting gain)
Low-pass cutoff frequency = 25 kHz
Second-order Chebyshev filter response with 3-dB gain peaking in the passband
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9.2.1.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 9-1. Use Equation 1
to calculate the voltage transfer function.
-1 R1R3C2C5
Output
Input
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
2
1
3
4
3 4 2 5
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 2:
R4
Gain =
R1
1
fC
=
1 R R C C
(
3 4 2 5
)
2p
(2)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer lets the user create optimized
filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows board-
level designers to create, optimize, and simulate complete multistage active filter solutions within minutes.
9.2.1.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 9-2. OPAx189 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
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9.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
Note
The TINA-TI™ software files shown in the following sections require that either the TINA™ software
(from DesignSoft™) or TINA-TI simulation software be installed. See Section 12.1.1.1 for more
information.
Figure 9-3 shows an example of how the OPAx189 is used as a high-voltage, high-impedance front end for a
precision, discrete instrumentation amplifier with attenuation. The INA159 provides the attenuation that allows
this circuit to simply interface with 3.3-V or 5-V analog-to-digital converters (ADCs). Click the following link
download the TINA-TI software file: Discrete INA.
15 V
OPAx189
VOUTP
5 V
RP
10 kΩ
VDIFF / 2
- 15 V
Ref 1
Ref 2
RG
500 Ω
(1)
VOUT
INA159
+
VCM
10V
Sense
RN
10 kΩ
15 V
œVDIFF / 2
OPAx189
VOUTN
-15 V
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(1) VOUT = VDIFF × (41 / 5) + (Ref 1) / 2.
Figure 9-3. Discrete INA + Attenuation for ADC With 3.3-V Supply
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9.2.3 Bridge Amplifier
Figure 9-4 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI
software file: Bridge Amplifier Circuit.
VEX
R1
R
R
R
R
+5V
VOUT
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 9-4. Bridge Amplifier
9.2.4 Low-Side Current Monitor
Figure 9-5 shows the OPAx189 configured in a low-side current-sensing application. The load current (ILOAD
)
creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the OPAx189, with a gain
of 201. In this example the load current is set from 0 A to 500 mA, which corresponds to an output voltage range
from 0 V to 10 V. The output range can be adjusted by changing the shunt resistor or gain of the configuration.
Click the following link to download the TINA-TI software file: Current-Sensing Circuit.
VSYSTEM
Load
15 V
+
VOUT = ILOAD * RSHUNT(1 + RF / RIN)
VOUT
OPAx189
RSHUNT
100 mꢀ
VOUT / ILOAD= 1 V / 49.75 mA
ILOAD
œ
RIN
RF
100 ꢀ
20 kꢀ
CF
150
pF
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Figure 9-5. Low-Side Current Monitor
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9.2.5 Programmable Power Supply
Figure 9-6 shows the OPAx189 configured as a precision programmable power supply using the 16-bit, voltage
output DAC8581 and the OPA548 high-current amplifier. This application amplifies the digital-to-analog converter
(DAC) voltage by a value of five, and handles a large variety of capacitive and current loads. The OPAx189 in
the front-end provides precision and low drift across a wide range of inputs and conditions. Click the following
link to download the TINA-TI software file: Programmable Power-Supply Circuit.
C1
500 nF
R1
10 kꢀ
R4
40 kꢀ
R2
1 kꢀ
GND
C2
500 nF
+30V
+15V
œ
R3
10 kꢀ
OPA548
VOUT
œ
OPAx189
+
Output = 25V
DAC8581
+
œ30V
œ15V
Input = 5V
Copyright © 2017, Texas Instruments Incorporated
Figure 9-6. Programmable Power Supply
9.2.6 RTD Amplifier With Linearization
See Analog Linearization of Resistance Temperature Detectors for an in-depth analysis of Figure 9-7. Click the
following link to download the TINA-TI software file: RTD Amplifier with Linearization.
15 V
(5 V)
Out
In
REF5050
1 µF
1 µF
R2
49.1 kΩ
R3
60.4 kΩ
R1
4.99 kΩ
0°C = 0 V
OPAx189
VOUT
200°C = 5 V
R5
105.8 kΩ(1)
RTD
Pt100
R4
1 kΩ
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(1) R5 provides positive-varying excitation to linearize output.
Figure 9-7. RTD Amplifier With Linearization
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9.3 System Examples
9.3.1 24-Bit, Delta-Sigma, Differential Load Cell or Strain Gauge Sensor Signal Conditioning
OPAx189 is used in a 24-bit, differential load cell or strain gauge sensor signal conditioning system alongside the
ADS1225. A pair of OPAx189 amplifiers are configured in a two-amp instrumentation amplifier (IA) configuration
and are band-limited to reduce noise and allow heavy capacitive drive. The load cell is powered by an excitation
voltage (denoted VEX) of 5-V and provides a differential voltage proportional to force applied. The differential
voltage can be quite small and both outputs are biased to VEX / 2.
In this example the OPAx189 is employed here due to the excellent input offset voltage (0.4 µV) and input offset
voltage drift (0.005 µV/°C), the low broadband noise (5.2 nV/√ Hz) and zero-flicker noise, and excellent linearity
and high input impedance. The two-amp IA configuration removes the dc bias and amplifies the differential
signal of interest and drives the 24-bit, delta-sigma ADS1225 analog-to-digital converter (ADC) for acquisition
and conversion. The ADS1225 features a 100-SPS data rate, single-cycle settling, and simple conversion control
with the dedicated START pin.
C4
0.1 nF
C5
0.1 µF
C6
0.1 nF
2 ® RF
G = 1 +
RG
GND
GND
GND
GND
+
OPAx189
+5V
+3V
AVDD
VREFN
VREFP
œ
RTRACE
RTRACE
+15V
C1
10 µF
DVDD
RF
10 kꢀ
DVDD
R1
1 kꢀ
START
SCLK
+OUT
+SENSE
-SENSE
AINP1
CF
1 µF
DRDY / DOUT
MSP430xxx
or other host
+5V
RG
50 ꢀ
C2
1 µF
ADS1225
CF
1 µF
R2
1 kꢀ
+3V
+
MODE
BUFEN
TEMPEN
GND
VEX
Load Cell
AINN1
œ
œOUT
RF
10 kꢀ
GND
GND
C3
10 µF
+15V
œ
GND
GND
OPAx189
+
GND
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Figure 9-8. 24-Bit, Differential Load Cell or Strain Gauge Sensor Signal Conditioning Schematic
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10 Power Supply Recommendations
The OPAx189 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant variance
with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the Absolute Maximum
Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information, see The
PCB is a component of op amp design techincal brief.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
•
•
•
Place the external components as close as possible to the device. As illustrated in Figure 11-1, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
For best performance, TI recommends cleaning the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
Place bypass
capacitors as close to
device as possible
(avoid use of vias)
Use ground pours for
shielding the input
signal pairs
GND
C3
C4
+V
R3
C3
C4
R3
INœ
+V
1
NC
œIN
+IN
Vœ
NC
V+
8
7
6
5
1
2
3
4
NC
œIN
+IN
Vœ
NC
V+
8
7
6
5
R1
R2
R1
2
3
4
INœ
œ
OUT
IN+
OUT
NC
OUT
OUT
NC
+
R2
-V
C1
C2
IN+
R4
GND
R4
-V
Place components
C1
C2
Use a low-
ESR,ceramic bypass
capacitor
close to device and to
each other to reduce
parasitic errors
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Figure 11-1. Operational Amplifier Board Layout for Difference Amplifier Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA-TI simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE
engine. TINA-TI simulation software is a free, fully-functional version of the TINA software, preloaded with a
library of macromodels in addition to a range of both passive and active models. TINA-TI simulation software
provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design
capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software (from DesignSoft) or TINA-TI software be installed.
Download the free TINA-TI simulation software from the TINA-TI folder.
12.1.1.2 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
•
•
•
•
Texas Instruments, Zero-drift Amplifiers: Features and Benefits application brief
Texas Instruments, The PCB is a component of op amp design technical brief
Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis technical brief
Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis technical brief
Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters technical brief
Texas Instruments, Op Amp Performance Analysis application bulletin
Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
Texas Instruments, Tuning in Amplifiers application bulletin
Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report
Texas Instruments, Feedback Plots Define Op Amp AC Performance application bulletin
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers (With OPA333 and OPA333-Q1 as an
Example) application report
•
•
Texas Instruments, Analog linearization of resistance temperature detectors technical brief
Texas Instruments, TI Precision Design TIPD102 High-Side Voltage-to-Current (V-I) Converter reference
guide
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: OPA189 OPA2189 OPA4189
OPA189, OPA2189, OPA4189
SBOS830I – SEPTEMBER 2017 – REVISED OCTOBER 2021
www.ti.com
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: OPA189 OPA2189 OPA4189
PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA189ID
OPA189IDBVR
OPA189IDBVT
OPA189IDGKR
OPA189IDGKT
OPA189IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
D
DBV
DBV
DGK
DGK
D
8
5
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA189
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAU
SN
1CTV
5
1CTV
8
1CS6
8
1CS6
8
OPA189
OP2189
1VQQ
OPA2189ID
SOIC
D
8
OPA2189IDGKR
OPA2189IDGKT
OPA2189IDR
OPA4189IDR
OPA4189IDT
OPA4189IPWR
OPA4189IPWT
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
SN
8
SN
1VQQ
8
2500 RoHS & Green
3000 RoHS & Green
SN
OP2189
OPA4189
OPA4189
OPA4189
OPA4189
SOIC
D
14
14
14
14
SN
SOIC
D
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
SN
TSSOP
TSSOP
PW
PW
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2021
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA189IDBVR
OPA189IDBVT
OPA189IDGKR
OPA189IDGKT
OPA189IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000
250
180.0
180.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
180.0
8.4
3.23
3.23
5.3
5.3
6.4
5.3
5.3
6.4
6.5
6.5
6.9
6.9
3.17
3.17
3.4
3.4
5.2
3.4
3.4
5.2
9.5
9.5
5.6
5.6
1.37
1.37
1.4
1.4
2.1
1.4
1.4
2.1
2.1
2.1
1.6
1.6
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8.4
8.0
8
2500
250
12.4
12.4
12.4
12.4
12.4
12.8
16.4
16.4
12.4
12.4
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
12.0
12.0
8
8
2500
2500
250
OPA2189IDGKR
OPA2189IDGKT
OPA2189IDR
OPA4189IDR
OPA4189IDT
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
3000
250
SOIC
D
14
14
14
14
SOIC
D
OPA4189IPWR
OPA4189IPWT
TSSOP
TSSOP
PW
PW
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA189IDBVR
OPA189IDBVT
OPA189IDGKR
OPA189IDGKT
OPA189IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000
250
213.0
213.0
366.0
366.0
853.0
366.0
366.0
366.0
366.0
366.0
853.0
210.0
191.0
191.0
364.0
364.0
449.0
364.0
364.0
364.0
364.0
364.0
449.0
185.0
35.0
35.0
50.0
50.0
35.0
50.0
50.0
50.0
50.0
50.0
35.0
35.0
8
2500
250
8
8
2500
2500
250
OPA2189IDGKR
OPA2189IDGKT
OPA2189IDR
OPA4189IDR
OPA4189IDT
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
3000
250
SOIC
D
14
14
14
14
SOIC
D
OPA4189IPWR
OPA4189IPWT
TSSOP
TSSOP
PW
PW
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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