OPA4191IRUMR_技术文档

OPA191, OPA2191, OPA4191

SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021

OPAx191 36-V, Low-Power, Precision, CMOS, Rail-to-Rail Input/Output,

Low Offset Voltage, Low Input Bias Current Op Amp

1 Features

3 Description

•

Low offset voltage: ±5 µV

The OPAx191 family (OPA191, OPA2191, and

OPA4191) is a new generation of 36-V, e-trim^™

operational amplifiers.

Low offset voltage drift: ±0.1 µV/°C

Low noise: 15 nV/√ Hz at 1 kHz

High common-mode rejection: 140 dB

Low bias current: ±5 pA

Rail-to-rail input and output

Wide bandwidth: 2.5-MHz GBW

High slew rate: 5 V/µs

Low quiescent current: 140 µA per amplifier

Wide supply: ±2.25 V to ±18 V, 4.5 V to 36 V

EMI/RFI filtered inputs

Differential input voltage range to supply rail

High capacitive load drive capability: 1 nF

Industry standard packages:

These devices offer outstanding dc precision and

ac performance, including rail-to-rail input/output, low

offset voltage (±5 µV, typ), low offset drift (±0.2 µV/°C,

typ), and 2-MHz bandwidth.

Unique features, such as differential input-voltage

range to the supply rail, high output current (±65 mA),

high capacitive load drive of up to 1 nF, and high

slew rate (5 V/µs), make the OPAx191 a robust, high-

performance operational amplifier for high-voltage

industrial applications.

– Single in SOIC-8, SOT-5, and VSSOP-8

– Dual in SOIC-8 and VSSOP-8

– Quad in SOIC-14, TSSOP-14, and WQFN-16

The OPAx191 family of op amps is available in

standard packages and is specified from –40°C to

+125°C.

2 Applications

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

4.90 mm × 3.90 mm

2.90 mm × 1.60 mm

3.00 mm × 3.00 mm

4.90 mm × 3.90 mm

3.00 mm × 3.00 mm

8.65 mm x 3.90 mm

5.00 mm x 4.40 mm

4.00 mm x 4.00 mm

•

Analog input module

Mixed module (AI, AO, DI, DO)

Data acquisition (DAQ)

Source measurement unit (SMU)

Pressure transmitter

Train control and management systems

Lab and field instrumentation

SOIC (8)

OPA191

SOT (5)

VSSOP (8)

SOIC (8)

OPA2191

OPA4191

VSSOP (8)

SOIC (14)

TSSOP (14)

WQFN (16)

(1) For all available packages, see the package option

addendum at the end of the data sheet.

Analog Inputs

REF3140

RC Filter

OPA625

Reference Driver

Bridge Sensor

Gain

OPA191

+

4:2

HV MUX

Thermocouple

REF

V_IN

+

OPA191

P

Gain

OPA191

+

Antialiasing

Filter

ADS8864

V_IN

Current Sensing

Optical Sensor

M

High-Voltage Multiplexed Input

High-Voltage Level Translation

VCM

OPA191 in a High-Voltage, Multiplexed, Data-Acquisition System

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

OPA191, OPA2191, OPA4191

SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information: OPA191 ................................... 6

6.5 Thermal Information: OPA2191 ................................. 6

6.6 Thermal Information: OPA4191 ................................. 6

6.7 Electrical Characteristics: V_S= ±4 V to ±18 V

8.2 Functional Block Diagram.........................................22

8.3 Feature Description...................................................23

8.4 Device Functional Modes..........................................30

9 Application and Implementation..................................31

9.1 Application Information............................................. 31

9.2 Typical Applications.................................................. 31

10 Power Supply Recommendations..............................35

11 Layout...........................................................................35

11.1 Layout Guidelines................................................... 35

11.2 Layout Example...................................................... 36

12 Device and Documentation Support..........................37

12.1 Device Support....................................................... 37

12.2 Documentation Support.......................................... 37

12.3 Receiving Notification of Documentation Updates..37

12.4 Support Resources................................................. 37

12.5 Trademarks.............................................................38

12.6 Electrostatic Discharge Caution..............................38

12.7 Glossary..................................................................38

13 Mechanical, Packaging, and Orderable

(V_S= 8 V to 36 V) .........................................................7

6.8 Electrical Characteristics: V_S= ±2.25 V to ±4 V

(V_S= 4.5 V to 8 V) ........................................................9

6.9 Typical Characteristics.............................................. 11

7 Parameter Measurement Information..........................20

7.1 Input Offset Voltage Drift...........................................20

8 Detailed Description......................................................22

8.1 Overview...................................................................22

Information.................................................................... 38

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (October 2019) to Revision D (August 2021)

Page

•

Changed OPA4191 PW (TSSOP-14) package from preview to production data (active).................................. 1

Changes from Revision B (July 2019) to Revision C (October 2019)

Page

•

Changed OPA4191 RUM package from preview to production data (active).....................................................1

Changes from Revision A (April 2016) to Revision B (July 2019)

Page

•

Added advanced information (preview) 16-pin RUM (WQFN) package and associated content to data sheet 1

Changed Figure 32 condition from G = –1 to G = 1..........................................................................................11

Changed Figure 33 condition from G = 1 to G = –1 .........................................................................................11

Changes from Revision * (December 2015) to Revision A (April 2016)

Page

•

Changed DBV and DGK packages from product preview to production data.................................................... 1

Changed Figure 23, 0.1-Hz to 10-Hz Noise......................................................................................................11

Added text regarding capacitive load drive to the Capacitive Load and Stability section.................................26

Added Figure 56 .............................................................................................................................................. 26

2

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5 Pin Configuration and Functions

NC

œIN

+IN

Vœ

1

2

3

4

8

7

6

5

NC

V+

OUT

Vœ

1

2

3

5

V+

œ

OUT

NC

+

+IN

4

œIN

Not to scale

Figure 5-1. OPA191 DBV (5-Pin SOT) Package,

Top View

Figure 5-2. OPA191 D (8-Pin SOIC) and

DGK (8-Pin VSSOP) Packages, Top View

Pin Functions: OPA191

OPA191

I/O

DESCRIPTION

NAME

D (SOIC),

DGK (VSSOP)

DBV (SOT)

+IN

–IN

NC

OUT

V+

3

4

I

Noninverting input

2

I

Inverting input

1, 5, 8

—

1

—

O

—

No internal connection (can be left floating)

Output

6

7

4

5

Positive (highest) power supply

Negative (lowest) power supply

V–

2

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OUT A

œIN A

+IN A

Vœ

1

2

3

4

8

7

6

5

V+

OUT B

œIN B

+IN B

Not to scale

Figure 5-3. OPA2191 D (8-Pin SOIC) and

DGK (8-Pin VSSOP) Packages, Top View

OUT A

œIN A

+IN A

V+

1

2

3

4

5

6

7

14

13

12

11

10

9

OUT D

œIN D

+IN D

Vœ

-IN A

+IN A

V+

1

2

3

4

12

11

10

9

-IN D

+IN D

Vœ

Thermal

Pad

+IN B

œIN B

OUT B

+IN C

œIN C

OUT C

+IN B

+IN C

8

Not to scale

Figure 5-4. OPA4191 D (14-Pin SOIC) and

PW (14-Pin TSSOP) Packages, Top View

Not to scale

Figure 5-5. OPA4191 RUM (16-Pin WQFN With

Exposed Thermal Pad) Package, Top View

Pin Functions: OPA2191 and OPA4191

OPA2191

D (SOIC),

OPA4191

I/O

DESCRIPTION

NAME

D (SOIC),

RUM (QFN)

DGK (VSSOP) PW (TSSOP)

+IN A

+IN B

+IN C

+IN D

–IN A

–IN B

–IN C

–IN D

OUT A

OUT B

OUT C

OUT D

V+

3

5

3

5

2

4

I

Noninverting input, channel A

Noninverting input, channel B

Noninverting input, channel C

Noninverting input, channel D

Inverting input, channel A

Inverting input, channel B

Inverting input,,channel C

Inverting input, channel D

Output, channel A

—

2

10

12

2

9

I

11

1

I

6

5

I

—

1

9

8

I

13

1

12

15

6

I

O

—

7

Output, channel B

—

8

7

Output, channel C

14

4

14

3

Output, channel D

Positive (highest) power supply

Negative (lowest) power supply

V–

4

11

10

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

±20

Supply voltage, V_S= (V+) – (V–)

V

(+40, single supply)

Common-mode

Voltage

(V–) – 0.5

(V+) + 0.5

(V+) – (V–) + 0.2

±10

V

Signal input pins

Output short circuit⁽²⁾

Temperature

Differential

Current

mA

Continuous

–40

Continuous Continuous

150

Operating

Junction

150

°C

Storage, T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE

±3000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

OPA4191IPW package only

,

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5 (±2.25)

–40

NOM

MAX

36 (±18)

125

UNIT

V

Supply voltage, V_S= (V+) – (V–)

Specified temperature

°C

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UNIT

SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021

6.4 Thermal Information: OPA191

OPA191

THERMAL METRIC⁽¹⁾

D (SOIC)

DGK (VSSOP)

DBV (SOT)

5 PINS

158.8

60.7

8 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

115.8

60.1

56.4

12.8

55.9

N/A

180.4

67.9

°C/W

R_θJC(top)

R_θJB

102.1

10.4

44.8

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

1.6

ψ_JB

100.3

N/A

4.2

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Thermal Information: OPA2191

OPA2191

THERMAL METRIC⁽¹⁾

D (SOIC)

DGK (VSSOP)

UNIT

8 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

107.9

53.9

48.9

6.6

158

48.6

78.7

3.9

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

ψ_JB

48.3

N/A

77.3

N/A

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.6 Thermal Information: OPA4191

OPA4191

THERMAL METRIC⁽¹⁾

D (SOIC)

PW (TSSOP)

14 PINS

RUM (QFN)

16 PINS

33.0

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

86.4

46.3

41.0

11.3

40.7

N/A

108.1

26.3

54.4

1.4

°C/W

R_θJC(top)

R_θJB

25.1

11.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.2

ψ_JB

53.3

N/A

11.5

R_θJC(bot)

2.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

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6.7 Electrical Characteristics: V_S= ±4 V to ±18 V (V_S= 8 V to 36 V)

at T_A= +25°C, V_CM= V_OUT= V_S/ 2, and R_L= 10 kΩ connected to V_S/ 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±5

±8

±25

±75

V_S= ±18 V

T_A= 0°C to 85°C

T_A= –40°C to +125°C

±10

±125

(V+) – 3.0 V < V_CM< (V+) – 1.5 V

See Typical Characteristics

±10

±25

±50

±150

±250

±50

V_OS

Input offset voltage

µV

V_S= ±18 V,

V_CM= (V+) – 1.5 V

T_A= 0°C to 85°C

T_A= –40°C to +125°C

±50

±5

OPA4191 (RUM, PW), V_S= ±18 V

VCM = (V+) – 1.5 V

T_A= 0°C to 85°C

±10

±475

±740

±0.8

±1.2

±0.9

±1.3

TA = –40°C to +125°C

T_A= 0°C to 85°C

±20

±0.1

±0.15

±0.1

±0.15

±0.5

V_S= ±18 V, D and PW packages

only

T_A= –40°C to +125°C

T_A= 0°C to 85°C

dV_OS/dT

PSRR

Input offset voltage drift

µV/°C

µV/V

V_S= ±18 V, RUM, DGK and DBV

packages only

T_A= –40°C to +125°C

V_S= ±18 V, V_CM= (V+) – 1.5 V

T_A= –40°C to +125°C

Power-supply rejection

ratio

±0.3

±1.0

INPUT BIAS CURRENT

±5

±2

±20

±9

pA

nA

pA

nA

I_B

Input bias current

T_A= –40°C to +125°C

±20

±2

I_OS

Input offset current

Input voltage noise

NOISE

E_n

(V–) – 0.1 V < V_CM< (V+) – 3 V

(V+) – 1.5 V < V_CM< (V+) + 0.1 V

f = 0.1 Hz to 10 Hz

f = 100 Hz

1.4

7

µV_PP

18

15

53

24

(V–) – 0.1 V < V_CM< (V+) – 3 V

f = 1 kHz

Input voltage noise

density

e_n

nV/√Hz

f = 100 Hz

(V+) – 1.5 V < V_CM< (V+) + 0.1 V

f = 1 kHz

Input current noise

density

i_n

1.5

fA/√Hz

V

INPUT VOLTAGE

Common-mode voltage

range

V_CM

(V–) – 0.1

120

(V+) + 0.1

V_S= ±18 V,

(V–) – 0.1 V < V_CM< (V+) – 3 V

140

126

V_S= ±18 V,

T_A= –40°C to +125°C

114

Common-mode rejection (V–) < V_CM< (V+) – 3 V

ratio

CMRR

dB

96

86

120

100

V_S= ±18 V,

(V+) – 1.5 V < V_CM< (V+)

(V+) – 3 V < V_CM< (V+) – 1.5 V

See Typical Characteristics

INPUT IMPEDANCE

Z_ID

Z_IC

Differential

100 || 1.6

1 || 6.4

MΩ || pF

10¹³Ω ||

pF

Common-mode

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6.7 Electrical Characteristics: V_S= ±4 V to ±18 V (V_S= 8 V to 36 V) (continued)

at T_A= +25°C, V_CM= V_OUT= V_S/ 2, and R_L= 10 kΩ connected to V_S/ 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OPEN-LOOP GAIN

V_S= ±18 V,

(V–) + 0.6 V < V_O< (V+) – 0.6 V,

R_L= 2 kΩ

124

114

126

120

134

126

140

134

V_S= ±18 V,

(V–) + 0.8 V < V_O< (V+) – 0.8 V,

R_L= 2 kΩ, RUM package

V_S= ±18 V,

(V–) + 0.6 V < V_O< (V+) – 0.6 V,

R_L= 2 kΩ

T_A= –40°C to +125°C

A_OL

Open-loop voltage gain

dB

V_S= ±18 V,

(V–) + 0.8 V < V_O< (V+) – 0.8 V,

R_L= 2 kΩ, RUM package

V_S= ±18 V,

(V–) + 0.3 V < V_O< (V+) – 0.3 V,

R_L= 10 kΩ

V_S= ±18 V,

(V–) + 0.3 V < V_O< (V+) – 0.3 V,

R_L= 10 kΩ

T_A= –40°C to +125°C

FREQUENCY RESPONSE

GBW

Unity gain bandwidth

2.5

7.5

5.5

0.7

1

MHz

V/µs

Falling

SR

Slew rate

V_S= ±18 V, G = 1, 10-V step

To 0.01%, C_L= 20 pF

Rising

V_S= ±18 V, G = 1, 2-V step

V_S= ±18 V, G = 1, 5-V step

V_S= ±18 V, G = 1, 2-V step

V_S= ±18 V, G = 1, 5-V step

From overload to negative rail

From overload to positive rail

t_s

Settling time

µs

1.8

3.7

0.4

1

To 0.001%, C_L= 20 pF

t_OR

Overload recovery time V_IN× G = V_S

Total harmonic distortion

THD+N

G = 1, f = 1 kHz, V_O= 3.5 V_RMS

0.0012%

+ noise

OPA2191 and OPA4191, at dc

150

130

dB

Crosstalk

OPA2191 and OPA4191, f = 100 kHz

OUTPUT

No load

5

50

15

110

500

15

Positive rail

R_L= 10 kΩ

R_L= 2 kΩ

No load

200

5

Voltage output swing

from rail

V_O

mV

Negative rail

V_S= ±18 V

R_L= 10 kΩ

R_L= 2 kΩ

50

110

500

200

±65

I_SC

C_L

Short-circuit current

Capacitive load drive

mA

Ω

See Typical Characteristics

700

Open-loop output

impedance

Z_O

f = 1 MHz, I_O= 0 A, See Typical Characteristics

POWER SUPPLY

140

200

250

Quiescent current per

amplifier

I_Q

I_O= 0 A

µA

T_A= –40°C to +125°C

TEMPERATURE

Thermal protection

180

30

°C

Thermal hysteresis

8

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6.8 Electrical Characteristics: V_S= ±2.25 V to ±4 V (V_S= 4.5 V to 8 V)

at T_A= +25°C, V_CM= V_OUT= V_S/ 2, and R_L= 10 kΩ connected to V_S/ 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±5

±8

±25

±75

V_S= ±2.25 V,

V_CM= (V+) – 3 V

T_A= 0°C to 85°C

T_A= –40°C to +125°C

±10

±125

(V+) – 3.0 V < V_CM< (V+) – 1.5 V

See Typical Characteristics

±10

±25

±50

±150

±250

±50

V_OS

Input offset voltage

µV

V_S= ±3 V,

V_CM= (V+) – 1.5 V

T_A= 0°C to 85°C

T_A= –40°C to +125°C

±50

±10

OPA4191 (RUM, PW), V_S= ±3 V,

V_CM= (V+) – 1.5 V

T_A= –40°C to +85°C

T_A= –40°C to +125°C

T_A= 0°C to 85°C

±90

±475

±740

±0.8

±1.2

±0.9

±150

±0.1

±0.15

±0.1

µV/°C

V_S= ±2.25 V, V_CM= (V+) – 3 V,

D and PW packages only

T_A= –40°C to +125°C

T_A= 0°C to 85°C

V_S= ±2.25 V, V_CM= (V+) – 3

V, RUM, DGK and DBV packages

only

dV_OS/dT

PSRR

Input offset voltage drift

T_A= –40°C to +125°C

±0.15

±0.5

±1.3

µV/°C

µV/V

V_S= ±2.25 V, V_CM= (V+) – 1.5 V

Power-supply rejection

ratio

T_A= –40°C to +125°C, V_CM= V_S/ 2 – 0.75 V

±1

INPUT BIAS CURRENT

±5

±2

±20

±9

pA

nA

pA

nA

I_B

Input bias current

T_A= –40°C to +125°C

±20

±2

I_OS

Input offset current

Input voltage noise

NOISE

E_n

(V–) – 0.1 V < V_CM< (V+) – 3 V

f = 0.1 Hz to 10 Hz

1.4

7

µV_PP

(V+) – 1.5 V < V_CM< (V+) + 0.1 V f = 0.1 Hz to 10 Hz

f = 100 Hz

(V–) – 0.1 V < V_CM< (V+) – 3 V

f = 1 kHz

18

15

53

24

1.5

e_n

Input voltage noise density

Input current noise density

nV/√Hz

f = 100 Hz

(V+) – 1.5 V < V_CM< (V+) + 0.1 V

f = 1 kHz

i_n

INPUT VOLTAGE

f = 1 kHz

fA/√Hz

V

Common-mode voltage

range

V_CM

(V–) – 0.1

(V+) + 0.1

V_S= ±2.25 V,

(V–) – 0.1 V < V_CM< (V+) – 3 V

96

90

110

104

V_S= ±2.25 V,

T_A= –40°C to +125°C

(V–) < V_CM< (V+) – 3 V

Common-mode rejection

ratio

CMRR

dB

96

84

120

100

V_S= ±2.25 V,

(V+) – 1.5 V < V_CM< (V+)

T_A= –40°C to +125°C

(V+) – 3 V < V_CM< (V+) – 1.5 V

See Typical Characteristics

INPUT IMPEDANCE

Z_ID

Z_IC

Differential

100 || 1.6

1 || 6.4

MΩ || pF

10¹³Ω ||

pF

Common-mode

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6.8 Electrical Characteristics: V_S= ±2.25 V to ±4 V (V_S= 4.5 V to 8 V) (continued)

at T_A= +25°C, V_CM= V_OUT= V_S/ 2, and R_L= 10 kΩ connected to V_S/ 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OPEN-LOOP GAIN

V_S= ±2.25 V,

(V–) + 0.6 V < V_O< (V+) – 0.6 V,

R_L= 2 kΩ

110

100

110

106

120

114

126

120

T_A= –40°C to +125°C

A_OL

Open-loop voltage gain

dB

V_S= ±2.25 V,

(V–) + 0.3 V < V_O< (V+) – 0.3 V,

R_L= 10 kΩ

FREQUENCY RESPONSE

GBW

Unity gain bandwidth

2.2

6.5

5.5

0.4

1

MHz

V/µs

Falling

SR

Slew rate

V_S= ±2.25 V, G = 1, 1-V step

V_IN× G = V_S

Rising

From overload to negative rail

From overload to positive rail

t_OR

Overload recovery time

Crosstalk

µs

OPA2191 and OPA4191, at dc

150

130

dB

OPA2191 and OPA4191, f = 100 kHz

OUTPUT

No load

5

15

60

5

15

110

500

15

Positive rail

R_L= 10 kΩ

R_L= 2 kΩ

No load

Voltage output swing from

rail

V_O

mV

Negative rail

V_S= ±2.25 V

R_L= 10 kΩ

R_L= 2 kΩ

15

60

±30

110

500

I_SC

C_L

Short-circuit current

Capacitive load drive

mA

Ω

See Typical Characteristics

700

Open-loop output

impedance

Z_O

f = 1 MHz, I_O= 0 A, see Typical Characteristics

POWER SUPPLY

140

200

250

Quiescent current per

amplifier

I_Q

I_O= 0 A

µA

T_A= –40°C to +125°C

TEMPERATURE

Thermal protection

180

30

°C

Thermal hysteresis

10

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6.9 Typical Characteristics

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

Table 6-1. Table of Graphs

DESCRIPTION

Offset Voltage Production Distribution

Offset Voltage Drift Distribution

FIGURE

Figure 6-1, Figure 6-2, Figure 6-3, Figure 6-4, Figure 6-5, Figure 6-6

Figure 6-7, Figure 6-8,

Figure 6-9, Figure 6-10

Figure 6-11, Figure 6-12

Figure 6-13

Offset Voltage vs Temperature

Offset Voltage vs Common-Mode Voltage

Offset Voltage vs Power Supply

Open-Loop Gain and Phase vs Frequency

Closed-Loop Gain and Phase vs Frequency

Input Bias Current vs Common-Mode Voltage

Input Bias Current vs Temperature

Output Voltage Swing vs Output Current (maximum supply)

CMRR and PSRR vs Frequency

CMRR vs Temperature

Figure 6-14

Figure 6-15

Figure 6-16

Figure 6-17

Figure 6-18, Figure 6-19

Figure 6-20

Figure 6-21

PSRR vs Temperature

Figure 6-22

0.1-Hz to 10-Hz Noise

Figure 6-23

Input Voltage Noise Spectral Density vs Frequency

THD+N Ratio vs Frequency

Figure 6-24

Figure 6-25

THD+N vs Output Amplitude

Figure 6-26

Quiescent Current vs Supply Voltage

Quiescent Current vs Temperature

Open Loop Gain vs Temperature

Open Loop Output Impedance vs Frequency

Small Signal Overshoot vs Capacitive Load (100-mV output step)

No Phase Reversal

Figure 6-27

Figure 6-28

Figure 6-29, Figure 6-30

Figure 6-31

Figure 6-32, Figure 6-33

Figure 6-34

Overload Recovery

Figure 6-35

Small-Signal Step Response (100 mV)

Large-Signal Step Response

Figure 6-36, Figure 6-37

Figure 6-38, Figure 6-39

Figure 6-40, Figure 6-41, Figure 6-42, Figure 6-43

Figure 6-44

Settling Time

Short-Circuit Current vs Temperature

Maximum Output Voltage vs Frequency

Propagation Delay Rising Edge

Figure 6-45

Figure 6-46

Propagation Delay Falling Edge

Figure 6-47

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6.9 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

35

30

25

20

15

10

5

48

42

36

30

24

18

12

6

0

-25 -20 -15 -10

-5

0

5

10

15

20

25

50

75

-50 -40 -30 -20 -10

0

10

20

30

40

50

75

Input Offset Voltage (mV)

T_A= 25°C

T_A= 125°C

Figure 6-1. Offset Voltage Production Distribution

48

Figure 6-2. Offset Voltage Production Distribution

48

42

36

30

24

18

12

6

42

36

30

24

18

12

6

0

-50 -40 -30 -20 -10

0

10

20

30

40

-50 -40 -30 -20 -10

0

10

20

30

40

Input Offset Voltage (mV)

T_A= 85°C

T_A= 0°C

Figure 6-3. Offset Voltage Production Distribution

48

Figure 6-4. Offset Voltage Production Distribution

48

42

36

30

24

18

12

6

42

36

30

24

18

12

6

0

-75 -60 -45 -30 -15

0

15

30

45

60

-75 -60 -45 -30 -15

0

15

30

45

60

Input Offset Voltage (mV)

T_A= –25°C

T_A= –40°C

Figure 6-5. Offset Voltage Production Distribution

Figure 6-6. Offset Voltage Production Distribution

12

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6.9 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

40

30

20

10

0

40

30

20

10

0

Offset Voltage Drift (µV/°C)

C013

T_A= –40°C to +125°C, SOIC package

T_A= 0°C to 85°C, SOIC package

Figure 6-7. Offset Voltage Drift Distribution

Figure 6-8. Offset Voltage Drift Distribution

125

100

75

125

Average ê 3d

Average ê 1d

75

50

25

0

œ25

œ75

œ125

-25

-50

-75

-100

-125

0

25

50

75

100 125 150

œ75 œ50 œ25

-75

-50

-25

0

25

50

75

100 125 150

Temperature (°C)

C001

Temperature (èC)

4 typical units

Statistical distribution

Figure 6-10. Offset Voltage vs Temperature

Figure 6-9. Offset Voltage vs Temperature

25

15

250

200

150

100

50

Transition

V_CM= œ18.1 V

P-Channel

5

V_CM= -18.1 V

0

œ5

œ50

œ100

œ150

œ200

œ250

N-Channel

V_CM= 18 V

œ15

œ25

0

5

10

15

13

14

15

16

17

18

19

œ20

œ15

œ10

œ5

Common Mode Voltage (V)

C001

Figure 6-11. Offset Voltage vs Common-Mode Voltage

Figure 6-12. Offset Voltage vs Common-Mode Voltage in

Transition Region

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6.9 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

25

160

180

135

90

20

140

Open-loop Gain

15

120

Phase

10

100

5

80

45

0

-5

60

40

0

-10

-15

-20

-25

20

-45

-90

-135

0

œ20

œ40

0

ê5

ê10

Power Supply Voltage (V)

ê15

ê20

0.1

1.0 10.0 100.0 1k

10k 100k 1M 10M 100M

Frequency (Hz)

C001

30 typical units

Figure 6-13. Offset Voltage vs Power Supply

Figure 6-14. Open-Loop Gain and Phase

vs Frequency

1000

800

60

40

20

0

G = -1

G = +1

G= -10

G= -100

600

400

200

0

œ200

œ400

œ600

œ800

œ1000

-20

100

1k

10k

100k

1M

10M

100M

0

5

10

15

20

œ20

œ15

œ10

œ5

Frequency (Hz)

Common Mode Voltage (V)

C004

C001

Figure 6-15. Closed-Loop Gain vs Frequency

Figure 6-16. Input Bias Current

vs Common-Mode Voltage

20

18

16

14

12

10

8

10

I_{B -}

I_B+

9

8

7

6

5

4

3

2

1

0

6

-40èC

25èC

85èC

125èC

4

2

0

25

50

75

100 125 150

œ75 œ50 œ25

0

20

40 60

Output Current (mA)

80

100

Temperature (°C)

C001

Sourcing

Figure 6-17. Input Bias Current vs Temperature

Figure 6-18. Output Voltage Swing

vs Output Current

14

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6.9 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

0

140

-40èC

-2

25èC

120

85èC

125èC

-4

100

80

60

40

20

0

-6

-8

-10

-12

-14

-16

-18

-20

CMRR

+PSRR

œPSRR

0.1

1.0

10.0 100.0

1k

10k 100k

1M

10M

0

20

40 60

Output Current (mA)

80

100

Frequency (Hz)

C004

Sinking

Figure 6-20. CMRR and PSRR vs Frequency

Figure 6-19. Output Voltage Swing

vs Output Current

10

5

V_S

= 2.25 V, (Vœ) ≤ V_CM≤ (V+) œ 3 V

8

6

4

3

4

2

1

0

-2

-4

-6

-8

-10

-1

-2

-3

-4

-5

V_S

= 18 V, (Vœ) ≤ V_CM≤ (V+) œ 3 V

0

25

50

75

100 125 150

0

25

50

75

100 125 150

œ75 œ50 œ25

Temperature (°C)

C001

Figure 6-21. CMRR vs Temperature

Figure 6-22. PSRR vs Temperature

100

10

1

10

100

1k

10k

100k

1M

10M

Time (1 s/div)

Frequency (Hz)

C002

Figure 6-23. 0.1-Hz to 10-Hz Noise

Figure 6-24. Input Voltage Noise Spectral Density vs Frequency

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6.9 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

0.5

1

0.1

-40

G = -1, 2k-ꢀ Load

G = -1, 10k-ꢀ Load

G = +1, 2k-ꢀ Load

G = +1, 10k-ꢀ Load

G = -1 V/V, R_L= 2 kW

G = -1 V/V, R_L= 10 kW

G = 1 V/V, R_L= 2 kW

G = 1 V/V, R_L= 10 kW

-60

0.1

0.01

-80

0.01

0.001

0.0001

0.00001

-100

-120

-140

0.001

20

200

2k

20k

0.0005

0.01

0.1 1

Output Amplitude (V_RMS

10 20

Frequency (Hz)

C004

)

Figure 6-25. THD+N vs Frequency

Figure 6-26. THD+N vs Output Amplitude

200

180

160

140

120

100

80

200

180

160

140

120

100

80

V_S= ê2.25 V

V_S= ê18 V

V_S

= 18 V

V_S

= 2.25 V

60

40

20

0

25

50

75

100 125 150

œ75 œ50 œ25

2

4

6

8

10

12

Supply Voltage (V)

14

16

18

20

Temperature (°C)

C001

Figure 6-28. Quiescent Current vs Temperature

Figure 6-27. Quiescent Current vs Supply Voltage

5.0

4.0

3.0

2.0

5.0

4.0

3.0

V_S

= 2.25 V

2.0

1.0

V_S

= 2.25 V

1.0

0.0

œ1.0

œ2.0

œ3.0

œ4.0

œ5.0

œ1.0

œ2.0

œ3.0

œ4.0

œ5.0

V_S

=

18 V

V_S

= 18 V

0

25

50

75

100 125 150

0

25

50

75

100 125 150

œ75 œ50 œ25

Temperature (°C)

C001

R_L= 10 kΩ

R_L= 2 kΩ

Figure 6-29. Open-Loop Gain vs Temperature

Figure 6-30. Open-Loop Gain vs Temperature

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6.9 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

100k

60

RISO = 0

RISO = 25

50

RISO = 50

10k

1k

40

30

20

10

0

100

10

100

1000

100m

1

10

100

1k

Frequency (Hz)

10k

100k

1M

10M

Capacitive Load (pF)

C004

G = 1, 100-mV output step

Figure 6-31. Open-Loop Output Impedance

vs Frequency

Figure 6-32. Small-Signal Overshoot

vs Capacitive Load (100-mV Output Step)

20

10

0

Output

Input

RISO = 0

RISO = 25

RISO = 50

10

100

1000

Time (50 ms/div)

Capacitive Load (pF)

C004

G = –1, 100-mV output step

Figure 6-34. No Phase Reversal

Figure 6-33. Small-Signal Overshoot

vs Capacitive Load

Negative overload

Positive overload

Time (2.5 µs/div)

Time (ms)

C017

V_S= ±18 V, G = –10 V/V

G = 1, C_L= 10 pF

Figure 6-35. Overload Recovery

Figure 6-36. Small-Signal Step Response

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6.9 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

Time (2.5 µs/div)

C017

G = –1, R_L= 1 kΩ, C_L= 10 pF

G = 1, C_L= 10 pF

Figure 6-37. Small-Signal Step Response

Figure 6-38. Large-Signal Step Response

0.01% settling = ê200 mV

Time (2.5 µs/div)

Time (500 ns/div)

C017

Gain = 1, 2-V step, rising, step applied at t = 0 µs

G = –1, R_L= 1 kΩ, C_L= 10 pF

Figure 6-40. 0.01% Settling Time

Figure 6-39. Large-Signal Step Response

0.01% settling = ê200 mV

0.01% settling = ê500 mV

Time (500 ns/div)

Gain = 1, 2-V step, falling, step applied at t = 0 µs

Gain = 1, 5-V step, rising, step applied at t = 0 µs

Figure 6-41. 0.01% Settling Time

Figure 6-42. 0.01% Settling Time

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6.9 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±18 V, V_CM= V_S/ 2, R_L= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

100

0.01% settling = ê500 mV

I_SC, Source

80

60

40

20

0

I_SC, Sink

0

25

50

75

100 125 150

œ75 œ50 œ25

Time (500 ns/div)

Temperature (°C)

C001

Gain = 1, 5-V step, falling, step applied at t = 0 µs

Figure 6-43. 0.01% Settling Time

Figure 6-44. Short-Circuit Current vs Temperature

35

30

25

20

15

10

5

Maximum output voltage without

slew-rate induced distortion.

Overdrive = 100 mV

V_S

= 15 V

t_pLH= 26 µs

V_OUTVoltage

V_S

= 4 V

=

2.25 V

1k

0

Time (10 µs/div)

100

10k

100k

1M

10M

Frequency (Hz)

C001

C017

Figure 6-45. Maximum Output Voltage vs Frequency

Figure 6-46. Propagation Delay Rising Edge

t_pHL= 26 µs

V_OUTVoltage

Overdrive = 100 mV

Time (10 µs/div)

C017

Figure 6-47. Propagation Delay Falling Edge

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7 Parameter Measurement Information

7.1 Input Offset Voltage Drift

The OPAx191 family of operational amplifiers is manufactured using TI’s e-trim operation amplifier technology.

This e-trim operational amplifier technology is a TI proprietary method of trimming internal device parameters

during either wafer probing or final testing. Each amplifier input offset voltage and input offset voltage drift is

trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage

drift. When trimming input offset voltage drift, the systematic or linear drift error on each device is trimmed to

zero. Figure 7-1 illustrates this concept.

V_OSbefore trim

V_OSafter trim

Linear component of drift

Temperature

Figure 7-1. Input Offset Before and After Drift Trim

A common method of specifying input offset voltage drift is the box method. The box method estimates a

maximum input offset drift by bounding an offset voltage versus temperature curve with a box and using the

corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of

the box corresponds to the input offset voltage drift. Figure 7-2 illustrates the box method concept. The box

method works particularly well when the input offset drift is dominated by the linear component of drift, but

because the OPA191 family uses TI’s e-trim operational amplifier technology to remove the linear component

input offset voltage drift, the box method is not a particularly useful method of accurately performing an error

analysis. Shown in Figure 7-2 are 30 typical units of OPAx191 with the box method superimposed for illustrative

purposes. The boundaries of the box are determined by the specified temperature range along the x-axis and

the maximum specified input offset voltage across that same temperature range along the y-axis. Using the

box method predicts an input offset voltage drift of 0.9 µV/°C. As shown in Figure 7-2, the slopes of the actual

input offset voltage versus temperature are much less than that predicted by the box method. The box method

predicts a pessimistic value for the maximum input offset voltage drift and is not recommended when performing

an error analysis.

Offset Voltage vs Temperature

100

75

50

25

0

-25

-50

-75

-100

-50

-25

0

25

50

75

100

125

150

Temperature (èC)

Figure 7-2. The Box Method

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Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input

offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along

the input offset voltage versus temperature curve. The results for the OPAx191 family are illustrated in Figure

7-3.

1.2

0.9

0.6

+3 1

0.3

1

0

-1

-0.3

-0.6

-0.9

-3 1

-1.2

0

25

50

75

100 125 150

œ75 œ50 œ25

Temperature (°C)

C001

Figure 7-3. Input Offset Voltage Drift vs Temperature (SOIC Package)

As illustrated in Figure 7-3, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C

to +125°C. When performing an error analysis over the full specified temperature range, use the typical and

maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced

temperature range is applicable, use the information illustrated in Figure 7-3 when performing an error analysis.

To determine the change in input offset voltage, use Equation 1:

ΔV_OS= ΔT × dV_OS/dT

(1)

where

•

ΔV_OS= Change in input offset voltage

ΔT = Change in temperature

dV_OS/dT = Input offset voltage drift

For example, determine the amount of OPA191ID input offset voltage change over the temperature range of

25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 7-3, the input offset drift is typically 0.25 µV/°C. This

input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.25 µV/°C = 12.5 µV.

For 3 σ (99.7%) of the units, Figure 7-3 shows a typical input offset drift of approximately 0.75 µV/°C. This input

offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.75 µV/°C = 37.5 µV.

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8 Detailed Description

8.1 Overview

The OPAx191 family of e-trim operational amplifiers use a method of package-level trim for offset and offset

temperature drift implemented during the final steps of manufacturing after the plastic molding process. This

method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package

molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points

are set, further communication to the trim structure is permanently disabled. Section 8.2 shows the simplified

diagram of the OPAx191.

Unlike previous e-trim operational amplifiers, the OPAx191 uses a patented two-temperature trim architecture to

achieve a very low offset voltage and low voltage offset drift over the full specified temperature range. This level

of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial

sensors, filters, and high-voltage data acquisition.

8.2 Functional Block Diagram

OPAx191

œ

NCH Input

Stage

+

IN+

œ

High

Capacitive Load

Compensation

VOUT

36-V

Differential

Front End

Output

Stage

Slew

Boost

+

INœ

+

PCH Input

Stage

œ

e-trim™

Operational Amplifier

Package Level Trim

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8.3 Feature Description

8.3.1 Input Protection Circuitry

The OPAx191 uses a unique input architecture to eliminate the need for input protection diodes but still provides

robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure

8-1 can be activated by fast transient step responses and can introduce signal distortion and settling time

delays because of alternate current paths, as shown in Figure 8-2. For low-gain circuits, these fast-ramping input

signals forward-bias back-to-back diodes that cause an increase in input current, resulting in extended settling

time.

V+

V_IN+

V_OUT

OPAx191

~0.7 V

36 V

V_IN-

V-

OPAx191 Provides Full 36-

V Differential Input Range

Conventional Input Protection

Limits Differential Input Range

Figure 8-1. OPA191 Input Protection Does Not Limit Differential Input Capability

1

R_{on_mux}

V_n= 10 V

R_FILT

10 V

S_n

D

1

2

~œ9.3 V

10 V

C_FILT

C_S

C_D

VINœ

2

R_{on_mux}

S_n+1

V_n+1= œ10 V R_FILT

œ10 V

~0.7 V

VOUT

C_FILT

C_S

I_{diode_transient}

VIN+

œ10 V

Input Low-Pass Filter

Simplified Mux Model

Buffer Amplifier

Figure 8-2. Back-to-Back Diodes Create Settling Issues

The OPAx191 family of operational amplifiers provides a true high-impedance differential input capability

for high-voltage applications. This patented input protection architecture does not introduce additional signal

distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input

applications. The OPAx191 tolerates a maximum differential swing (voltage between inverting and noninverting

pins of the op amp) of up to 36 V, making the device an excellent choice for use as a comparator or in

applications with fast-ramping input signals such as multiplexed data-acquisition systems (see Figure 9-4).

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8.3.2 EMI Rejection

The OPAx191 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the OPAx191 benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure

8-3 shows the results of this testing on the OPAx191. Table 8-1 shows the EMIRR IN+ values for the OPAx191 at

particular frequencies commonly encountered in real-world applications. Applications listed in Table 8-1 may be

centered on or operated near the particular frequency shown. Detailed information can also be found in the EMI

Rejection Ratio of Operational Amplifiers application report , available for download from www.ti.com.

120

100

80

60

40

20

0

10

100

Frequency (MHz)

1k

10k

P_RF= –10 dBm, V_S= ±15 V, V_CM= 0 V

Figure 8-3. EMIRR Testing

Table 8-1. OPA191 EMIRR IN+ For Frequencies of Interest

FREQUENCY

APPLICATION OR ALLOCATION

EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications

400 MHz

36 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

1.8 GHz

2.4 GHz

3.6 GHz

5.0 GHz

45 dB

57 dB

62 dB

76 dB

86 dB

GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

Radiolocation, aero communication and navigation, satellite, mobile, S-band

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz)

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8.3.3 Phase Reversal Protection

The OPAx191 family has internal phase-reversal protection. Many op amps exhibit phase reversal when the

input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting

circuits when the input is driven beyond the specified common-mode voltage range, causing the output to

reverse into the opposite rail. The OPAx191 is a rail-to-rail input op amp, and therefore the common-mode range

can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits

into the appropriate rail. This performance is shown in Figure 8-4.

V_IN

V_OUT

Time (35 ms/div)

C017

Figure 8-4. No Phase Reversal

8.3.4 Thermal Protection

The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This

phenomenon is called self heating. The OPAx191 has a thermal protection feature that prevents damage from

self heating.

This thermal protection works by monitoring the temperature of the output stage and turning off the op

amp output drive for temperatures above approximately 180°C. Thermal protection forces the output to a

high-impedance state. The OPAx191 is also designed with approximately 30°C of thermal hysteresis. Thermal

hysteresis prevents the output stage from cycling in and out of the high-impedance state. The OPAx191 returns

to normal operation when the output stage temperature falls below approximately 150°C.

The absolute maximum junction temperature of the OPAx191 is 150°C. Exceeding the limits shown in Section

6.1 may cause damage to the device. Thermal protection triggers at 180°C because of unit-to-unit variance,

but does not interfere with device operation up to the absolute maximum ratings. This thermal protection is not

designed to prevent this device from exceeding absolute maximum ratings, but rather from excessive thermal

overload.

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8.3.5 Capacitive Load and Stability

The OPAx191 features a patented output stage capable of driving large capacitive loads, and in a unity-gain

configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the

amplifier to drive greater capacitive loads; see Figure 8-5. The particular op amp circuit configuration, layout,

gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable

in operation.

G = +1 V/V

Time (2 ms/Div)

Figure 8-5. Transient Response with a Purely Capacitive Load of 1 nF

Like many low-power amplifiers, some ringing can occur even with capacitive loads less than 100 pF. In

unity-gain configurations with no or very light dc loads, place an RC snubber circuit at the OPAx191 output

to reduce any possibility of ringing in lightly-loaded applications. Figure 8-6 illustrates the recommended RC

snubber circuit.

œ

Output

Input

+

R 619 ꢀ

C 320 pF

Figure 8-6. RC Snubber Circuit for Lightly-Loaded Applications in Unity Gain

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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small,

10-Ω to 20-Ω resistor (R_ISO) in series with the output, as shown in Figure 8-7. This resistor significantly reduces

ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in

parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly

reducing the output swing. The error introduced is proportional to the ratio R_ISO/ R_L, and is generally negligible

at low output levels. A high capacitive load drive makes the OPA191 a great choice for applications such as

reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 8-7 uses R_ISOto

stabilize the output of an op amp. R_ISOmodifies the open-loop gain of the system for increased phase margin.

Results using the OPA191 are summarized in Table 8-2. For additional information on techniques to optimize

and design using this circuit, TI Precision Design TIPD128, Capacitive Load Drive Verified Reference Design

Using an Isolation Resistor, details complete design goals, simulation, and test results.

+V_s

V_out

R_iso

+

C_load

+

V_in

-V_s

œ

Figure 8-7. Extending Capacitive Load Drive With the OPA191

Table 8-2. OPA191 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated

and Measured Results

PARAMETER

Capacitive Load

Phase Margin

R_ISO(Ω)

VALUE

100 pF

45°

1000 pF

0.01 µF

0.1 µF

1 µF

45°

60°

45°

60°

45°

60°

45°

60°

280

113

432

68

210

17.8

53.6

3.6

10

Measured

Overshoot (%)

23

8

23

8

23

8

23

8

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8.3.6 Common-Mode Voltage Range

The OPAx191 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that

extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel

and P-channel differential input pairs, as shown in Figure 8-8. The N-channel pair is active for input voltages

close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active

for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition

region, typically ( V+) –3 V to (V+) – 1.5 V in which both input pairs are active. This transition region varies

modestly with process variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD

performance are degraded compared to operation outside this region.

+Vsupply

IS1

VINœ

PCH1

NCH4

NCH3

PCH2

VIN+

e-Trim^TMIntegrated Circuit

FUSE BANK

VOS TRIM VOS DRIFT TRIM

œVsupply

Figure 8-8. Rail-to-Rail Input Stage

To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when

possible. The OPAx191 uses a precision trim for both the N-channel and P-channel regions. This technique

enables significantly lower levels of offset than previous-generation devices, causing variance in the transition

region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown

in Figure 8-9.

P-Channel

Region

Transition

Region

N-Channel

Region

P-Channel

Region

Transition

Region

N-Channel

Region

200

100

200

100

0

œ100

œ200

œ300

OPAx191 e-trim™ Operational Amplifier

Input Offset Voltage vs Vcm

œ200

œ300

Input Offset Voltage vs Vcm

Without e-trim™ Integrated Circuit

œ15.0 œ14.0

…

11.0

12.0

Common-Mode Voltage (V)

13.0

14.0

15.0

œ15.0 œ14.0

…

11.0

12.0

Common-Mode Voltage (V)

13.0

14.0

15.0

Figure 8-9. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers

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8.3.7 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress

(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even

the output pin. Each of these different pin functions have electrical stress limits determined by the voltage

breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to

the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them

from accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. See Figure 8-10 for an illustration of the ESD circuits contained in the OPAx191 (indicated by the dashed

line area). The ESD protection circuitry involves several current-steering diodes connected from the input and

output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device

or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain

inactive during normal circuit operation.

TVS

R_F

+V_S

V_DD

OPAx191

100 Ω

R₁

R_S

INœ

œ

IN+

+

Power-Supply

ESD Cell

R_L

I_D

+

V_IN

œ

V_SS

œV_S

TVS

Figure 8-10. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

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An ESD event is very high voltage for a very short duration (for example, 1 kV for 100 ns); whereas, an EOS

event is lower voltage for a longer duration (for example, 50 V for 100 ms). The ESD diodes are designed for

out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to

the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption

circuit labeled ESD power-supply circuit. The ESD absorption circuit clamps the supplies to a safe level.

Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if

activated in-circuit. A transient voltage suppressor (TVS) can be used to prevent against damage caused by

turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting

resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

8.3.8 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to

a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds

the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the

saturation region, the charge carriers in the output devices require time to return back to the linear state. After

the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the

propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.

8.4 Device Functional Modes

The OPAx191 has a single functional mode and is operational when the power-supply voltage is greater than

4.5 V (±2.25 V). The maximum power supply voltage for the OPAx191 is 36 V (±18 V).

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The OPAx191 family offers outstanding dc precision and ac performance. These devices operate up to 36-V

supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as

2-MHz bandwidth and high capacitive load drive. These features make the OPAx191 a robust, high-performance

operational amplifier for high-voltage industrial applications.

9.2 Typical Applications

9.2.1 Low-side Current Measurement

Figure 9-1 shows the OPA191 configured in a low-side current sensing application. For a full analysis of the

circuit shown in Figure 9-1 including theory, calculations, simulations, and measured data, see TI Precision

Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution .

V_CC

5 V

LOAD

OPA191

+

V_OUT

œ

R_SHUNT

I_LOAD

100 mꢀ

LM7705

R_F

360 kꢀ

R_G

7.5 kꢀ

Figure 9-1. OPA191 in a Low-Side, Current-Sensing Application

9.2.1.1 Design Requirements

The design requirements for this design are:

•

Load current: 0 A to 1 A

Output voltage: 4.9 V

Maximum shunt voltage: 100 mV

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9.2.1.2 Detailed Design Procedure

The transfer function of the circuit in Figure 9-1 is given in Equation 2

V_OUT= I_LOADìR_SHUNTìGain

(2)

The load current (I_LOAD) produces a voltage drop across the shunt resistor (R_SHUNT). The load current is set

from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is

defined using Equation 3.

V_{SHUNT _MAX}

100mV

1A

R_SHUNT

=

=100mW

I_{LOAD_MAX}

(3)

Using Equation 3, R_SHUNTis calculated to be 100 mΩ. The voltage drop produced by I_LOADand R_SHUNTis

amplified by the OPA191 to produce an output voltage of 0 V to 4.9 V. The gain needed by the OPA191 to

produce the necessary output voltage is calculated using Equation 4:

V

_{OUT _MAX}- V_{OUT _MIN}

(

)

Gain =

V_{IN_MAX}- V

(

)

IN_MIN

(4)

Using Equation 4, the required gain is calculated to be 49 V/V, which is set with resistors R_Fand R_G. Equation 5

is used to size the resistors, R_Fand R_G, to set the gain of the OPA191 to 49 V/V.

R

(

)

F

Gain = 1+

R

G

(5)

Choosing R_Fas 360 kΩ, R_Gis calculated to be 7.5 kΩ. R_Fand R_Gwere chosen as 360 kΩ and 7.5 kΩ because

they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be

used. Figure 2 shows the measured transfer function of the circuit shown in Figure 9-1.

9.2.1.3 Application Curves

5

4

3

2

1

0

0.1

0.08

0.06

0.04

0.02

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I_LOAD(A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I_LOAD(A)

1

Figure 9-2. Low-Side, Current-Sense, Transfer

Function

Figure 9-3. Low-Side, Current-Sense, Full-Scale

Error

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9.2.2 16-Bit Precision Multiplexed Data-Acquisition System

Figure 9-4 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical

in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the

ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR), analog-to-digital converter (ADC), along

with a precision, high-voltage, signal-conditioning front-end, and a 4-channel differential multiplexer (mux). This

application example shows the process for optimizing the precision, high-voltage, front-end drive circuit using the

OPA191 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. The full design

can be found in TI Precision Design TIPD151, 16-Bit, 400-kSPS, Four-Channel MUX Data Acquisition System

for High-Voltage Inputs.

1

2

3

4

High-Impedance Inputs

No Differential Input Clamps

Fast Settling-Time Requirements

Attenuate High-Voltage Input Signal

Fast-Settling Time Requirements

Stability of the Input Driver

Attenuate ADC Kickback Noise

V_REFOutput: Value and Accuracy

Low Temp and Long-Term Drift

Very Low Output Impedance

Input-Filter Bandwidth

Voltage

Reference

CH0+

CH0-

RC Filter

Buffer

RC Filter

+

20-V,

10-kHz

Sine Wave

OPA191

Reference Driver

Gain

Network

Gain

Network

OPA191

+

4:2

Mux

REFP

+

OPA140

V_INP

Gain

Network

CH3+

+

OPA191

Antialiasing

Filter

SAR

ADC

+

20-V,

10-kHz

Sine Wave

OPA191

V_INM

CH3-

n

CONV

16 Bits

400 kSPS

High-Voltage Level Translation

High-Voltage Multiplexed Input

VCM

Voltage

Divider

REF3240

OPA350

Shmidtt

Trigger

VCM Generation Circuit

Counter

Delay

n

Digital Counter For Multiplexer

5

Fast logic transition

Figure 9-4. OPA191 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage

Inputs With Lowest Distortion

9.2.2.1 Design Requirements

The primary objective is to design a ±20-V, differential, 4-channel, multiplexed, data acquisition system with

lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure sine-wave

input. The design requirements for this block design are:

•

System supply voltage: ±15 V

ADC supply voltage: 3.3 V

ADC sampling rate: 400 kSPS

ADC reference voltage (REFP): 4.096 V

System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency (f_IN)

of 10 kHz are applied to each differential input of the mux.

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9.2.2.2 Detailed Design Procedure

The purpose of this application example is to design an optimal, high-voltage, multiplexed, data-acquisition

system for highest system linearity and fast settling. The overall system block diagram is shown in Figure 9-4.

The circuit is a multichannel, data-acquisition, signal chain consisting of an input low-pass filter, multiplexer

(mux), mux output buffer, attenuating SAR ADC driver, digital counter for the mux, and the reference driver. The

architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two

primary design considerations to maximize the performance of a precision, multiplexed, data-acquisition system

are the mux input analog front-end and the high-voltage, level translation, SAR ADC driver design. However,

carefully design each analog circuit block based on the ADC performance specifications in order to achieve

the fastest settling at 16-bit resolution and lowest distortion system. Figure 9-4 includes the most important

specifications for each individual analog block.

This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input

stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the

design is to understand the requirement for an extremely-low-impedance input-filter design for the mux. This

understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system

settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to

level translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability.

Then, the next step is to design a digital interface to switch the mux input channels with minimum delay. The final

design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference

voltage with low offset, drift, and noise contributions.

9.2.3 Slew Rate Limit for Input Protection

In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.

By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and

down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one

additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high

output current and slew rate of the OPAx191 make the device an optimal amplifier to achieve slew rate control

for both dual-supply and single-supply systems. Figure 9-5 shows the OPA191 in a slew-rate limit design. For

step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results,

refer to TI Precision Design TIPD140, Single Op-Amp Slew Rate Limiter..

Op Amp Gain Stage

Slew Rate Limiter

C1

R1

V_CC

-

R2

-

OPA191

+

V_IN

OPA191

V_OUT

+

V_EE

R_L

V_EE

Figure 9-5. Slew Rate Limiter Uses One Op Amp

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10 Power Supply Recommendations

The OPAx191 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –

40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature

are presented in Section 6.9.

CAUTION

Supply voltages larger than 40 V can permanently damage the device; see Section 6.1.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or

high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close

to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply

applications.

– Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources

local to the analog circuitry.

•

Make sure to physically separate digital and analog grounds paying attention to the flow of the ground

current. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-

effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to

ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. For more detailed

information, refer to Circuit Board Layout Techniques.

In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as

opposed to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As shown in Figure 11-2, keeping RF and

RG close to the inverting input minimizes parasitic capacitance.

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

•

Clean the PCB following board assembly for best performance.

Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced

into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30

minutes is sufficient for most circumstances.

Submit Document Feedback

35

Product Folder Links: OPA191 OPA2191 OPA4191

OPA191, OPA2191, OPA4191

SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021

www.ti.com

11.2 Layout Example

VIN

+

VOUT

RG

RF

Figure 11-1. Schematic Representation

Place components close

to device and to each

other to reduce parasitic

errors

Run the input traces

as far away from

the supply lines

as possible

VS+

RF

NC

Use a low-ESR,

ceramic bypass

capacitor

RG

GND

œIN

+IN

Vœ

V+

OUTPUT

NC

VIN

GND

VSœ

VOUT

Ground (GND) plane on another layer

Use low-ESR,

ceramic bypass

capacitor

Figure 11-2. Operational Amplifier Board Layout for Noninverting Configuration

36

Submit Document Feedback

Product Folder Links: OPA191 OPA2191 OPA4191

OPA191, OPA2191, OPA4191

SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021

www.ti.com

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 TINA-TI™ SImulation Software (Free Download)

TINA^™is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI

simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro

models in addition to a range of both passive and active models. TINA-TI simulation software provides all the

conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive

post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer

the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic

quick-start tool.

Note

These files require that either the TINA software (from DesignSoft^™) or TINA-TI software be installed.

Download the free TINA-TI software from the TINA-TI folder at http://www.ti.com/tool/tina-ti.

12.1.1.2 TI Precision Designs

TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/, are analog solutions

created by TI’s precision analog applications experts and offer the theory of operation, component selection,

simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful

circuits.

12.2 Documentation Support

12.2.1 Related Documentation

•

Texas Instruments, Circuit Board Layout Techniques

Texas Instruments, Op Amps for Everyone design reference

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

Submit Document Feedback

37

Product Folder Links: OPA191 OPA2191 OPA4191

OPA191, OPA2191, OPA4191

SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021

www.ti.com

12.5 Trademarks

e-trim^™and TI E2E^™are trademarks of Texas Instruments.

TINA^™and DesignSoft^™are trademarks of DesignSoft, Inc.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

38

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Product Folder Links: OPA191 OPA2191 OPA4191

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Aug-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OPA191IDBVR

OPA191IDBVT

OPA191IDGKR

OPA191IDGKT

OPA191IDR

SOT-23

VSSOP

SOIC

DBV

DGK

D

5

3000

250

180.0

330.0

177.8

330.0

180.0

330.0

180.0

330.0

180.0

8.4

3.23

5.3

3.17

3.4

1.37

1.4

4.0

8.0

Q3

Q1

Q2

8.4

8.0

8

2500

250

12.4

16.4

12.4

12.0

16.0

12.0

8

5.3

3.4

1.4

8

2500

250

6.4

5.2

2.1

OPA2191IDGKR

OPA2191IDGKT

OPA2191IDR

VSSOP

SOIC

DGK

D

8

5.3

3.4

1.4

8

5.3

3.4

1.4

8

2500

250

6.4

5.2

2.1

OPA4191IDR

SOIC

D

14

16

6.5

9.0

2.1

OPA4191IPWT

OPA4191IRUMR

OPA4191IRUMT

TSSOP

WQFN

PW

RUM

6.9

5.6

1.6

3000

250

4.25

1.15

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Aug-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

OPA191IDBVR

OPA191IDBVT

OPA191IDGKR

OPA191IDGKT

OPA191IDR

SOT-23

VSSOP

SOIC

DBV

DGK

D

5

3000

250

213.0

223.0

346.0

213.0

853.0

210.0

853.0

210.0

367.0

210.0

191.0

270.0

346.0

191.0

449.0

185.0

449.0

185.0

367.0

185.0

35.0

29.0

35.0

8

2500

250

8

2500

250

OPA2191IDGKR

OPA2191IDGKT

OPA2191IDR

VSSOP

SOIC

DGK

D

8

2500

250

OPA4191IDR

SOIC

D

14

16

OPA4191IPWT

OPA4191IRUMR

OPA4191IRUMT

TSSOP

WQFN

PW

RUM

3000

250

Pack Materials-Page 2

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

S

C

A

L

E

4

.

0

SMALL OUTLINE TRANSISTOR

C

3.0

2.6

0.1 C

1.75

1.45

0.90

B

A

PIN 1

INDEX AREA

1

2

5

2X 0.95

1.9

3.05

2.75

1.9

4

3

0.5

5X

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

0.25

GAGE PLANE

0.22

0.08

TYP

8

0

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X (0.95)

4

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X(0.95)

4

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

RUM 16

4 x 4, 0.65 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224843/A

www.ti.com

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	OPA4191IRUMR
厂家：	TEXAS INSTRUMENTS
描述：	具有 RRIO 的四路低功耗 36V 精密 e-trim 放大器 \| RUM \| 16 \| -40 to 125 放大器
文件：	总59页 (文件大小：5063K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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