OPA4196ID [TI]
具有多路复用器友好型输入的四路、36V、低功耗通用放大器 | D | 14 | -40 to 125;
| 型号： | OPA4196ID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有多路复用器友好型输入的四路、36V、低功耗通用放大器 | D | 14 | -40 to 125 放大器 复用器 |
| 文件： | 总47页 (文件大小：3184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
OPAx196 36V 低功耗、低偏移电压、轨至轨运算放大器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
•
•
•
低偏移电压：±100µV（最大值）
OPAx196 系列（OPA196、OPA2196 和 OPA4196）
是新一代 36V 轨至轨 e-trim™运算放大器。
低偏移电压漂移：±0.5µV/°C（典型值）
低偏置电流：±5pA（典型值）
高共模抑制：140dB
这些器件在整个输出范围内提供非常低的偏移电压（典
型值为 ±25μV）、漂移（典型值为 ±0.5μV/°C）和低
偏置电流（典型值为 ±5pA），同时还具有非常低的静
态电流（典型值为 140μA/通道）。
低噪声：1kHz 时为 15nV/√Hz
轨至轨输入和输出
可提供电源轨的差分输入电压范围
高带宽：2.5MHz GBW
OPAx196 拥有诸多独一无二的特性，例如可提供电源
轨的差分输入电压范围、高输出电流 (±65mA) 以及高
达 1nF 的高电容负载驱动能力，是稳健耐用的高性能
运算放大器，适用于各种高电压工业 应用。
低静态电流：每个放大器为 140µA（典型值）
宽电源范围：±2.25V 至 ±18V，4.5V 至 36V
已过滤电磁干扰 (EMI)/射频干扰 (RFI) 的输入
高电容负载驱动能力：1nF
OPAx196 系列运算放大器采用标准封装，在 -40°C 至
+125°C 的额定温度范围内工作。
行业标准封装：
–
–
–
SOIC-8、SOT-5 和 VSSOP-8 单体封装
SOIC-8 和 VSSOP-8 双列封装
器件信息(1)
器件型号
封装
SOIC (8)
封装尺寸（标称值）
SOIC-14、TSSOP-14 和 QFN-16 四列封装
4.90mm × 3.90mm
小外形尺寸晶体管
(SOT) (5)
2 应用
OPA196
2.90mm x 1.60mm
•
•
•
•
•
•
•
•
多路复用数据采集系统
VSSOP (8)
SOIC (8)
3.00mm × 3.00mm
4.90mm × 3.90mm
3.00mm × 3.00mm
8.65mm x 3.90mm
5.00mm x 4.40mm
测试和测量设备
OPA2196
OPA4196
VSSOP (8)
SOIC (14)
TSSOP (14)
高分辨率模数转换器 (ADC) 驱动器放大器
SAR ADC 基准缓冲器
模拟输入和输出模块
高侧和低侧电流感应
高精度比较器
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
医疗仪器
OPA196 应用于高压多路复用数据采集系统
Analog
Inputs
RC
RC
REF3140
Filter
Filter
Bridge
Sensor
OPA625
OPA196
Gain
Gain
+
4:2
HV
Thermocouple
MUX
REF
+
OPA196
+
VINP
ADS8864
VINM
Antialiasing
Filter
OPA196
Gain
Current Sensing
Reference
Driver
High-Voltage Multiplexed
Input
High-Voltage Level
Translation
VCM
Optical Sensor
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS869
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
目录
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 26
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
Power-Supply Recommendations...................... 31
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information: OPA196 .................................. 5
6.5 Thermal Information: OPA2196 ................................ 6
6.6 Thermal Information: OPA4196 ................................ 6
8
9
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
11 器件和文档支持 ..................................................... 33
11.1 器件支持................................................................ 33
11.2 文档支持................................................................ 33
11.3 相关链接................................................................ 33
11.4 接收文档更新通知 ................................................. 33
11.5 社区资源................................................................ 34
11.6 商标....................................................................... 34
11.7 静电放电警告......................................................... 34
11.8 Glossary................................................................ 34
12 机械、封装和可订购信息....................................... 34
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8
V to 36 V)................................................................... 7
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS
=
4.5 V to 8 V)............................................................... 9
6.9 Typical Characteristics............................................ 11
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注意
2017 年 7 月
*
最初发布版本
2
Copyright © 2017, Texas Instruments Incorporated
OPA196, OPA2196, OPA4196
www.ti.com.cn
ZHCSGE9 –JULY 2017
5 Pin Configuration and Functions
DBV Package: OPA196
5-Pin SOT
D and DGK Packages: OPA2196
8-Pin SOIC and VSSOP
Top View
Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT
Vœ
1
2
3
5
V+
OUT B
œIN B
+IN B
+IN
4
œIN
Not to scale
Not to scale
D and DGK Packages: OPA196
8-Pin SOIC and VSSOP
Top View
D and PW Packages: OPA4196
14-Pin SOIC and TSSOP
Top View
NC
œIN
+IN
Vœ
1
2
3
4
8
7
6
5
NC
OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
V+
œ
OUT
NC
+
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
Not to scale
8
Not to scale
(1) NC = No internal connection.
Copyright © 2017, Texas Instruments Incorporated
3
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
Pin Functions: OPA196
PIN
OPA196
I/O
DESCRIPTION
NAME
D (SOIC),
DGK (VSSOP)
DBV (SOT)
+IN
–IN
NC
OUT
V+
3
3
4
I
Noninverting input
Inverting input
2
I
1, 5, 8
—
1
—
O
—
—
No internal connection (can be left floating)
Output
6
7
4
5
Positive (highest) power supply
Negative (lowest) power supply
V–
2
Pin Functions: OPA2196 and OPA4196
PIN
OPA2196
OPA4196
I/O
DESCRIPTION
NAME
D (SOIC),
D (SOIC),
DGK (VSSOP)
PW (TSSOP)
+IN A
+IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
3
5
3
5
I
I
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input,,channel C
Inverting input, channel D
Output, channel A
—
—
2
10
12
2
I
I
I
6
6
I
—
—
1
9
I
13
1
I
O
O
O
O
—
—
7
7
Output, channel B
—
—
8
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
V–
4
11
4
Copyright © 2017, Texas Instruments Incorporated
OPA196, OPA2196, OPA4196
www.ti.com.cn
ZHCSGE9 –JULY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
±20
Supply voltage, VS = (V+) – (V–)
V
(+40, single supply)
Common-mode
Voltage
(V–) – 0.5
(V+) + 0.5
(V+) – (V–) + 0.2
±10
V
Signal input pins
Output short circuit(2)
Temperature
Differential
Current
mA
Continuous
–40
Continuous
150
Continuous
Operating
Junction
150
°C
Storage, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Electrostatic
discharge
V(ESD)
OPAx196
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
V
OPA196
OPA2196
OPA4196
±1000
±500
±500
V
V
V
Electrostatic
discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
V(ESD)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5 (±2.25)
–40
NOM
MAX
UNIT
Supply voltage, VS = (V+) – (V–)
Specified temperature
36 (±18)
125
V
°C
6.4 Thermal Information: OPA196
OPA196
DGK
(VSSOP)
180.4
67.9
8 PINS
5 PINS
THERMAL METRIC(1)
UNIT
D (SOIC)
DBV (SOT)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
115.8
60.1
56.4
12.8
55.9
N/A
158.8
60.7
44.8
1.6
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
102.1
10.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
100.3
N/A
4.2
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
5
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
6.5 Thermal Information: OPA2196
OPA2196
8 PINS
THERMAL METRIC(1)
UNIT
D (SOIC)
107.9
53.9
DGK (VSSOP)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
158
48.6
78.7
3.9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
48.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
6.6
ψJB
48.3
77.3
N/A
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4196
OPA4196
THERMAL METRIC(1)
14 PINS
UNIT
D (SOIC)
86.4
PW (TSSOP)
92.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
46.3
27.5
41.0
33.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
11.3
1.9
ψJB
40.7
33.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2017, Texas Instruments Incorporated
OPA196, OPA2196, OPA4196
www.ti.com.cn
ZHCSGE9 –JULY 2017
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±18 V
±25
±100
µV
(V+) – 3.0 V < VCM < (V+) – 1.5 V
See Common-Mode Voltage Range
VS = ±18 V,
VCM = (V+) – 1.5 V
±25
±100
VS = ±18 V, VCM = (V+) – 3 V
VS = ±18 V, VCM = (V+) – 1.5 V
±0.5
±0.8
dVOS/dT
PSRR
Input offset voltage drift
TA = –40°C to +125°C
µV/°C
µV/V
Power-supply rejection
ratio
TA = –40°C to +125°C
±0.3
±1
INPUT BIAS CURRENT
IB
Input bias current
±5
±2
±20
±20
pA
pA
IOS
Input offset current
NOISE
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 100 Hz
1.4
7
En
Input voltage noise
µVPP
18
15
53
24
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 1 kHz
Input voltage noise
density
en
nV/√Hz
f = 100 Hz
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 1 kHz
f = 1 kHz
Input current noise
density
in
1.5
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
120
(V+) + 0.1
V
VS = ±18 V,
(V–) – 0.1 V < VCM < (V+) – 3 V
140
126
VS = ±18 V,
(V–) < VCM < (V+) – 3 V
TA = –40°C to +125°C
TA = –40°C to +125°C
114
Common-mode
rejection ratio
CMRR
dB
96
86
120
100
VS = ±18 V,
(V+) – 1.5 V < VCM < (V+)
(V+) – 3 V < VCM < (V+) – 1.5 V
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
100 || 1.6
1 || 6.4
MΩ || pF
1013Ω ||
pF
ZIC
Common-mode
OPEN-LOOP GAIN
VS = ±18 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
124
114
126
120
134
126
140
134
TA = –40°C to +125°C
TA = –40°C to +125°C
AOL
Open-loop voltage gain
dB
VS = ±18 V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
Copyright © 2017, Texas Instruments Incorporated
7
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
2.5
7.5
5.5
0.7
1
MHz
V/µs
Rising
SR
Slew rate
VS = ±18 V, G = 1, 10-V step
Falling
VS = ±18 V, G = 1, 2-V step
VS = ±18 V, G = 1, 5-V step
VS = ±18 V, G = 1, 2-V step
VS = ±18 V, G = 1, 5-V step
From overload to negative rail
From overload to positive rail
To 0.01%, CL = 20 pF
To 0.001%, CL = 20 pF
ts
Settling time
µs
µs
1.8
3.7
0.4
1
tOR
Overload recovery time VIN × G = VS
Total harmonic
THD+N
G = 1, f = 1 kHz, VO = 3.5 VRMS
0.0012%
distortion + noise
OPA2196 and OPA4196, at dc
150
130
dB
dB
Crosstalk
OPA2196 and OPA4196, f = 100 kHz
OUTPUT
No load
5
50
15
110
500
15
Positive rail
RL = 10 kΩ
RL = 2 kΩ
No load
200
5
Voltage output swing
from rail
VO
mV
Negative rail
VS = ±18 V
RL = 10 kΩ
RL = 2 kΩ
50
110
500
200
±65
ISC
CL
Short-circuit current
Capacitive load drive
mA
See Typical Characteristics
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A, See Figure 19
700
Ω
POWER SUPPLY
140
200
250
Quiescent current per
IQ
IO = 0 A
µA
amplifier
TEMPERATURE
Thermal protection
Thermal hysteresis
TA = –40°C to +125°C
180
30
°C
°C
8
Copyright © 2017, Texas Instruments Incorporated
OPA196, OPA2196, OPA4196
www.ti.com.cn
ZHCSGE9 –JULY 2017
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = ±2.25V,
VCM = (V+) – 3 V
VOS
Input offset voltage
±25
±100
µV
(V+) – 3.0 V < VCM < (V+) – 1.5 V
See Common-Mode Voltage Range
VS = ±3V,
VCM = (V+) – 1.5 V
±25
±100
VS = ±2.25V, VCM = (V+) – 3 V
VS = ±2.25V, VCM = (V+) – 1.5 V
±0.5
±0.5
dVOS/dT
PSRR
Input offset voltage drift
TA = –40°C to +125°C
µV/°C
µV/V
Power-supply rejection
ratio
TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V
±1
INPUT BIAS CURRENT
IB
Input bias current
±5
±2
±20
±20
pA
pA
IOS
Input offset current
NOISE
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
1.4
7
En
Input voltage noise
µVPP
f = 0.1 Hz to 10 Hz
f = 100 Hz
f = 1 kHz
18
15
53
24
1.5
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
en
Input voltage noise density
Input current noise density
nV/√Hz
f = 100 Hz
f = 1 kHz
in
INPUT VOLTAGE
f = 1 kHz
fA/√Hz
Common-mode voltage
range
VCM
(V–) – 0.1
(V+) + 0.1
V
VS = ±2.25 V,
(V–) – 0.1 V < VCM < (V+) – 3 V
96
90
110
104
VS = ±2.25 V,
(V–) < VCM < (V+) – 3 V
TA = –40°C to +125°C
TA = –40°C to +125°C
Common-mode rejection
ratio
CMRR
dB
96
84
120
100
VS = ±2.25 V,
(V+) – 1.5 V < VCM < (V+)
(V+) – 3 V < VCM < (V+) – 1.5 V
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
100 || 1.6
1 || 6.4
MΩ || pF
1013Ω ||
pF
ZIC
Common-mode
OPEN-LOOP GAIN
VS = ±2.25V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
110
100
110
106
120
114
126
120
TA = –40°C to +125°C
TA = –40°C to +125°C
AOL
Open-loop voltage gain
dB
VS = ±2.25V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
Copyright © 2017, Texas Instruments Incorporated
9
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
2.2
6.5
5.5
0.4
1
MHz
V/µs
Rising
SR
Slew rate
VS = ±2.25V, G = 1, 1-V step
Falling
From overload to negative rail
From overload to positive rail
tOR
Overload recovery time
Crosstalk
VIN × G = VS
µs
OPA2196 and OPA4196, at dc
150
130
dB
dB
OPA2196 and OPA4196, f = 100 kHz
OUTPUT
No load
5
15
60
5
15
110
500
15
Positive rail
RL = 10 kΩ
RL = 2 kΩ
No load
Voltage output swing from
rail
VO
mV
Negative rail
VS = ±2.25V
RL = 10 kΩ
RL = 2 kΩ
15
60
±30
110
500
ISC
CL
Short-circuit current
Capacitive load drive
mA
See Typical Characteristics
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A, see Figure 19
700
Ω
POWER SUPPLY
140
200
250
Quiescent current per
IQ
IO = 0 A
µA
amplifier
TEMPERATURE
Thermal protection
Thermal hysteresis
TA = –40°C to +125°C
180
30
°C
°C
10
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6.9 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Offset Voltage vs Common-Mode Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain and Phase vs Frequency
Input Bias Current vs Common-Mode Voltage
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (maximum supply)
CMRR and PSRR vs Frequency
CMRR vs Temperature
Figure 6, Figure 7
Figure 8
Figure 9
PSRR vs Temperature
Figure 10
0.1-Hz to 10-Hz Noise
Figure 11
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
Figure 12
Figure 13
THD+N vs Output Amplitude
Figure 14
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open Loop Gain vs Temperature
Open Loop Output Impedance vs Frequency
Small Signal Overshoot vs Capacitive Load (100-mV output step)
No Phase Reversal
Figure 15
Figure 16
Figure 17, Figure 18
Figure 19
Figure 20, Figure 21
Figure 22
Overload Recovery
Figure 23
Small-Signal Step Response (100 mV)
Large-Signal Step Response
Figure 24, Figure 25
Figure 26, Figure 27
Figure 28, Figure 29, Figure 30, Figure 31
Figure 32
Settling Time
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Propagation Delay Rising Edge
Figure 33
Figure 34
Propagation Delay Falling Edge
Figure 35
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
25
160
180
135
90
140
Open-loop Gain
15
5
120
100
80
Phase
VCM = œ18.1 V
45
60
0
œ5
40
20
-45
-90
-135
œ15
œ25
0
œ20
œ40
0
5
10
15
œ20
œ15
œ10
œ5
0.1
1.0 10.0 100.0 1k
10k 100k 1M 10M 100M
Common Mode Voltage (V)
Frequency (Hz)
C001
C001
Figure 1. Offset Voltage vs Common-Mode Voltage
Figure 2. Open-Loop Gain and Phase vs Frequency
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
1000
60
G = -1
800
G = +1
600
40
G= -10
400
200
G= -100
0
20
0
œ200
œ400
œ600
œ800
œ1000
-20
100
1k
10k
100k
1M
10M
100M
0
5
10
15
20
œ20
œ15
œ10
œ5
Frequency (Hz)
Common Mode Voltage (V)
C004
C001
Figure 3. Closed-Loop Gain vs Frequency
Figure 4. Input Bias Current vs Common-Mode Voltage
20
18
16
14
12
10
8
10
IB -
IB+
9
8
7
6
5
4
3
2
1
0
6
-40èC
4
25èC
85èC
2
125èC
0
0
25
50
75
100 125 150
œ75 œ50 œ25
0
20
40
60
80
100
Output Current (mA)
Temperature (°C)
C001
Sourcing
Figure 6. Output Voltage Swing vs Output Current
Figure 5. Input Bias Current vs Temperature
0
-2
140
120
100
80
-40èC
25èC
85èC
-4
125èC
-6
-8
-10
-12
-14
-16
-18
-20
60
40
CMRR
+PSRR
œPSRR
20
0
0.1
1.0
10.0 100.0
1k
10k 100k
1M
10M
0
20
40
60
80
100
Frequency (Hz)
Output Current (mA)
C004
Sinking
Figure 8. CMRR and PSRR vs Frequency
Figure 7. Output Voltage Swing vs Output Current
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
10
5
VS = ±2.25 V, (Vœ) ≤ VCM ≤ (V+) œ 3 V
8
4
6
3
4
2
2
1
0
0
-2
-4
-6
-8
-10
-1
-2
-3
-4
-5
VS = ±18 V, (Vœ) ≤ VCM ≤ (V+) œ 3 V
0
25
50
75
100 125 150
0
25
50
75
100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
Figure 9. CMRR vs Temperature
Figure 10. PSRR vs Temperature
100
10
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
C002
Time (1 s/div)
Figure 12. Input Voltage Noise Spectral Density
vs Frequency
Figure 11. 0.1-Hz to 10-Hz Noise
0.5
0.1
1
-40
G = -1, 2k-ꢀ Load
G = -1, 10k-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 10k-ꢀ Load
G = -1 V/V, RL = 2 kW
G = -1 V/V, RL = 10 kW
G = 1 V/V, RL = 2 kW
G = 1 V/V, RL = 10 kW
0.1
0.01
-60
-80
0.01
0.001
-100
-120
-140
0.0001
0.00001
0.001
0.0005
20
200
2k
20k
0.01
0.1
1
10 20
Output Amplitude (VRMS
)
Frequency (Hz)
C004
Figure 14. THD+N vs Output Amplitude
Figure 13. THD+N vs Frequency
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
200
180
160
140
120
100
80
200
180
160
140
120
100
80
VS = ê2.25 V
VS = ê18 V
VS = ±18 V
VS = ±2.25 V
60
60
40
40
20
20
0
0
0
25
50
75
100 125 150
œ75 œ50 œ25
0
2
4
6
8
10
12
14
16
18
20
Supply Voltage (V)
Temperature (°C)
C001
Figure 15. Quiescent Current vs Supply Voltage
Figure 16. Quiescent Current vs Temperature
5.0
4.0
5.0
4.0
3.0
3.0
VS = ±2.25 V
2.0
2.0
VS = ±2.25 V
1.0
1.0
0.0
0.0
œ1.0
œ2.0
œ3.0
œ4.0
œ5.0
œ1.0
œ2.0
œ3.0
œ4.0
œ5.0
VS = ±18 V
VS = ±18 V
0
25
50
75
100 125 150
0
25
50
75
100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
RL = 10 kΩ
Figure 17. Open-Loop Gain vs Temperature
RL = 2 kΩ
Figure 18. Open-Loop Gain vs Temperature
100k
60
RISO = 0
RISO = 25
RISO = 50
50
40
30
20
10
0
10k
1k
100
100m
10
100
1000
1
10
100
1k
10k
100k
1M
10M
Capacitive Load (pF)
G = –1, 100-mV output step
C004
Frequency (Hz)
Figure 20. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 19. Open-Loop Output Impedance vs Frequency
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
20
Output
Input
RISO = 0
RISO = 25
RISO = 50
10
0
10
100
1000
Capacitive Load (pF)
G = 1, 100-mV output step
Time (50 ms/div)
C004
Figure 21. Small-Signal Overshoot vs Capacitive Load
Figure 22. No Phase Reversal
Negative overload
Positive overload
Time (2.5 µs/div)
C017
Time (ms)
G = 1, CL = 10 pF
VS = ±18 V, G = –10 V/V
Figure 24. Small-Signal Step Response
Figure 23. Overload Recovery
Time (2.5 µs/div)
Time (2.5 µs/div)
C017
C017
G = –1, RL = 1 kΩ, CL = 10 pF
G = 1, CL = 10 pF
Figure 25. Small-Signal Step Response
Figure 26. Large-Signal Step Response
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
0.01% settling = ê200 mV
Time (2.5 µs/div)
Time (500 ns/div)
C017
Gain = 1, 2-V step, rising, step applied at t = 0 µs on all four plots
G = –1, RL = 1 kΩ, CL = 10 pF
Figure 28. 0.01% Settling Time
Figure 27. Large-Signal Step Response
0.01% settling = ê200 mV
0.01% settling = ê500 mV
Time (500 ns/div)
Time (500 ns/div)
Gain = 1, 5-V step, rising, step applied at t = 0 µs
Gain = 1, 2-V step, falling, step applied at t = 0 µs
Figure 29. 0.01% Settling Time
0.01% settling = ê500 mV
Figure 30. 0.01% Settling Time
100
ISC, Source
80
60
40
20
0
ISC, Sink
0
25
50
75
100 125 150
œ75 œ50 œ25
Temperature (°C)
C001
Time (500 ns/div)
Gain = 1, 5-V step, falling, step applied at t = 0 µs
Figure 32. Short-Circuit Current vs Temperature
Figure 31. 0.01% Settling Time
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
35
Maximum output voltage without
slew-rate induced distortion.
30
25
20
15
10
5
Overdrive = 100 mV
VS = ±15 V
tpLH = 26 µs
VOUT Voltage
VS = ±4 V
VS = ±2.25 V
1k
0
Time (10 µs/div)
100
10k
100k
1M
10M
Frequency (Hz)
C001
C017
Figure 33. Maximum Output Voltage vs Frequency
Figure 34. Propagation Delay Rising Edge
tpHL = 26 µs
VOUT Voltage
Overdrive = 100 mV
Time (10 µs/div)
C017
Figure 35. Propagation Delay Falling Edge
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7 Detailed Description
7.1 Overview
The OPAx196 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset
temperature drift implemented during the final steps of manufacturing after the plastic molding process. This
method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package
molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are
set, further communication to the trim structure is permanently disabled. The Functional Block Diagram shows
the simplified diagram of the OPA196 with e-trim.
Unlike previous e-trim op amps, the OPAx196 uses a patented two-temperature trim architecture to achieve a
very low offset voltage and low voltage offset drift over the full specified temperature range. This level of
precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial
sensors, filters, and high-voltage data acquisition.
7.2 Functional Block Diagram
OPAx196
NCH Input
Stage
IN+
High
Capacitive Load
Compensation
VOUT
36-V
Differential
Front End
Output
Stage
Slew
Boost
IN-
PCH Input
Stage
e-trim
Package Level Trim
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The OPAx196 uses a unique input architecture to eliminate the need for input protection diodes but still provides
robust input protection under transient conditions. Conventional input diode protection schemes shown in
Figure 36 can be activated by fast transient step responses and can introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 37. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes that cause an increase in input current, resulting in extended settling
time.
V+
V+
VIN+
VIN+
VOUT
VOUT
OPAx196
~0.7 V
36 V
VIN-
VIN-
V-
V-
OPAx196 Provides Full 36-
V Differential Input Range
Conventional Input Protection
Limits Differential Input Range
Figure 36. OPA196 Input Protection Does Not Limit Differential Input Capability
1
Ron_mux
Vn = +10 V
RFILT
+10 V
Sn
D
1
2
~œ9.3 V
+10 V
CFILT
CS
CD
Vinœ
2
Ron_mux
Sn+1
Vn+1 = œ10 V RFILT
œ10 V
~0.7 V
Vout
CFILT
CS
Idiode_transient
Vin+
œ10 V
Input Low Pass Filter
Simplified Mux Model
Buffer Amplifier
Figure 37. Back-to-Back Diodes Create Settling Issues
The OPAx196 family of operational amplifiers provides a true high-impedance differential input capability for high-
voltage applications. This patented input protection architecture does not introduce additional signal distortion or
delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications.
The OPA196 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the
op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping
input signals such as multiplexed data-acquisition systems (see Figure 49).
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Feature Description (continued)
7.3.2 EMI Rejection
The OPAx196 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx196 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 38 shows the results of this testing on the OPAx196. Table 2 shows the EMIRR IN+ values for the
OPAx196 at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be
found in the application report EMI Rejection Ratio of Operational Amplifiers, available for download from
www.ti.com.
120
100
80
60
40
20
0
10
100
Frequency (MHz)
1k
10k
PRF = –10 dBm, VS = ±15 V, VCM = 0 V
Figure 38. EMIRR Testing
Table 2. OPA196 EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
36 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5.0 GHz
45 dB
57 dB
62 dB
76 dB
86 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
20
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7.3.3 Phase Reversal Protection
The OPAx196 family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx196 is a rail-to-rail input op amp, and therefore the common-mode range
can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits
into the appropriate rail. This performance is shown in Figure 39.
VIN
VOUT
Time (35 ms/div)
C017
Figure 39. No Phase Reversal
7.3.4 Thermal Protection
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This
phenomenon is called self heating. The OPAx196 has a thermal protection feature that prevents damage from
self heating.
This thermal protection works by monitoring the temperature of the output stage and turning off the op amp
output drive for temperatures above approximately 180°C. Thermal protection forces the output to a high-
impedance state. The OPAx196 is also designed with approximately 30°C of thermal hysteresis. Thermal
hysteresis prevents the output stage from cycling in and out of the high-impedance state. The OPAx196 returns
to normal operation when the output stage temperature falls below approximately 150°C.
The absolute maximum junction temperature of the OPAx196 is 150°C. Exceeding the limits shown in the
Absolute Maximum Ratings table may cause damage to the device. Thermal protection triggers at 180°C
because of unit-to-unit variance, but does not interfere with device operation up to the absolute maximum ratings.
This thermal protection is not designed to prevent this device from exceeding absolute maximum ratings, but
rather from excessive thermal overload.
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7.3.5 Capacitive Load and Stability
The OPAx196 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads; see Figure 40. The particular op amp circuit configuration, layout, gain,
and output loading are some of the factors to consider when establishing whether an amplifier will be stable in
operation.
G = +1 V/V
Time (2 ms/Div)
Figure 40. Transient Response with a Purely Capacitive Load of 1 nF
Like many low-power amplifiers, some ringing can occur even with capacitive loads less than 100 pF. In unity-
gain configurations with no or very light dc loads, place an RC snubber circuit at the OPAx196 output to reduce
any possibility of ringing in lightly-loaded applications. Figure 41 illustrates the recommended RC snubber circuit.
œ
Output
Input
+
R 619 ꢀ
C 320 pF
Figure 41. RC Snubber Circuit for Lightly-Loaded Applications in Unity Gain
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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small,
10-Ω to 20-Ω resistor (RISO) in series with the output, as shown in Figure 42. This resistor significantly reduces
ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in
parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL and is generally negligible at
low output levels. A high capacitive load drive makes the OPA196 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 42 uses RISO to stabilize the
output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin. Results using
the OPA196 are summarized in Table 3. For additional information on techniques to optimize and design using
this circuit, TI Precision Design TIDU032 details complete design goals, simulation, and test results.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
Figure 42. Extending Capacitive Load Drive With the OPA196
Table 3. OPA196 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and
Measured Results
PARAMETER
Capacitive Load
Phase Margin
RISO (Ω)
VALUE
0.01 µF
100 pF
45°
1000 pF
0.1 µF
1 µF
45°
60°
45°
60°
45°
60°
45°
60°
280
113
432
68
210
17.8
53.6
3.6
10
Measured
Overshoot (%)
23
23
8
23
8
23
8
23
8
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using
an Isolation Resistor .
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7.3.6 Common-Mode Voltage Range
The OPAx196 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 43. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition
region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are active. This transition region varies
modestly with process variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD
performance are degraded compared to operation outside this region.
+Vsupply
IS1
VIN-
PCH1
NCH4
NCH3
PCH2
VIN+
e-ÇrimÇa
CÜ{9 .!bY
ëh{ ÇwLa
ëh{ 5wLCÇ ÇwLa
-Vsupply
Figure 43. Rail-to-Rail Input Stage
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPAx196 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in
Figure 44.
P-Channel
Region
Transition
Region
N-Channel
Region
P-Channel
Region
Transition
Region
N-Channel
Region
200
100
200
100
0
0
œ100
œ100
œ200
œ300
OPAx196 e-Trim
Input Offset Voltage vs Vcm
œ200
œ300
Input Offset Voltage vs Vcm
without e-Trim Input
œ15.0 œ14.0
…
11.0
12.0
13.0
14.0
15.0
œ15.0 œ14.0
…
11.0
12.0
13.0
14.0
15.0
Common-Mode Voltage (V)
Common-Mode Voltage (V)
Figure 44. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See Figure 45 for an illustration of the ESD circuits contained in the OPAx196 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
RF
+VS
VDD
OPAx196
100 Ω
100 Ω
R1
RS
INœ
œ
IN+
+
Power-Supply
ESD Cell
RL
ID
+
VIN
œ
VSS
œVS
TVS
Figure 45. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
Copyright © 2017, Texas Instruments Incorporated
25
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
An ESD event is very high voltage for a very short duration (for example, 1 kV for 100 ns); whereas, an EOS
event is lower voltage for a longer duration (for example, 50 V for 100 ms). The ESD diodes are designed for
out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to
the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption
circuit labeled ESD power-supply circuit. The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressor (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
7.4 Device Functional Modes
The OPAx196 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx196 is 36 V (±18 V).
26
Copyright © 2017, Texas Instruments Incorporated
OPA196, OPA2196, OPA4196
www.ti.com.cn
ZHCSGE9 –JULY 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx196 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as
2-MHz bandwidth and high capacitive load drive. These features make the OPAx196 a robust, high-performance
operational amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-side Current Measurement
Figure 46 shows the OPA196 configured in a low-side current sensing application. For a full analysis of the
circuit shown in Figure 46 including theory, calculations, simulations, and measured data see the 0-1A, single-
supply, low-side, current sensing solution, see TIPD129.
VCC
5 V
LOAD
OPA196
+
VOUT
œ
RSHUNT
100m ꢀ
ILOAD
LM7705
RF
360k ꢀ
RG
7.5k ꢀ
Figure 46. OPA196 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
Copyright © 2017, Texas Instruments Incorporated
27
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 46 is given in Equation 1:
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the OPA196 to produce an output voltage of 0 V to 4.9 V. The gain needed by the OPA196 to
produce the necessary output voltage is calculated using Equation 3:
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the OPA196 to 49 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Choosing RF as 360 kΩ, RG is calculated to be 7.5 kΩ. RF and RG were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 2 shows the measured transfer function of the circuit shown in Figure 46.
8.2.1.3 Application Curves
5
4
3
2
1
0
0.1
0.08
0.06
0.04
0.02
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ILOAD (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ILOAD (A)
1
Figure 47. Low-Side, Current-Sense, Transfer Function
Figure 48. Low-Side, Current-Sense, Full-Scale Error
28
Copyright © 2017, Texas Instruments Incorporated
OPA196, OPA2196, OPA4196
www.ti.com.cn
ZHCSGE9 –JULY 2017
Typical Applications (continued)
8.2.2 16-Bit Precision Multiplexed Data-Acquisition System
Figure 49 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR), analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front-end, and a 4-channel differential multiplexer (mux). This
application example shows the process for optimizing the precision, high-voltage, front-end drive circuit using the
OPA196 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. The full TI
Precision Design can be found in TIDU181.
1
2
3
4
Attenuate ADC Kickback
Noise
VREF Output: Value and
Accuracy
Low Temp and Long-Term
Drift
High-Impedance Inputs
No Differential Input
Clamps
Fast Settling-Time
Requirements
Attenuate High-Voltage Input
Signal
Fast-Settling Time
Requirements
Stability of the Input Driver
Very Low Output
Impedance
Input-Filter Bandwidth
RC
Filter
RC
Filter
Voltage
Reference
/I0+
/I0-
.uffer
±20-V,
10-kHz
Sine
+
ht!196
Reference
Driver
+
Gain
Network
Gain
Network
Wave
ht!196
+
ht!196
4:2
aux
REFP
+
ht!140
VINP
Gain
Network
±20-V,
10-kHz
Sine
/I3+
Antialiasing
Filter
+
ht!196
SAR
ADC
+
ht!196
+
VINM
Wave
/I3-
n
CONV
ht!196
16 Bits
400 kSPS
High-Voltage Level
Translation
Iigh-ëoltage ꢀultiplexed Lnput
ë/a
Voltage
Divider
REF3240
ht!350
VCM Generation Circuit
Shmidtt
Trigger
Counter
Delay
n
Digital Counter For
Multiplexer
5
Fast logic transition
Figure 49. OPA196 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage
Inputs With Lowest Distortion
8.2.2.1 Design Requirements
The primary objective is to design a ±20-V, differential, 4-channel, multiplexed, data acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure sine-wave
input. The design requirements for this block design are:
•
•
•
•
•
System supply voltage: ±15 V
ADC supply voltage: 3.3 V
ADC sampling rate: 400 kSPS
ADC reference voltage (REFP): 4.096 V
System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
8.2.2.2 Detailed Design Procedure
The purpose of this application example is to design an optimal, high-voltage, multiplexed, data-acquisition
system for highest system linearity and fast settling. The overall system block diagram is shown in Figure 49.
The circuit is a multichannel, data-acquisition, signal chain consisting of an input low-pass filter, multiplexer
(mux), mux output buffer, attenuating SAR ADC driver, digital counter for the mux, and the reference driver. The
architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two
primary design considerations to maximize the performance of a precision, multiplexed, data-acquisition system
are the mux input analog front-end and the high-voltage, level translation, SAR ADC driver design. However,
carefully design each analog circuit block based on the ADC performance specifications in order to achieve the
fastest settling at 16-bit resolution and lowest distortion system. Figure 49 includes the most important
specifications for each individual analog block.
Copyright © 2017, Texas Instruments Incorporated
29
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
Typical Applications (continued)
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for an extremely-low-impedance input-filter design for the mux. This
understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system
settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to
level translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability.
Then, the next step is to design a digital interface to switch the mux input channels with minimum delay. The final
design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference
voltage with low offset, drift, and noise contributions.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition
System for High Voltage Inputs with Lowest Distortion.
8.2.3 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx196 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems.Figure 50 shows the OPA196 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
R1
VCC
VCC
-
R2
-
OPA196
+
VIN
OPA196
VOUT
+
VEE
RL
VEE
Figure 50. Slew Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
30
Copyright © 2017, Texas Instruments Incorporated
OPA196, OPA2196, OPA4196
www.ti.com.cn
ZHCSGE9 –JULY 2017
9 Power-Supply Recommendations
The OPAx196 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
–
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
•
•
Make sure to physically separate digital and analog grounds paying attention to the flow of the ground
current. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup.
In order to reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 52, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Clean the PCB following board assembly for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced
into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
Copyright © 2017, Texas Instruments Incorporated
31
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
10.2 Layout Example
VIN
+
VOUT
RG
RF
Figure 51. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
RF
VS+
N/C
N/C
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
Copyright © 2017, Texas Instruments Incorporated
Figure 52. Operational Amplifier Board Layout for Non-inverting Configuration
32
版权 © 2017, Texas Instruments Incorporated
OPA196, OPA2196, OPA4196
www.ti.com.cn
ZHCSGE9 –JULY 2017
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的功能，从而构建
一个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹中下载免费的 TINA-TI 软件（网址为 http://www.ti.com.cn/tool/cn/tina-ti）。
11.1.1.2 TI 高精度设计
TI 高精度设计（请访问 http://www.ti.com.cn/ww/analog/precision-designs/ 获取）是由 TI 公司高精度模拟 应用 专
家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选择、仿真、完整印刷电路板 (PCB) 电路原理图和
布局布线、物料清单以及性能测量结果。
11.2 文档支持
11.2.1 相关文档
•
•
•
《运算放大器的电磁干扰 (EMI) 抑制比》
0-1A 单电源低侧电流传感解决方案
《适合所有人的运算放大器》
11.3 相关链接
表 4 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
OPA196
OPA2196
OPA4196
11.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
版权 © 2017, Texas Instruments Incorporated
33
OPA196, OPA2196, OPA4196
ZHCSGE9 –JULY 2017
www.ti.com.cn
11.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.6 商标
e-trim, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
11.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
34
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA196ID
OPA196IDBVR
OPA196IDBVT
OPA196IDGKR
OPA196IDGKT
OPA196IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
D
DBV
DBV
DGK
DGK
D
8
5
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA196
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
50 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
O196
5
O196
8
NIPDAU
O196
8
NIPDAU
O196
8
NIPDAU
OPA196
OP2196
2196
OPA2196ID
SOIC
D
8
NIPDAU
OPA2196IDGKR
OPA2196IDGKT
OPA2196IDR
OPA4196ID
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
Call TI | NIPDAU
Call TI | NIPDAU
NIPDAU
8
2196
8
OP2196
OPA4196
OPA4196
SOIC
D
14
14
NIPDAU
OPA4196IDR
SOIC
D
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2022
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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Addendum-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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